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DSP56321 Reference Manual 24-Bit Digital Signal Processor

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DSP56321 Reference Manual 24-Bit Digital Signal Processor DSP56321 Reference Manual 24-Bit Digital Signal Processor DSP56321RM Rev. 1, March 2005 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses Home Page: granted hereunder to design or fabricate any integrated circuits or integrated circuits based on www.freescale.com the information in this document. E-mail: [email protected] Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee USA/Europe or Locations not listed: regarding the suitability of its products for any particular purpose, nor does Freescale Freescale Semiconductor Semiconductor assume any liability arising out of the application or use of any product or Technical Information Center, CH370 1300 N. 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Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] Document Order Number: DSP56321RM Rev. 1 3/2005 Overview 1 Signals/Connections 2 Memory Configuration 3 Core Configuration 4 Clock Configuration 5 Programming the Peripherals 6 Host Interface (HI08) 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communications Interface (SCI) 9 Triple Timer Module 10 Enhanced Filter Coprocessor (EFCOP) 11 Bootstrap Program A Programming Reference B Index IND 1 Overview 2 Signals/Connections 3 Memory Configuration 4 Core Configuration 5 Clock Configuration 6 Programming the Peripherals 7 Host Interface (HI08) 8 Enhanced Synchronous Serial Interface (ESSI) 9 Serial Communications Interface (SCI) 10 Triple Timer Module 11 Enhanced Filter Coprocessor (EFCOP) A Bootstrap Program B Programming Reference IND Index Contents 1 Overview 1.1 Manual Organization. 1-2 1.2 Manual Conventions . 1-3 1.3 Features . 1-4 1.4 DSP56300 Core Functional Blocks . .1-5 1.4.1 Data ALU. 1-6 1.4.1.1 Data ALU Registers . 1-6 1.4.1.2 Multiplier-Accumulator (MAC). .1-6 1.4.2 Address Generation Unit (AGU). .1-7 1.4.3 Program Control Unit (PCU). 1-7 1.4.4 Clock Generator Circuit. 1-8 1.4.5 JTAG TAP and OnCE Module . 1-8 1.4.6 On-Chip Memory. 1-9 1.4.7 Off-Chip Memory Expansion . .1-10 1.5 Internal Buses . 1-10 1.6 Block Diagram . 1-11 1.7 DMA Controller . 1-11 1.8 Peripherals. 1-12 1.8.1 GPIO Functionality . 1-12 1.8.2 HI08 . 1-12 1.8.3 ESSI . 1-12 1.8.4 SCI . 1-13 1.8.5 Timer Module . 1-13 1.8.6 EFCOP . 1-14 2 Signals/Connections 2.1 Power . 2-3 2.2 Ground . 2-3 2.3 Clock . 2-4 2.4 PLL . 2-4 2.5 External Memory Expansion Port (Port A). 2-4 2.5.1 External Address Bus . 2-4 2.5.2 External Data Bus . 2-5 2.5.3 External Bus Control . 2-5 2.6 Interrupt and Mode Control . 2-7 2.7 HI08 . 2-8 2.8 Enhanced Synchronous Serial Interface 0 . 2-10 2.9 Enhanced Synchronous Serial Interface 1 . 2-12 2.10 SCI . 2-14 2.11 Timers . 2-15 2.12 JTAG and OnCE Interface . 2-15 DSP56321 Reference Manual, Rev. 1 Freescale Semiconductor v Contents 3 Memory Configuration 3.1 Program Memory Space . 3-1 3.1.1 Internal Program Memory . 3-1 3.1.2 Memory Switch Modes—Program Memory . 3-2 3.1.3 Program Bootstrap ROM . 3-2 3.2 X Data Memory Space . 3-2 3.2.1 Internal X Data Memory . 3-2 3.2.2 Memory Switch Modes—X Data Memory . 3-3 3.2.3 Internal X I/O Space . 3-3 3.3 Y Data Memory Space . 3-3 3.3.1 Internal Y Data Memory . 3-3 3.3.2 Memory.
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