Field Engineering Technical Manual SPD 10/20 Stored Program Display
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- ' FIELD ENGINEERING T EC HNI CAL MANUAL SPD™ 10/20 STORED PROGRAM DISPLAY ., INCOTERM Corporation FS 002 "This document contains information proprietary to INCOTERM Corporation and is delivered on the express condition that it is not to be dis closed, reproduced in whole or in part, or used for manufacture for anyone other than INCOTERM Corporation without its written consent, and that no right is granted to disclose or so use any in formation obtained in said document. This re striction does not limit the right to use information obtained from another source. 11 SPDTM Copyright © 1971 by INCOTERM Corporation, Marlboro, Mass. TABLE OF CONTENTS Chapter LIST OF ILLUSTRATIONS ix LIST OF TABLES xi I INTRODUCTION · 1-1 1. 1 Scope 1-1 1. 2 General Specifications 1-1 1. 3 Configuration 1 -1 1. 3. 1 Minimum Configurations 1-2 1. 3. 2 Units Available for Expanded Configurations 1-2 1. 4 Reference Documents 1-3 II INSTALL.A TION 2-1 2. 1 Visual Inspection 2-1 2. 2 Configuration Chart 2-3 2. 3 Site Preparation 2-10 2. 4 Installation 2-10 2. 4. 1 Cabling of Product 005, Model 00010 2-10 2. 4. 2 Cabling of Product 005, Model 00011 2-13 2. 4. 3 Cabling of Product 005, Model 00014 2-13 III OPERATION 3-1 3. 1 General Information 3-1 3. 2 Keyboard 3-1 3. 2. 1 Introduction 3-1 3. 2. 2 Key Functions 3-2 3. 2. 3 Indicator Functions 3-6 3. 3 Initial Turn On and Check Out 3 -6 3. 3. 1 Initial Turn On Procedures and Indications 3-6 3. 3. 2 Programmed Operation 3-7 IV SYSTEM DESCRIPTION 4-1 4. 1 Introduction 4-1 4. 2 System Functional Description 4-1 iii TABLE OF CONTENTS (Cont. ) Chapter 4. 2. 1 General Information 4-1 4. 2. 2 Terminal Processing Unit 4-3 4. 2. 3 Interface Control 4-6 4. 3 Addressing and Instruction Formats 4-7 4. 3. 1 Introduction 4-7 4. 3. 2 Hexadecimal Notation 4-8 4. 3. 3 Word Formats 4-9 4. 3. 4 Instruction Classes 4-10 4. 3. 5 Effective Address Calculation 4-11 4. 3. 6 Basic System Timing and Data Flow 4-14 V THEORY OF OPERATION 5-1 5. 1 Logic Utilized 5-1 5. 1. 1 Logic Levels 5-1 5. 1. 2 Schematic Interpretation 5-5 5. 2 Data Flow Electronics 5-8 5. 2. 1 Introduction 5-8 5. 2. 2 General Discussion of Data Flow 5-9 5. 2. 3 Bus System 5-12 5. 2. 4 Memory Address Register 5-12 5. 2. 5 Arithmetic Unit Adder 5-13 5. 2. 6 Arithmetic Unit Bus 5-13 5. 2. 7 Auxiliary Arithmetic Unit 5-13 5. 2. 8 Character Register 5-15 5. 2. 9 Line Register 5-16 5. 2. 10 Accumulator Register 5-16 5. 2. 11 Condition Store Register 5-17 5. 2. 12 Program Counter Register 5-17 5. 2. 13 Test Compara tor 5-18 5. 2. 14 Bus Enable Decoders for the MDR 5-18 5. 2. 15 Memory Data Register 5-19 5. 2. 16 Memory Data Bus Drivers 5-20 iv TABLE OF CONTENTS (Cont.) Chapter 5. 2. 17 Exclusive-Or Unit 5-20 5. 2. 18 TPU Register-Clock Drivers 5-21 5. 3 Data Control Electronics 5-21 5. 3. 1 General Information 5-21 5. 3. 2 Instruction Register and Decoder 5-25 5. 3. 3 Generic Opcode Decoder 5-26 5. 3. 4 Miscellaneous Control Functions 5-27 5. 3. 5 State Counter 5-35 5. 3. 6 Auxiliary Arithmetic Unit 5-39 5. 3. 7 Arithmetic Unit Control 5-43 5. 3. 8 Real Time Clock Module 5-45 5. 3. 9 Interrupt Controls 5-46 5. 3. 10 Controller Decoder and Wired Option Matrix 5-48 5. 3. 11 Control Line Drivers 5-49 5. 4 Memory Electronics 5-49 5. 4. 1 Introduction 5-49 5. 4. 2 General Discussion of Memory Organization and Operation 5-49 5. 4. 3 X and Y Drivers and Associated Logic 5-54 5. 4. 4 Inhibit Logic and Drivers 5-57 5. 4. 5 Memory Stack Sense Electronics 5-58 5. 4. 6 Memory Sense Logic 5-60 5. 5 Timing and Refresh Electronics 5-61 5. 5. 1 Introduction 5-61 5. 5. 2 20-Phase Clock Timing Unit 5-64 5. 5. 3 Control, Start and Last Line Control 5-65 5. 5. 4 Line Computation Logic 5-66 5. 5. 5 Character Code Translator 5-66 5. 5. 6 Refresh Video Circuit 5-67 5. 5. 7 Read-Only-Memory and Input Logic 5-68 5. 5. 8 ROM Data Buffer 5-70 5. 6 High Efficiency Power Supply 5-71 5. 6. 1 Operation 5-74 V TABLE OF CONTENTS (Cont.) Chapter 5. 6. 2 Operation 5-74 5. 6. 3 Regulation 5-74 5. 6. 4 Typical Checks 5-75 5. 7 Line Lock Oscillator 5-76 VI INPUT /OUTPUT INTERFACE CONTROL 6-1 6. 1 Input/ Output System 6-1 6. 2 Keyboard 6-1 6. 3 Keyboard Controller 6-5 6. 3. 1 Introduction 6-5 6. 3. 2 Input/Output Data 6-5 6. 3. 3 Control Logic 6-9 6. 4 Asynchronous Controller 6-11 6. 4. 1 General 6-11 6. 4. 2 Timing Circuits 6-20 6. 4. 3 Input/ Output Commands 6-21 6. 4. 4 Write Mode 6-22 6. 4. 5 Read Mode 6-23 6. 4. 6 Boot Mode 6-24 6. 5 Synchronous Controller 6-24 6. 5. 1 General 6-24 6. 5. 2 Circuit Options 6-24 6. 5. 3 TPU Control and Modem Interface 6-26 6. 5. 4 Multiplexer Operation with Synchronous Controller 6-27 6. 5. 5 Synchronous Operation in BOOT Mode 6-27 6. 5. 6 Basic Operation 6-28 6. 6 Split Screen Controller 6-29 6. 6. 1 Operation 6-33 6. 7 Boot Controller 6-34 6. 7. 1 Introduction 6-34 6. 7. 2 Remote Load Sequence 6-34 6. 7. 3 Boot Controller Circuitry 6-35 vi TABLE OF CONTENTS (Cont.) Chapter Page VII 7-1 7. 1 General 7-1 7. 2 Field Substitution 7-1 7. 3 Test Console 7-9 7. 3. 1 Wiring Procedure 7-11 7. 3. 2 Detailed Explanation of Control Switches 7-17 7. 4 Test Points Not Console Tested 7-20 7. 5 Waveforms 7-27 7. 6 CRT Adjustments 7-33 APPENDIX A-SIGNAL MNEMONICS A-1 APPENDIX B-OPTION BLOCKS B-1 APPENDIX C-MISCELLANEOUS CABLE DATA C-1 vii LIST OF ILLUSTRATIONS Figure 1-1 Minimum Terminal Configurations 1-5 1-2 SPD Product Line 1-6 2-1 Factory Packing 2-2 2-2 Removal of Plywood Base 2-3 2-3 Circuit Board Identification and Location 2-4 2-4 Bottom View of Terminal Showing Fuse and Connector Locations 2-5 2-5 TPU Chas sis Photo 2-6 2-6 Actual Bottom View Photo 2-7 2-7 Sample Shipping Memo 2-11 2-8 Cabling Diagram Dual Display 2-12 2-9 Cabling Diagram Master Terminal 2-13 3-1 Typical Keyboard Arrangement 3-3 4-1 SPD 10/20 Stored Program Display System 4-2 4-2 Circuit Board Identification 4-4 4-3 2K Core Memory Layout 4-12 4-4 Effective Address Calculation 4-13 4-5 System Timing Example 4-17 5-1 Integrated Circuit Pin Identification 5-2 5-2 Simplified Block Diagram TPU Data Flow 5-10 5-3 Data Flow Module 5-11 5-4 Data Control Circuit Module 5-22 5-5 Simplified Block Diagram Data Control 5-23 5-6 Detailed Block Diagram Instruction Register and Decoder 5-24 5-7 Memory Electronics Module 5-50 5-8 Memory Module 5-51 5-9 Simplified Block Diagram Memory System 5-52 5-10 Simplified Functional Diagram and Logic Table SN 7 5324 Memory Driver 5-55 5-11 Memory Timing 5-59 ix LIST OF ILLUSTRATIONS (Cont. ) Figure 5-12 Refresh Module Timing Unit 5-62 5-13 Simplified Block Diagram Refresh Module Refresh Module Timing Unit 5-63 5-14 Internal View Power Supply 5-72 5-15 Simplified Block Diagram Power Supply 5-73 5-16 Line Lock Oscillator Schematic 5-76 6-1 Code Chart, 1090-C Keyboard 6-2 6-2 Simplified Keyboard Block Diagram Current Path Illustrated for J Key 6-3 6-3 Keyboard Controller 6-6 6-4 Typical Keyboard Lamp Driver Circuit 6-7 6-5 Asynchronous Controller 6-12 6-6 Block Diagram Asynchronous Controller 6-14 6-7 Synchronous Controller 6-25 6-8 Split Screen Controller 6-30 6-9 Simplified Block Diagram Split Screen Controller 6-31 6-10 Split Screen Timing 6-32 6-11 Simplified Diagram Boot Controller 6-36 7 -1 Bottom View of Terminal Illustrating Voltage Test Points and Adjustment Locations 7-6 7-2 Keyboard Bottom View 7-8 7-3 INCOTERM Test Console 7-10 7-4 Controller Circuit Board Extender 7-12 7-5 Computer Circuit Board Extender 7-13 7-6 T. V. Monitor Adjustments 7-34 7-7 Cathode Ray Tube Adjustments 7-35 X LIST OF TABLES Table Page 1-1 SPD 10/20 TPU Specifications 1-3 1-2 SPD Product Physical and Electrical Data 1-4 2-1 Configuration Chart 2-8 4-1 SPD 10 / 20 Controllers, Related Function and External Devices 4-7 4-2 Decimal, Binary and Hexadecimal Equivalents 4-8 5-1 Integrated Circuit Reference Table 5-3 6-1 Keyboard Connectors 6-4 6-2 Asynchronous Controller Option Blocks 6-15 7-1 Field Problem Identification 7-2 7-2 Test Point Wiring From TPU to Console 7-14 7-3 Test Points Not Console Tested 7-21 xi FOREWORD This manual provides the installation, theory of operation and maintenance procedures for the SPD™ -10/ 20 stored Program Display Terminal.