ARM Architecture and the Lab's Hardware
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Wind River Vxworks Platforms 3.8
Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................ -
AVR32 EVK1105 Evaluation Kit
Your Electronic Engineering Resource ATMEL - ATEVK1105 - AVR32 EVK1105 Evaluation Kit Product Overview: The AVR32 EVK1105 is an evaluation kit for the AT32UC3A3256 which combines Atmel’s state of art AVR32 microcontroller with an unrivalled selection of communication interface like USB device including On-The-Go functionality, SDcard, NAND flash with ECC and stereo 16-bit DAC. The AVR32 EVK1105 is an evaluation kit for the AT32UC3A0512 which demonstrates Atmel’s state-of-the-art AVR32 microcontroller in Hi-Fi audio decoding and streaming applications. Kit Contents: The kit contains reference hardware and software for generic MP3 player docking stations. Key Features: High Performance, Low Power AVR®32 UC 32-Bit Microcontroller Multi-Layer Bus System Internal High-Speed Flash Internal High-Speed SRAM Interrupt Controller Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), Watchdog Timer, Real-Time Clock Timer External Memories MultiMediaCard (MMC), Secure-Digital (SD), SDIO V1.1 CE-ATA, FastSD, SmartMedia, Compact Flash Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S and AT32UC3A364S Universal Serial Bus (USB) One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Legal Disclaimer: The content of the pages of this website is for your general information and use only. It is subject to change without notice. From time to time, this website may also include links to other websites. These links are provided for your convenience to provide further information. They do not signify that we endorse the website(s). -
Schedule 14A Employee Slides Supertex Sunnyvale
UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 SCHEDULE 14A Proxy Statement Pursuant to Section 14(a) of the Securities Exchange Act of 1934 Filed by the Registrant Filed by a Party other than the Registrant Check the appropriate box: Preliminary Proxy Statement Confidential, for Use of the Commission Only (as permitted by Rule 14a-6(e)(2)) Definitive Proxy Statement Definitive Additional Materials Soliciting Material Pursuant to §240.14a-12 Supertex, Inc. (Name of Registrant as Specified In Its Charter) Microchip Technology Incorporated (Name of Person(s) Filing Proxy Statement, if other than the Registrant) Payment of Filing Fee (Check the appropriate box): No fee required. Fee computed on table below per Exchange Act Rules 14a-6(i)(1) and 0-11. (1) Title of each class of securities to which transaction applies: (2) Aggregate number of securities to which transaction applies: (3) Per unit price or other underlying value of transaction computed pursuant to Exchange Act Rule 0-11 (set forth the amount on which the filing fee is calculated and state how it was determined): (4) Proposed maximum aggregate value of transaction: (5) Total fee paid: Fee paid previously with preliminary materials. Check box if any part of the fee is offset as provided by Exchange Act Rule 0-11(a)(2) and identify the filing for which the offsetting fee was paid previously. Identify the previous filing by registration statement number, or the Form or Schedule and the date of its filing. (1) Amount Previously Paid: (2) Form, Schedule or Registration Statement No.: (3) Filing Party: (4) Date Filed: Filed by Microchip Technology Incorporated Pursuant to Rule 14a-12 of the Securities Exchange Act of 1934 Subject Company: Supertex, Inc. -
Vxworks Architecture Supplement, 6.2
VxWorks Architecture Supplement VxWorks® ARCHITECTURE SUPPLEMENT 6.2 Copyright © 2005 Wind River Systems, Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means without the prior written permission of Wind River Systems, Inc. Wind River, the Wind River logo, Tornado, and VxWorks are registered trademarks of Wind River Systems, Inc. Any third-party trademarks referenced are the property of their respective owners. For further information regarding Wind River trademarks, please see: http://www.windriver.com/company/terms/trademark.html This product may include software licensed to Wind River by third parties. Relevant notices (if any) are provided in your product installation at the following location: installDir/product_name/3rd_party_licensor_notice.pdf. Wind River may refer to third-party documentation by listing publications or providing links to third-party Web sites for informational purposes. Wind River accepts no responsibility for the information provided in such third-party documentation. Corporate Headquarters Wind River Systems, Inc. 500 Wind River Way Alameda, CA 94501-1153 U.S.A. toll free (U.S.): (800) 545-WIND telephone: (510) 748-4100 facsimile: (510) 749-2010 For additional contact information, please visit the Wind River URL: http://www.windriver.com For information on how to contact Customer Support, please visit the following URL: http://www.windriver.com/support VxWorks Architecture Supplement, 6.2 11 Oct 05 Part #: DOC-15660-ND-00 Contents 1 Introduction -
Methods for Fitting the Linear Ballistic Accumulator
Behavior Research Methods 2009, 41 (4), 1095-1110 doi:10.3758/BRM.41.4.1095 Getting more from accuracy and response time data: Methods for fitting the linear ballistic accumulator CHRIS DONKIN , LEE A VERE ll , SC OTT BROWN , A N D A N D REW HE ATH C OTE University of Newcastle, Callaghan, New South Wales, Australia Cognitive models of the decision process provide greater insight into response time and accuracy than do stan- dard ANOVA techniques. However, such models can be mathematically and computationally difficult to apply. We provide instructions and computer code for three methods for estimating the parameters of the linear ballistic accumulator (LBA), a new and computationally tractable model of decisions between two or more choices. These methods—a Microsoft Excel worksheet, scripts for the statistical program R, and code for implementation of the LBA into the Bayesian sampling software WinBUGS—vary in their flexibility and user accessibility. We also provide scripts in R that produce a graphical summary of the data and model predictions. In a simulation study, we explored the effect of sample size on parameter recovery for each method. The materials discussed in this article may be downloaded as a supplement from http://brm.psychonomic-journals.org/content/supplemental. Many tasks used in experimental psychology involve edly samples information from the environment and that participants making relatively simple decisions, for which this information is used as evidence for one of the potential the experimenter measures the response times (RTs) and responses. As soon as the evidence in favor of one potential the accuracy of the responses. -
ARM Architecture
ARM Architecture Comppgzuter Organization and Assembly ygg Languages Yung-Yu Chuang with slides by Peng-Sheng Chen, Ville Pietikainen ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simp lic ity comes from the inexper ience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Mac hine ), owned by Acorn, Apple and VLSI ARM Ltd Design and license ARM core design but not fabricate Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 90% of 32-bit embedded RISC processors till 2009 • Used especially in portable devices due to its low power consumption and reasonable performance ARM powered products ARM processors • A simple but powerful design • A whlhole filfamily of didesigns shiharing siilimilar didesign principles and a common instruction set Naming ARM •ARMxyzTDMIEJFS – x: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazell e (JVM) – F: Floating-point – S: SthiiblSynthesizible version (source code version for EDA tools) Popular ARM architectures •ARM7TDMI – 3 pipe line stages (ft(fetc h/deco de /execu te ) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fe tc h/deco de /execu te /memory /wr ite ) – Separate instruction and data cache •ARM11 ARM family comparison year 1995 1997 1999 2003 ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed. -
Implementation, Verification and Validation of an Openrisc-1200
(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019 Implementation, Verification and Validation of an OpenRISC-1200 Soft-core Processor on FPGA Abdul Rafay Khatri Department of Electronic Engineering, QUEST, NawabShah, Pakistan Abstract—An embedded system is a dedicated computer system in which hardware and software are combined to per- form some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and Fig. 1. General block diagram of embedded systems. written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from (RISC) processor. This processor consists of all necessary GNU is configured and installed. The software is written in C components which are available in any other microproces- and Assembly languages. The communication between the host computer and FPGA board is carried out through the serial RS- sor. These components are connected through a bus called 232 port. Wishbone bus. In this work, the OR1200 processor is used to implement the system on a chip technology on a Virtex-5 Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open- FPGA board from Xilinx. -
Programmable Logic Design Grzegorz Budzyń Lecture 11: Microcontroller
ProgrammableProgrammable LogicLogic DesignDesign GrzegorzGrzegorz BudzyBudzy ńń LLectureecture 11:11: MicrocontrollerMicrocontroller corescores inin FPGAFPGA Plan • Introduction • PicoBlaze • MicroBlaze • Cortex-M1 Introduction Introduction • There are dozens of 8-bit microcontroller architectures and instruction sets • Modern FPGAs can efficiently implement practically any 8-bit microcontroller • Available FPGA soft cores support popular instruction sets such as the PIC, 8051, AVR, 6502, 8080, and Z80 microcontrollers • Each significant FPGA producer offers their own soft core solution Introduction • Microcontrollers and FPGAs both successfully implement practically any digital logic function. • Each solution has unique advantages in cost, performance, and ease of use. • Microcontrollers are well suited to control applications, especially with widely changing requirements. • The FPGA resources required to implement the microcontroller are relatively constant. Introduction • The same FPGA logic is re-used by the various microcontroller instructions, conserving resources. • The program memory requirements grow with increasing complexity • Programming control sequences or state machines in assembly code is often easier than creating similar structures in FPGA logic • Microcontrollers are typically limited by performance. Each instruction executes sequentially. Introduction – block diagram Source:[1] FPGA vs Soft Core Microcontroller: – Easy to program, excellent for control and state machine applications – Resource requirements remain constant -
Acorn Risc Pc 600
ACORN RISC PC 600 Acorn Acorns retort to the PowerMacs is an example of innovative design, with extensive expansion, the promise of RISC better cross-platform compatibility and graphics performance Archimedes owners only dreamed about. Ian PC 600 Burley gets a slice of the action. and CPU fans as the chip generates less than 1W of heat. Current ARM610s are 0.8 micron parts, and sample 0.6 micron parts are testing at 40MHz. One of the most striking aspects of the new RISC PC is its case, designed under the auspices of Allen Boothroyd, who designed the original BBC Micro and was a force behind hi-fi manufacturer Meridian. It is made of tough Bayer Bayblend ABS/Polycarbonate, which is used to make riot shields. Internal surfaces are coated to reduce radio frequency interference (RFI) but the external surface is an unpainted light grey. There is provision for screw-mounted peripherals inside but devices like CD-ROMs and hard disks will be clip-mounted Apple-style. Two twist-locking pins need to be turned 90° to get the case lid off. These can be padlocked and the case tethered. It takes less than a minute to open the case, swap processor modules and refit the lid, without any tools. Standard models have a slimline base case with ^ RISC PC Acorn Computers of Cambridge, and not their a two-expansion slot backplane; the front panel has a 600s get the colleagues from Cupertino, were the first to bring spring-loaded door to hide the floppy drive. If you need latest release affordable RISC computing to the masses. -
ETH Eidgenossische Technische Hochschule Zurich H.Eberle
ETH Eidgenossische lnstitut Technische fur lnformatik Hochschule ZUrich H.Eberle Hardware Description of the Workstation Ceres 11nuar 1987 ,70 70 . 61 .10 ETH Eidgenossische lnstitut Technische fur lnformatik Hochschule Zurich Eidrg. ~hn. ZI!rich lrricrm!!~!~:.~~lb;i::1H1a-k ETH~Zentrum CH..oo92 Zurich H.Eberle Hardware Description of the Workstation Ceres EidQ. lechn. He:ch'?~h'Jle Zilr\J::;!-: lnforme::!':.uib~iuthek El'l I-lei ili rn 11 CH-8002 ZOrtch gl,4-,23 Address of the author: lnstitut fiJr lnformatik ETH-Zentrum CH-8092 Zurich I Switzerland © 1987 lnstitut tor lnformatik, ETH Zurich 1 Hardware Description of the Workstation Ceres H.Eberle Abstract Ceres is a single-user computer based on the 32-bit microprocessor NS32000. The processor is oriented to the use of high-level languages. The hardware design concentrates on simplicity and modularity. The key features are the arbitrated memory bus and the high resolution bitmapped graphics display which promotes the attractivity of a programming workstation. This paper documents the hardware of the Ceres computer. 2 Contents 1 Introduction 3 2 Hardware Structure 4 2.1 Processor 4 2.2 Primary Memory 4 2.3 Secondary Memory 4 2.4 Input/Output Devices 4 3 Hardware Implementation 6 3.1 Processor Board 6 3.1.1 Processor 6 3.1.2 Memory Bus Arbiter 9 3.1.3 Boot ROM and Standard Input/Output Devices 12 3.2 Memory Board 15 3.3 Display Controller Board 18 3.3.1 Display Memory 18 3.3.2 Display Refresh Controller 19 3.4 Disk Controller Board 23 3.5 Motherboard 23 4 Hardware Extensions 24 References 26 Appendices A Circuit Diagrams 28 A.1 Processor Board 28 A.2 Memory Board 35 A.3 Display Controller Board 37 B PAL Design Specifications 42 c Interface Connectors 47 C.1 Processor Board 47 C.2 Display Controller Board 48 C.3 Motherboard 48 3 1 Introduction Todays working tools of a software engineer at the lnstitut fUr lnformatik of ETH ZOrich are the programming language Modula-2 [1] and the workstation computer Lilith [2]. -
Realtime Capabilities of Low-End Powerpc and ARM Boards for Embedded Systems
Realtime capabilities of low-end PowerPC and ARM boards for embedded systems Alexander Bauer PHYTEC Messtechnik Gmbh Robert-Koch-Str.39, 55129 Mainz, Germany [email protected] Abstract With the stepwise integration of the Realtime Preemption Patches (RT-Preempt) into the Mainline Linux kernel and their support for architectures other than Intel and AMD, there are now a number of choices which board to use for a particular embedded realtime project running Mainline Linux. In order to select the appropriate processor and clock frequency, it would be desirable to have some generally applicable ranges of worst-case latencies that can be obtained using the various processor types and conditions. We, therefore, determined the internal worst-case latency of PowerPC and ARM boards running Linux 2.6.20 and above patched with RT-Preempt. The PowerPC-board (Phytec phyCORE-MPC5200B) was running at 266 and 400 MHz, the ARM board (Phytec phyCORE-PXA270) was running at 266 and 520 MHz. This article will provide the details of the various measurement set-ups, present the results and discuss them with respect to the design differences between PowerPC and ARM. 1 Introduction This paper presents the results of the latency tests and discusses the results with respect of the different In the embedded market there is a wide range of processor designs. processors to choose from. A processor is typically selected for a customer design because of it features, e.g. video interface and peripherals, and the clock 2 Latency Tests frequency. With the growing importance of Linux and especially realtime Linux for customer designs For the latency tests based on MPC5200 we used in the embedded market, it is also essential to choose the PHYTEC phyCORE MPC5200 board with 400 the right processor that will cope with the realtime MHz as a reference platform. -
MODULA-2 TRANSLATOR USER's MANUAL First Edition May 1986
LOGITECH SOFTWARE ENGINEERING LIBRARY PASCAL TO MODULA-2 TRANSLATOR USER'S MANUAL First Edition May 1986 Copyright (C) 1984, 1985, 1986, 1987 LOGITECH, Inc. All Rights Reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of LOGITECH, Inc. LOGITECH, MODULA-2186,and MODULA-2IVX86 are trademarks ofLOGITECH, Inc. Microsoft is a registered trademark of Microsoft Corporation. MS-DOS is a trademark of Microsoft Corporation. Intel is a registered trademark ofIntel Corporation. IBM is a registered trademark ofInternational Business Machines Corporation. Turbo Pascal is a registered trademark ofBorland International, Inc. LOGITECH, Inc. makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability and fitness for a particular purpose. The information in this document is subject to change without notice. LOGITECH, Inc. assumes no responsibility for any errors that may appear in this document. From time to time changes may occur in the filenames and in the files actually included on the distribution disks. LOGITECH, Inc. makes no warranties that such files or facilities as mentioned in this documentation exist on the distribution disks or as part of the materials distributed. LU-GUllO-1 Initial issue: May 1986 Reprinted: September 1987 This edition applies to Release 1.00 or later of the software. ii TRANSLATOR Preface LOGITECH'S POLICIES AND SERVICES Congratulations on the purchase of your LOGITECH Pascal To Modula-2 Translator. Please refer to the following infonnation for details about LOGITECH's policies and services. We feel that effective communication with our customers is the key to quality service.