Electrical Characterisation of Ion Implantation Induced Defects in Silicon Based Devices for Quantum Applications

Aochen Duan

Supervised by Professor Jeﬀrey C. McCallum and Doctor Brett C. Johnson

School of Physics The University of Melbourne Australia

1 Abstract

Quantum devices that leverage the manufacturing techniques of silicon-based classical computers make them strong candidates for future quantum computers. However, the demands on device quality are much more stringent given that quantum states can decohere via interactions with their environment. In this thesis, a detailed investigation of ion implantation induced defects generated during device fabrication in a regime relevant to quantum device fabrication is presented. We identify diﬀerent types of defects in Si using various advanced electrical characterisation techniques. The ﬁrst experimental technique, electrical conductance, was used for the investigation of the interface state density of both n- and p-type MOS capacitors after ion implantation of various species followed by a rapid thermal anneal. As precise atomic placement is critical for building Si based quantum computers, implantation through the oxide in fully fabricated devices is necessary for some applications. However, implanting through the

oxide might affect the quality of the Si/SiO2 interface which is in close proximity to the region in which manipulation of the qubits take place. Implanting ions in MOS capacitors through the oxide is a model for the damage that might be observed in other fabricated devices. It will be shown that the interface state density only changes significantly after a fluence of 1013 ions/cm2 except for Bi in p-type silicon, where significant increase in interface state density was observed after a fluence of 1011 Bi/cm2. The second experimental technique, deep level transient spectroscopy, was used to study the defects in the substrate of Si after ion implantation. As Er has the potential of interfacing electrical and optical properties of Si based quantum computers, it is important to know what defects will be present after the implantation because of its large atomic mass. H and Er implantation damages were compared to demonstrate the more complex defect evolution for Er implantation. Although defects were still present after a 400 ˝C anneal, the concentration was reduced by at least one order of magnitude. The last experimental technique, charge pumping, was used on MOSFETs to study the interface state density directly in device structures that can be directly used in, for example, magnetic resonance and quantum sensing applications. Charge pumping has the potential of allowing measurement and manipulation of both electronic and magnetic properties of the interface defects and defects in the MOSFET channel. For such applications it may be necessary to operate the device close to absolute zero temperature. The work presented here represents a first step towards device and technique development with the ultimate aim of pushing measurements to mK temperatures where quantum device operations typically operate.

Declaration

This is to clarify that:

1. the thesis compromises only my original work towards the PhD except where indicated,

2. due acknowledgement has been made in the text to all other materials used,

3. the thesis is fewer than 100,000 words in length, exclusive of tables, maps, bibli- ographies and appendices.

Aochen Duan

Acknowledgements

Firstly, I want to acknowledge the difficulty the current pandemic has caused for all of us. It has changed some of our lives forever including mine. I want to hijack the beginning of this Thesis to promote mental health awareness: please reach out to people near you if you feel isolated, whether they are friends or family. A conversation with someone you care about can go a long way especially in these uncertain times. This Thesis would not have been possible without everyone who has helped along the way. I would like to start by thanking my supervisors Jeffrey McCallum and Brett Johnson for their immense support through my PhD journey, especially towards the end when completing this PhD seemed impossible due to the lockdown measures in Melbourne. They went above and beyond to ensure I was able to cross the finish line. For that I will be forever grateful. My gratitude also goes to my PhD panelist and Chair, David Jamieson and Rob Scholten, respectively, for giving me valuable feedback and constructive criticism during the progress review meetings. Both of you have helped me stay on track and motivated throughout my PhD journey. I would like to thank Chris Lew for helping me with the various critical electrical measurements presented in this Thesis. I also want to thank Stephen Gregory for your endless patience with the wire bonding, Kaijian Xing and Steve Yanni for the helpful discussions and warm company in the laboratories, and Daniel Creedon for kindly lending me various apparatuses. I would like to express my gratitude to the people in my Lunch Time in the Office group, Wee Chaimanowong, Gary Mooney, Alex Tsai, Sam Tonetto, and James Webb, for all the intellectual and entertaining conversations. You made my PhD journey much more enjoyable. Especially Gary for your companionship during the Stage 4 lockdown. Last but not least, I want to thank my partner Janny Lee for all the food you have created as it added much flavour to my PhD journey.

Contents

1 Introduction 8 1.1 Quantum Computing ...... 8 1.2 Criteria for Realising a Quantum Computer ...... 9 1.3 Quantum Computer Candidates ...... 10 1.3.1 Photons ...... 10 1.3.2 Trapped Atoms ...... 11 1.3.3 Nuclear Magnetic Resonance ...... 11 1.3.4 Quantum Dots in Solids ...... 12 1.3.5 Superconductors ...... 13 1.4 The Signiﬁcance of Phosphorus in Silicon Quantum Computing . . . . . 13 1.5 Complementing Silicon-Based Quantum Computing with Erbium . . . . 14 1.6 Building a Silicon-Based Quantum Computer from Top-Down ...... 15 1.7 Summary ...... 17

2 Background 18 2.1 Silicon ...... 18 2.1.1 Ion Implantation ...... 19 2.1.2 Simulations of Ion Implantation ...... 20 2.1.3 Bulk Defects ...... 21

2.1.4 Defects in the SiO2-Si System ...... 22 2.2 Characterisation Technique for Bulk Defects ...... 23 2.2.1 Bulk Defect Statistics ...... 24 2.2.2 Physics of Capacitance Transient ...... 28 2.2.3 Deep Level Transient Spectroscopy Technique ...... 31 2.3 Characterisation Techniques for Interface Defects ...... 33 2.3.1 Conductance Technique ...... 33 2.3.2 Charge Pumping ...... 36

4 CONTENTS 5

2.4 Conclusions ...... 42

3 Experimental Methods 44 3.1 Introduction ...... 44 3.2 Sample Cleaning ...... 44 3.3 Oxidation and Annealing ...... 45 3.4 Ion Implantation ...... 46 3.5 Annealing ...... 47 3.5.1 Metal Anneal ...... 47 3.5.2 Dopant Activation ...... 48 3.5.3 Post Ion Implantation Anneal ...... 48 3.6 Photolithography ...... 48 3.7 Defect Characterisation ...... 52 3.8 Examples of Capacitance and Conductance Curves for MOS ...... 53 3.9 Deep Level Transient Spectroscopy Measurement ...... 55 3.10 Charge Pumping Measurement ...... 57 3.11 Summary ...... 58

4 Ion Implantation Through the Si/SiO2 Interface 59 4.1 Introduction ...... 59 4.2 Background ...... 60 4.3 Experiment ...... 63 4.4 Capacitance and Conductance of Implanted

Si/SiO2 ...... 66

4.4.1 P implanted Si/SiO2 ...... 66

4.4.2 Er implanted Si/SiO2 ...... 69

4.4.3 Bi implanted Si/SiO2 ...... 71 4.4.4 Discussion ...... 72 4.5 Conclusions ...... 75 4.6 Future Work ...... 77

5 Deep Level Transient Spectroscopy Study of Defects in H- and Er- Irradiated p-Type Si 78 5.1 Introduction ...... 78 5.2 Background ...... 80 5.3 Experiment ...... 81 5.4 Results ...... 84 CONTENTS 6

5.4.1 Device Characterisation ...... 84 5.4.2 Defect Analysis and Discussion ...... 85 5.4.3 Further Discussion ...... 91 5.5 Conclusions ...... 93 5.6 Future Work ...... 94

6 Charge Pumping in Si MOSFETs: A Step Toward Developing a Sensi- tive Probe of Spin-Defect Interactions 95 6.1 Introduction ...... 95 6.2 Background ...... 96 6.3 Device Fabrication ...... 97 6.4 MOSFET Characterisation ...... 100 6.4.1 Van der Pauw Measurement ...... 101 6.4.2 Transmission Line Measurement ...... 101 6.4.3 IV Characteristics ...... 101 6.5 Charge Pumping Measurement ...... 104 6.6 Discussion ...... 113 6.7 Conclusions ...... 114 6.8 Future Work ...... 114

7 Summary, Conclusions, and Future Work 115

7.1 Ion Implantation Through the Si/SiO2 Interface ...... 115 7.1.1 Summary and Conclusions ...... 115 7.1.2 Future Work ...... 116 7.2 Deep Level Transient Spectroscopy Studies on p-Type Si ...... 116 7.2.1 Summary and Conclusions ...... 116 7.2.2 Future Work ...... 117 7.3 Charge Pumping in Si MOSFETs ...... 117 7.3.1 Summary and Conclusions ...... 117 7.3.2 Future Work ...... 118 7.4 Final Remarks ...... 118

Appendices 119 A Photolithography ...... 120 B MOSFET Fabrication Process ...... 122 C Anneal Schemes ...... 128 D Complementary SRIM Simulations for Chapter 4 ...... 129 CONTENTS 7

E Arrhenius Plots ...... 131 F Complementary Figures for Chapter 6 ...... 133

Bibliography 133

Chapter 1

Introduction

Silicon-based solid-state quantum computers are promising because they can leverage the fabrication techniques used in the manufacture of classical computers. However, the demands on device quality are much more stringent given that quantum states can decohere via interactions with their environment. This thesis addresses aspects of this challenge with an investigation of the defects generated during device fabrication using the industry standard technique of ion implantation, but in a regime relevant to quantum device fabrication. In this chapter, the concept of quantum computers and the motivation for building them will be introduced. The current state of quantum computers will be discussed including the materials that are being used to build a practical quantum computer and their corresponding advantages and disadvantages. One of the proposed ways to allow communication between qubits is optically addressing Er in Si. Development of Er in Si will be discussed both in the context of optical ﬁbre technology and quantum computing.

1.1 Quantum Computing

Classical computers are what drive our current technology. From smartphones to the state-of-the-art supercomputers, which are capable of solving complex computational problems. These all rely on the processing units that consist of what are known as bits. A bit is a binary state which is either in the 0 or the 1 state. Quantum computers likewise use bits, however, instead of being distinct states, they can be in a superposition of 0 and 1 states, known as qubits. This unique property is believed to potentially provide exponential speed-up over their classical counterparts for solving certain important problems like eﬃciently facterising large integers [1]. The concept of quantum computers was ﬁrst

8 1.2. CRITERIA FOR REALISING A QUANTUM COMPUTER 9

proposed by Feynman [2]. He realised quantum systems, which are hard to simulate on classical computers, could potentially be simulated efficiently on quantum computers, i.e. using quantum systems to simulate quantum systems. One of the biggest motivations for the realisation of a working quantum computer comes from the potential to efficiently factorise large integers as mentioned earlier, for which there is no known efficient classical algorithm. Shor’s quantum algorithm can factorise large integers within a time of Oplog Nq where N is the integer of interest [1,3]. Another quantum algorithm that provides quadratic speed-up over classical algorithms is called Grover’s algorithm which is used for searching an unsorted database with N entries [4,5]. It finds the correct targets with high probability. Motivated by the potential speed-up over solving certain problems, tremendous progress towards the fabrication of a working quantum computer has been made over the past couple of decades, examples will be given in next section.

1.2 Criteria for Realising a Quantum Computer

Having discussed the potential beneﬁts of a quantum computer, it is time to visit what criteria are needed for implementing a quantum computer. Initially, DiVincenzo proposed ﬁve criteria to realise a quantum computer [6],

• A physical system that is scalable and the qubits are well characterised.

• The ability to initialize the state of the qubits to a simple known state, such as |000...i.

• Long decoherence time.

• A universal set of quantum gates.

• The ability to measure the state of the qubits.

Since the DiVicenzo’s criteria were initially published, quantum computing consider- ations have diversiﬁed and the criteria have been rephrased into three three more general criteria to accommodate other emerging concepts with the long decoherence times still being an essential underlying criteria [7],

• The physical system is scalable.

• A universal logic. 1.3. QUANTUM COMPUTER CANDIDATES 10

• The quantum computation is correctable.

These three new criteria are the updated version of DiVincenzo’s five criteria. The first is similar to DiVincenzo’s with well-charactersied qubits assumed. The second looks similar to DiVincenzo’s fourth, but it does not specifically require gates because it was realised that gates are not a necessity for quantum computers. For example, an adiabatic quantum computer finds the answer to a computational problem by finding the ground state of the qubits that the original problem was mapped onto. The ground state is achieved by adiabatically evolving the “problem” qubits. The third criterion contains DiVincenzo’s second and fifth criteria because any quantum error correction code would require the efficient initialisation and measurement of the qubits, this is to ensure no unwanted entropy is introduced to the system. Now that we are familiar with the criteria for implementing a quantum computer, let us examine the materials that have been employed to tackle this daunting task.

1.3 Quantum Computer Candidates

To control quantum systems and measure them while preserving their strong isolation from their environment is not an easy task to accomplish. However, tremendous eﬀorts have been made to move towards that goal. Here, we report the candidates for realistically building a quantum computer.

1.3.1 Photons

Optical quantum computers use polarised photons as qubits. In 2001, a scheme known as the KLM (Knill–Laflamme–Milburn) protocol [8] showed that single-photon sources and detectors, and linear optical circuits are enough to realise scalable quantum computers. One of the early examples of the protocol was using an integrated waveguide silica-on-silicon chip that guides four single-photon qubits to factor the integer 15 using Shor’s algorithm [9]. The daunting resource overhead to operate a optical quantum computer was reduced owing to the use of cluster states or error encoding, more information about this achievement can be found in Ref [10]. Efforts have been made to devise efficient single-photon detectors [11] and sources [12], and devices that could enable a deterministic interaction between photons [13], and large-scale photonic circuits [14]. Despite the advancement since the proposal of the KLM protocol, a significant challenge in realising photonic quantum computers is the photon loss. However, the technology used in pho- 1.3. QUANTUM COMPUTER CANDIDATES 11 tonic quantum computing could benefit other types of quantum computer hardware by allowing quantum communication between matter qubits using photons.

1.3.2 Trapped Atoms

Quantum computers can also be realised by confining cold ions in a linear trap in free space, and the interaction between them can be achieved using laser beams, this idea was first introduced in 1995 by Cirac and Zoller [15]. Since the proposal, a six-atom “Schrodinger cat” state [16], which is an equal superposition of two maximally different quantum states, and up to eight-particle entangled states of the W type [17] have been achieved with trapped ions. A W type entangled state is a superposition of n two-level systems where exactly one system is in the one of two states while all others are in the other state, for example, an n-qubit W type state is

1 |W i “ ? p|100...0i ` |010...0iq ` |000...1iq. (1.3.2.1) n

One of the challenges in scaling a trapped ion quantum computer lies in the large number of controlled and stabilised lasers. A recent architecture proposal seemed to circumvent this by using a global microwave and locally applied magnetic ﬁelds [18]. This architecture does not require the lasers to be precisely aligned nor individually controlled. Furthermore, the design consists of modules where each module is a standalone quantum computer, and when faulty, they could be replaced individually. That is a huge advantage in building a large scale quantum computer. However, in order to execute quantum gates, a number of major challenges still remain. They include creating magnetic ﬁeld gradients, calibration operations, and well-controlled voltages. Despite the challenges, trapped ions have demonstrated long decoherence time greater than 10 seconds [19], it remains to be seen if a large scale trapped ion quantum computer can preserve the long decoherence time.

1.3.3 Nuclear Magnetic Resonance

Nuclear spins in molecules in liquid solutions have been proposed as building blocks of a quantum computer [20,21]. By subjecting these spins to an external magnetic field, they can be identified individually through their Larmor frequency. The variation in the Larmor frequency comes from the shielding effects from electrons in molecular bonds. Hence, each spin can be controlled using a resonant radio-frequency pulse of a distinct frequency. Using seven qubits, factorising the number 15 was realised in liquid state 1.3. QUANTUM COMPUTER CANDIDATES 12 nuclear magnetic resonance [22]. Furthermore, universal control methods that allow the access of the full Hilbert space of the system was benchmarked using twelve qubits with the same technique [23]. One of major challenges in realising a nuclear magnetic resonance quantum computer is initialisation. The experiments mentioned earlier used initialisation techniques that are not scalable in liquids. A possible solution could be to incorperate the nuclear spins in solid-state materials rather than liquids, for example 29Si nuclear spins in a 28Si ma- trix [24]. The decoherence time of nuclear spins of 29Si exceeds 25s [25]. However, no sufficient initialization or measurement capabilities for effective correctability have been demonstrated for bulk nuclear magnetic resonance quantum computing.

1.3.4 Quantum Dots in Solids

The basic idea for a quantum dot is that it is an artificially structured system that can be filled with electrons (or holes). Some of the examples of quantum dots include transistors incorporating a transition-metal complex containing Co ions designed so that electron transport occurs through the charge states of Co [26], ultra small metallic grains that are sufficiently small that an individual grain can be measured by single-electron tunneling spectroscopy [27], ferromagnetic Co particles where there is no degeneracy between the spin-up and spin-down tunneling levels near zero magnetic field [28], and InP double barrier heterostructures in InAs nanowires [29]. Quantum computation using coupled quantum dots was first proposed by Loss and DiVincenzo in 1998 [30]. The qubits were made from the spins of the excess electrons on single-electron quantum dots. The interactions of the qubits were controlled by adjusting the voltages on the electrical gating of the tunneling barrier between neighboring quantum dots. One of drawbacks of this method is the use of semiconductor materials which contain non-zero nuclear spins. The inhomogeneous magnetic field created by nuclear spins can decrease the coherence time significantly. One way to eliminate the nuclear spins is to use material such as Si [31] or SiGe [32]. The scaling problem was addressed in 2008 [33], however, it remains to be seen how the qubits can be coupled on a large scale. Another way of using Si is by incorporating donors such as 31P [34]. In later sections, we will discuss the details of using 31P in silicon to realise a quantum computer. 1.4. THE SIGNIFICANCE OF PHOSPHORUS IN SILICON QUANTUM COMPUTING 13 1.3.5 Superconductors

Up until now, we have only introduced atomic scale quantum computers. A “larger” quantum computer that uses capacitors and inductors is built using superconductors. A superconductor circuit can be thought of as an ordinary LC-resonator circuit that acts like a quantum harmonic oscillator. However, the equidistant level quantisation of the harmonic oscillator makes it degenerate, hence, no distinct two levels can be found. A Josephson junction which is a thin insulating layer in-between supercondutors breaks the harmonicity allowing two quantised levels in the resulting anharmonic potential which gives rise to a qubit. Superconducting qubits have found success in both adiabatic quantum computing from D-Wave [35] and universal quantum computing from IBM [36]. Although the decoherence time for a superconducting qubit has increased from a few nanoseconds [37] to a few microseconds [38], improving the decoherence time and elimi- nating noise sources are still the biggest challenges for superconducting qubits.

1.4 The Signiﬁcance of Phosphorus in Silicon Quan- tum Computing

Silicon has been the backbone of the electronic industry over half a century, thanks to the continuous advances in silicon materials technologies [39]. If the current silicon complementary metal-oxide-semiconductor (CMOS) technologies can be leveraged to make a quantum computer, it would be a great advantage. Additionally, Si is one of the purest materials so decoherence could possibly be minimised. Recently, an architecture based on the current silicon technologies was proposed to realise a spin-based quantum computer [40], this is great news for the community of silicon-based quantum computers. The details of realising a silicon-based quantum computer will be discussed in the following paragraphs. In addition to the various candidates for realising a quantum computer, another potential is using 31P in 28Si [34] which was alluded to earlier. It was shown that 31P in Si is a suitable candidate for a scalable quantum computer. The zero spin of 28Si atoms 1 31 makes them an ideal environment in which to place 2 -spin donors such as P atoms.

The long longitudinal electron spin relaxation time [41], T1, and transverse relaxation

time [42], T2, make phosphorous doped silicon very appealing for quantum computing. Although natural Si contains the non-zero spin isotope 29Si, isotopically enriched 28Si can be engineered, and the coherence time of 31P in such an environment is orders of 1.5. COMPLEMENTING SILICON-BASED QUANTUM COMPUTING WITH ERBIUM 14

magnitude higher compared to a natural Si environment [43]. Although complete isolation of the qubits is impossible, fortunately there are quantum error-correcting codes that allow a certain degree of interaction between the quantum system and the environment, which makes it possible to build a practical quantum computer [44,45]. In light of error correction codes such as the surface code which pushes the threshold error rate to over 1% [46, 47], recently, a surface code architecture speciﬁcally designed for silicon based quantum computers proved in principle that error correction is indeed possible for the silicon approach [48]. However, millions of qubits are required to achieve that, hence the scalability of a quantum computer is also important. Many of the building blocks of a 31P in 28Si based quantum computer have been addressed, these include placing a single 31P in epitaxial Si using scanning tunnelling microscopy and hydrogen-resist lithography [49], loading and unloading [50, 51], and co- herently manipulating [52] single electrons, nanowires that are compatible with atom size devices [53]. Control over exchange interaction was recently achieved in two precision placed 31P donors [54]. All these show promise towards eventually realising a universal fault-tolerant quantum computer. Scaling a P based Si quantum computer includes precisely placing the P atoms in Si which has been explored [55], however, controlling more than two qubits and allowing long range communication between the qubits in Si are still to be achieved. One of the ways to remedy the long range communications is to incorporate photons. Strong spin- photon coupling has been observed in a silicon double quantum dot [56] with the photon stored in an on-chip high-impedance superconducting resonator, it is yet to be seen if this can be realised in 31P doped silicon. A possible way of creating photon-spin coupling in 31P doped silicon is using erbium, it has been demonstrated that individual erbium atoms can be addressed optically and detected electrically [57], it looks promising that photon-spin coupling could be achieved in 31P doped silicon in the near future.

1.5 Complementing Silicon-Based Quantum Comput- ing with Erbium

Erbium in silicon has been extensively studied for optical applications given its strong luminescence at 1.54 um arising from the intra-4f shell transitions of Er3` first discovered by Ennen et al. in 1983 [58]. Erbium has promising applications in optoelectronics [59– 63] and more recently spintronics which use the 4f shell transitions to optically address individual erbium ions in silicon for possible quantum computation and communication 1.6. BUILDING A SILICON-BASED QUANTUM COMPUTER FROM TOP-DOWN15 technologies [57]. This demonstrated for the first time the readout of a single spin by a combination of electrical and optical measurements. Our goal ultimately is to build a quantum computer. As mentioned earlier, one of the biggest challenges is to put the phosphorus atoms in an ordered array in silicon. Once that is done, we need to find a way to allow communications between the phosphorus donors. Coupling between erbium and phosphorus could be a viable way to achieve that. The idea is that the quantum state of phosphorus can be readout optically via erbium quantum states. The erbium pathway is still under investigation and it is yet to be demonstrated that coupling between erbium and phosphorus is viable. There is also a need to better understand the environment of the Er ions in the Si lattice and how to optimise this for quantum computing applications. However, given that optically addressing of a single erbium ion in silicon has been achieved, this provides the motivation to further explore the Er-Si system and eventually to see if information can be efficiently transferred between phosphorus donors in Si via a photon mediated pathway.

1.6 Building a Silicon-Based Quantum Computer from Top-Down

There are two approaches to building a Si-based quantum computer. One of them is the so-called bottom-up approach where P atoms are placed in the Si lattice with atomic precision via scanning tunnelling-microscopy (STM) hydrogen lithography [64], and the other one is the so-called top-down approach where P atoms are introduced in Si via deterministic ion implantation [55] often on fully fabricated devices [50, 57]. Although the latter does not yield the atomic precision achieved by the former, certain Si qubit architectures are much more relaxed about the requirement on the qubit distance than the Kane architecture such as the flip-flop architecture [65] where qubits are allowed to be placed more than 100 nm apart. One of the disadvantages of the bottom-up approach is that it is currently not versa- tile, i.e. no other atoms apart from P and As [66] have been incorporated into Si using the bottom-up approach. With ion implantation, various other ions have been introduced in Si including Sb [67], Er [57], and Bi [68]. The top-down approach requires low fluence implantation and typically through a gate oxide for quantum devices. A schematic illustration of a universal Si quantum computer is shown in Fig. 1.1 where qubits (blue spherical clouds) made of individual atoms are implanted through the gate electrodes. 1.6. BUILDING A SILICON-BASED QUANTUM COMPUTER FROM TOP-DOWN16

Figure 1.1: Schematic illustration of a universal Si quantum computer where qubits (blue spherical clouds) made of individual atoms are implanted through the gate electrodes. The environment near the qubits need to be pristine to ensure long coherence time of the qubit spins (represented by the arrows). Credit: Tony Melov/UNSW.

The environment near the qubits need to be pristine to ensure long coherence time of the qubit spins (represented by the arrows in Fig. 1.1). It is thus important to study any damage due to ion implantation. The damage in Si caused due to implantation of ions such as Er and Bi through an oxide in the low ﬂuence regime has not been studied previously. This Thesis will explore the damage in various Si-based devices due to ion implantation directly into the Si substrate or through the oxide in the low ﬂuence regime. In Chapter 4, we will present the studies on the oxide quality in MOS capacitors due to P, Er, and Bi implantation followed by annealing. The results reveal that the

Si/SiO2 interface density does not change noticeably after implantation through the oxide followed by a 5-second 1000 ˝C anneal up to a fluence of 1011 ions/cm2 except for the Bi implanted p-type samples where the interface density increases with implantation fluence. In Chapter 5, we will focus on Er implantation through oxide and directly in Si using MOS capacitors and Schottky diodes, respectively. The results are contrasted with light ions, H, implanted Si leading to observed significant differences that are likely related to the structure and evolution of the dense damage cascades created during Er ion implantation. In Chapter 6, we will investigate the Si/SiO2 interface quality in metal- oxide-semiconductor field-effect transistors (MOSFETs) some of which went through Er implantation during the MOSFET fabrication process. Our results move us closer to the possibility of identifying and quantifying individual spins at low temperatures relevant to quantum computer operations combining two widely used experimental techniques 1.7. SUMMARY 17 in Si device characterisation, charge pumping (CP) and electrically detected magnetic resonance (EDMR).

1.7 Summary

The motivation for building a quantum computer has been introduced. A brief survey of the literature of possible quantum computer candidates has been presented. Phospho- rus in silicon was discussed in some detail as it is considered a scalable way of building a quantum computer using the current silicon CMOS technologies. The possibility of coupling erbium ions and phosphorus donors in silicon has been introduced. The optical addressing of erbium ions in silicon provides a possible pathway of local information transfer between the phosphorus donors, which is an essential step towards a fully functional quantum computer. Chapter 2

Background

Silicon is the foundational material of the electronics industry and also solid state quantum computing. The basic material properties to this work are introduced in this Chapter together with the processing techniques employed to meld the material into a functioning device. Several electrical techniques are available for the characterisation of the defects that exist in silicon devices. Electrical techniques are most appropriate for determining what impact a defect may have on the operation of an electrical device. For qubit devices, microwaves and sometimes light can be used to control the spin state of an impurity in silicon, but spin readout and electrostatic control are all electrical. In this work, the conductance technique, deep level capacitance transient spectroscopy (DLTS) and charge pumping (CP) technique are employed. These are all sensitive to the low defect densities expected in state of the art quantum devices. These techniques will also be detailed in this Chapter.

2.1 Silicon

Silicon is the 14th element in the periodic table. It is thermally stable due to its high melting temperature (1410 ˝C), and it is the second most abundant element in Earth’s crust behind oxygen. Silicon is best known for its electronic applications which have transformed our society fundamentally for the past half century or so. The electrical properties of silicon are extremely sensitive to the impurity/dopant content. The conductivity can be increased by several orders of magnitude with the introduction of group III or V elements like B or P which needs to placed on substitutional lattice sites during growth, or afterwards by diﬀusion or implantation.

18 2.1. SILICON 19

2.1.1 Ion Implantation

Ion implantation involves the irradiation of a target with accelerated ion beams. When they enter the device, they will interact with the lattice through electronic and nuclear processes. Electronic interactions are between the incident ions and the electron clouds of the atoms of the lattice, while nuclear interactions are the collisions between the ions and the nuclei of lattice atoms within the device. After a nuclear collision, if the incident ion has enough energy, it can dislodge a target atom from its lattice site. If the dislodged secondary atom has enough energy, it can go on to displace other target atoms creating a collision cascade. The dislodged atom could come to rest at a non-lattice site making it an interstitial defect or it could substitute for a lattice atom. Vacancy defects can also be produced by these processes. These two defects can also form a pair known as the Frenkel pair. Isolated interstitials and vacancies are mobile at room temperature, so they will migrate and interact with other defects until immobile and stable defect complexes are formed including the divcancy, impurity-vacancy complexes. The implanted ion creates a cascade of displaced atoms, hence the production of defects. The implanted ion, losing its energy through electronic and nuclear interactions, will come to rest at a certain depth under the surface. This depth is determined by the implanted ion’s initial energy and the lattice into which it is implanted. The interactions are statistical in nature, hence, a Gaussian-like distribution of the implanted ion depth is expected. Figures 2.1(a) and (b) show schematics for a light ion and a heavy ion implanted into the Si substrate, respectively. As illustrated, the damage (grey bubbles) created around the ion track (green) is far more dense and complex for the heavy ion than the light ion due to more secondary collisions (black arrows). 2.1. SILICON 20

Light ion Heavy ion

(a) (b)

Figure 2.1: Schematics of a light ion (a) and a heavy ion (b) implantation into the Si substrate, respectively. The damage (greyIon bubbles) track created around the ion track (green) is far more dense and complex for the heavySecondary ion than collisions the light ion due to more secondary collisions (black arrows).

2.1.2 Simulations of Ion Implantation

There are many ways to model the implantation process to aid in the development of fabrication processes. These include Monte Carlo and Molecular Dynamics methods. Monte Carlo in particular accurately captures the stochastic nature of the implantation process. The simulation software employed in our work is based on this method which is called the Stopping and Range of Ions in Matter (SRIM) [69]. SRIM is extremely popular in the implantation field given it has been benchmarked against many different experiments. Additionally, it is user-friendly and free. At the core of SRIM is the program called the Transport of Ions in Matter (TRIM) which accepts input parameters such as the ion type and energy, and target material. In addition to information about the ion distribution in the target material in three dimensions, TRIM also outputs the vacancy concentration, straggle of the ions, and other parameters. Although SRIM predicts well the depth of the ions, it does not take into account the dynamics of the implantation induced damage cascade evolution with time and temperature. As a result, the actual defect concentration is expected to be much lower than that predicted [70]. Nonetheless, it is sufficient as a tool to estimate the ion concentration against depth. For Si based quantum computing applications, a depth of 20 nm or less under the surface is considered optimal for qubits in Si based quantum computers [55], it is therefore important to estimate the depth of the implanted ions before the implantation. An example of B implanted Si is shown in Fig. 2.2. The energy and fluence of the implantation are 6 keV and 1.7 ˆ 1015 B{cm2, respectively, resulting in a peak concentration of 4.7 ˆ 1020 B{cm3 at 25 nm below the Si surface. 2.1. SILICON 21

B, 6 keV )

3 4 B/cm

20 3 10

1 Concentration ( Concentration

0 0 10 20 30 40 50 60 70 80 90 100 Depth (nm)

Figure 2.2: SRIM simulation of B implanted Si with an energy of 6 keV and a ﬂuence of 1.7 ˆ 1015 B{cm2. The peak concentration is 4.7 ˆ 1020 B{cm3 at 25 nm below the Si surface.

2.1.3 Bulk Defects

One of the advantages of ion implantation is that it can introduce dopants in localised regions, however, it creates defects during the process. Schematics of the various defects mentioned earlier are shown in Fig. 2.3. There are two types of defects; one type includes foreign atoms or impurities, such as foreign interstitial (Fig. 2.3(b)) and foreign substitutional atoms (Fig. 2.3(c)). The other type includes lattice defects, such as vacancies (Fig. 2.3(d)), and self interstitials. These are simple defects which by themselves are not stable at any reasonable temperature and they are also mobile in the lattice so they migrate until they either annihilate or form complexes with other defects and hence form stable entities such as the vacancy-phosphorus defect (VP), or the carbon-oxygen interstitial defect (CiOi). After ion implantation, the concentration of these defects will most likely increase due to the atomic displacements in the collision cascades. The identiﬁcation and quantiﬁca- tion of some of these defects will be presented in Chapter 5. 2.1. SILICON 22

(a) (b)

Figure 2.3: A schematic picture of a pure lattice of silicon (blue dots) (a) that can have diﬀerent kinds of impurity, examples include an interstitial defect (green dot) (b), a substitutional defect (orange dot) (c), and vacancy defect (d).

2.1.4 Defects in the SiO2-Si System

Growing an oxide on silicon is a common process in fabrication of silicon-based electronic devices. However, during the oxide growth, defects in the oxide and at the oxide- sliicon interface can appear and this can adversely aﬀect the oxide quality and performance. The types of oxide defects include ﬁxed oxide charge, oxide trapped charge, mobile oxide charge, and interface trapped charge. They are illustrated in Fig. 2.4.

Na+ Oxide trapped charge Fixed oxide charge Li+ K+ + + + SiO x x x x 2

Interface trapped charge Si

Figure 2.4: Schematic diagram of diﬀerent types of oxide defects. 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 23

• Fixed oxide charge is a positive charge near the Si/SiO2 interface, it can be reduced during the oxide growth by annealing the oxidised sample in a nitrogen ambient immediately after oxidation [71].

• Oxide trapped charges can be either positive or negative, and they can be annealed out during the post oxidation anneal for reducing the ﬁxed oxide charge.

• Mobile oxide charge originates from ionic impurities such as Na`, Li`, and K` and these need to be avoided by processing control and cleanliness. Negative ions and heavy metals also need to be avoided by taking adequate care during the wafer cleaning stage immediately before the oxidation.

• Interface trapped charge is also known as the interface defect because it is a struc-

tural defect due to the lattice mismatch between Si and SiO2. The analysis on interface defects will be presented in Chapter 4.

The interface defects have been identiﬁed as the so-called “Pb” centres which are the dangling bonds at the Si/SiO2 interface [72, 73]. They are paramagnetic and have a broad distribution of possible energy levels close to the centre of the band gap. These paramagnetic centres can greatly reduce the coherence time of qubits if their concentration is high. Although interface traps naturally exist, their density is likely to change after implanting ions through the oxide. In addition to reducing the coherence time, an increase in interface traps can also lead to oxide current leakage and a ﬂat band voltage shift which can result in more negative impact on the device function. In the substrate, ion implantation will increase the density of interstitial, substitutional, and vacancy defect complexes and this can also have a negative impact on the device performance and function. The following sections will discuss the characterisation techniques used for our

devices to study the bulk and Si/Si2 interface defects.

2.2 Characterisation Technique for Bulk Defects

Characterising electrically active defects in ion-implanted electronic devices is crucial for reliable device performance and process control. Energy levels of deep traps in the band gap and their densities can be measured electrically. Optical identiﬁcation of trap states is also a valuable technique, but quantiﬁcation of the defect densities is generally not feasible. One of the electrical methods to study the bulk defects is DLTS which 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 24 monitors the change in capacitance of the device of interest [74]. It provides great sensitivity, speed, and resolution. This technique allows measuring the thermal emission rate, activation energy, concentration, and capture rate of each distinguishable trap. Before delving into the technical details of the DLTS technique, the basic defect physics behind the technique will be introduced alongside a capacitance transient measurement based on the mathematical model for quantitative analysis on the defects. Building on the capacitance transient measurement, the DLTS technique will then be introduced. It is a spectroscopic technique that yields information about the trap energy in the band gap which can be valuable information in deducing the composition of the defect.

2.2.1 Bulk Defect Statistics

For pure semiconductors, the valence band and the conduction band are separated by a band gap and there are defects or impurities present to produce energy levels in the band gap. When defects are introduced, they can produce discrete energy levels in the band gap, These defects can also be called traps or generation-recombination (G-R) centers. Fig. 2.5 is a schematic diagram of the capture and emission processes between the defect centres and the charge carriers. The energy level of the defect centre is labelled by either pT when the trap is occupied by a hole or nT when it is occupied by an electron. The centre could first capture an electron (blue) from the conduction band as shown 3 ´1 in Fig. 2.5(a) with a capture coefficient cn in cm s . This electron could then be re- emitted back to the conduction band shown in Fig. 2.5(b) with an electron emission rate ´1 en in s , or capture a hole (green) from the valence band shown in Fig. 2.5(c) with a capture coefficient cp in the same units as cn. And lastly, the hole could be re-emitted back to the valence band shown in Fig. 2.5(d) with a hole emission rate ep. When there are excess carriers in the semiconductor, these traps act as recombination centers (Fig. 2.5(a) followed by 2.5(c)), and when the carrier density is below the equilibrium value, for example in the reverse-biased space-charge region (scr) of a MOS-capacitor, they act as generation centers (Fig. 2.5(b) followed by 2.5(d)). When it is not acting as a recombination or generation centre, it is called a trapping centre where (a) is followed by (b) or (c) followed by (d), i.e. a carrier is captured but subsequently emitted back to the band from which it was captured. All these types of centres will be referred to as traps from now on.

Now let ET be the trap energy, NT the total trap concentration, n the electron concentration in the conduction band, and p the hole concentration in the valence band 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 25

cn en

pT nT nT pT

cp ep

Ev p

(a) (b) (c) (d)

Figure 2.5: Energy band diagram for a semiconductor with deep level centres. The processes depicted in the diagram are (a) a deep level centre pT occupied by a hole (green) capturing an electron n (blue) with an electron capture coeﬃcient cn, (b) a deep level centre nT occupied by an electron emitting the electron with an electron emission rate en, (c) a deep level centre nT occupied by an electron capturing a hole p with a hole capture coeﬃcient cp, and (d) a deep level centre pT occupied by a hole emitting the hole with a hole emission rate ep. introduced by the dopants (concentrations are in cm´3). The change in hole concentration is

dp “ e p ´ c pn , (2.2.1.1) dt p T p T where nT and pT are now the concentrations of the traps occupied by electrons and holes respectively, and nT ` pT “ NT . The hole capture coeﬃcient is deﬁned as

cp “ σpvth, (2.2.1.2)

where σp is hole capture cross-section and vth is the hole thermal velocity. Similarly for electron density

dn “ e n ´ c np , (2.2.1.3) dt n T n T 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 26

where en is the electron emission rate, cn is the coeﬃcient for electron captures, analogous to hole capture coeﬃcient. The appropriate equations for electrons will be introduced in the following sections, however, the formulation is not restricted to electrons, the equations for holes are analogous. When electrons or holes are captured or emitted, the trap occupancy changes with a rate of

dn dp dn T “ ´ dt dt dt

“ pcnn ` epqpNT ´ nT q ´ pcpp ` enqnT . (2.2.1.4)

There are four scenarios to be considered when solving the above equation.

Scenario One: Device under Reverse Bias

In the space-charge region (scr), both n and p are small enough to be neglected, and the equation reduces to

dn T “ e N ´ pe ` e qn , (2.2.1.5) dt p T p n T

which has a standard solution

´pep`enqt`a e ´ epNT nT ptq “ ´ , (2.2.1.6) ep ` en

where a is a constant subject to initial condition of nT ptq. The steady-state density in the scr is then

ep nT p8q “ NT (2.2.1.7) ep ` en

Scenario Two: Device under Zero Bias

Then we have a quasi-neutral region where n and p can be considered constant. Under this condition

´t{τ pep ` cnnqNT ´t{τ nT ptq “ nT p0qe ` p1 ´ e q, (2.2.1.8) en ` cnn ` ep ` cpp 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 27

where nT p0q is the initial concentration of the traps occupied by electrons, and τ “ 1 . The steady-state concentration in those regions is en`cnn`ep`cpp

e ` c n n p8q “ p n N . (2.2.1.9) T τ T

Therefore we know the steady-state solutions for both the scr and the quasi-neutral regions. In general, Eq. (2.2.1.8) is hard to solve, because we know neither capture rate nor emission rate. However Eq. (2.2.1.8) can be simpliﬁed if the substrate is of a particular type, for instance n-type. Then p can be ignored, and the equation becomes

´t{τ 1 pep ` cnnqNT ´t{τ 1 nT ptq “ nT p0qe ` p1 ´ e q (2.2.1.10) en ` cnn ` ep

where τ 1 “ 1 . When it is under zeros bias, with n mobile electrons, capture rates en`cnn`ep dominate emission rates, i.e. cnn " ep, en, then nT p8q « NT .

Scenario Three: Device Pulsed from Zero to Reverse Bias

Deﬁne the time at the start of the pulse t “ t1 then Eq. 2.2.1.10 becomes

1 ´t1{τ 1 pep ` cnnqNT ´t1{τ 1 nT pt q “ nT p0qe ` p1 ´ e q. (2.2.1.11) en ` cnn ` ep

The trap energy level in general is closer to either the conduction band or the valence band, if we assume it is closer to the conduction band, then en " ep. This reasonable assumption allows ep to be ignored from Eq. (2.2.1.11). When the pulse is initially generated, electron transit time is on the orders of picoseconds which is much shorter than the capture times, this means emission dominates capture en " ep " cnn, hence only en needs to be considered. Eq. (2.2.1.11) becomes

1 1 ´t {τe nT pt q “ nT p0qe (2.2.1.12) where τ “ 1 , and n p0q « N . e en T T

Scenario Four: Pulse Removed

Now electrons rush back to the scr, ready to be captured by pT state. As we mentioned earlier, electron transit time is very short, the region becomes a quasi-neutral region very quickly, which means Eq. (2.2.1.10) applies. Now capture dominates emission, i.e. 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 28

cnn " en, ep, Eq. (2.2.1.10) becomes

´t{τc ´t{τc nT ptq “ nT p0qe ` NT p1 ´ e q

´t{τc “ NT ´ pNT ´ nT p0qqe , (2.2.1.13) where n p0q “ ep N , i.e. the steady-state density in the scr and τ “ 1 . T ep`en T c cnn Later on, it will be shown that scenario three is used to extract the total trap concentration. Scenarios one and two allowed the derivation of scenario three, and scenario four was presented for completeness.

2.2.2 Physics of Capacitance Transient

Early examples of capacitance transient spectroscopy measurements of trap states include the work of Williams [75], Sah et al. [76], and Yau and Sah [77]. The particular implementation of capacitance transient spectroscopy used in this thesis is DLTS originally described by Lang [74]. The capacitance in the scr of a semiconductor junction is given by

ε A C “ s W ε A “ s 2εspVbi´V q qNscr b qε N “ A s scr (2.2.2.1) d2pVbi ´ V q

where εs is the permittivity of the semiconductor, A is the area of semiconductor that

is under bias, W is the depletion width in the scr, Vbi is the built-in voltage, V is the

bias voltage, q is the electron charge, and Nscr is the ionised impurity density in the scr. The capacitance changes when the bias condition changes, which is the result of the time

dependence of nT ptq and pT ptq. When the bias is changed from zero to reverse bias, the 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 29

capacitance is

qε N ´ n C “ A s D T d 2pVbi ´ V q qε N n “ A s D 1 ´ T 2pV ´ V q N d bi c D n “ C 1 ´ T . (2.2.2.2) o N c D

qεsND where ND is the doping concentration and Co “ A . 2pVbi´V q If the concentration of deep level impurities is farb less than the doping concentration, which is normally the case, then

nT C “ Cop1 ´ q. (2.2.2.3) 2ND

However, if the impurity concentration is comparable to the doping concentration, constant capacitance DLTS (CC-DLTS) technique should be used. More details about CC- DLTS can be found in Ref [78]. When the device is ﬁrst under zero bias, the capacitance is constant. After a reverse bias pulse, electrons are emitted according to Eq. (2.2.1.12). Substituting it into the above expression we get

nT p0q ´t{τe C “ Cop1 ´ e q. (2.2.2.4) 2ND

If this capacitance change is plotted against time, one can ﬁnd τe. At equilibrium, the emission and capture processes will balance each other so that

dn “ 0; (2.2.2.5) dt

eno nTo “ cno nopTo

“ cno nopNT ´ nTo q, (2.2.2.6)

EF Éi N kT T where the subscript ‘o’ stands for equilibrium, no “ nie , nTo “ ET ÉF , ni is the 1è kT intrinsic electron concentration, EF is the Fermi energy level, Ei is the intrinsic Fermi

energy level, ET is the trap energy level, k is the Boltzmann constant, and T is the 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 30

temperature. Hence

EF Éi NT e n c n e kT N no To “ no i p T ´ ET ÉF q 1 ` e kT ET ÉF NT EF Éi NT e kT e c n e kT ùñ no ET ÉF “ no i ET ÉF 1 ` e kT 1 ` e kT ET Éi kT ùñ eno “ cno nie . (2.2.2.7)

ET Éi If we define n1 “ nie kT and assume the emission and capture coefficients remain constant, then we have

en “ cnn1. (2.2.2.8)

Recall en “ 1{τe and cn “ σnvth, we arrive at an expression for τe

Ei´ET e kT τe “ (2.2.2.9) σnvthni Ec´ET e kT “ , (2.2.2.10) σnvthNC

EiÉC where the last line is obtained by using ni “ NC e kT and NC is the effective density of states. The electron thermal velocity and the effective density of states in the conduction band respectively are

3kT v “ ; (2.2.2.11) th m c n 2πm kT N “ 2p n q3{2. (2.2.2.12) C h2

where mn is the eﬀective electron mass and h is the Planck’s constant. Finally the emission time constant can be written as

Ec´ET 2 e kT τeT “ (2.2.2.13) γnσn

1{2 3{2 where γn “ pvth{T qpNC {T q. The trap energy and the cross-section capture can then 2 1 be obtained by plotting lnpτeT q against kT . 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 31

2.2.3 Deep Level Transient Spectroscopy Technique

Measuring the full transient and finding out the time constant can be a very tedious and long process. DLTS bypasses this obstacle by using a double boxcar approach [74]. The key to the method is the use of a rate window. By measuring the capacitance difference of the transient at two fixed times using two boxcar averagers, the difference will reach a peak at a particular temperature for each trap level in the band gap, because the decay rate changes with temperature. A schematic example of how this works this is shown in Fig. 2.6. The difference in capacitance at t1 and t2 is recorded against the temperature. A maximum in capacitance different occurs at some temperature Tmax.

Tmax Temperature

ΔCmax Capacitance at various temperatures various at Capacitance

t 1 t2 ΔC = C(t1) – C(t2) Time

Figure 2.6: Schematic diagrams of capacitance transient at diﬀerent temperatures (left), and the corresponding diﬀerence in capacitance measured at t1 and t2 (right).

Using Eq. (2.2.2.4), the capacitance diﬀerence at two diﬀerent times t1 and t2 is

n 0 T p q ´t2{τe ´t1{τe ∆C “ Co pe ´ e q. (2.2.3.1) 2ND

Diﬀerentiating the above equation with respect to τe and setting it to zero we get a 2.2. CHARACTERISATION TECHNIQUE FOR BULK DEFECTS 32

maximum for τe at ∆Cmax, which is

t2 ´ t1 τe, max “ . (2.2.3.2) lnp t2 q t1

t2 By keeping the ratio constant as we vary the values of t1 and t2, for a given trap t1 level in the band gap we are able to obtain peaks at diﬀerent temperatures. An example of the DLTS spectra obtained from an Er-implanted MOS capacitor is shown in Fig. 2.7.

Each DLTS spectrum corresponds to slightly diﬀerent values of t1 and t2. However, the ratio t2 is the same for all spectra. The trap energy corresponding to the DLTS spectra t1 2 1 peaks is then obtained by extracting the gradient of lnpτe, maxT q against kT . To obtain

the trap concentration, we substitute τe, max and ∆Cmax into Eq. (2.2.2.4) while assuming nT p0q “ NT we arrive at

r ∆Cmax 2r r´1 NT “ ND, (2.2.3.3) Co 1 ´ r

where r “ t2 .

t1 DLTS signal (A. U.) (A. signal DLTS

140 160 180 200 220 Temperature (K)

Figure 2.7: DLTS spectra from an Er-implanted MOS capacitor. Each spectrum is t2 obtained by keeping constant while varying the values of t1 and t2. t1 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 33

2.3 Characterisation Techniques for Interface Defects

In silicon based quantum computing, devices fabricated by top-down processes are often made by implanting ions through a pre-existing gate oxide [57]. Although at ﬁrst sight this may not appear to be ideal, it is a necessity due to limitations on the thermal budget that prevent post-implantation growth of thermal oxide. Hence, it can be important to learn what the quality of the interface is in a structure that is part of a fully fabricated device such as as a MOS capacitor or in a fully fabricated device itself such as a MOSFET. The following two sections will detail two diﬀerent techniques used to study the interface states in MOS capacitors and MOSFETs, respectively.

2.3.1 Conductance Technique

One of the early methods used to study the interface quality is the capacitance technique [79]. However, it required the knowledge of the depletion layer capacitance which is diﬃcult to obtain. Instead, an equivalent parallel conductance technique was proposed, and it was shown that the measured conductance is only due to the interface, not the oxide nor the depletion region [80]. The conductance technique was developed by Nicol- lian and Goetzberger (N-G), and a comprehensive discussion of the technique can be found in Ref. [81]. Although the technique is accurate and thorough, it is however very tedious and lengthy requiring measurements at multiple frequencies and time consuming data analysis which is not practical for large numbers of samples. For our devices, we used an alternative single frequency conductance method proposed by Hill and Coleman (H-C), which is simple and fast to obtain the approximate Si mid band gap interface state density [82]. Since it is an approximation, it is less accurate than the N-G method. However, the estimation is still within an order of magnitude of the N-G value and gives a suitably useful indication of the quality of the interface. Figure 2.8(a) shows the equivalent circuit for a MOS capacitor device as utilised by Nicollian and Goetzberger in their conductance technique [83]. As noted already this technique requires conductance measurements at multipe frequencies and extensive and time consuming data analysis which is not suitable for high throughput measurement of device parameters. Figure 2.8(a) shows the simpliﬁed equivalent circuit utilised in the single-frequency H-C conductance technique [82]. The H-C method is a simple approximation of the interface state density near the mid band gap, which serves as a great alternative to the N-G method if one has many samples 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 34

Cox Cox

Cit C C Gp D Rit p

Rs Rs

(a) (b)

Figure 2.8: The equivalent circuit of the MOS capacitors measured and analysed in Chapter 4 (a), where Cox is the oxide capacitance, CD is the depletion capacitance, Cit is the interface capacitance, Rit is the majority carrier capture resistance at the interface, and Rs is the series resistance. A simpliﬁed version of the equivalent circuit (b) consists of the parallel capacitance CP and parallel conductance GP , this is the version used to derive the interface state density.

to measure. Below we will introduce the necessary expressions from the N-G method, and the results from the H-C method, detailed derivations can be found in Refs. [81] and [82], respectively.

Let Gw be the weighted conductance which is deﬁned as the measured conductance

Gm divided by the angular frequency of the applied ac voltage, i.e. Gw “ ω where Gm is the measured conductance, Gma be the weighted conductance and Cma be the measured capacitance in accumulation, i.e. Gma is Gw in accumulation. Let Rs be the series resistance, then

Gmaω Rs “ 2 2 . (2.3.1.1) pGmaωq ` pCmaωq

The series resistance can cause serious errors in extracting the interface state density [81]. A few common sources of series resistance are

1. the contact between the front needle and the gate electrode;

2. the silicon substrate;

3. the back contact to the silicon substrate; 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 35

4. an impurity between the back contact and the stage on which the sample sits.

If series resistance exists, the measured capacitance and conductance need to be cor-

rected before evaluating the interface state density. The corrected capacitance, Cc, and

conductance, Gc, can be obtained through the following

ppG ωq2 ` pCωq2qC C “ w , (2.3.1.2) c a2 ` pCωq2 ppG ωq2 ` pCωq2qa G “ w , (2.3.1.3) c ωpa2 ` pCωq2q

2 2 where a “ Gwω ´ ppGwωq ` pCωq qRs [81].

The parallel conductance, GP , is then related to the corrected capacitance and conductance according to the following

ωGc GP “ . (2.3.1.4) Gc 2 Cc 2 p Cma q ` p1 ´ Cma q

Up to this point, all the equations can be found in the N-G method [81]. In their

method, GP was obtained across a range of frequencies with the surface potential (con-

trolled by VG) as a parameter. The surface potential is deﬁned as the electric potential

at the Si/SiO2 interface. The interface state density, Dit, is then calculated from the following expression for a given surface potential.

G D “ P,max fpσ q, (2.3.1.5) it ω s where f(σs) is a function of the standard deviation, σs, of the band bending at the interface

GP at a fixed surface potential. The value of σs can be determined by using the ω vs ω plot. The non-uniformity of the band bending results from localised charges such as ions and charged interface defects randomly distributed across the interface. A detailed derivation of the conductance technique can be found in Chapter five in Ref [81]. The above steps are then repeated for different surface potentials by adjusting the applied DC bias on the

capacitor to obtain a distribution of Dit across the Si band gap at the interface. As noted the H-C technique provides a much faster method of finding a representative measure of the interface state density for restricted regions of the band gap but where the interface states still have a large effect on the conductance. Now define y as the following

2G y “ P , (2.3.1.6) qAω 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 36

then according to the H-C method, the maximum value of y is an estimation of the maximum interface state density across the band gap, i.e.

2G D “ P,max . (2.3.1.7) it qAω

This only requires one set of G-V and C-V data at one frequency, which drastically reduces the analysis time for extracting Dit. However, one does expect an underestimation 12 ´1 ´2 of Dit, but the error is less than 10% for Dit up to 1ˆ10 eV cm [82]. This is particularly useful when considering variations between large numbers of samples.

2.3.2 Charge Pumping

One of the most popular techniques to investigate the interface quality in MOSFETs is the CP method. A schematic of the CP measurement on a MOSFET is shown in Fig. 2.9. From this particular device structure, the source and drain regions (red) of the MOSFET are p-type and the substrate (blue) n-type. It also has a thin gate oxide (light yellow) and a thicker ﬁeld oxide (orange). Here, Al is used for the electrical contacts.

A pulse generator is used to attract either majority or minority carriers to the Si/SiO2 interface. DC current is measured at the back contact. The source-drain and back could be reversed biased to eliminate the geometric current (explained later), however, with suﬃcient short channel length, no reverse bias is needed. It has been found that gate pulses applied to MOSFETs can stimulate a net ﬂow of current into the substrate [84]. The net current is associated with the defects at the interface between the gate and the substrate, and it is commonly known as the charge pumping current. More details will be presented soon including a schematic illustration of a CP measurement.

The theory behind the CP current, ICP , can be explained using a p-channel MOSFET (p-type source and drain, and n-type substrate). When a negative gate pulse which is larger than the threshold voltage is applied, i.e. when the surface is inverted, the holes from the source and drain flow into the channel region. If there are surface states present, then some of the holes will be captured by the surface states, while the rest will be mobile carriers. When the pulse is turned off, and the gate returns to ground potential, the excess mobile carriers will flow back to the source and drain, but the trapped holes will remain. When the pulse is off, the excess electrons in the n-type substrate will come back to the surface, hence recombining with the holes in the surface, this gives rise to a net flow of positive charge to the substrate. If the negative pulses are repeated, then a current 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 37

Pulse generator

Current

Figure 2.9: A schematic diagram of the CP measurement on a MOSFET. This particular device has p-type source and drain regions (red), an n-type substrate (blue), a thin gate oxide (light yellow), and thicker field oxide (orange). Al is used for making the electrical contacts. A pulse generator is applied to attract either majority or minority carriers to the Si/SiO2 interface. DC current is measured at the back contact. Source-drain and back can also be reverse biased to eliminate the geometric current, however, with sufficient short channel length, no reverse bias is needed. of majority carriers from the source and drain to the substrate will be observed, which resembles a pumping process, hence it is called the charge pumping current. The brief derivation of the relevant equations will be introduced in the next section. Unless stated otherwise, all equations in the next section can be found in Ref. [85]. CP can be used to find the energy distribution of the interface states across the Si band gap. However, since we are interested in quick measurements, only the knowledge of the average interface state density, Dit, across the band gap is required. One of the ways to do CP is to measure ICP as a function of the gate pulse base level while keeping the pulse amplitude constant as proposed by Elliot [86]. ICP is related to Dit by the following equation

ICP “ f ¨ Qss 2 “ f ¨ AG ¨ q ¨ Dit ¨ ∆ψs, (2.3.2.1)

where f is the pulsing frequency, Qss is the interface state charge, AG is the channel 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 38

area of the MOSFET, q is the electron charge, and ∆ψs is the total sweep of the surface potential during the pulse.

It can be seen that, in order to ﬁnd Dit, the surface potential change needs to be calculated. However, it is not an easy task to achieve considering this needs to be done for every pulse base level change. A workaround is to design the pulse shape cleverly, so the knowledge of the surface potential change can be bypassed. Two diﬀerent pulse shapes

are shown in Fig. 2.10. Depending on the shape, Dit is calculated diﬀerently. Details of the calculations are presented towards the end of this section. Both the trapezium pulse,

Fig. 2.10(a), and the sawtooth pulse, Fig. 2.10(b), drive the MOSFET from VGL to VGH

where VGL is a voltage below the ﬂat band voltage VFB and towards accumulation, and

VGH above the threshold voltage VT and towards inversion. The pulse amplitude ∆VG

is then given by VGH -VGL. The trapezium pulse has a rise time tr and a fall time tf , α 1´α while the sawtooth pulse has a rise time f and a fall time f , where α is the fraction of the period where the gate voltage, VG, is rising, and f is the frequency of the pulse. The period during which the pulse stays at VGL is deﬁned as tL and the period during which the pulse stays at VGH is deﬁned as tH . t H VGH

VT VT

VFB V ΔVG FB

t V L GL α 1 − α tr tf f f (a) (b)

Figure 2.10: The trapezium pulse (a) with a rise time tr and a fall time tf . The sawtooth α 1´α pulse (b) with a rise time f and a fall time f , where α is the fraction of the period where VG is rising, and f is the frequency of the pulse. Both pulses drive the MOSFET from VGL to VGH where VGL is a voltage below the ﬂat band voltage VFB and towards accumulation, and VGH above the threshold voltage VT and towards inversion. ∆VG is the pulse amplitude, it is given by VGH -VGL. tL is the period during which the pulse stays at VGL and tH is the period during which the pulse stays at VGH .

The following describes what happens during one pulse cycle for a p-channel (n-type 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 39

substrate) MOSFET. The process can also be applied to n-channel MOSFETs with minor changes to majority and minority carrier descriptions. During one pulse cycle, diﬀerent

capture and emission processes take place. The pulse starts at VGL, the channel is in accumulation and the device is in equilibrium. As the pulse starts to move towards depletion, electrons will be emitted from the interface traps and ﬂow back to the substrate in order to maintain equilibrium. Initially, electron emission is able to keep up with the change of the Fermi level, this is shown in Fig. 2.11(a), where the shaded region represents the electron occupancy, the upper bound is the conduction band edge, the lower bound is the valence band edge, the line in the middle is the intrinsic electron energy level, and the

dotted red line is where the Fermi level is. However, as VG crosses the ﬂat band voltage,

VFB, the emission rate is not able to keep up anymore, this is when the emission becomes

non-equilibrium as shown in Fig. 2.11(b). Once VG reaches the threshold voltage, VT , the non-steady state emission of electrons continues, additionally, holes from the source

and drain regions will ﬂow in and be trapped at the interface. When VG ﬁnally exceeds

VT , the holes from the source and drain regions will ﬁll the remaining traps as shown in Fig. 2.11(d), and the channel will be back in equilibrium.

The channel will stay in equilibrium for a period of tH until the pulse starts to fall. A similar process begins. Initially, the holes are emitted from the traps and ﬂow back to

the source and drain regions (Fig. 2.11(e)). Once VG drops below VT , the emission of

the holes become non-steady (Fig. 2.11(f)). When VG reaches VFB, in addition to hole emissions, the electrons start to ﬂow into the channel from the substrate and are trapped

at the interface (Fig. 2.11(g)). Once VG is beyond VFB, the capture of the electrons

becomes steady state (Fig. 2.11(h)). Eventually, when VG falls back to VGL, the channel is back to equilibrium. Consideration of the details of the electron/hole capture and emission processes as described above allows Eq. 2.3.2.1 to be re-written in terms of parameters other than the

surface potential. According the nature of the charge ﬂow, ICP can be divided into two

categories. One is the net current measured at the substrate, ISUB, i.e. current due to the electrons emitted or captured at the interface, and the other one is the net current

measured at the source and drain, IS{D, i.e. current due to the holes emitted or captured at the interface. Only ISUB is of interest here, and it can be expressed as the following

2 ISUB “ ICP “ f ¨ AG ¨ q ¨ Dit ¨ p∆ψe ´ ∆ψeeq, (2.3.2.2)

where ∆ψee is the potential diﬀerence between the Fermi level at accumulation and the

lowermost-ﬁlled electron level, Eem,e, during the non-steady state electron emission, and 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 40

E (eV) 1

- - - EC - 0 - + E + F + + Ei + (d) (e) (c) (f) (b) (g) -1 EV (a) (h) Gate voltage

VFB VT VT VFB Pulse time

tr tH tf

Figure 2.11: Diﬀerent capture and emission processes happen during one pulse cycle, the shaded region represents the electron occupancy. Steady emission of the electrons from the interface traps when VG starts to rise from VGL (a). Once VG rises past VFB, the emission of the electrons become non-steady (b). When VG reaches VT , in addition to non-steady state electron emission, holes will ﬂow into the channel region from the source and drain regions and be captured. Once VG exceeds VT , the capture of the holes will become steady (d). Finally, after VG reaches VGH , the channel will stay in equilibrium for a period of tH . Once VG starts to fall, the holes will emitted to the source and drain region steadily (e). After VG falls below VT , the emission of holes will become non-steady (f), and in addition to hole emission, electrons from the substrate will become captured (g) once VG reaches VFB. Eventually, once VG drops below VFB, the no more hole emission will occur, and the capture of the electrons becomes steady (h).

∆ψe is the potential diﬀerence between the Fermi level at inversion and the uppermost-

ﬁlled hole level, Eem,h, during the non-steady state electron capture. By using a Taylor series expansion of the exponential time dependent term in Ref. [87] Eq. (31) and assuming the emission levels are situated further from the band edges than the quasi-Fermi levels, we have the following expressions

Eem,e ´ Ei “ ´kBT lnpvthσnnitem,eq, (2.3.2.3)

Eem,h ´ Ei “ kBT lnpvthσpnitem,pq, (2.3.2.4)

where kB is the Boltzmann constant, T is the temperature, vth is the thermal velocity of the carriers, ni is the intrinsic carrier concentration, σn and σp are the electron and hole 2.3. CHARACTERISATION TECHNIQUES FOR INTERFACE DEFECTS 41

capture cross sections, respectively, and tem,e and tem,p are the times of non-steady state emissions for electrons and holes, respectively.

∆ψe ´ ∆ψee can then be re-written as

qp∆ψe ´ ∆ψeeq “ pEem,e ´ Eem,hq ? “ ´2kBT ln vthni σnσp ` ln tem,etem,h . (2.3.2.5) ´ ¯ ´a ¯ Depending on the shape of the pulse, tem,e and tem,p are expressed diﬀerently. For a trapezium pulse,

For a sawtooth pulse,

|VFB ´ VT | 1 tem,e “ ¨ α, (2.3.2.8) |∆VG| f |VFB ´ VT | 1 tem,h “ ¨ p1 ´ αq. (2.3.2.9) |∆VG| f

Therefore, ICP can be re-written in terms of other known parameters without a sepa- rate measurement to extract the surface potential change during the gate voltage sweep,

? |VFB ´ VT | I “ 2qD f ¨ A ¨ kT ¨ ln v n σ σ ¨ t ¨ t , (2.3.2.10) CP it G th i n p |∆V | f r ˆ G ˙ a for a trapezium pulse, and

? |VFB ´ VT | 1 I “ 2qD f ¨ A ¨ kT ¨ ln v n σ σ ¨ αp1 ´ αq , (2.3.2.11) CP it G th i n p |∆V | f ˆ G ˙ a for a sawtooth pulse. Fig. 2.12 is a schematic illustration of a CP measurement on a p-channel (n-type

substrate) MOSFET. A sawtooth pulse’s amplitude is kept constant while varying VGL.

The corresponding ICP is recorded against each VGL value. The signiﬁcance of each pulse is as follows:

1. VFB ă VGH ,VGL: minimum current.

2. VT ă VGH ă VFB ă VGL: transition from minimum to maximum current. 2.4. CONCLUSIONS 42

3. VGH ă VT ă VFB ă VGL: maximum current.

4. VGH ă VT ă VGL ă VFB: transition from maximum to minimum current.

5. VGH ,VGL ă VT : minimum current.

ICP

ICP, max

VGL VFB VT -ΔV

(1) VFB (2) VT

VGL (3)

ΔV (4)

VGH (5)

Figure 2.12: Schematic illustration of a CP measurement on a p-channel (n-type substrate) MOSFET. A sawtooth pulse’s amplitude is kept constant while varying VGL. For each VGL value, the corresponding ICP is recorded. The signiﬁcance of each pulse is explained in the text.

ICP reaches a maximum, ICP, max, when VFB and VT are sandwiched between VGL and

VGH . Dit can then be extracted by substituting ICP, max for ICP in Eq. (2.3.2.11).

2.4 Conclusions

Three diﬀerent experimental techniques were introduced in this Chapter, they were the conductance technique, DLTS, and CP. The former two methods were used to study the 2.4. CONCLUSIONS 43 interface quality and the bulk defects in the substrate, respectively, in MOS capacitors, while the last one was employed to study the interface quality of MOSFETs. Relevant physics was also reviewed behind the three experimental techniques. The derivations of the equations served as an introduction and an overview, for full details of the derivations, readers were referred to the relevant resources. From Chapters 4 to 6, we will present how each of techniques introduced in this Chap- ter was used to study the defects in MOS capacitors and MOSFETs. Their signiﬁcance in the context of quantum computing will also be discussed wherever necessary. Chapter 3

Experimental Methods

3.1 Introduction

This Chapter presents an overview of the technical aspects of the techniques used in the experiments described in the following experimental chapters and consists of two parts. The first relates to the protocols developed to fabricate a broad range of Si devices including metal-oxide-semiconductor (MOS) capacitors, Schottky diodes and metal- oxide-semiconductor field-effect transistors (MOSFETs) as well as ion implantation into these structures. The ion implantation is used here as a step in the device fabrication or as a method to introduce different types of defects into the device for subsequent characterisation. The second part of this Chapter is on the characterisation techniques used to identify and quantify the defects introduced during fabrication and subsequent implantation. More specific technical information concerning the particular experiments will be provided in the relevant chapters.

3.2 Sample Cleaning

Single crystal ă100ą Si wafers were used for all experiments reported in this thesis. Before any oxidation, samples were degreased in acetone, isopropyl alcohol (IPA), and de-ionised (DI) water, in this order, for 5 minutes each. They were then cleaned for 10 minutes at 90 ˝C in 25 ml of piranha solution which was mixed with 20 ml of concentrated sulphuric acid (98% H2S04) and 5 ml of hydrogen peroxide (30% H202). After the piranha clean, the samples were transferred to a new beaker of DI water for 1 minute before being cleaned again in 70 ml of RCA 2 for 10 minutes at 70 ˝C. The RCA 2 solution consisted

of 50 ml of DI water, 10 ml of hydrogen peroxide (30% H202), and 10 ml of hydrochloric

44 3.3. OXIDATION AND ANNEALING 45 acid (30% HCl). The samples were placed in another beaker of DI water for 1 minute after the RCA 2 clean, before the native oxide was removed from the samples in diluted hydroﬂuoric acid (4.9% HF) for 15 seconds. The details of the cleaning process are outlined in Table 3.1.

Table 3.1: Sample cleaning steps as detailed section 3.2. Step Solution Composition Cleaning details Comments 5 min, room tem- Removes organic im- 1 Acetone - perature (RT) purities. Removes organic im- 2 IPA - 5 min, RT purities and acetone. 3 DI water - 5 min, RT Removes IPA. 20 ml 98% H SO Removes organic im- 4 Piranha 2 4 10 min, 90 ˝C 5 ml 30% H2O2 purities. 5 DI water - 1 min, RT Removes Piranha. 50 ml DI Removes metals and ˝ 6 RCA 2 10 ml 30% H2O2 10 min, 70 C creates passivating 10 ml 30% HCl layer. 7 DI water - 1 min, RT Removes RCA 2. 8 Diluted HF 4.9% HF 15 sec, RT Removes native oxide. 9 DI water - 1 min, RT Removes diluted HF.

3.3 Oxidation and Annealing

Small chips of n- and p-type silicon were cleaned according to the steps described in the previous section. After the last step of the chemical etching process (i.e. diluted HF etching), samples were immediately put on a clean piece of silicon in a quartz boat in the loading chamber of the silicon oxidation furnace housed in the Advanced Materials 3 Laboratory at the University of Melbourne in a N2 ambient flowing at about 1 cm /s. The center of the furnace is maintained at 900 ˝C or 1000 ˝C throughout the whole oxidation process for thin oxide (gate oxide) or thick oxide (field oxide) growth respectively. The 3 furnace was then flushed with O2 flowing at about 1 cm /s for 10 minutes to clear any organics that may have inadvertently entered the quartz tube. O2 was then stopped and

N2 was turned on again for 20 minutes so that the sample could be loaded in an N2 atmosphere to avoid oxidation before the sample reaches the oxidation temperature. The samples were then slowly moved into the centre of the furnace. Before the oxidation, they were left in the furnace in a N2 ambient for 5 minutes. O2 was then turned on for 3.4. ION IMPLANTATION 46

10 minutes (2 hours) for gate oxide (ﬁeld oxide) growth. After the oxidation, the samples

were annealed in a N2 ambient at the same temperature for 1 hour (2 hours) before being moved back to the loading chamber. The anneal after the oxidation was to reduce the ﬁxed oxide charge [71].

3.4 Ion Implantation

Implantation was used both in the high and low ﬂuence regimes to form metallic regions in MOSFET devices and to investigate donor qubit formation in test structures. 2 MeV Er implantations were performed on the 1.7 MV NEC tandem ion implanter (Model: 5SDH-4) at the Department of Electronic Materials Engineering at the Aus- tralian National University (ANU). A schematic diagram of the implanter is shown in Fig. 3.1. It consists of three sections. These are the beam production section, beam acceleration section, and the target chamber. All sections were under ultra-high vacuum. The ion beam was produced by a “source of negative ions by cesium sputtering” (SNICS). The Er ions were implanted into p-type MOS capacitors and p-type silicon which was used to make Schottky diodes for the deep level transient spectroscopy (DLTS) studies presented in Chapter 5. Source and drain regions of the MOSFETs were made by implanting As into p-type silicon, and B into n-type silicon. These implantations were performed on the in-house made 150 kV ion implanter at ANU. Er implantation in the channel regions was done on the same implanter. In addition to the implantation for the MOSFETs, the 150 kV ion implanter was also used for P, Er, and Bi implantations for the MOS capacitors for the interface quality studies in Chapter 4. H was implanted in p-type MOS capacitors and p-type Schottky diodes also for the DLTS studies. The implantations were done on the 5U Pelletron accelerator in the School of Physics, the University of Melbourne. 3.5. ANNEALING 47

Figure 3.1: Schematic of the 1.7 MV NEC tandem ion implanter.

3.5 Annealing

To electrically activate the implanted dopants and to investigate the evolution of implantation-induced defects during device fabrication, we used thermal annealing systems to controllably heat the samples in various ambients.

3.5.1 Metal Anneal

Devices were subject to diﬀerent anneal treatments depending on the type of device. However, all the devices that were fully fabricated (i.e. after metalisation) were annealed in the same furnace where oxidation took place in a forming gas ambient (5% H2, 95% Ar) ﬂowing at about 1 cm3/s at 400 ˝C for 30 minutes to reduce the interface state density between the metal and the semiconductor [88]. This will be referred to as the “metal anneal”. 3.6. PHOTOLITHOGRAPHY 48

3.5.2 Dopant Activation

The MOS capacitors that were used for studying the interface state density after ion implantation were annealed at 1000 ˝C for 5 seconds in an Ar ambient in the Rapid Thermal Processing System (Model: RTP-600xp at the University of Melbourne) before metalisation. After the metalisation, they went through the metal anneal.

3.5.3 Post Ion Implantation Anneal

For the MOS capacitors that were used in the DLTS experiments, they were annealed between 100 and 400 ˝C (inclusive) for 15 minutes in an Ar ambient in the same Rapid Thermal Processing System had been metalised and metal annealed prior. A summary of the anneal schemes for diﬀerent types of devices can be found in Appendix C.

3.6 Photolithography

Photolithography was used for making MOSFETs. The device structures were defined on a Quintel Mask Aligner (Model: Q4000-6) using an image reversal resist (TI 35E). The resist was chosen for its high HF resistance (no visible degradation of the resist after 10 minutes in diluted HF), as the diluted HF was used to etch back the oxide. The following describes the sequence of developing a typical pattern on a silicon sample. Samples were first cleaned as described in section 3.2 (sometimes only acetone, IPA, and DI water were used, this will be clarified later). They were then heated on a hotplate at 120 ˝C for 10 minutes to ensure no water residue remained. A SCS 8” desk-top precision spin coating system (Model: P-6708D) was used for uniformly distributing the TI 35E resist over the surface of the silicon samples. The final thickness of the resist was about 3.5 µm. The samples were then placed on the hotplate at 95 ˝C for 2 minutes before they were transferred to the mask aligner for UV exposure. A shadow mask was used to block certain parts of the samples, the blocked parts were the patterns of the devices. The samples were exposed for 13.5 seconds at about 10 mW/cm2, and then left in a dark or UV light free environment for 20 minutes. This was to let nitrogen gas formed during the UV exposure to diffuse out, this is also called outgasing. After the outgasing, the samples were placed on the hotplate at 120 ˝C for 2 minutes, this step was to reverse the solubility of the resist (i.e. the exposed parts were now insoluble in a developer, while the unexposed parts were soluble). A flood exposure followed the baking for 50 seconds (i.e. an UV exposure without a mask aligner). The samples were 3.6. PHOTOLITHOGRAPHY 49 now ready to be developed. AZ 400K (based on buffered KOH) was used in a 1:2 or 1:3 dilution for development. Developing time varied, the samples were checked every minute to avoid over-development. The samples were then hard baked on the hotplate at 140 ˝C for 2 minutes for more resistance to HF etching. They were subsequently cleaned in an oxygen plasma for 2 minutes. Both hard baking and plasma cleaning were skipped for the lift-off step. The exposure steps can be found in Appendix A. For each component of the MOSFET (i.e. the source and drain regions, the gate region, and etc.), the above steps were repeated. The blueprint of the MOSFETs is shown in Fig. 3.2. The MOSFETs are labelled with numbers 11 to 33. The regions coloured in red were implanted with either B or As. Orange regions indicate regions where the gate oxide growth took place. Green areas are where the gate oxide was etched off so metal contacts could be deposited in direct contact with the substrate. Shaded patterns represent Al contacts. The two disks and two squares at the top right corner are the MOS capacitors, they were used to extract the gate and field oxide thicknesses. The middle pattern on the right is a Van der Pauw structure. It was used to find the sheet resistivity. The strip line structure at the bottom right was used to obtain the contact resistance via the transmission line measurement method. A complete pictorial summary of the process flow can be found in Appendix B for a clearer understanding of the fabrication steps. A photo of fully fabricated MOSFETs and the test structures is shown in Fig. 3.3. As can be seen in this particular case, MOSFETs 21, 22, and 23 were bonded to the chip carrier. 3.6. PHOTOLITHOGRAPHY 50

Figure 3.2: The blueprint used for fabricating the MOSFETs. The regions coloured in red were implanted with either B or As. Orange regions indicate where the gate oxide growth took place. Green areas are where the gate oxide was etched off so metal contacts could be in direct contact with the substrate. Shaded patterns represent Al contacts. The two disks and two squares at the top right corner are the MOS capacitors, they were used to extract the gate and field oxides thickness. The middle pattern on the right is a Van der Pauw structure used to find the sheet resistivity. The strip line structure at the bottom right was used to obtain the contact resistance via the transmission line measurement method. 3.6. PHOTOLITHOGRAPHY 51

1 mm

Figure 3.3: Photo of fully fabricated MOSFETs and the test structures MOSFETs. MOS- FETs 21, 22, and 23 were bonded to the chip carrier. 3.7. DEFECT CHARACTERISATION 52

3.7 Defect Characterisation

Two types of defects were characterised in this thesis. They were interface states residing at the interface of SiO2 and Si, and the bulk traps in the Si substrate after ion implantation. For bulk traps in Si, depending on where they are in the silicon band gap, they are categorised as either shallow or deep traps. For shallow traps, luminescence has been used widely to characterise them [89]. For deep traps, several characterisation techniques exist, including thermally stimulated current (TSC) [90], thermally stimulated capacitance (TSCAP) [91], admittance spectroscopy [92], deep level transient spectroscopy (DLTS) [74], and a variation of DLTS called Laplace DLTS [93]. TSC is able to characterise conducting as well as semi-insulating substrates. However, if there is leakage current, it can interfere with the measurement, while TSCAP [94] and DLTS [95] can tolerate leakage current to a certain extent. The admittance spectroscopy method is able to resolve peaks corresponding to each trap and is independent of thermal scan rate or direction. However, it is limited to only majority carrier traps. Additionally, its sensitivity decreases as the trap energy becomes deeper. Both TSCAP and DLTS use commercial capacitance meters or bridges in addition to signal-processing functions, e.g. lock-in ampliﬁers and boxcar integrators. All of these can be easily employed in electronic laboratories. These techniques also allow the distinction between majority and minority carrier traps. However, they are unable to characterise devices with high resistivity substrates. Additionally, their time constant resolution is poor. While Laplace DLTS overcomes this resolution problem through Laplace transform [93]. The bulk traps characterised in this thesis used DLTS over other techniques for its sensitivity, the range of observable trap depths, and the spectroscopic nature. As a comparison, DLTS is able to detect trap concentrations as low as 1ˆ1012 cm´3, while TSCAP has only been demonstrated to detect traps with a concentration down to 2ˆ1014 cm´3 [74]. DLTS could be used on both MOS capacitors [96] and MOSFETs [97]. Other methods for studying interface states on a MOS capacitor include capacitance methods [79, 98, 99] and conductance methods [82, 83]. For MOSFETs, a popular method called charge pumping (CP) is described in the literature [85]. This thesis employs the single frequency conductance method developed by Hill and Coleman (H-C) [82], and CP to study the interface states in MOS capacitors and MOS- FETs respectively. The single frequency conductance method was chosen for its fast and simple approach, while the capacitance techniques require the knowledge of surface state capacitance. While the comprehensive conductance technique developed by Nicollian 3.8. EXAMPLES OF CAPACITANCE AND CONDUCTANCE CURVES FOR MOS53 and Goetzberger (N-G) [83] gives detailed information about the energy distribution of the interface states within the silicon band gap (as introduced in Chapter 2), the single frequency H-C conductance technique gives an approximation of the interface state density within the band gap over the range that is most relevant for device performance and is within 10% of the N-G value for most reasonable interface state densities. CP was adopted for measuring interface states in our MOSFETs over DLTS because it has a simpler setup and can be measured at room temperature. Additionally, CP can be combined with electrically detected magnetic resonance (EDMR) to probe the atomic origin of those interface defects [100], hence it was deemed the appropriate method for moving towards spin resonance measurements in the context of quantum computing.

3.8 Examples of Capacitance and Conductance Curves for MOS

Capacitance and conductance were measured on an Andeen-Hagerling (Model: AH2500A) 1 kHz capacitance bridge. The samples were mounted on a stage inside a breakout box as shown in Fig. 3.4. The samples were placed on an In sheet which was attached to a copper block using silver paint. The copper block sat on a piece of sapphire to ensure electrical isolation from the other parts of the stage. The front probe is made of a metal needle whose height is adjustable. The front probe holder sat on two pieces of sapphire to ensure electrical isolation. Once the sample was mounted properly, the stage was then covered to avoid the generation of a photocurrent. 3.8. EXAMPLES OF CAPACITANCE AND CONDUCTANCE CURVES FOR MOS54

Front probe

Sample stage Back contact

Figure 3.4: The stage used for the C-V and G-V measurements on the MOS capacitors (that will be discussed in more detail in Chapter 4). The samples sit on an In sheet which was attached to a copper block using silver paint. The copper block sits on a piece sapphire to ensure electrical isolation from the other parts of the stage. The front probe is made of a metal needle whose height is adjustable. The front probe holder sat on two pieces of sapphire to ensure electrical isolation. Once the sample was mounted properly, the stage was then covered to avoid the generation of a photocurrent.

The devices were biased from inversion to accumulation in steps of 0.01 or 0.02 V. The accumulation capacitance was used to find the oxide thickness and the knees of the C-V curves were used to find the flatband voltage. Combined with the conductance data, an approximation of the interface state density was obtained. A LabVIEW (2016) program was used to facilitate the data collection. Examples of a CV and a GV measurement for an n-type unimplanted Si MOS capacitor are shown in Figs. 3.5(a) and (b), respectively. From the CV and GV data, the oxide thickness, the flatband voltage, and the approximated interface state density using the H-C method for this device were found to be 22.2 nm, -0.1 V, and 1.17ˆ1010 eV´1cm´2, respectively. 3.9. DEEP LEVEL TRANSIENT SPECTROSCOPY MEASUREMENT 55

800 3

2.5

600 nS)

4 2 10

400 1.5

Capacitance (pF) Capacitance 200

0.5 Conductance ( Conductance

0 0 -2 0 2 -2 0 2 Voltage (V) Voltage (V) (a) (b)

Figure 3.5: Examples of a CV (a) and a GV (b) measurement on an n-type unimplanted Si MOS capacitor.

3.9 Deep Level Transient Spectroscopy Measurement

DLTS measurements were performed with an AC probe frequency of 1 MHz on a SULA Technologies DLTS system. Samples sit on the PCB board in the middle of a stage as shown in Fig. 3.6. Back contact is made by soldering a wire to the PCB board. The front probe holder sits on two pieces of sapphire to ensure electical isolation from the rest of the stage. A schematic diagram of the SULA stage is shown in Fig. 3.7. A double boxcar method was used in the SULA system to enhance signal averaging capability which resulted in higher signal-to-noise ratio for the detection of traps of low concentration. During the measurement, samples were mounted on a cryostat that was pumped down to 0.8 Torr. The cryostat was mounted on a liquid nitrogen (LN) dewar, and the flow of the LN was manually controlled via a pump. A LakeShore (Model: 331) Cryogenic Temperature Controller was used to control the temperature via a heater attached to the DLTS stage. A rate value of 3 K/min was used to ramp up and down the temperature. A 1-second pulse of width 40 ms and height -5 V was applied to the MOS capacitors. The Pulse base was kept at 2 V. For Schottky diodes, A 1-second pulse of width 40 ms and height -3 V was applied, the pulse base was kept at 3 V. The DLTS signals were collected in the temperature range of 84 to 250 K for the MOS capacitors and 84 to 300 K for the Schottky diodes. The reason for choosing different temperature ranges for different types of devices will be explained in chapter 5. A couple of sets of delay times (as explained in chapter 2) were chosen that were compatible with the pulse period. Background signals were taken after turning off the 3.9. DEEP LEVEL TRANSIENT SPECTROSCOPY MEASUREMENT 56

Front probe

Back contact

Sample stage

Figure 3.6: The stage used for DLTS measurements. Samples sit on the PCB board in the middle of the stage. Back contact is made by soldering a wire to the PCB board. The front probe holder sits on two pieces of sapphire to ensure electrical isolation from the rest of the stage.

Front probe Al contacts SiO PCB board 2 Si Back contact

Copper stage

Liquid N2 cooling coil

Figure 3.7: A schematic representation of the SULA stage shown in Fig. 3.6. The copper stage was cooled using liquid N2. A MOS capacitor is placed on a PCB board which sits on the copper stage. pulse, as there were non-zero correlator oﬀsets. The non-zero oﬀset was subtracted from each measurement spectrum during the data analysis so that accurate trap concentrations 3.10. CHARGE PUMPING MEASUREMENT 57

could be obtained. After the DLTS data were taken, the samples were cooled to LN temperature again. The capacitance of the samples was measured at a constant reverse bias of 2 V for MOS capacitors and 3 V for Schottky diodes for the same temperature range in their respective DLTS measurements. This capacitance was used to obtain the trap concentrations as explained in Chapter 2. The capacitance signals were processed by a National Instruments rack-mount analogue breakout accessory (Model: BNC-2090). The accessory converts analogue signals to digital signals via a National Instruments data acquisition (DAQ) board (Model: PC- LPM-16), the data were then collected by a LabVIEW (2016) program which was also used to program the LakeShore temperature controller.

3.10 Charge Pumping Measurement

CP measurements were performed using a Keithley picoammeter/voltage source (Model: 6487) and a Rigol function/arbitrary waveform generator (Model: DG4162). The samples were attached to chip carriers using silver paint. An example of a chip bonded into a chip carrier was shown in Fig. 3.3. A home-made chip carrier holder was used to house the samples. The holder is shown in Fig. 3.8. There are twenty BNC connectors (Fig. 3.8(a)) connecting the twenty pins on the chip carrier. The interior of the breakout box is shown in Fig. 3.8(b). Chip carriers were placed in the 1ˆ1 cm2 holder in the middle. Various pulse frequencies were used in CP measurements on our devices. The most commonly pulse shape was a sawtooth waveform at a frequency of 1 kHz. The pulse amplitude was ﬁxed at a value between 3 to 4.5 V depending on the threshold and ﬂatband voltage of the MOSFET. The base level of the pulse was varied from inversion to accumulation. Data were collected using a LabVIEW (2016) program. Characterisation measurements were also done on this setup as detailed in Chapter 6. 3.11. SUMMARY 58

1 cm

(a) (b)

Figure 3.8: The breakout box used for CP measurements. Top view (a) shows that there are twenty BNC connectors connecting the twenty pins on the chip carrier. Chip carriers were placed in the 1ˆ1 cm2 holder in the middle on the inside of the breakout box (b).

3.11 Summary

This Chapter detailed the fabrication processes of the MOS capacitors and MOSFETs used for this thesis. Tables of summaries of some fabrication processes can be found in Appendices A and B, respectively. Photos of the devices are shown at the relevant sections. The experimental set-ups and the methods that were used to characterise the defects in the devices were discussed. Their advantages and disadvantages were compared to other methods in the literature. The details of the results from those measurements will be presented in the following chapters. Chapter 4

Ion Implantation Through the

Si/SiO2 Interface

4.1 Introduction

For Si-based quantum computing (QC) where individual P atoms function as qubits [34], implanted atoms need to be placed close to the surface so that the overlying gates have ﬁne control over them. To achieve this, donors are implanted through the surface oxide so that any diﬀusion during oxidation processes are avoided [101]. This is particularly important for qubit device architectures that require precision placement of donor atoms such as the surface code architecture proposed by Hill et al. [48].

Such implantations through the gate SiO2 dielectric have also been considered for classical transistor devices. In this context the implants function to adjust the threshold voltage characteristics [102] or extend the source drain leads under the gate [103]. In this Chapter, we will present a systematic study of through-oxide implantation for three species of interest in QC fabrication: P, a medium-mass species that has contributed to most of the Si QC device development thus far [34, 50] and which has been at least partially studied for through-oxide implantation [104]; Er, which is not a traditional dopant in Si but is being explored for applications in Si QC and has been implanted through the oxide gate-stack into the channel of a FinFET device which demonstrated the first successful electrical readout of optically addressed individual Er atoms [57]; and Bi, which is of interest for QC applications but has not yet been addressed on an individual atom basis [68]. Although the success of FinFET devices justifies the exploration of the effect of through-oxide implantation on the oxide and oxide interface characteristics due to Er implantation, it is not clear that Bi atoms have to be implanted through the oxide.

59 4.2. BACKGROUND 60

Nonetheless, investigation of these heavy mass species in comparison to P is informative. Prior to the work presented in this Thesis it was not generally known whether Bi or Er causes irreparable damage to the Si/SiO2 interface that would be detrimental to the device operation. However, damage on device operation has been studied with other implants. For example, in MOSFETs, implanting decaborane (B10H14) can cause greater threshold voltage fluctuation [105], while implanting P and As causes severe degradation in the form of leakage current [106], and the same implants can also lead to unacceptably large diffusion of the source and drain junctions upon annealing [107]. But reports on the effects from Er and Bi are scarce, because they are not standard dopant atoms. This will be discussed further in the next section. Furthermore, the low implantation fluences often sought for qubit devices have also not been considered. In this work, P and heavy ions such as Er and Bi are implanted into Si after the oxide has been thermally grown. We find that the Si/SiO2 interface density does not change noticeably after implantation through the oxide followed by a 5-second 1000 ˝C anneal up to a fluence of 1011 ions/cm2 except for the Bi implanted p-type samples where the interface density increases with implantation fluence.

4.2 Background

Previous motivation for studying implantation through a SiO2 layer was prompted originally largely by the need to tailor and adjust the channel characteristics of MOS devices as mentioned in the previous section. Tokuyama et al. carried out a study on the

Si/SiO2 interface states induced by implantation of a range of different ions [108]. Oxides ˝ with thicknesses of 50 to 85 nm were grown on p-type Si at 1100 C in dry O2 followed ˝ ˝ by a 900 C anneal in N2. Their samples were annealed up to 900 C after implantation fluences up to 2ˆ1012 ions/cm2. They found that the number of displaced atoms affected the interface quality directly rather than the ion species. Our Si/SiO2 interface state density (Dit) measurements give us an indication of any changes in Dit as a function of species and fluence for the implantation and annealing condition used in the study: room temperature (RT) implants and 1000 ˝C, 5-second anneals. Except for Bi implanted p-type Si, Dit did not change significantly for any of the three species up to a fluence of 1011 ions{cm2. Additionally, for the n-type Si, the 1013 ions{cm2 fluence implants showed a monotonic increase in Dit with increasing damage concentration at the Si/SiO2 interface as predicted by the Stopping and Range of Ions in Matter (SRIM) [69]. The results of the simulations will be presented in the next section. For the p-type Si, there 4.2. BACKGROUND 61

was a more complicated dependence with for example P implants exhibiting a higher

increase in Dit than Er implants. The reason for this is unclear but may indicate that some other mechanism such as a chemical eﬀect could be involved but this would require further investigation for a wider range of implant species before anything deﬁnitive could be concluded.

In another study, Peterstr¨ominvestigated the Si/SiO2 interface state density due to B and P implantation both prior to the oxidation process and through the oxide layer [109]. B was implanted in p-type Si while P in n-type up to a dose of 4ˆ1012 ions/cm2. For both types, a 50 nm oxide was grown in steam at 850 ˝C followed by a 1050 ˝C anneal in ˝ N2. They were then annealed at 450 C in forming gas after the contact pad formation. They concluded that it was favorable to implant B after the oxidation process to reach the lowest number of interface traps and the opposite was true for P. Their study does

not agree with what we observed for P implanted n-type Si where the Si/SiO2 interface density decreased slightly after implanting up to 1011 P/cm2. However, an increase in

the Si/SiO2 interface state density was observed for our p-type Si after a P implantation. Peterstr¨om’sﬁnding also contrasts with the study by McCallum et al. where implanting P into n-type MOS capacitors followed by a rapid thermal anneal improved the interface

quality [104]. However, McCallum et al. only observed the effect when the initial Dit values were abnormally high. This may suggest that the introduction of defects at the interface results in a reconfiguration of the interface into a higher quality state. Otherwise, another more complex effect may be operative involving the interaction of these newly formed defects and the H that is introduced during the last step in the MOS formation process (details of which can be found in the next section) to passivate the interface states. The implant energies and doses considered in the aforementioned studies are comparable to those used in Si based QC device fabrication and those considered here. For Si QC related devices, a qubit spacing of „15 nm was initially proposed by Kane [34] for a P-based nuclear-spin quantum computer. A 15 nm spacing corresponds to a fluence of „1.5ˆ1012 cm´2. Although these qubits are likely to be strongly coupled, it is difficult to control them independently. Relaxed requirements on the qubit spacing allow the qubits to be placed 30 - 45 nm apart [48,110], this corresponds to a fluence of 1011 cm´2 which was not explored by either Tokuyama et al. or Peterström.An even more relaxed qubit spacing of ą150 nm was recently proposed by Tosi et al. [65] based on the so-called flip-flop architecture. This reduces the ion implantation dose further to 109 cm´2. This low energy and low fluence regime has never been explored in the context of investigating 4.2. BACKGROUND 62

the Si/SiO2 interface quality until now. Furthermore, for Si QC devices, it is preferable to implant after oxidation since the dopant can diffuse during this fabrication step. If implantation precedes oxidation the main concern for channel doping is that the dopant will be incorporated into the oxide or accumulate at the Si/SiO2 interface causing unpredictable device behaviour. For both Tokuyama et al. and Peterström’sstudies, the heaviest ion implanted was P. The impact of through-oxide implantation of larger ions such as Er and Bi is not known. Such ions have not been considered previously since neither are common doping impurities. Er in Si has been studied significantly for photonic applications [59–63]. However, the situation where Er is placed close to the Si/SiO2 interface does not arise in these applications. More recently, Er is being explored for applications in Si QC in a FinFET device which demonstrated the first successful electrical readout of optically addressed individual Er atoms [57] as mentioned previously. In that work, the Er ions were implanted into a fully fabricated FinFET device where the oxide and gate-stack had already been formed. Implantation was followed by an anneal designed not to compromise the device operation. Indeed, on illumination with a laser having a wavelength resonant with an Er transition, current fluctuations were observed through the source-drain current. The device survived Er implantation and annealing beyond initial expectations. Bi has a low solid solubility limit in Si of 8ˆ1017 cm´3 at 1320 ˝C (compared to P at 1.5ˆ1021 cm´3 at 1200 ˝C or B at 6ˆ1020 cm´3 at 1400 ˝C) [111]. However, the spin sublevels of the Bi system show several interesting characteristics. Firstly, Bi has a nuclear spin of 9/2 resulting in a 20-dimensional Hilbert space through the hyperfine interaction. Secondly, within a certain magnetic field range, particular spin transitions in Bi are insensitive to magnetic field fluctuations [68]. These are the so-called clock transitions which lead to drastic increase in electron spin coherence time exceeding seconds. Therefore, Si:Bi has important applications in quantum computing where long spin coherence times are desired. In addition to the lack of exploration of heavy ions, each ion species was only implanted in one type of Si in both Tokuyama et al. and Peterström’swork. In this Chapter, we

systematically investigate the change in the Si/SiO2 interface quality after implantation and annealing as a function of the implanted ion mass and its ﬂuence in both n- and p-type

Si. We ﬁnd that Dit does not change after implantation through the oxide followed by a 5-second 1000 ˝C anneal up to a ﬂuence of 1011 cm´2 except for the Bi implanted p-type

MOS capacitors where Dit increases with implantation ﬂuence. Therefore, employing the standard qubit fabrication process to these more exotic species is entirely justiﬁed as 4.3. EXPERIMENT 63

long as care is taken to limit the overlap between the Si/SiO2 interface and the dopant concentration proﬁle. SRIM simulations can be used as a guide in this instance. This study also applies to other ions of interest such as As and Sb which are expected to show similar trends.

4.3 Experiment

The Hill and Coleman (H-C) conductance method described in detail in Section 2.3.1 was used to characterise the P, Er, and Bi implanted n- and p-type MOS capacitors. n- and p-type Si x100y wafers (1-10 Ω¨cm) were cut into 1ˆ1 cm2 pieces before they were cleaned in batches including a native oxide removal followed by an immediate oxidation process. Details of the oxidation process can be found in Section 3.3. All samples were oxidised for 10 minutes except for the Bi implanted p-type samples which were oxidised for 15 minutes due to an oversight which resulted in a thicker oxide than intended. While the variation in the other samples was due to the statistical nature of the oxide growth in our furnace. After the oxide growth, they were taken to the Australian National University (ANU) for the ion implantation. Each batch contained four Si pieces, one for the control measurement, the other three went through ion implantation with ﬂuences of 109, 1011, and 1013 ions/cm2, respectively. The ion species included P, Er, and Bi. Implantation energies were chosen so that the maximum concentration was „20 nm below the Si/SiO2 interface, as for QC applications, the donor atoms need to be within suﬃcient proximity of the surface to be addressed and controlled by surface gates and therefore a depth of „20 nm or less is considered optimal [55]. Table 4.1 shows the implantation parameters obtained from SRIM simulations and oxide thickness for each sample. The details of the SRIM simulations will be presented shortly.

Table 4.1: Implantation parameters for P, Bi, and Er implanted n- and p-type Si. Projected Total Oxide Ion Substrate Ion range Straggle displacements thickness energy type species under the oxide (nm) at the interface (nm) (keV) (nm) (ˆ1017 cm´3) P31 22 30 18 19 1.3 n-type Er167 16 90 24 10 4.6 Bi209 16 90 24 8.5 5.3 P31 14 30 26 19 1.1 p-type Er167 20 90 20 10 4.9 Bi209 35 190 25 14 5.5 4.3. EXPERIMENT 64

The samples are labelled by the substrate type, the ion species, and the fluence. For example, the n-type sample implanted with 1013 P/cm2 and the n-type control sample for the P implants are referred to as n-P-13 and n-P, respectively, whereas the p-type sample implanted with 1011 Bi/cm2 is referred to as p-Bi-11. Immediately following the native oxide removal, the Si samples were placed in the waiting chamber of the Si furnace one batch at a time. They were oxidised for 10 minutes except the p-type ones that were later implanted with Bi, those were oxidised for 15 minutes. The difference in the oxide growth time was unintentional, however, Dit was not expected to be affected by the thickness. The oxide thickness ranged from 15 to 35 nm. We find that the thickness of the oxide can vary depending on its exact position in our furnace given it’s relatively high thermal gradient. That is, the resultant oxide thickness grown on two identical samples oxidised simultaneously will be slightly different. We have attempted to minimise this by at least growing samples from the same set at the same time. Simulations of the P, Er, and Bi implantations are shown in Fig. 4.1 for the n-type samples. The corresponding simulations for the p-type samples can be found in Ap- pendix D. The ion (blue curves, left-hand axes) and displacement (red curves, right-hand axes) profiles are plotted as a function of depth below the surface of the oxide. A fluence of 109 ions/cm2 is used for the simulations as an example. For other fluences, the corresponding concentrations can be scaled accordingly. 4.3. EXPERIMENT 65 ) ) -3 -3 5 7 ) 5 7 )

SiO n-type Si -3 SiO n-type Si -3 2 P 2 Er Damage 6 cm Damage 6 cm cm 17 17 cm 4 4 14 14 5 10 5 10 10 10 3 4 3 4

2 3 2 3 2 2 1 1 1 1 P concentration ( 0 0 Er concentration ( 0 0 0 10 20 30 40 50 60 70 80 90 100 Total displacements ( 0 10 20 30 40 50 60 70 80 90 100 Total displacements ( Depth (nm) Depth (nm) (a) (b) ) -3 ) 5 7

-3 SiO n-type Si 2 Bi Damage 6 cm cm 4 17 14 5 10 10 3 4

2 3 2 1 1

Bi concentration ( 0 0 0 10 20 30 40 50 60 70 80 90 100 Total displacements ( Depth (nm) (c)

Figure 4.1: SRIM simulations of the P, Er, and Bi implanted projected range (blue curves) and displacement (red curves) profiles as a function of depth. The oxide surface layer is shown in gold. The fluence used to simulate the profiles is 109 ions/cm2.

The projected range proﬁles of the ion implanted (blue curves) are all about 20 -

25 nm below the Si/SiO2 interface. For displacement profiles (red curves), in each case for a given fluence, the total displacements at the Si/SiO2 interface are predicted to be approximately a factor of 3 - 4 higher for Er and Bi than P. This reflects the higher damage density produced by the heavier ions. Noting that SRIM does not take into account the dynamics of cascade evolution with time and temperature, the actual concentration is expected to be much lower than that predicted [70]. Simulations of the p-type samples show similar characteristics to their n-type counterparts. To electrically activate the implanted dopants, samples were annealed at 1000 ˝C for 5 seconds in the Rapid Thermal Annealer. This anneal schedule has been used extensively to activate donors in qubit devices [50]. To make MOS capacitors, 200 nm Al was electron- 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 66 beam evaporated onto the samples to form the front contact pads with a diameter of „0.8 mm. A “metal anneal” was performed after the metalisation at 400 ˝C in forming gas

(5% H2, 95% Ar) for 30 minutes. InGa eutectic was applied to the back of the samples to produce an Ohmic contact. Capacitance (C-V) and conductance (G-V) measurements were made on the 1 kHz Andeen system at room temperature with an AC modulation voltage of 0.01 V which is to ensure that it is smaller than the thermal voltage, i.e. smaller than the width of the edge of the depletion region. Devices were biased from inversion to accumulation to ensure that the device was not driven into deep depletion.

4.4 Capacitance and Conductance of Implanted

Si/SiO2

This section details the C-V and G-V results for the MOS capacitors fabricated from the P, Er and Bi implanted n- and p-type Si with a surface oxide. Defects at the Si/SiO2 interface exist as a continuum of states (as detailed in section 2.1.4) so that an approximate defect density can be determined at a single energy in the band gap. In this work, the H-C method is employed. As mentioned in section 2.3.1, this technique offers a rapid assessment of the interface quality at the expense of a detailed energy dependent distribution. Results are first presented for the P implanted MOS devices. The general characteristics of the C-V and G-V curves are described. This is followed by similar data for the Er and Bi implanted MOS capacitors. Less variation in the C-V and G-V curves is observed for the n-type samples for fluences less than 1013 ions/cm2. A clear trend with fluence is identified. In the low fluence regime employed for qubit device fabrication, all devices retain relatively low defect densities except the Bi implanted p-type MOS capacitors where

Dit increases with implantation ﬂuence.

4.4.1 P implanted Si/SiO2

The capacitance results for the P implanted n- and p-type samples are shown in Fig. 4.2. The data collected from the unimplanted MOS capacitors are also shown for comparison. For the MOS capacitors implanted with ﬂuences up to 1011 P/cm2, the C-V curves show the expected shape with accumulation and inversion clearly discernible. The oxide capacitance varies slightly likely due to a change in the SiO2 dielectric constant. 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 67

800 1200 1000 600 800

400 600

n-P 400 p-P Capacitance (pF) Capacitance Capacitance (pF) Capacitance 200 n-P-9 p-P-9 n-P-11 200 p-P-11 n-P-13 p-P-13 0 0 -8 -6 -4 -2 0 2 -6 -5 -4 -3 -2 -1 0 1 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.2: The capacitance as a function of the applied voltage for the unimplanted and P implanted MOS capacitors in n-type Si (a) and p-type Si (b).

As mentioned earlier, measurements were performed from inversion to accumulation. A small measurement artifact can be observed at -3 V in the n-type samples. This small increase in capacitance signiﬁes the slow formation of an inversion layer during the course of the measurement. This is often observed and is a consequence of the recombination and generation processes at the interface.

The flat-band voltage, Vfb, defined as the point of inflection on the C-V curve, does not shift with ion fluences lower than 1013 ions/cm2 for the n-type samples, and for the p-

type samples the shift is insignificant. Vfb is determined by both the metal-semiconductor work function difference and the fixed oxide charge density. Theoretically, for an Al top contact Vfb is expected to be at -0.2 V and -0.8 V for these n- and p-type MOS capacitors, respectively (see Section 6.1.2 in Ref. [112]). For our devices, Vfb is found to be -0.1 V and -0.8 V for the n- and p-type unimplanted MOS capacitors, respectively, agreeing well with the theoretical values. For the higher 1013 P/cm2 fluence, the effect of electrically active implanted P atoms becomes clear. For n-P-13, both the inversion capacitance and Vfb increase in magnitude dramatically. The ratio between the inversion and accumulation capacitance can be related to the doping density (see Section 2.2.3 in Ref. [78]). Although this technique is not strictly appropriate for non-uniform doping profiles, the doping level changes from 1.0 ˆ 1015 to 1.6 ˆ 1018 cm´3. The latter value for n-P-13 is very close to the expected value based on Fig. 4.1 where the implanted P profile is expected to reach „2ˆ1018 cm´3 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 68 for a 1013 P/cm2 implant fluence. For p-P-13, the 1013 P/cm2 implant forms an additional junction under the oxide. The C-V curve then becomes more complicated. A portion of the curve between -4 to 2 V shows the characteristics of an n-type MOS curve. Once the bias reaches a high enough negative voltage the capacitance then becomes associated with the p-type majority carriers in the substrate. For both n-P-13 and p-P-13, the C-V curves displace a large stretch-out feature which is likely due to a high interface state density as discussed in Section 2.1.4. The corresponding parallel G-V curves are shown in Fig. 4.3. These were collected simultaneously to the C-V data (Fig. 4.2). For the n-type MOS capacitors, the expected G-V shape is observed for fluences up to 1011 P/cm2. The conductance increases in accumulation due to a small series resistance term as shown in the equivalent circuit in Fig. 2.8. This can be corrected with Eq. 2.3.1.3.

0.3 10 n-P 0.4 n-P-9

0.25 8 nS)

nS) n-P-11 5

5 n-P-13 10 10 0.2 0.2 6 0.15 0 4 -1 0 1 0.1 p-P

2 p-P-9 Conductance ( Conductance Conductance ( Conductance 0.05 p-P-11 p-P-13 0 0 -8 -6 -4 -2 0 2 -8 -6 -4 -2 0 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.3: The parallel conductance as a function of the applied voltage for the unimplanted and P implanted MOS capacitors in n-type Si (a) and p-type Si (b).

Around Vfb there is a large Gaussian peak which arises from loss by the interface states. The height of this peak can be used to estimate Dit at mid-gap. For fluences of 1011 P/cm2 and below the G-V curves show only slight differences. Again the 1013 P/cm2 implant into the n-type MOS results in a different G-V curve.

However, the interface trap peak can still be observed around Vfb at -6.5 V. The conductance in accumulation does not show any signiﬁcant series resistance. For this device the conductance has a high value in inversion. Such a signal is commonly associated with 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 69

the presence of an inversion layer formation. This could be a consequence of an increase

in the number of traps in the near Si/SiO2 region which act to generate a larger number of minority carriers. For the p-type MOS capacitors, the low ﬂuence G-V curves are again similar, however, they are not as uniform as their n-type counterparts. For p-P and p-P-9, the central peaks consist of more than one Gaussian. This behaviour may arise if the density of interface states and/or the associated defect time constants vary over the voltages of

the measurement. In extracting the Dit values from these curves (discussed below in Section 4.4.4), we have used the maximum parallel conductance value. This is found to give fairly consistent results.

4.4.2 Er implanted Si/SiO2

The capacitance results for the Er implanted n- and p-type MOS capacitors are shown in Fig. 4.4. Like the P implanted n-type MOS capacitors, the C-V curves show only slight variations with Er implantation ﬂuences up to 1011 Er/cm2. However, for the p-type MOS capacitors, this is not the case. Vfb shifts to the left by about 0.5 V for both p-Er-9 and p-Er-11 compared to p-Er.

1200 1000 n-Er 1000 n-Er-9 n-Er-11 800 800 n-Er-13 600 600 400

400 p-Er

Capacitance (pF) Capacitance Capacitance (pF) Capacitance 200 p-Er-9 200 p-Er-11 p-Er-13 0 0 -3 -2 -1 0 1 2 3 -4 -3 -2 -1 0 1 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.4: The capacitance as a function of the applied voltage for the unimplanted and Er implanted MOS capacitors in n-type Si (a) and p-type Si (b).

For both n-Er-13 and p-Er-13, Vfb shifts to the left by „1.5 V and a distortion is

observed near Vfb which is likely dominated by the damage introduced by the implant at the ﬂuence of 1013 Er/cm2 rather than an electrical eﬀect. The inversion capacitance 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 70

for these two samples is higher than the lower fluence ones, especially for p-Er-13 whose inversion capacitance has a similar magnitude as its accumulation capacitance. Addi- tionally for n-Er-13, the C-V curve displaces a large stretch-out feature towards inversion which is likely due to a high interface state density. The change in the inversion capacitance for the 1013 Er/cm2 fluence indicates a larger number of majority (minority) carriers for the n-type (p-type) MOS capacitor. This is because Er can act like a donor in Si [113], and according to the SRIM plot for Er in 13 2 Fig. 4.1, for a fluence of 10 Er/cm , the concentration for Er near the Si/SiO2 interface is „2ˆ1016 Er/cm3. According to Benton et al. [113], a concentration of 2ˆ1016 Er/cm3 corresponds to „1ˆ1016 cm´3 in the donor states which is 10 times higher than the majority carrier concentration in the unimplanted n-type Si samples („1ˆ1015 cm´3) and 2 times higher than the unimplanted p-type Si samples („5ˆ1015 cm´3). The parallel conductance results for the same Er implanted MOS capacitors are shown in Fig. 4.5. For the n-type samples, a slight variation in the G-V curves can be observed for n-Er, n-Er-9, and n-Er-11. While for n-Er-13, the peak of the conductance has increased by about 30 times compared to n-Er, and the location of the peak is consistent with the shift in Vfb.

8 8 n-Er p-Er

n-Er-9 p-Er-9 nS)

n-Er-11 nS) p-Er-11 5 6 5 6

n-Er-13 p-Er-13

10 10 0.4 4 4 0.5 0.2 2 2 0.25

0 Conductance ( Conductance -1 0 ( Conductance 0 -1 0 0 0 -3 -2 -1 0 1 2 3 -4 -3 -2 -1 0 1 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.5: The parallel conductance as a function of the applied voltage for the unimplanted and Er implanted MOS capacitors in n-type Si (a) and p-type Si (b).

For the p-type samples, the peaks of the conductance for p-Er, p-Er-9, and p-Er-11 are in the same order of magnitude, however, like the P implanted p-type devices, they are not as uniform as their n-type counterparts. More than one Gaussian can be observed 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 71

for all p-type devices. For p-Er-13, the central peak increases in magnitude by more than 12 times and shifts to the left by „1 V compared to p-Er. We propose again that the cause of multiple Gaussians in the peaks is due to the density of interface states and/or the associated defect time constants varying over the voltages of the measurement.

4.4.3 Bi implanted Si/SiO2

We now turn towards the Bi implanted MOS capacitors with the data presented in Fig. 4.6. Like the P and Er implanted n-type MOS capacitors, the C-V curves show only slight changes with Bi implant ﬂuences up to 1011 Bi/cm2. For n-Bi-13, a slight stretch- out towards accumulation and a distortion near Vfb are observed. Again, the stretch-out indicates a high interface state density while a distortion near Vfb is likely due to the damage introduced by the implant at the ﬂuence of 1013 Bi/cm2.

1200 500 n-Bi 1000 n-Bi-9 n-Bi-11 400 800 n-Bi-13 300 600 200

400 p-Bi

Capacitance (pF) Capacitance Capacitance (pF) Capacitance 100 p-Bi-9 200 p-Bi-11 p-Bi-13 0 0 -3 -2 -1 0 1 2 3 -12 -10 -8 -6 -4 -2 0 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.6: The capacitance as a function of the applied voltage for the unimplanted and Bi implanted MOS capacitors in n-type Si (a) and p-type Si (b).

For the Bi implanted p-type MOS capacitors, a fluence of 109 Bi/cm2 does not cause much variation in the C-V curve, however, after a fluence of 1011 Bi/cm2, a slight stretch- out towards inversion and a distortion near Vfb are observed. For p-Bi-13, the stretch-out moves towards accumulation and the inversion capacitance increases compared to the others. Bi is not expected to have the same level of electrical activation as P. It has been found recently that the Bi electrical activation is 46% to 64% in the low fluence regime [114]. 13 2 15 ´3 A fluence of 10 Bi/cm gives a concentration of „1ˆ10 Bi/cm near the Si/SiO2 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 72 interface according to the SRIM simulation. This results in an electrically active concentration of „5ˆ1014 Bi/cm´3 which is half of the doping concentration of the n-type materials we used, hence the inversion capacitance does not change much compared to the other fluences. However, for p-Bi-13 the doping concentration is „5ˆ1015 cm´3, the large Bi concentration allows a larger minority carriers population to form at the Si/SiO2 interface which likely contributed to the large inversion capacitance. The parallel conductance results for the Bi implanted MOS capacitors are shown in Fig. 4.7. Again, like the P and Er implanted n-type samples, a slight variation in the G-V curves is observed for fluences up to 1011 Bi/cm2. While for n-Bi-13, the peak of the conductance increases by more than 50 times and shifts to the right by „0.7 V which is consistent with the shift in Vfb.

12 n-Bi p-Bi 8

10 n-Bi-9 p-Bi-9 nS)

nS) n-Bi-11 p-Bi-11 5

5 n-Bi-13 p-Bi-13 10 10 8 6

6 0.4 4 0.4 4 0.2 0.2

0 2 Conductance ( Conductance Conductance ( Conductance 2 -1 0 0 -2 -1 0 0 0 -3 -2 -1 0 1 2 3 -12 -10 -8 -6 -4 -2 0 2 Voltage (V) Voltage (V) (a) (b)

Figure 4.7: The parallel conductance as a function of the applied voltage for the unimplanted and Bi implanted MOS capacitors in n-type Si (a) and p-type Si (b).

Compared to the n-type samples where only one peak is observed for the G-V curve, multiple peaks can be observed for the p-type samples except for p-Bi-13. This is similar to the P implanted p-type samples, hence it is likely that the interface states have a bigger dispersion in the time constant for the Bi implanted p-type samples as well except for p-Bi-13.

4.4.4 Discussion

As discussed in previous sections, the doping concentration can be quite diﬀerent at the Si/SiO2 interface after the ion implantation. However, the H-C method used to 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 73

extract the Dit values does not depend on the doping concentration, hence the variation in the doping concentration near the interface does not aﬀect our results. Figures 4.8(a) shows the interface state density extracted from the C-V and G-V data in Figs. 4.2 to 4.7. The normalised Dit values in Fig. 4.8(b) are normalised against the Dit values obtained from the corresponding unimplanted samples. The black horizontal line

corresponds to a normalised Dit value of 1. The error of the interface state density came from the measurement of the area of the metal contact according to equation (2.3.1.7) which was calculated to be less than 3%. This error is too small to be seen in the plots, hence error bars are not included.

15 6 ) 10 10 -2 n-type Bi:Si n-type Bi:Si 5 cm 14 n-type Er:Si 10 n-type Er:Si

-1 10 n-type P:Si n-type P:Si 104 1013 p-type Bi:Si p-type Bi:Si p-type Er:Si 3 p-type Er:Si 10 1012 p-type P:Si p-type P:Si 102 1011 101 10

10 100 Interface state density (eV density state Interface 109 density state interface Normalised 10-1 0 109 1011 1013 0 109 1011 1013 Fluence (ions/cm2) Fluence (ions/cm2) (a) (b)

Figure 4.8: The interface state density (a) and normalised interface state density (b) plotted on a log scale as a function of ﬂuence for the n- and p-type MOS capacitors. The normalised Dit values were normalised against Dit obtained from the corresponding unimplanted samples. The black horizontal line corresponds to a normalisd Dit value of 1.

For all the n-type samples and Er implanted p-type samples, implantation with ﬂu- 13 2 ences lower than 10 ion/cm followed by a rapid thermal anneal decreases Dit slightly

compared to the unimplanted samples. The decrease in Dit for the P implanted n-type samples contrasts with the study by Peterstr¨omwhere an increase was observed [109].

The decrease in Dit was also found in P implanted n-type MOS capacitors followed by a rapid thermal anneal when the initial Dit values are abnormally high according to Mc- Callum et al. [104]. McCallum et al. argued that a possible reason for their observed decrease in Dit was due to the bond-breaking at the Si/SiO2 interface during the implantation process, where the broken bonds caused by the implantation may somehow have a 4.4. CAPACITANCE AND CONDUCTANCE OF IMPLANTED SI/SIO2 74 diﬀerent energy conﬁguration that can be readily repaired during the post-implantation anneal. Although for our samples, the initial Dit values are all low, and the improvement in the interface quality is found in the samples implanted with much larger atomic masses too. The bond breaking explanation provided by McCallum et al. can also be employed to explain our observed decrease in Dit.

For the P implanted p-type samples, although there is an increase in Dit for fluences less than 1013 P/cm2, the increase is less than 10% compared to the unimplanted sample, hence a P implant up to 1011 P/cm2 does not decrease the interface quality to any significant extent. For the Bi implanted p-type samples, a consistent increase in Dit is observed as the fluence increases. There are two factors that could explain this. The first could be that Bi has a much larger atomic mass than P and Er as the damage in the oxide quality is correlated with the atomic mass [115]. The lateral extent of the damage produced by the ion as it traverses across the interface boundary will be different for different ions and that extent will generally be larger for the larger ions. One could consider an areal extent of the damage at the interface and an increasing probability that those damage areas will overlap as the fluence. However, atomic mass alone does not explain the increase in Dit for the Bi implanted p-type samples, as p-P-13 has a large Dit than p-Er-13. The second factor could be that it is a p-type material. As observed in the G-V curves for all p-type samples, there is more variation in the parallel conductance peaks than their n-type counterparts due to the density of interface states and/or the associated defect time constants varying over the voltages of the measurement. Having a bigger atomic mass and being implanted in p-type Si could have contributed to the observed consistent increase in Dit in the Bi implanted p-type samples. However, this needs to be confirmed with other heavy ions implanted p-type Si.

The second factor can also be observed in the P implanted samples where Dit increases by 3 orders of magnitude for p-P-13 compared to n-P-13. However, this is not observed for Er where the diﬀerence in Dit between n-Er-13 and p-Er-13 is negligible. Further investigations are needed to explore what other factors aﬀect the interface quality.

Our results, except for the Bi implanted p-type samples, demonstrate that the Si/SiO2 interface quality is relative independent of the ion species up to 1011 ions/cm2, a result that is also observed in the p-type samples studied by Tokuyama et al. [108]. For quantum computing purposes, when implantation through the oxide is necessary for precise atom placement, Dit needs to be reduced or kept as low as possible to retain proper device function and further to limit sources of decoherence. The peak concentrations for fluences of 109, 1011, 1013 ions/cm2 correspond to distances of „215, „46, 4.5. CONCLUSIONS 75 and „10 nm between the nearest qubits, respectively. As mentioned in the Background section, relaxed requirements on the qubit spacing allow the qubits to be placed 30 - 45 nm apart [48, 110]. This implies that a fluence of 1011 ions/cm2 is enough to achieve this. For this fluence, Dit either decreases or increases by no more than 10% compared to the unimplanted ones except for the Bi implanted p-type samples where Dit is one order of magnitude higher than its P and Er counterparts. This means if P and Er are used for building Si quantum computers, interface quality will not be an issue for the device performance. While operating Bi implanted p-type Si devices at a fluence 1011 Bi/cm2 or higher, the larger Dit values will likely decrease the qubit coherence time. However, as mentioned in the Background section, Bi has clock transitions which are insensitive to magnetic field fluctuations within a certain magnetic field range [68]. The increase in

Dit might not be an issue for Bi qubit operations if an appropriate magnetic ﬁeld range is chosen.

4.5 Conclusions

The eﬀect of P, Er and Bi implantation through the surface gate oxide on the subsequent MOS device operation was investigated. Dit was extracted from the C-V and

G-V measurements using the H-C method, and Vfb was extracted from the C-V measurements alone. This allowed rapid characterisation of the devices as a function of ion implant fluence and made no assumptions on the doping concentration at the Si/SiO2 interface. The energies and fluences were chosen specifically to be most relevant to QC related device fabrication where the implanted atom depth is around 20 nm, and the spacing between the atoms is nanometers apart. This is a low energy, low fluence regime and few investigations, like the studies by Tokuyama et al. [108] and Peterström[109], are present in the literature even though such implants are used in industry for threshold voltage adjustments [102]. In agreement with the findings by McCallum et al., we also observed a reduction in

Dit for P implantation in n-type Si. However, this contrasts with the study by Peterström who found an increase in Dit in his P implanted n-type samples. The interface quality was unaffected by implant fluences up to 1011 ions/cm2 except for the Bi implanted p- type samples where a consistent increase in Dit was observed for all fluences considered, a result that has also been observed by Tokuyama et al. for their p-type Si samples implanted with P and other ions with smaller masses. This work presents for the first time a systematic study of P, Er and Bi implantation 4.5. CONCLUSIONS 76

through the Si/SiO2 interface, especially in the context of building Si quantum computers where ion implantation of low fluences through the oxide is adopted. Our results showed that a fluence of 109 ions/cm2 will not adversely affect the interface quality. This fluence corresponds to a donor-donor spacing of 135-215 nm which is entirely appropriate for qubit devices based on the flip-flop architecture where donors can be placed 100-500 nm apart [65]. Furthermore, if implanting Bi in p-type materials is not necessary, then a higher fluence 1011 ions/cm2 can be used without affecting the interface quality to any significant extent. This fluence corresponds to a much reduced donor-donor spacing of 30-45 nm apart which benefits other architectures that require shorter spacings [48,110]. 4.6. FUTURE WORK 77

4.6 Future Work

In order to conﬁrm the results for the Bi implanted p-type samples, more Bi implanted p-type MOS capacitors need to be fabricated and measured to see if the same results can be reproduced.

Although the Si/SiO2 interface quality does not change significantly up to a fluence of 1011 ions/cm2, except for the Bi implanted p-type samples, the limit of fluence up to which the quality of the Si/SiO2 interface does not change is not known. Finer steps of fluence are required to probe that limit. Furthermore, as mentioned in the Background section, As and Sb are expected to show similar trends in Dit. However, for completeness, measurements on As and Sb implanted MOS samples are needed to confirm the expectation. Chapter 5

Deep Level Transient Spectroscopy Study of Defects in H- and Er-Irradiated p-Type Si

5.1 Introduction

For Si based quantum computing (QC) devices, realising long distance communication between qubits remains a challenge. The ability to allow qubits to communicate over long distances is essential to building a scalable quantum computer. This required feature has been achieved with superconducting qubits [116], trapped ions [117], and more recently quantum dots on a Si/SiGe heterostructure [118]. However, it is yet to be realised with qubits based on individual atoms in Si. Yin et al. demonstrated the first successful electrical readout of optically addressed individual Er atoms in a FinFET device [57], this provided a potential solution towards the long distance communication problem between qubits in Si based quantum computers using photons as mediators. In that work, Er was implanted into p-type channel FinFET devices. When a laser was directed onto the FinFET at a wavelength resonant with the Er transitions, an increase in the FinFET source-drain current was detected. Studies on Er implanted Si have a long history as described in the next section. 4 4 3` Briefly, the I13{2 to I15{2 optical transitions of Er are in the near-infrared where Si is transparent. This wavelength also coincides with the minimum in absorption of silica optical fibers, therefore, the initial motivation was to incorporate Er into Si to make light emitting devices. Si-based photonics would be a cost-effective alternative to the more expensive and complex integration of other light emitting components onto a Si platform.

78 5.1. INTRODUCTION 79

The Er concentrations required to achieve sufficiently intense emission are in the general range between 1016 to 1018 Er/cm3 [119,120]. Higher concentrations exceed the solubility limit of Er in Si [120, 121]. It has been found that Er can exist in a number of atomic configurations in Si [122]. Its optical activity can be enhanced by co-implantation of oxygen which increases the likelihood of Er being in a 3` charge state [120]. Importantly, since Er is a heavy ion, its implantation causes a significant level of damage in Si. Within the high implantation fluence regime, Si can be amorphorised. Defect studies are thus an important aspect of Er implanted Si studies. In quantum applications, the spin sub-levels of the Er atom are addressed through resonant excitation. However, these levels are sensitive to electric fields, local strain and presumably the atomic configuration of the Er ion within the Si lattice. Therefore, an ensemble measurement would yield a signal which is greatly broadened and the individual states would not be resolved. The FinFET device described in Ref [57] allows a single Er to be addressed. The implantation fluences employed in that work were 4 ˆ 1012 cm´2. This resulted in an average of 30 - 40 Er atoms in the FinFET channel. These fluences are much lower than those previously studied for optical communication endeavours. The damage distributions and defect concentrations are therefore expected to be very different to those studies. The process related to the excitation of a charge carrier into the Si band on resonant excitation of an Er spin sub-level may require interaction with a level within the band- gap [62,123]. It is important then to understand what kinds of defect may be present in the device and the evolution of these defect structures with post-implantation processing. Er implantation and deep level transient spectroscopy (DLTS) studies on p-type Si will be presented in the following sections. The reason for choosing p-type Si was due to the fact that the Er-implanted FinFET used to address individual Er atoms by Yin et al. had a B-doped channel. Additionally, DLTS studies of heavy ion implanted p-type Si and the evolution of defect types and defect concentrations with annealing have not been previously explored to any significant extent in the literature. To provide a point of comparison with the existing literature, companion DLTS studies were performed on light ions, H, implanted p-type Si. Significant differences were observed that are likely related to the structure and evolution of the dense damage cascades created during Er ion implantation. 5.2. BACKGROUND 80

5.2 Background

Er in Si has promising applications in optoelectronics [59–63]. Optical applications of Er:Si arise from the strong luminescence at „1.54 µm due to the intra-4f shell transitions of Er3` first explored in 1983 by Ennen et al. [58]. Er is usually implanted to high fluences in Si in order to obtain the most intense luminescence possible. For this reason, Er implantation usually surpasses the threshold for amorphisation and most studies are concerned with Er diffusion during solid phase epitaxial regrowth in the amorphous Si phase. In such cases, Er redistribution during an anneal is complex, displaying strong segregation behaviour at the crystal–amorphous (c-a) Si interface. Generally it is difficult to incorporate significant concentrations of Er into the crystal although concentrations as high as 1020 cm´3 have been reported [124]. In these studies the Er in the c-Si is assumed to have a negligible diffusion coefficient [125]. Density functional theory (DFT) calculations suggest that Er diffuses from one tetrahedral interstitial position to the next via a hexagonal interstitial state with an energy barrier of 1.9 eV [126]. The diffusion of Er depends strongly on the concentration of O traps and the strength at which it binds to them [125, 127]. Er binds strongly with O [126]. Even without a thermal anneal, a redistribution of O can be observed after Er implantation [128]. This increases the solubility limit of Er from 1014 ´ 1016 cm´3 to 1018 cm´3. Er-O clusters are then stable up to at least 1000 ˝C [120]. If there is a lack of O relative to the Er concentration, Er may precipitate into clusters [120]. Implanting high fluences of Er in Si results in amorphisation, and during thermal annealing, crystallisation occurs via solid phase epitaxy. In the low fluence regime, Er, being a heavy ion, is expected to cause dense cascades of damage around the ion track. The damage morphology and number of displacements per incident ion are markedly different to that produced by electrons or protons for energies that give rise to a similar implanted depth range as explain in Section 2.1.1. Electron and proton irradiations give rise to sparse distributions of point defects and the annealing behaviour of light ion irradiated Si can be expected to be markedly different to that of heavy ion irradiated Si where complex vacancy cluster formation has been theorised to accompany heavy ion implantation of n-type material [129–131]. The thermal stability of implantation induced defects is not as well studied in p-type Si as it is in n-type Si, and due to the relevance of Er implantation to the recent work [57], we are motivated to study the damage and annealing behaviour of Er-implanted p-type Si. It was described in Section 2.2.3 that DLTS has been used to identify and quantify electrically active defects in Si. Previous DLTS studies on p-type Si relevant to this 5.3. EXPERIMENT 81

Chapter include the early electron irradiation studies by Mooney et al. [132], neutron irradiation studies by Tokuda et al [133], and the DLTS and minority carrier transient spectroscopy studies of proton-irradiated p-type Si by Vines et al. [134]. In a study of Er-implantation induced defects in both n- and p-type Si, Benton et al. [113] reported that they were unable to observe any DLTS signals in Er-implanted p-type Si which they believed was caused by the implanted Er profile producing a buried compensation layer bending the bands in the vicinity of the impurity and preventing the free charge carriers from completely filling the traps. However, this is not consistent with the work of Kan et al. [135] or our own observations reported here. Cavallini and co-workers have also performed a series of DLTS studies on Er-doped liquid phase epitaxy grown Si where the Er has been incorporated during the growth and not by ion implantation [136–140]. None of the DLTS studies on Er-implanted p-type Si have reported on the defect evolution during thermal annealing which would give further insight into the role such defects may play in quantum devices. In this work we present a DLTS study on as-implanted and thermally annealed H and Er irradiated p-type Si and compare the defect evolution upon thermal annealing of the light and heavy ion irradiated samples. Both metal- oxide-semiconductor (MOS) and Schottky-diode structures were measured. The MOS structures are of particular relevance to work report in Ref. [57] where the Er implantation was performed through the pre-existing gate oxide into the device channel. For quantum computing applications, a low fluence channel implantation may be required after the gate oxide growth in order to limit the thermal budget [50], but for sufficiently low fluences, implantation through the gate oxide followed by thermal annealing is not found to be detrimental to the density of defect states at the Si/SiO2 interface or device performance as presented in detail in Chapter 4.

5.3 Experiment

DLTS was used to characterise H- and Er-implanted MOS capacitors. MOS capacitors were used so as to understand the FinFET situation better. For the fabrication of the ˝ MOS capacitors, an oxide was thermally grown at 900 C for 10 minutes in a dry O2 ˝ ambient on p-type x100y, 1-10 Ω¨cm, CZ-grown Si followed by a 900 C anneal in N2 ambient for one hour in order to reduce the ﬁxed oxide charge at the Si/SiO2 [71]. The resultant oxide was 23 nm thick as determined by a capacitance measurement assuming a relative SiO2 dielectric constant of 3.9 (for H-implanted MOS capacitors, they were fabricated separately at the same temperature for the same duration, but in a diﬀerent 5.3. EXPERIMENT 82

furnace, hence they have a diﬀerent oxide thickness of 30 nm. However, the rest of the fabrication steps were carried out in the same laboratory as the Er-implanted MOS capacitors). All samples were degreased before depositing circular Al electrodes on the

resultant SiO2 surface with a 0.82 mm diameter and 200 nm thickness by evaporating Al through a shadow mask using an electron beam evaporator. The pressure during evaporation was kept as low as possible („6ˆ10´6 Torr) to minimise the electron current in order to reduce damage created by this process [141]. A forming gas (Ar/H(5%)) anneal (referred to as a “metal anneal”) was then performed at 400 ˝C for 30 minutes to reduce the density of Si/SiO2 interface states [88] so that their contribution to the DLTS measurements were minimised. In order to be able to measure the defect types and concentrations in the as-implanted state in the MOS capacitors it was necessary to fabricate the Al contacts and perform the metal anneal prior to ion implantation. Hence, the Er and H implants were performed at 2.0 MeV and 600 keV, respectively, into the Si 12 ´2 9 ´2 substrate through the metal contact and SiO2 layer. Fluences of 10 cm and 10 cm were used for H and Er, respectively. Schottky diodes were also fabricated on the same p-type Si substrate by evaporating 200 nm of Al using electron beams through the same shadow mask directly onto the substrate. For the Schottky diodes, a metal anneal was not necessary, therefore the implantation preceded cleaning and metallisation. The same implantation parameters were used on these Schottky diodes as their MOS counterparts. Various post-implantation anneals were undertaken in forming gas for 15 minutes. For all devices, InGa eutectic was applied to the back of the samples to produce an Ohmic contact. Figures 5.1(a) and (b) show the range proﬁles with concentration as a function of depth simulated using the Stopping and Range of Ions in Matter (SRIM) [69] for H and Er, respectively. Implantation was done through the Al contact (grey) and the oxide

(green). The shaded region (yellow) shows the depth under the Si/SiO2 interface probed by the DLTS measurements (0.23 to 1.39 µm). The implanted H has a projected range of 8 µm, while Er has a projected range of 1 µm. No erbium diffusion was expected at the anneal temperatures considered in this work. The peak concentration was approximately 7.8 µm below the interface for H, and 300 nm for Er. Therefore, the part of the implant profiles addressed with DLTS is different. That is, only the near surface, vacancy rich region of the H implant is measured whereas the entire Er profile lies within the probed region. The simulated range and vacancy profiles for the Schottky devices are similar to their MOS counterparts (figures not shown). The depths probed in the H- and Er-implanted 5.3. EXPERIMENT 83

17 17 16 16 10 SiO Si 10 10 Al SiO Si 10 Al ) ) 2 2 -3 -3 15 15 ) 14 14 ) 10 10 -3 10 10 -3 Region Region 1013 1013 1012 1012 probed probed

1011 1011 1010 1010 Vacancies (cm Vacancies (cm H concentration (cm Er concentration (cm 109 109 108 108 0 2 4 6 8 0 0.5 1 1.5 2 Depth ( m) Depth ( m) (a) (b)

Figure 5.1: Simulated range profile of (a) H and (b) Er with concentration plotted against the left hand axis and the vacancy profile plotted against the right hand axis as a function of depth using SRIM. Implantation was done through the Al contact (grey) and the oxide (yellow). The shaded region (dark grey) shows the depth under the Al/SiO2 interface probed by the DLTS measurements (0.23 to 1.39 µm). H has a projected range of 8 µm, while Er has a projected range of 1 µm. No erbium diffusion was expected at the anneal temperatures considered in this work. The peak concentration was approximately 7.8 µm below the interface for H, and 300 nm for Er

Schottky devices were between 0.3 to 1 µm and 0.3 to 1.5 µm below the Si surface, respectively. The probe depth never reached the Si surface due to a built-in voltage at the Al/Si interface at zero bias. For the H-implanted Schottky and MOS devices, the variation in the probe depth is not significant since the range and vacancy profiles are relatively uniform in the first few microns for both types of devices. For the Er-implanted Schottky and MOS deviecs, the variation in the probe depth is „0.1 µm, and the majority of the range and vacancy profiles can be accessed in both devices. DLTS measurements were performed with an AC probe frequency of 1 MHz on a SULA Technologies DLTS system to characterise the devices in a temperature range of 80 to 250 K for the MOS capacitors and 80 to 300 K for the Schottky devices. For the MOS capacitors, transients above 200 K were found to be dominated by the formation of an inversion layer in these devices and no attempt was made to analyse the data in this range. For features that appeared near or above 200 K in the as-implanted devices, the measurement of the Schottky diodes was employed to confirm the DLTS features in this temperature range. For the MOS capacitors, a 40 ms filling pulse of -5 V in amplitude was used and the reverse bias was set at 2 V. While for the Schottky diodes, a 40 ms filling pulse of -4 V in amplitude was used and the reverse bias was set at 4 V. The SULA system outputs the value of the change in the capacitance (∆C) via a 5.4. RESULTS 84 box-car method. In these experiments, rate windows for the measurements ranged from 2.23 to 447 Hz. To characterise the MOS capacitors before the DLTS measurements, capacitance-voltage (C-V) measurements were carried out on an Andeen-Hagerling (AH 2500A) 1 kHz capacitance bridge. The results of the various measurements mentioned above will be presented in the following sections.

5.4 Results

5.4.1 Device Characterisation

The room temperature C-V curves measured from inversion to accumulation for the unimplanted, and the H as-implanted and 400 ˝C annealed MOS capacitors are shown in Fig. 5.2(a) while the C-V curves for the Er counterparts are shown in Fig. 5.2 (b). As mentioned in the previous section, the devices received a 400 ˝C anneal prior to implantation and further annealing. Also, the two sets of samples differed in oxide thickness, hence for the C-V curves of the unimplanted devices, the capacitance in the accumulation region is different. No hysteresis was observed for these capacitors which indicates an absence of mobile charge contamination in the oxide and a low interface state density. The flat-band voltage shift which depends on the metal-semiconductor work function difference and the fixed oxide charge density was determined by the point-of-inflection method [142]. The values for the flat-band voltage shifts for the unimplanted, and the H as-implanted and 400 ˝C annealed MOS capacitors are -1.2, -1.0, and -0.8 V, respectively. While the flat-band voltage shifts for the Er counterparts are -0.8, -1.0, and -0.8 V, respectively. The flat-band voltage change is not significant enough in both sets of devices, hence the same set of gate pulsing parameters was applied across all MOS capacitors. We observe that the accumulation capacitance increases appreciably during processing for the H-implanted samples while the opposite is observed for the Er-implanted ones. This change in the capacitance for the devices is most likely due to the ion implantation induced impact on the dielectric constant. The variation in the front electrode area is ruled out to be the major contributor because there was less than 5% variation in the electrode area being formed with a shadow mask, while the capacitance has increased by 60% for the H 400 ˝C annealed MOS capacitor and decreased by 20% for the Er 400 ˝C annealed MOS capacitor compared to their unimplanted counterparts. For the Er implanted devices, a similar behaviour has been observed in other systems such as 50

MeV Li implanted HfO2/Si capacitors [143]. A possible explanation is that the dielectric constant depends on the structure of the material. Ion implantation may have caused a 5.4. RESULTS 85

structural modiﬁcation in the oxide that changed the dielectric constant [144]. However, it is unclear what caused the decrease in the accumulation capacitance in the H implanted MOS capacitors. Nonetheless, the change in the accumulation capacitance did not aﬀect the DLTS analysis and the C-V curves allowed us to determine the appropriate pulsing conditions to probe the bulk defects caused by the ion implantation.

1000 800 unimplanted unimplanted as-implanted as-implanted 800 400 °C 600 400 °C 600 400

400 Capacitance (pF) Capacitance Capacitance (pF) Capacitance 200 200 H Er 0 0 -4 -3 -2 -1 0 1 2 -4 -3 -2 -1 0 1 2 Voltage (V) Voltage (V) (a) (b)

Figure 5.2: Room temperature C-V curves from inversion to accumulation for the unimplanted, and the H as-implanted and 400 ˝C annealed MOS capacitors (a) and their Er counterparts (b).

5.4.2 Defect Analysis and Discussion

As-Implanted Samples

Figures 5.3(a) and (b) show the DLTS spectra using a rate window of 44.7 Hz for the as-implanted H- and Er-irradiated p-type Si samples, respectively. The spectra for the MOS capacitors are shown in dark blue and Schottky diodes in light blue. Each DLTS feature is labelled by H, hole trap, and the trap energy with respect to the valence band edge as determined from the Arrhenius analysis of the DLTS spectra from the rate windows spanning the range 2.23 to 447 Hz (not shown). The DLTS spectra for the MOS capacitors contain contributions from the bulk traps, which appear as well-deﬁned peaks in the spectra, and a sloping continuum background due to the interface states. For the MOS capacitors there is a sharp increase in the DLTS signal for temperatures above 200 K, because capacitance transients above this temperature are dominated by minority carrier generation–recombination processes at the Si/SiO2 interface [145, 146]. 5.4. RESULTS 86

These complicate the spectra in this region. As expected, this eﬀect was not present for the Schottky diodes.

MOS H as-implanted MOS Er as-implanted Schottky Schottky H[0.35(2)] H[0.35(3)]

H[0.15(2)] DLTS signal (A.U.) signal DLTS DLTS signal (A.U.) signal DLTS H[0.19(2)] H[0.48(4)]

80 120 160 200 240 100 150 200 250 Temperature (K) Temperature (K) (a) (b)

Figure 5.3: The DLTS spectra for the as-implanted H-irradiated (a) and Er-irradiated (b) p-type Si samples. The spectra for the MOS capacitors are shown in dark blue and Schottky diodes in light blue. Each DLTS feature is labelled by H, hole trap, and the trap energy with respect to the valence band edge.

For the Schottky diode data, there are two prominent peaks at „115 K and „190 K and a less well-deﬁned feature at „240 K for both the H and Er as-implanted devices. This third peak at 240 K appears more deﬁned in the Er as-implanted device than in the H as-implanted one, hence the energy level for the third peak could only be calculated and labelled for the Er as-implanted sample. The two peaks at „115 K and „190 K are also present in the MOS capacitor data but are sitting on the sloping background. The third peak is completely hidden under the sloping background. A slight position shift to the left for the two prominent peaks is observed in the H-implanted MOS capacitor data which is due to the sloping background from the Si/SiO2 interface states of the MOS device having a greater gradient compared to the Er-implanted MOS capacitor data. Comparing to the DLTS studies of proton and electron irradiated p-type Si samples by Vines et al. [134] and following their peak assignments, the peaks in our data at „115 K,

H[0.15(2)] and H[0.19(2)], can be attributed to V2p`{0q, the positive to neutral state transition of the divacancy defect. It is worth noting that the predicted divcancy defect proﬁles simulated through SRIM are not particularly prominent, only a small fraction of the defects generated in the collision cascade end up contributing to the detected signal.

The peaks at „190 K, H[0.35(3)] and H[0.35(2)], are attributed to CiOi, the interstitial 5.4. RESULTS 87 oxygen and interstitial carbon pair. Vines et al. also observed a peak with a trap energy of

Ev `0.42 eV which would be in the region of the ill-deﬁned feature at „240 K, H[0.48(4)], in our data. However, they were not able to make a deﬁnitive statement about the likely origin of this defect. A defect with a similar energy to H[0.48(4)] has been observed in Er-doped LPE grown Si [136,138–140,147] and a peak at 240 K has also been observed in Er-implanted p-type Schottky diodes although an activation energy was not quoted [135].

One additional peak was observed by Vines et al. between the V2(+/0) and CiOi peaks with an energy level in the band-gap of Ev ` 0.30 eV. This trap was attributed to

Ci. They observed that this Ci peak disappeared after a few days of sample storage at room temperature and that the CiOi peak increased proportionally with the decrease in the Ci peak. Presumably, as our samples were stored at room temperature for a few days before the DLTS measurements, we did not observe the Ci peak in our samples.

The V2(+/0) and CiOi defects have also been observed by other authors for H- implanted p-type Si [148–152] and Er-implanted p-type Si [135] and Er-doped liquid phase epitaxy Si [138, 139]. The identifications of these defects are traced back to the work of earlier authors including Corbett, Watkins and Kimerling et al. [153–155], where electron spin resonance (ESR) was used to investigate the origins of the defects. It is interesting to point out that although H and Er are expected to have completely different damage cascades and different sections of the vacancy distribution were probed as seen in the simulations in Fig. 5.1, we observe the same stable defect features in the H and Er as-implanted samples. This points to the particular stability of these defect species in p-type Si. The peak height ratios for the two prominent defects are quite different in the Er as- implanted samples compared to the H as-implanted samples, indicating the formation of the CiOi defect dominates over the V2(+/0) defect in the heavy-ion irradiated samples. A 2´ similar effect was observed in n-type Si for the doubly charged divacancy defect (V2 ) and ´ the singly charged divacancy defect (V2 ) at around 140 K and 220 K, respectively [156]. 2´ The height of the peak corresponding to the V2 defect decreased compared to the peak ´ corresponding to the V2 defect as the mass of the implanted ion increased. However, in that work two different charge states of the same defect were being compared and they are different from the defects observed in our samples. Additionally, different depth ranges were probed in our samples as highlighted in Fig. 5.1, hence further investigation is needed to determine if the peak ratio difference in our samples is correlated with mass of the implant species or due to the range of the damage distribution probed in the measurements or both. 5.4. RESULTS 88

Although both the V2(+/0) and CiOi defects are observed in the as-implanted samples, diﬀerences in the annealing behaviour of these defects emerge when the low temperature annealing data are considered, details of which are now presented.

Annealed Samples

The DLTS spectra for the annealed devices are plotted together with those of the as- implanted devices in Fig. 5.4(a) and 5.4 for the H- and Er-implanted devices, respectively. For the H-implanted samples, only peaks for the as-implanted and 100 ˝C annealed samples are labelled. As the anneal temperature is increased the spectrum becomes much more complex. The energy levels and capture cross-sections were determined but the labels are not included here because of the large error bars associated with these values. As a result the atomic origin of these defects could not be unambiguously identified and linked with the previous literature. In any case, a qualitative description of the evolution of defects in the H-implanted p-type Si devices follows. Where possible, similar peaks observed in the literature are contrasted with these results. The H-implanted data set will be discussed first. For all defect peaks, their values and possible identifications are quoted in Table 5.1.

Table 5.1: Defect parameters for the H- and Er-implanted samples Trap from this Watkins Kimerling Identiﬁcation work (eV) [154] (eV) [155] H[0.15 - 0.19] Ev + 0.21 - V2p`{0q H[0.32 - 0.38] - Ev + 0.36 CiOi H[0.26 - 0.29] - - - H[0.23(2)] - - - H[0.17(3)] - - - 5.4. RESULTS 89

H MOS Er H[0.15(2)] H[0.35(3)] MOS H[0.35(2)] Schottky as-implanted Schottky as-implanted H[0.19(2)] H[0.48(4)] H[0.35(2)] H[0.15(2)] H[0.32(2)]

H[0.16(2)] 100 °C 100 °C H[0.34(1)] 5 H[0.18(1)] H[0.26(1)] 200 °C

200 °C H[0.33(2)] DLTS signal (A.U.) signal DLTS DLTS signal (A.U.) signal DLTS 5 H[0.23(2)] H[0.29(2)] 300 °C 300 °C H[0.26(2)] * 2 H[0.17(3)] H[0.38(3)] 5 400 °C 400 °C 50 100 150 200 250 100 150 200 250 Temperature (K) Temperature (K) (a) (b)

Figure 5.4: The DLTS spectra from the H (a) and Er (b) as-implanted MOS capacitors and the as-implanted Schottky diodes, and the MOS capacitors annealed at temperatures ranging from 100 to 400 ˝C. For the H-implanted 200 ˝C and 300 ˝C annealed samples, the vertical scale of the data has been increased by a factor of 5, and for the H-implanted 400 ˝C annealed sample, the vertical scale has been increased by a factor of 3. For the Er-implanted 400 ˝C annealed MOS capacitor, the vertical scale of the data has been increased by a factor of 5. The scaled data are also plotted alongside their original data. The peak labelled with an asterisk in the spectrum of the Er implanted 400 ˝C annealed device is suspected to be a convolution of two or more peaks and is not identiﬁable with respect to any known defect species in Si. Spectra are oﬀset vertically for clarity.

After a 200 ˝C or higher anneal all spectra of the H-implanted samples reduce sig- niﬁcantly in intensity. For clarity, these spectra are scaled and plotted together with the unscaled spectra. The scaling factors are indicated alongside the spectra. The peak

associated with the V2(+/0) defect at 115 K is eﬀectively replaced by two distinct peaks after a 200 ˝C anneal. After a 300 ˝C anneal, the two peaks are in turn replaced with a prominent peak at „115 K with one defect peak on the low temperature side and a broader feature on the high temperature side. After a 400 ˝C anneal, the prominent peak

disappears and is replaced by two smaller peaks. The CiOi defect disappears after a 200 ˝C anneal. Another defect appears after a 300 ˝C anneal at the same place where the

CiOi defect was. Its energy level is found to be Ev ` 0.28 eV, however, that cannot be reconciled with its appearance at „180 K, and given the low concentration of residual 5.4. RESULTS 90

defects and the proximity to the noise floor of the measurement, the trap energy could not be determined with confidence, hence it is not labelled. The peak at 200 K for the 400 ˝C annealed sample is also not labelled for the same reason. For the Er-implanted samples, the evolution of defects is quite different to that from the H-implanted ones. Over the temperature range of 100 to 300 ˝C, the peak correspond-

ing to the CiOi defect shifts to slightly higher temperatures and becomes narrower. There are a number of factors that may cause the difference in location. Firstly, the nature of the damage produced by heavy ion implantation, when compared to light ion irradiation, results in dense damage cascades around the ion track. This is seen in the schematic diagrams in Chapter 2 in Figs. 2.1(a) and (b). It is expected that these regions will contain significant local strain and, during thermal annealing, enhanced defect interactions as observed in heavy-ion implanted n-type Si [157]. These effects will cause inhomogeneous broadening of the defect energy level and may also introduce additional energy levels, re- ˝ spectively. After a 400 C anneal, the CiOi defect concentration diminishes significantly which is consistent with the literature that it is stable up to 400 ˝C [155]. However, this

stability of the CiOi defect is not observed in the H-implanted samples where there is ˝ ˝ little suggestion of a CiOi defect after a 200 C anneal. Although at 400 C a broad peak appears at „200 K in the DLTS spectrum for the H-implanted sample, it cannot be

identiﬁed with the CiOi defect as explained earlier. This suggests that the CiOi defect in the Er-implanted samples is much more stable over a broader annealing temperature range than for the H-implants, which is also observed for the peak corresponding to the ˝ V2p`{0q defect. Only after 300 C do the peaks present in the Er as-implanted sample completely disappear. After a 300 ˝C anneal, a defect, H[0.29(2)], appears at „150 K, and it decreases in magnitude after a 400 ˝C anneal. Given the similar peak location for H[0.26(1)] and H[0.29(2)], it is possible that these two peaks correspond to the same defect, and the same strain eﬀect which was mentioned earlier could explain this shift in location. A defect with

a similar energy level (Ev ` 0.27 eV) at „150 was observed by Khan et al. [152] in proton irradiated p-type Si where it appeared after a 225 ˝C anneal and increased in concentration to a maximum when the anneal temperature reached 350 ˝C. Benton et al. [158] also

observed a defect with a similar energy level (Ev ` 0.26 eV) at „145 K in Si-implanted p-type Si after a 150 ˝C anneal, and it decreased in concentration by a factor of „5 after a 350 ˝C anneal. Their observations would be consistent with ours if H[0.26(1)] and H[0.29(2)] are the same defect. The H[0.23(2)] defect of the Er-implanted 300 ˝C annealed sample appears over a 5.4. RESULTS 91

narrow anneal temperature window and only appears in the 300 ˝C spectrum. H[0.17(3)] ˝ of the 400 C sample has a similar activation energy to the V2p`{0q defect, however, sitting at a distinctively different temperature suggests that it is a distinct defect type. After a 300 ˝C anneal, the spectrum of the Er-implanted sample reduces significantly in intensity. For clarity, it is scaled and plotted with the original data, the scaling factor is indicated alongside the spectra. In the Er-implanted 400 ˝C annealed sample, one broad feature was not identified given that it appears to be convoluted with other peaks (marked with an asterisk in Fig. 5.4 (b)). The evolution of the defects as a function of annealing temperature is quite complex in both the H- and Er-implanted samples. It would be worthwhile exploring this further in the Schottky diode samples where there is not a contribution from the signal from the sloping continuum background due to the Si/SiO2 interface states. Furthermore, the annealing behaviour to higher temperatures is required to discover the entire defect evolution as residual defect states are still present after a 400 ˝C in both the H- and Er-implanted samples.

5.4.3 Further Discussion

The Arrhenius plots of the defect emission rate determined from the peaks corresponding to the CiOi defect near 180 K in Fig. 5.4(b) observed in the Er as-implanted and annealed p-type devices are shown in Fig. 5.5 to demonstrate that the activation energy for a particular defect can vary signiﬁcantly during annealing. For example, the eﬀective activation energy for the defect assigned to CiOi varies in a non-monotonic way between values of 0.32 - 0.38 eV above the valence band. As mentioned in the previous section this is likely due to a convolution with additional defects and/or changes in the local strain around the defect. The variation is not observed in the H-implanted samples (not shown). This is particularly prevalent in samples implanted with heavy ions where defect interactions are enhanced through the dense distribution of damage.

The concentration of the CiOi defect increases as the anneal temperature increases up to 100 ˝C for the H-implanted samples, and up to 300 ˝C for the Er-implanted samples. We propose that again the nature of the damage formed by heavy ion implantation are responsible for this diﬀerence in the annealing behaviour for the CiOi defect. Alternatively, other defect clusters with a similar energy may form and increase the apparent intensity of the CiOi defect, although there is no clear evidence of this. It quickly dissolves above 300 ˝C for the Er-implanted samples and disappears above 100 ˝C for the H-implanted samples. 5.4. RESULTS 92

as-implanted 10-2 100 °C 200 °C

) 300 °C -2 °

K -3 400 C

-1

p e 10-4

5 5.5 6 1000/T (K-1)

Figure 5.5: Arrhenius plots of the defect emission rate determined from the peaks corresponding to the CiOi defect near 180 K in Fig. 5.4(b) observed in Er as-implanted and annealed p-type devices. Solid lines are linear ﬁts from which the eﬀective activation energies are obtained.

The V2(+/0) defect is also more stable in the Er-implanted samples, it anneals out by 300 ˝C compared to 200 ˝C for the H-implanted samples where we also see defects evolve continuously for anneals above 100 ˝C. Although the eﬀective activation energies are similar between the H and Er as-implanted and 100 ˝C annealed samples, as seen in Figs. 5.4(a) and (b), respectively, the annealing kinetics of the defects for the Er- implanted samples discussed above are decidedly diﬀerent to that in the H-implanted ones. To obtain information about the peaks above 200 K and to investigate more about the

peak location shift (for example the peak corresponding to the CiOi defect), the anneal study presented in this Chapter needs to be done on the Schottky devices too in order to remove the contribution from the signal from the sloping continuum background due

to the Si/SiO2 interface states. Higher temperature anneals are also needed in order to map out the entire defect evolution against temperature, as there are still peaks present in both the H and Er DLTS spectra after a 400 ˝C anneal. The DLTS defect studies provide a baseline study that can contribute to improved understanding of Er and its annealing characteristics and evolution of its local environment in Si which can in turn contribute to the development of quantum computer related architectures that utilize Er implantation into Si. To date, the FinFETs studied for the resonant excitation have been fully fabricated which have limited the temperature of the 5.5. CONCLUSIONS 93

post-implantation activation anneal. It is known from previous studies that the optimal anneal is around 900 ˝C whereas the studies on the FinFETs employed a 700 ˝C anneal. These studies have been surprisingly successful in proof-of-principle experiments. Future devices might employ Si substrates that are doped with Er during device processing. Since the MOS structure is a common component in most fully fabricated devices, the defect studies on MOS capacitors provide important information on the possible defects that could be formed in the fully fabricated ones after ion implantation. Additionally, realising long distance communication between qubits based on individual atoms in Si is yet to be achieved. The demonstration of the first successful electrical readout of optically addressed individual Er atoms by Yin et al. [57] provided a possible solution towards the long distance communication problem between qubits using photons as mediators. Heavy ions like Er were predominantly studied in the high fluence region, we presented a low fluence study in p-type Si for the first time. Er ions cause dense cascades of damage around the ion track as shown in the schematic diagrams in Figs. 2.1(a) and (b). The dense cascades result from the formation of vacancy-interstitial pairs via nuclear stopping processes, and the damage is decidedly different to that produced by protons which form a sparse array of point defects which can also be observed in the defect evolution in the DLTS spectra in Figs. 5.4(a) and (b). As a consequence, defects formed in Er implanted Si are more thermally stable than those formed in light ion irradiated Si and may persist up to higher temperatures which may impact the operation of Er qubit devices or Er recombination kinetics.

5.5 Conclusions

H and Er implantation induced damages in p-type Si MOS capacitors and Schottky diodes were studied. Both the H and Er as-implanted samples produced the V2 and

CiOi defects. However, more CiOi defects were produced in the Er as-implanted samples than the light ion counterparts. The defects for the H-implanted samples dropped in concentration significantly after a 200 ˝C anneal, and the defects evolved continuously for ˝ anneals above 100 C. While for the Er-implanted samples, the V2 defect remained stable ˝ ˝ until after a 300 C anneal and the CiOi defect was still present after a 400 C anneal. The difference in the annealing kinetics of the defects for the Er-implanted samples and the H-implanted ones was likely due to the much denser cascades of the damage around the Er ion tracks. For the purpose of building a Si-based quantum computer, ion implantation needs 5.6. FUTURE WORK 94 to be introduced in fully fabricated devices. Studying defects on a MOS capacitor provides much insight into the possible defects in fully fabricated devices. Furthermore, although the defect types produced by Er and H implantations are the same initially, the defect evolution during the subsequent thermal annealing is markedly different for the two species.

5.6 Future Work

We have laid the ground work for further studying the defect evolution at higher temperatures to complement the efforts made to realise the long distance communications between qubits using Er atoms. The higher temperature anneals are needed to discover what defects remain after the anneals as the process related to the excitation of a charge carrier into the Si band on resonant excitation of an Er spin sub-level may require interaction with a defect level within the band-gap as mentioned in section 5.1. Given the complexity of the defect evolution as observed in the DLTS of p-type Si, it would be beneficial to attempt to perform the anneals in-situ so that the defects could be tracked in more detail. Anneals at higher temperatures require a different sample processing framework which has not been pursued in the present work. Within the annealing temperature range probed in this study, for the highest annealing temperature the residual defect states are approaching the detection limit of the measurement, hence for higher temperature anneal studies, a different methodology might be required in order to follow the evolution of defects in the low concentration regime. Additionally, the implantation parameters for H and Er should be adjusted such that they create a damage cascade much closer to the surface to eliminate the damage cascade depth as a variable. Chapter 6

Charge Pumping in Si MOSFETs: A Step Toward Developing a Sensitive Probe of Spin-Defect Interactions

6.1 Introduction

For a fully fabricated device like a Si MOSFET, defects at the Si/SiO2 interface can have great impact on the device performance. A method to study the quality of the interface of a MOSFET is called charge pumping (CP). It allows the extraction

of the average interface state density, Dit, over part of the Si band gap. CP can also be used to study the atomic origin of interface defects by combining it with electrically detected magnetic resonance (EDMR). This has been demonstrated for room temperature (RT) measurements of SiC MOSFETs [159] and has been shown to provide an improved sensitivity over the conventional EDMR method by about a factor of 1000. The same technique has also been applied to a Si MOSFET at RT [100]. Although in this case the sensitivity was not improved over the conventional EDMR method at RT, it allowed the extraction of the energy levels of the defects in the band gap which gave CP EDMR an extra advantage compared to the conventional EDMR method. Furthermore, it was shown that the sensitivity of CP EDMR on Si MOSFETs can be improved when the temperature is reduced [160]. In the context of quantum computing (QC) in Si where qubits are near the interface [55], the presence of interface defects can be expected to adversely aﬀect the qubit performance under yet to be explored conditions, a limiting factor to the operation of the qubits in terms of the decoherence time. CP and CP EDMR can oﬀer a viable pathway for studying the likely impact of interfacial defects.

95 6.2. BACKGROUND 96

Si QC devices usually operate at temperatures below 4 K [161] and in many cases signiﬁcantly below 4 K [162]. The lowest temperature at which CP EDMR has been performed to date on a Si MOSFET is 27 K [160]. In this case the limitation on the CP EDMR measurement was due to charge carrier freeze-out in the device. It may be possible to circumvent this problem through, for example, photo-generation of carriers, but before this step is taken our group needed to develop a full Si MOSFET fabrication methodology suitable for generating CP devices and to develop and explore the temperature dependent CP measurement techniques. In this chapter, we will present the successful fabrication of in-house MOSFETs which are suitable for charge pumping experiments and the corresponding CP measurements down to 80 K demonstrating its

utility for measuring Dit. Although the thickness of the field oxide for the MOSFETs was much thinner than expected which resulted in unwanted signals from the field oxide for the CP measurements, the evolution of the CP current with respect to the temperature was consistent with the literature for both the field and gate oxides. Additionally, the field oxide did not affect the classic MOSFET current-voltage (IV) characteristics which confirmed the success in the fabrication steps except the field oxide growth.

6.2 Background

The conductance technique used in Chapter 4 to study the interface quality only works on MOS capacitors. It is possible to fabricate test structures like a MOS capacitor alongside the actual devices as we have done here for the MOSFETs presented in this Chapter (see Fig. 3.2). However, even if the MOS capacitors and the MOSFETs were fabricated on the same wafer, the measured Dit from the two types of devices, MOS capacitor versus MOSFET, might have diﬀerent values due to the processing steps applied to each type of device and also other factors such as diﬀerences in geometry and interactions with/proximity to other device elements such as source-drain contacts. Hence,

Dit extracted from a MOS capacitor can only be used as an indicative measure of what might be expected for the MOSFET. Therefore, it is desirable to be able to measure Dit directly in a device where the interface state quality is crucial for the device’s function such as in qubit manipulations in Si QC devices. Another technique that has been used to study the interface on a MOSFET is the deep level transient spectroscopy (DLTS) method [97]. Compared to CP, it is not as straightforward to apply DLTS to the fully fabricated MOSFET structure. DLTS requires a high-quality averager to detect the small capacitance transients and the analysis is rather complex. Hence, CP has been a more 6.3. DEVICE FABRICATION 97

appropriate tool to study the interface quality of a MOSFET because of its relative ease of setup and straightforward analysis. Current Si QC architectures involving ion implanted qubits require the qubits to reside within 20 nm or so [55] of a high quality oxide interface and it is important to be able to study the quality of the interface and the local environment in which the qubits will reside under the processing conditions that are used to produce the qubit

devices. EDMR has been used to probe the atomic origin of the defects at the Si/SiO2 interface [163, 164]. CP EDMR was not shown to provide improved sensitivity over conventional EDMR [100] for Si MOSFET devices, however, these measurements were performed on different devices with different setups in two different laboratories while the measurements on SiC devices that showed a ˆ1000 improvement in sensitivity were performed on the same devices in one laboratory [159], so a better comparison for the Si MOSFET devices would also be to perform the two types of measurements on the same device. Also, it was estimated that by utilising a high frequency above 1 GHz, detection of individual charges and spins in a small channel region „ 100 nm2 would become possible [100] and this would be of benefit for developments in QC where probing the environments of individual impurities/qubits is important. The sensitivity can be further improved by reducing the temperature in order to increase the spin polarisation [160]. Our success in the fabrication of in-house MOSFETs and the subsequent CP measurements down to 80 K (details will be presented in the upcoming sections) provide a suitable avenue for the direct comparison measurements. Furthermore, our results move us closer to extending CP measurements to low temperatures which will be the first step towards exploring CP EDMR in the temperature range in which QC devices operate. Ultimately, we want to explore the possibility of extending CP EDMR to identifying and quantifying other spin-defect interactions which will contribute to QC technologies.

6.3 Device Fabrication

Both n- and p-channel MOSFETs were fabricated. However, only the p-channel devices were characterised due to time constraints. Hence, only the fabrication steps for the p-channel devices will be presented here (fabrication steps for both n- and p-channel MOSFETs can be found in Appendix B). It is worth noting that this was the ﬁrst time that MOSFETs were fully fabricated at The School of Physics, University of Melbourne, and that all of the processing steps were developed and tested in-house. This achievement marked the possibility of fabricating other device types using the critical steps employed 6.3. DEVICE FABRICATION 98

in fabricating the MOSFETs such as the good quality oxide growth and the optimised application of etch-resistant photoresist. A brief summary of the fabrication steps will be introduced here. An n-type Si wafer (1 - 10 Ω¨cm) was cut into 1ˆ1 cm2 pieces. After degreasing and cleaning the pieces with the appropriate chemical solutions, they were immediately put in a Si furnace for a field oxide growth. The role of the field oxide was to isolate different devices on the same chip and to isolate device components such as the gate lead extensions from affecting the device characteristics. The target field oxide thickness was 150 nm but through some unidentified processing error the measured oxide thickness was 65 nm. As discussed in subsequent sections this led to unwanted features in the CP data but did not prevent the devices from performing as MOSFETs. The source and drain, and the gate regions were patterned using both photolithography and HF etching. The samples were then covered with a layer of photoresist except the source and drain regions for ion implantation. The samples were implanted with 2.5ˆ1015 Si/cm2 at 16 keV followed by 1.7ˆ1015 B/cm2 at 6 keV. The Si implantation was used to amorphise the source-drain regions prior to B implantation to prevent channeling implantation of B. The simulation of the B implantation profile using the Stopping and Range of Ions in Matter (SRIM) [69] is shown in Fig. 6.1. According to the simulation, the peak concentration for B was „25 nm beneath the sample surface after the implantation.

This was chosen so that after consuming „10 nm of Si for a target 20 nm SiO2 growth for the gate oxide, the B concentration in the near-surface region would be high enough to form a reliable ohmic contact with Al. The inset shows that the as-implanted B concentration is expected to fall below 1016 cm´3 at „ 90 nm beneath the original surface. The substrate doping concentration was around 5 ˆ 1015 P/cm3, therefore a pn junction would be formed at around 90 nm beneath the surface. After the gate oxide growth, this value became „ 80 nm which was used as the depth of the source and drain regions for calculating the source-drain region resistivity using the van der Pauw Measurement. It is noted that this is only approximate because the actual post-oxide growth B-proﬁle was not measured. After having the photoresist removed, half of the samples were then implanted with 11 2 12 1ˆ10 ErO/cm at 56 keV followed by 1.3ˆ10 O2 at 10 keV. The implantation of Er was for future investigations of possible spin interactions between the Er ions and the defects at the Si/SiO2. The addition of O2 was for maximising the optical activation of the Er ions in Si [119, 165]. The optical properties of Er allow its spin properties to be measured electrically [57]. ErO implantation was done globally, but it was not expected 6.3. DEVICE FABRICATION 99

to affect the function of the source and drain elements considering the concentration of B was orders of magnitude higher. This was confirmed later with the van der Pauw and transmission line measurements presented in the following sections. „20 nm gate oxide ˝ was then grown in a dry O2 ambient at 900 C for 10 minutes immediately after the samples were degreased and cleaned. After the gate oxide growth, the samples were left ˝ in the furnace in N2 ambient at 900 C for one hour. This was to reduce the fixed oxide charge at the Si/SiO2 [71], and it also helped recrystallise the source and drain regions in order to electrically activate B for the ohmic contact formation. A small area was then patterned on top of the source and drain for HF removal of the oxide. This was to allow a direct contact between the Al metal and the source and drain regions. A final photolithography step was performed to expose the source and drain, and gate regions upon which Al was deposited using electron beam evaporation. After the Al metalisation, ˝ the samples were annealed in forming gas (5% H2, 95% Ar) at 400 C for 30 minutes which

ensured the formation of the ohmic contacts and the reduction of Si/SiO2 interface traps in the channel region. The back contacts were formed by using InGa eutectic. 6.4. MOSFET CHARACTERISATION 100

5 B, 6 keV

4.5 ) 3 4 10-3

B/cm 3.5 2 20 3 1.5 10 1 2.5 0.5 2 0 1.5 80 85 90 95

1 Concentration ( Concentration 0.5 0 0 10 20 30 40 50 60 70 80 90 100 Depth (nm)

Figure 6.1: SRIM simulation of B in Si. The peak concentration is „25 nm under the surface for the chosen implantation energy which ensured that after consuming „10 nm of Si for growing 20 nm SiO2, the B concentration in the near-surface region would be high enough to form a reliable ohmic contact with Al. The inset shows that the concentration of B drops to below 1016 cm´3 at „ 90 nm below the surface. The substrate doping concentration was around 5 ˆ 1015 P/cm3, therefore the pn junction was estimated to form „ 90 nm below the surface. After the gate oxide growth, this value became „ 80 nm which was used as the depth of the source and drain regions for calculating the source-drain region resistivity using the van der Pauw Measurement.

6.4 MOSFET Characterisation

As mentioned in Chapter 3, three types of test structures were include on the chips alongside the MOSFETs. They were MOS capacitors, a van der Pauw structure, and a strip line structure. The MOS capacitors were used to ﬁnd the oxide thickness from the C-V measurements and the interface state density from the Hill and Coleman (H-C) conductance method. The interface state density extracted using the H-C conductance method was compared to the value extracted using the CP method on the MOSFET to demonstrate the consistency of the two methods (results are shown in section 6.5). The following two sections will present the van der Pauw and the transmission line measurements in detail. 6.4. MOSFET CHARACTERISATION 101

6.4.1 Van der Pauw Measurement

A Keithley Switch (Model: 7001) was used to perform the van der Pauw (vdP) measurements in order to test the resistivity of the implanted source and drain regions. Schematic examples of the arrangement can be found in Appendix F. The resistivity is calculated to be ρ “ 1.63p3q ˆ 10´3 Ω¨cm. This resistivity translates to „7.05ˆ1019 B/cm3 which is „6.5 times lower than the simulated peak concentration of B in Fig. 6.1. Under the oxide growth conditions described in previous Section, the active B concentration would be expected to approach the equilibrium solubility of B in Si at 900 ˝C which is 1ˆ2020cm´3 [166] and this is expected to have contributed to the difference between the implanted and active concentrations. The resistivity of the MOSFETs implanted with both B and ErO is also extracted this way and found to agree with the control sample within error. This confirms our expectation that the implantation of ErO did not affect the resistivity in the source and drain regions which was also confirmed by the transmission line measurement (TLM) on the stripline structure. The results can be found in Appendix F.

6.4.2 Transmission Line Measurement

For the transmission line measurement (TLM) on the strip line structure, the resistance between the adjacent contacts was obtained by applying a range of voltages across the two contacts and measuring the corresponding range of currents. The same measurement was repeated between all adjacent contacts, and the resistance is plotted against the distance between the corresponding contacts which can be found in Appendix F. From the TLM, the values for the resistivity (ρc), contact resistance (Rc), transfer length (LT ), and sheet resistance (Rs) for the control sample are obtained. Compared with the values obtained from the sample implanted with both B and ErO, they agree well within error, conﬁrming our expectation once again that the implantation of ErO did not aﬀect the ohmic contact formation for the source and drain regions.

6.4.3 IV Characteristics

Before the CP measurements, the IV characteristics of the control p-channel MOS- FETs were obtained. The MOSFET used for the measurements was labelled 11 in Fig. 3.2. It had a channel width of 41 µm and length of 13 µm. A range of voltages was applied between the source and drain for a ﬁxed gate voltage, VG, and the corresponding range of currents was recorded. The same range of voltages was applied for a few diﬀerent 6.4. MOSFET CHARACTERISATION 102

VG values, and the corresponding range of currents was recorded again. The results are shown in Fig. 6.2 for the RT measurement of the control device. It is worth noting here that although the ﬁeld oxide was much thinner than expected which aﬀected the CP measurements, the classic MOSFET IV characteristics are observed, i.e. the source-drain

current, (ISD), increases as VG decreases for the p-channel MOSFET, and ISD approaches saturation as the source-drain voltage, VSD, approaches VG. This highlights the difference between the two measurements, as the IV measurements are parallel to the channel region while the CP measurements are perpendicular to the channel region. The IV characteristics for the device with the same geometry implanted with both B and ErO show identical behaviours, again confirming that the incorporation of ErO did not affect the device characteristics. These values are used to extract the threshold voltage, VT , and the subthreshold swing, S.

-0.05

-0.1

-0.15 V = 0 V G -0.2 V = -1.5 V G V = -2 V G Source-drain current (mA) current Source-drain -0.25 V = -2.5 V G RT control V = -3 V G -0.3 -3 -2.5 -2 -1.5 -1 -0.5 0 Source-drain voltage (V) Figure 6.2: IV characteristics of the control p-channel MOSFET. Although the field oxide was much thinner than expected which affected the CP measurements, the RT IV curves are unaffected showing the classic characteristics of a p-channel MOSFET, i.e. ISD increases as VG decreases for the p-channel MOSFET, and ISD approaches saturation as VSD approaches VG.

The square root of the magnitude of ISD is plotted against VG while ISD is in saturation as shown in Fig. 6.3. The saturation was achieved by keeping VSD at -2.5 V. A linear fit is applied to the most linear region of the data. VT is obtained from the x-intercept of the linear fit which gives a value of -1.08 V as shown in the same figure.

S is normally obtained by plotting ISD against VG on a log scale [112]. The inverse 6.4. MOSFET CHARACTERISATION 103

0.02 Data

Fitted line )

1/2 0.015 V = -2.5 V

(A SD

1/2 V = -1.08 V T

0.01

0.005 Source-drain current Source-drain RT control 0 -3 -2.5 -2 -1.5 -1 -0.5 0 Gate voltage (V)

Figure 6.3: The square root of ISD against VG (blue). A linear ﬁt (red) was applied to the most linear region of the data. VT was obtained from the x-intercept of the linear ﬁt. VT increased in magnitude for the measurement at LNT (not shown here). This is consistent with the semiconductor thermodynamics as the temperature is lowered.

of the slope of the linear region gives the value for S, i.e.

1 log I “ V ` b, (6.4.3.1) 10 SD S G

1 where b is a constant. Multiplying both sides by 2 we get

1 1 1 log I “ V ` b, 2 10 SD 2S G 2 1 ùñ log I1{2 “ V ` b1. (6.4.3.2) 10 SD 2S G

From the equation above we can see that the magnitude of S can also be obtained by

plotting the square root of the magnitude of ISD against VG on a log scale as shown in Fig. 6.4. We obtain an S value of „77 mV/decade which falls within the typical range of 70

to 100 mV/decade for a MOSFET at RT [112]. The magnitudes of VT and S are also

extracted at liquid nitrogen temperature (LNT). VT is found to be greater than its RT counterpart while S is smaller which is consistent with the semiconductor thermodynam-

ics as the temperature decreased [78]. These values of VT and S demonstrate that our MOSFETs are fully functioning. 6.5. CHARGE PUMPING MEASUREMENT 104

10-1 Data Fitted line ) -2

1/2 10

(A V = -2.5 V SD 1/2 S = 77 mV/dec 10-3

10-4

10-5 Source-drain current Source-drain RT control 10-6 -3 -2.5 -2 -1.5 -1 -0.5 0 Gate voltage (V)

Figure 6.4: The square root of the magnitude of ISD against VG (blue) on a log scale. A linear ﬁt (red) was applied to the most linear region of the data. S was obtained from the gradient of the linear ﬁt. S lowered in magnitude for the measurement at LNT (not shown here). This is consistent with the semiconductor thermodynamics as the temperature is lowered.

The sample implanted with both B and ErO have the same VT and S values as its control counterpart, demonstrating that the implantation of ErO did not aﬀect the device characteristics.

6.5 Charge Pumping Measurement

The physics of CP was introduced in Chapter 2. The idea is to apply a pulse that drives the substrate of a MOSFET from accumulation towards inversion while grounding or reverse biasing the source and drain regions and recording the resultant substrate

current. By recording the maximum current value, Dit can be obtained. Although it is also possible to map the distribution of the interface states in the band gap with CP, this level of detail is not required in this preliminary exploration and hence obtaining only

Dit will suﬃce. The measurement setup was introduced in Chapter 3. Sawtooth pulses with a pulse amplitude (∆V ) of -3.5 V were applied to the control p-channel MOSFET of which the IV

characteristics were shown in Fig. 6.2. The CP current, ICP , against the sawtooth pulse

base level, Vbase, is shown in the top half of Fig. 6.5. The ICP curve shows two plateaus 6.5. CHARGE PUMPING MEASUREMENT 105 with the lower magnitude one highlighted in the inset. According to CP theory for a p- channel MOSFET, ICP would reach a maximum when Vbase reaches the diﬀerence between

VT and ∆V . From the IV measurements as mentioned in the previous section, VT “ -1.08 V, and ∆V “ -3.5 V, therefore the difference between the two is 2.42 V. Looking at the inset of Fig. 6.5, the lower plateau starts to form at Vbase “„2.5 V, hence it is identified as the desired ICP maximum signal for the device channel. The higher magnitude one is believed to be due to ICP from the interface between the substrate and the field oxide. Further investigations are needed to verify the origin of the higher plateau. The bottom half of Fig. 6.5 shows the schematic illustration of the CP measurement method where each pulse corresponds to the Vbase value directly above (indicated by the red arrows) and covers a specific region in the Si band gap. Vfb and VT in blue correspond to the flat-band and threshold voltages of the gate oxide, respectively, while Vfb and VT correspond to the flat-band and threshold voltages of the field oxide, respectively. The significance of each pulse is as follows:

1. Vfb (blue) ă Vtop, Vbase: minimum current.

2. VT (blue) ă Vtop ă Vfb (blue) ă Vbase: rising edge of the lower plateau.

3. Vtop ă VT (blue) ă Vfb (blue) ă Vbase: lower plateau.

4. VT (green) ă Vtop ă Vfb (green) ă Vbase: rising edge of the higher plateau.

5. Vtop ă VT (green) ă Vfb (green) ă Vbase: higher plateau.

6. Vtop ă VT (green) ă Vbase ă Vfb (green): falling edge of the higher plateau.

7. Vtop, Vbase ă VT (green): minimum current. 6.5. CHARGE PUMPING MEASUREMENT 106

(1) Vfb V (2) T (3) Vfb

(4) V T (5) Vbase (6) ΔV

Vtop (7)

Figure 6.5: ICP against Vbase is shown in the top half. The ICP curve shows two plateaus with the lower one highlighted in the inset. The lower plateau is identified as the desired ICP maximum as it starts to form at Vbase “„2.5 V which is the difference between VT of the gate oxide and ∆V . The higher plateau is believed to be due to ICP from the interface between the substrate and the field oxide. Further investigations are needed to verify the origin of the higher plateau. Schematic illustration of the CP measurement method is shown in the bottom half. Each pulse corresponds to the Vbase value directly above and covers a specific region in the Si band gap across both gate and field oxides as indicated by the red arrows. Vfb and VT in blue correspond to the flat-band and threshold voltages of the gate oxide, respectively, while Vfb and VT correspond to the flat-band and threshold voltages of the field oxide, respectively. The significance of the seven pulses is explained in the text. 6.5. CHARGE PUMPING MEASUREMENT 107

We identify the higher plateau as arising from an ICP signal from the interface between the substrate and the ﬁeld oxide. This is based on several observations. Firstly, according

to CP theory, ICP drops sharply from a maximum to 0 when Vbase reaches the ﬂat-band

voltage, Vfb. For the second plateau, ICP starts to drop oﬀ near Vbase “ -1.5 V which is

close to Vfb for the field oxide („-1.6 V). The field oxide thickness of „65 nm being much smaller than the desired value of „150 nm is expected to give rise to a larger electric field at the field oxide interface under the gate extension resulting in a charge concentration outside the geometric channel region that also contributes to a CP signal. The schematic diagram of the MOSFET used for the CP measurements is shown Fig. 6.6(a) and the top view of the MOSFET is shown in (b). Approximately „96% of the surface area of the

gate electrode is on top of the ﬁeld oxide. Since ICP is directly proportional to the area of the gate, and this region constitutes a signiﬁcantly larger area than the channel, we

measure a larger ICP .

Source Drain Gate 100 μm Field Field Gate oxide Gate oxide oxide p+ p+

n-Si Source Drain InGa

(a) (b)

Figure 6.6: Schematic diagram of the MOSFET (a) and top view of the MOSFET (b). Approximately „96% of the surface area of the gate electrode is on top of the ﬁeld oxide. Since ICP is directly proportional to the area of the gate, and this region constitutes a signiﬁcantly larger area than the channel, we measure a larger ICP .

An example illustrating a convolution of two CP signals is shown in Fig. 6.7. If the desired signal 1 (blue) is much smaller than the undesired signal 2 (orange), then the resulting signal (green) will be dominated by the undesired signal. Although this explanation does match the observed CP current, further quantitative investigations are needed to conﬁrm this, for example repeating the measurements on a MOSFET with a much thicker ﬁeld oxide. 6.5. CHARGE PUMPING MEASUREMENT 108

Signal 1+2 Signal 1 Signal 2 Charge pumping signal (A.U.)

Pulse base level (A.U.) Figure 6.7: Schematic example illustrating how the measured CP signal could have two plateaus, where the resulting signal (green) is a convolution of the desired signal 1 (blue) and the undesired signal 2 (orange).

Despite this undesirable contribution from the region outside the channel the two

signals are distinguishable and it is possible to extract Dit values for both the channel

and for the region under the gate lead. To extract Dit from ICP , we need to revisit Eq. 2.3.2.11 in Chapter 2. For a sawtooth pulse shape,

? |VFB ´ VT | 1 I “ 2qD fA kT ln v n σ σ αp1 ´ αq . CP it G th i n p |∆V | f ˆ G ˙ a 7 At RT, vth “ 10 cm/s for electrons (for p-channel MOSFETs, the majority carriers in 9 ´3 16 2 the substrate are electrons), ni “ 9.65 ˆ 10 cm , σn,p “ 4.4 ˆ 10 cm [85]. For our

p-channel MOSFET, the maximum ICP from the lower plateau is 0.045 nA, f “ 1 kHz, 2 AG “ 41 ˆ 13 µm , VFB “ 0 V, VT “-1.08 V, ∆VG “ 3.5 V, and α “ 0.5. Using these 10 ´2 ´1 values, Dit for the device channel is found to be 1.52 ˆ 10 cm eV . Using the H-C conductance technique on one of the gate oxide MOS capacitor test structures fabricated 10 ´2 ´1 alongside the p-channel MOSFET, we obtain a Dit value of 1.26 ˆ 10 cm eV . These two values agree well with each other demonstrating the consistency between the two

methods. A similar Dit value is also observed in the ErO implanted devices demonstrating that the ErO implantation did not aﬀect the interface state quality.

The higher plateau current is also used to estimate Dit at the ﬁeld oxide interface. In making the gate contact for the MOSFET, „ 200ˆ200µm2 Al was deposited on top of the 6.5. CHARGE PUMPING MEASUREMENT 109

field oxide which is used as an approximation for the effective area for this parallel device. 9 ´2 ´1 We obtain a Dit value of 4.11 ˆ 10 cm eV which is in the same order of magnitude as Dit measured using the H-C conductance method on the field oxide MOS capacitor. ˝ ˝ The decrease in Dit is likely because the field oxide was grown at 1000 C, 100 C higher than the temperature at which the gate oxide was grown, as higher temperature oxide growth was found to reduce Dit in MOS capacitors [167].

ICP against Vbase is also recorded with the temperature as a parameter for the control p-channel MOSFET. The temperature was lowered from 300 to 80 K in steps of 5 K. A subset of the data is shown in Fig. 6.8 with larger temperature steps (20 K) for clarity of presentation. As seen in the ﬁgure, the magnitude of the two plateaus increases as the temperature decreases to LNT. For the second plateau, it also becomes narrower as the temperature decreases. This behaviour was also observed by Van den Bosch et al. [168] where they found that ICP increased linearly as the temperature decreased from 350 to

100 K which matched the calculated values well demonstrating that Dit stayed more or less constant across the temperature range. The linearity is also observed in our MOSFET below a temperature of „200 K. Details will be presented shortly. 2 80 K Pulse amplitude = -3.5 V 100 K 120 K 0.15 140 K 1.5 160 K 180 K 200 K 0.1 220 K 1 240 K 260 K 0.05 280 K 300 K 0.5 0 Charge pumping current (nA) current pumping Charge 1 1.5 2 2.5 3

0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Pulse base level (V)

Figure 6.8: ICP against Vbase with the temperature as a parameter for the control p- channel MOSFET. ICP increases as the temperature decreases to LNT, this is consistent with the reports in the literature.

To better understand the evolution of ICP , Vbase at the points of inﬂection is plotted against temperature as shown in Fig. 6.9(a). There are three points of inﬂection for the CP curves. Two on the rising edges of both the lower plateau (blue) and higher plateau 6.5. CHARGE PUMPING MEASUREMENT 110

(orange) and one on the falling edge of the higher plateau (purple). As the temperature

decreases, Vbase at the point of inﬂection decreases on the rising edges whereas on the falling edge it increases. Vbase at the point of inﬂection on the rising edge is close to

VT , hence a decrease in Vbase implies a decrease in VT . In other words, VT decreases

as the temperature decreases. This behaviour is expected since VT is a function of the

energy diﬀerence between the Fermi level, EF , and the intrinsic Fermi level, Ei. As the temperature decreases, the energy diﬀerence increases [112], hence an increase in the

magnitude of VT . The substrate for our control p-channel MOSFET is n-type, VT would

become more negative as temperature decreases, therefore a decrease in VT is observed.

The values for VT for the MOSFET are extracted at RT and LNT. Indeed, VT is found to

increase in magnitude for the MOSFET, and the corresponding value for Vbase is „2.11 V which is where the lower plateau started to form at LNT as seen in the inset of Fig. 6.8. For the higher plateau, it narrows and increases in magnitude as the temperature decreases. This was also reported in the literature for other well-deﬁned CP curves [160,

168]. The narrowing of the plateau can be explained in terms of the change in VT and

Vfb with the temperature. The position shift for the rising edge for the higher plateau occurs for the same reason as the lower plateau rising edge shift since it is determined by

VT . The falling edge is determined by Vfb according to CP theory. Like VT , Vfb is also

a function of the energy diﬀerence between EF and Ei. It decreases in magnitude as the

temperature decreases [112], which predicts a shift toward more positive Vbase values for the falling edge, which is indeed observed in Fig. 6.8. The increase in the plateau magnitude can be understood by looking at the CP re-

combination process which contributes to the maximum ICP for a p-channel MOSFET more closely. During the ﬁrst half of a single cycle of the gate pulse, holes are captured

(by recombining with electrons) at the interface of Si/SiO2 in the channel while electrons are emitted to the substrate. The electron emission is temperature dependent, the higher the temperature the higher the electron emission rate. Thermal emission of electrons to the substrate competes with the electron-hole recombination process, and as the temperature increases, more electrons are emitted than holes captured, resulting in a reduction

in ICP . During the second half of the single cycle of the gate pulse, holes are emitted from the interface while electrons are captured. The emission of holes is also temperature dependent, and the higher the temperature, the higher the hole emission rate. Thermal emission of holes to the source and drain regions competes with the electron-hole recombination process, and as the temperature increases, more holes are emitted than electrons

captured, again resulting in a reduction in ICP . For an n-channel MOSFET, the same 6.5. CHARGE PUMPING MEASUREMENT 111 explanation applies except the roles of the electrons and holes are swapped. In other words, the maximum of ICP decreases as the temperature increases as seen in Fig. 6.8.

Figure 6.9 (b) shows the maximum ICP against the temperature. The maximum

ICP increases as the temperature decreases, and a linear increase can be observed for temperatures lower than „ 180 K. The linear increase in the maximum ICP was also observed by Van den Bosch et al. from 350 to 100 K [168]. For our data, the non- linearity above 180 K is due to the maximum ICP having a contribution from the lower (device channel-related) plateau. As the temperature decreases, the influence from the lower plateau decreases as seen in Fig. 6.8 resulting in the maximum ICP from the higher plateau being more dominant, hence the linearity is observed for lower temperatures. There are two reasons that could explain the dominance of the higher plateau at lower temperatures. In calculating the maximum ICP , the capture cross-section, σ, is assumed to be constant against temperature. This can be a good assumption as shown by Van den Bosch et al. where σ only changed by 50% as the temperature decreased from 350 to 100 K [168]. However, for our device, ICP has contribution from two different oxides, the variation in σ might not be as constant across the two oxides. The second reason is that we do not know how the effective area changes for the two oxides as the temperature decreases. This could also play a role in the larger difference between the two plateaus at lower temperatures.

5 Point of inflection lower plateau Point of inflection higher plateau (rising edge) 4 Point of inflection higher plateau (falling edge)

Pulse base level (V) level base Pulse 0

-1

-2 50 100 150 200 250 300 350 Temperature (K) (a) 6.5. CHARGE PUMPING MEASUREMENT 112

1.8

1.6

1.4

1.2

Maximum charge pumping current (nA) current pumping charge Maximum 0.8 50 100 150 200 250 300 350 Temperature (K) (b)

Figure 6.9: Vbase at the points of inflection against the temperature is shown in (a). The curves for the points of inflection on the rising edges of the lower plateau and higher plateau are in blue and orange, respectively, and the one for the falling edge of the higher plateau is in purple. As the temperature decreases, Vbase at the point of inflection decreases on the risings edges whereas on the falling edge it increases. The maximum ICP against the temperature is shown in (b). The maximum ICP increases as the temperature decreases, and a linear increase can be observed for temperatures lower than „180 K. The non-linearity part of the curve is due to the maximum ICP having more contribution from the lower plateau at higher temperatures than lower temperatures. As the temperature decreases, the influence from the lower plateau decreases as seen in Fig. 6.8 resulting in the maximum ICP from the higher plateau being more dominant, hence the linearity is observed for lower temperatures. 6.6. DISCUSSION 113

CP measurements below the liquid nitrogen temperature need above the band gap light to induce free carriers in the channel region due to carrier freeze-out at low temperatures [112]. Our measurements did not reach the freeze-out limit, hence no external light source was required. However, freeze-out needs to be considered for future CP measurements near temperatures at which QC devices normally operate.

6.6 Discussion

Well defined CP signals were observed for the field oxide against the temperature. The locations of the points of inflection correspond to the change in flat-band and threshold voltages according to CP theory as expected and our data at RT and LNT confirmed this. The maximum CP signal increased linearly once the temperature dropped below 200 K which was consistent with the observations in the literature. The non-linear behaviour at higher temperatures was due to the convolution of the two CP signals from the field and gate oxides and hence an increasing relative contribution form the channel region. As temperature decreased, the CP signal from the field oxide dominated resulting in the observed linear trend. To improve the CP measurements, a device with a well-defined and characterised active region is desired. This can be achieved by having a thicker field oxide so its influence on the CP measurements becomes negligible. The eventual goal with CP is to explore the possibility of combining it with EDMR to

identify and quantify the defects at the Si/SiO2 interface where they are relevant to the operation of Si QC devices. This requires the detection of single spins. Single defects have been detected in Si using either EDMR [169] for single donors or CP [170] for interface traps. However, single defect detection is yet to be achieved in CP EDMR. As low as 4 4 ˆ 10 spins have been observed at a Si/SiO2 interface using CP EDMR, and it was predicted that by using a higher gate pulse frequency (ą 1 GHz), single defect detection would be possible in a small channel region („100 nm2) [100]. Although RT CP EDMR did not have a higher sensitivity in Si MOSFETs compared to SiC MOSFETs where the sensitivity was about a factor of 1000 higher than the conventional EDMR, the decrease in temperature did improve the CP EDMR signals [160]. Additionally, the comparison between the conventional EDMR and CP EDMR for the Si MOSFETs was made between different devices measured in different laboratories as pointed out at the beginning of this Chapter. In the future it will be possible to compare CP EDMR with the conventional EDMR using our in-house MOSFETs at School of Physics, the University of Melbourne and this can be expected to clarify the difference 6.7. CONCLUSIONS 114

in sensitivity for CP EDMR and EDMR for Si MOSFET devices. Furthermore, instead of delivering resonant microwaves globally as for a conventional EDMR measurement, on-chip co-planar strip lines could be incorporated in the MOSFET fabrication process to deliver resonant ﬁeld locally allowing broadband operations [171] which is expected to increase the accuracy of the resonance measurements. In the next generation of devices with a ﬁeld oxide of suitable thickness further exploration is planned in the freeze-out region where photo-excitation of carriers will be trialled as a means of studying CP EDMR at low temperatures.

6.7 Conclusions

A Si MOSFET fabrication process ﬂow was set up at the University of Melbourne and used to fabricate MOSFETs with geometries appropriately optimised for CP measure-

ments. The CP technique was used to extract Dit for a p-channel MOSFET and its ErO implanted counterpart. No signiﬁcant change in Dit was observed demonstrating that the

incorporation of ErO did not affect the Si/SiO2 interface quality of the MOSFETs. How- ever, the CP signal for our p-channel devices had an extra plateau which was determined to most likely arise from the interface states in the field oxide where the gate extended across this region. This occurred because the field oxide was considerably thinner than the target value due to a processing error. Further investigations are needed to confirm this. CP measurements were also performed down to LNT which is the first step towards performing CP at temperatures closer to those of interest for QC device operation. The higher plateau of the CP signal increased in magnitude and became narrow in width as the temperature decreased, a behaviour that is consistent with the observations in the literature.

6.8 Future Work

The measurements presented here show that our devices are suitable for CP measurements and the next generation of MOSFET devices, with a correct ﬁeld oxide thickness, can be expected to allow us to explore CP and CP EDMR at low temperatures. This will allow suitable conditions to be sought that will allow spin-dependent process involving interface states to be explored down to very low temperatures which will aid in development of knowledge about interface state processes that can be expected to be of interest in QC device development. Chapter 7

Summary, Conclusions, and Future Work

As introduced in Chapter 1, quantum computing (QC) has the potential of speeding up certain computational tasks exponentially such as eﬃciently factorising large integers, or polynomially such as searching an entry in an unstructured database. Among the various methods to realise a universal quantum computer, phosphorus in silicon is a strong candidate, because it leverages the manufacturing techniques of silicon-based classical computers. However, the demands on device quality are much more stringent given that quantum states can decohere via interactions with their environment. It is thus important to investigate all types of defects present in quantum devices. To that end, we used diﬀerent experimental techniques to present detailed investigations of the defects generated during device fabrication using classical industrial techniques, but in a regime relevant to quantum device fabrication.

7.1 Ion Implantation Through the Si/SiO2 Interface

7.1.1 Summary and Conclusions

As noted in Chapter 4, the effect of P, Er, and Bi implantation through the surface gate oxide on the subsequent metal-oxide-semiconductor (MOS) device operation was investigated. The interface state density (Dit) was extracted from the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements using the Hill and Coleman (H-C) method which allowed rapid characterisation of the devices as a function of ion implant fluence. The energies and fluences were chosen specifically to be most relevant to QC related device fabrication where the implanted atom depth is around 20 nm, and the

115 7.2. DEEP LEVEL TRANSIENT SPECTROSCOPY STUDIES ON P-TYPE SI 116 spacing between the atoms is nanometers apart. This is a low energy, low fluence regime and few investigations are present in the literature even though such implants are used in industry. We presented for the first time a systematic study of P, Er and Bi implantation through the Si/SiO2 interface, especially in the context of building Si quantum computers where ion implantation of low fluences through the oxide is adopted. Our results showed that a fluence of 109 ions/cm2 will not adversely affect the interface quality. This fluence corresponds to a donor-donor spacing of 135-215 nm which is entirely appropriate for qubit devices based on the flip-flop architecture where donors can be placed 100-500 nm apart [65]. Furthermore, if implanting Bi in p-type materials is not necessary, then a higher fluence 1011 ions/cm2 can be used without affecting the interface quality to any significant extent. This fluence corresponds to a much reduced donor- donor spacing of 30-45 nm apart which benefits other architectures that require shorter spacings [48,110].

7.1.2 Future Work

In order to conﬁrm the results for the Bi implanted p-type samples where a consistent increase in Dit was observed for all ﬂuences considered, more Bi implanted p-type MOS capacitors need to be fabricated and measured to see if the same results can be reproduced.

Although the Si/SiO2 interface quality does not change significantly until after a fluence of 1013 ions/cm2, except for the Bi implanted p-type samples, finer steps of fluence are required to probe the limit of fluence up to which the quality of the Si/SiO2 interface does not change.

Furthermore, As and Sb are expected to show similar trends in Dit. However, measurements on As and Sb implanted MOS samples are needed to conﬁrm the expectation.

7.2 Deep Level Transient Spectroscopy Studies on p-Type Si

7.2.1 Summary and Conclusions

Chapter 5 introduced the studies of H and Er implantation induced damages in p- type Si MOS capacitors and Schottky diodes using deep level transient spectroscopy

(DLTS). Although both the H and Er as-implanted samples produced the V2 and CiOi ˝ defects, more CiOi defects were detected in the Er as-implanted samples. After a 200 C 7.3. CHARGE PUMPING IN SI MOSFETS 117 anneal, the defects for the H-implanted samples dropped in concentration significantly. Additionally, they evolved continuously for anneals above 100 ˝C. This contrasts the defect evolution in the Er-implanted samples where the V2 defect remained stable until ˝ ˝ after a 300 C anneal and the CiOi defect was still present after a 400 C anneal. The difference in the annealing kinetics of the defects for the Er-implanted samples and the H-implanted ones was likely due to the much denser cascades of the damage around the Er ion tracks. Although the defect types produced by Er and H implantations are the same initially, the defect evolution during the subsequent thermal annealing is markedly different for the two species. Our study of defects in MOS capacitors provided much insight into the possible defects in fully fabricated devices as ion implantation needs to be introduced in fully fabricated devices for the purpose of building a Si-based quantum computer.

7.2.2 Future Work

We have laid the ground work for further studying the defect evolution at higher temperatures to complement the efforts made to realise the long distance communications between qubits using Er atoms. The higher temperature anneals are needed to discover what defects remain after the anneals as the process related to the excitation of a charge carrier into the Si band on resonant excitation of an Er spin sub-level may require interaction with a defect level within the band-gap [62, 123]. Given the complexity of the defect evolution as observed in the DLTS of p-type Si, it would be beneficial to attempt to perform the anneals in-situ so that the defects could be tracked in more detail. Anneals at higher temperatures also require a different sample processing framework which has not been pursued in this Thesis. Within the annealing temperature range probed in our work, for the highest annealing temperature the residual defect states are approaching the detection limit of the measurement, hence for higher temperature anneal studies, a different methodology might be required in order to follow the evolution of defects in the low concentration regime.

7.3 Charge Pumping in Si MOSFETs

7.3.1 Summary and Conclusions

In Chapter 6, a Si metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication process flow was introduced. The process flow was set up at the University of 7.4. FINAL REMARKS 118

Melbourne and used to fabricate MOSFETs with geometries appropriately optimised for charge pumping (CP) measurements. The CP technique was used to extract the average interface state density, Dit, over part of the Si band gap for p-channel MOSFET with and without ErO implanted. No significant change in Dit was observed demonstrating that the incorporation of ErO did not affect the Si/SiO2 interface quality of the MOSFETs. However, an extra plateau was observed in the CP signal for our p-channel devices which was most likely due to the interface states in the field oxide where the gate extended across this region. This occurred because the field oxide was considerably thinner than the target value due to a processing error. Further investigations are needed to confirm this. CP measurements were also performed down to liquid-nitrogen temperature which is the first step towards performing CP at temperatures closer to those of interest for QC device operation. The higher plateau of the CP signal increased in magnitude and became narrow in width as the temperature decreased which is consistent with the observations in the literature.

7.3.2 Future Work

The measurements presented in Chapter 6 showed that our devices are suitable for CP measurements, and the next generation of MOSFET devices, with a correct ﬁeld oxide thickness, can be expected to allow us to explore CP and charge pumping electrically detected magnetic resonance (CP EDMR) at low temperatures. This will allow suitable conditions to be sought that will allow spin-dependent process involving interface states to be explored down to very low temperatures which will aid in development of knowledge about interface state processes that can be expected to be of interest in QC device development.

7.4 Final Remarks

In this exciting era of QC, it remains to be seen what the true power of a fully functional universal quantum computer will be. Towards that ultimate goal of building one such powerful quantum computer, we have investigated the possible environment in which a Si-based quantum computer will operate. The quality control types of measurements presented in this Thesis have provided useful information for the teams that will be responsible for assembling the world-ﬁrst Si-based quantum computers. Appendices

119 Appendix A

Photolithography

Table A.1: A summary of a typical photolithography process.

Step Detail Comments The cleaning process was strictly fol- Clean samples as described in section lowed before the oxidation, otherwise, 1 3.2 unless specified otherwise. only acetone, IPA, and DI water were used to remove the resist. Heat the samples on the hotplate at This gets rid of the water residue from 2 120 ˝C for 2 minutes the cleaning process. Spin TI 35E on the top surface of the 3 - samples to form a 3.5 µm resist layer. This makes the resist slight hard so Heat the samples on the hotplate at 4 the samples do not stick to the Mask 95 ˝C for 2 minutes Aligner. This defines the patterns on the sam- 5 UV exposure using a shadow mask. ples. Leave the samples to outgas for 20 min- The UV exposure in the previous step 6 utes in a dark or UV light free environ- produced nitrogen gas, this step allows ment. it to diffuse. This is the reversal bake where exposed Heat the samples on the hotplate at regions become insoluble in AZ 400K 7 120 ˝C for 2 minutes developer, and the unexposed regions become soluble.

120 121

This avoids nitrogen bubbles in the re- Flood expose the samples for 50 sec- 8 sist when depositing metal on the sam- onds. ples. The developing time varies, hence the Develop the samples in diluted AZ development needs to be checked ev- 9 400K developer (1:2 or 1:3), check the ery minute to ensure there is no over- patterns every minute. development. This is to prepare the samples for HF etching, it allows the samples to Hard bake the samples at 140 ˝C for 2 be more etch resistant. This step 10 minutes. is skipped if the samples are to be deposited with metal contacts, which makes life-oﬀ process easier. To remove organic impurities on the ex- 11 Plasma clean the samples for 2 minutes. posed surfaces. Appendix B

MOSFET Fabrication Process

Table B.1: MOSFET fabrication steps.

Step Description Schematic diagram

Cross-section of an n or p-type silicon 0 (300 µm).

1 100 nm ﬁeld oxide (orange) was grown.

TI35E resist (green) was uniformly dis- 2 tributed on the top surface of the sample.

After a sequence of UV light exposures as described in the chapter 3, the source and drain patterns were ready to be de- 3 veloped (light green), the details of this step were summarised in table A.1. All future steps involving deﬁning patterns used the same procedure.

122 123

The source and drain (SD) regions were 4 developed.

The ﬁeld oxide in the source and drain 5 regions were etched oﬀ using dilute HF.

The resist was cleaned oﬀ using ace- 6 tone, IPA, and DI water.

7 TI 35E was applied again.

The region deﬁned as the gate was 8 ready to be developed.

9 The gate region was developed.

The ﬁeld oxide in the gate region was 10 etched oﬀ using dilute HF. 124

The resist was cleaned oﬀ using ace- 11 tone, IPA, and DI water.

12 TI 35E was applied again.

The same SD regions were deﬁned for 13 the second time.

The SD regions were developed for ion 14 implantation.

P-type samples were implanted with As (13 keV, 8ˆ1014 cm´2) followed by As (35 keV, 3.4ˆ1015 cm´2) for n-type SD, and n-type samples were implanted 15 with Si (16 keV, 2.5ˆ1015 cm´2) followed by B (6 keV, 1.7ˆ1015 cm´2) for p-type SD. The implanted regions are highlighted in red.

The resist was cleaned oﬀ with acetone, 16 IPA, and DI water. 125

Both n and p-type samples were implanted with ErO (56 keV, 1011 cm´2)

and then followed by O2 (10 keV, 17 1.3ˆ1012 cm´2) highlighted in pink. Since the dosages of these implants were much lower than the SD implants, they did not impact SD regions.

After the implantation, samples were cleaned as described in section 3.2 be- 18 fore growing a gate oxide (yellow) of about 15 nm.

19 TI 35E was applied.

The new SD regions were deﬁned, they 20 were for depositing metal on the SD regions.

21 The new SD regions were developed.

The gate oxide in the developed regions 22 was etched oﬀ using dilute HF. 126

The resist was cleaned oﬀ with acetone, 23 IPA, and DI water.

TI 35E was applied for the last time for 24 metal deposition later.

Patterns over the necessary areas of the 25 gate and the SD regions were made.

The patterns were developed. After the 26 development, no hard bake was done for easier lift oﬀ later.

200 nm Al was deposited on the sam- 27 ples.

Samples were soaked in acetone in a 28 sonicator for a few minutes until the resist came oﬀ.

The back of the samples was scratched S G D with InGe eutectic for ohmic contact. 29 MOSFETs were fully fabricated and ready to be characterised electrically. B 127 Appendix C

Anneal Schemes

Table C.1: Anneal schemes for diﬀerent types of devices.

Device type Before metalisation After metalisation MOSFET - Metal anneal. MOS capacitors 1000 ˝C for 5 seconds after the ion (interface states Metal anneal. implantation. studies) Metal anneal followed by ion implantation, and then diﬀerent de- MOS capacitors - vices were annealed from 100 ˝C (DLTS) to 400 ˝C for 15 minutes in steps of 100 ˝C.

128 129 130

Appendix D

Complementary SRIM Simulations for Chapter 4 ) ) -3 -3 5 7 ) 5 7 )

SiO p-type Si -3 SiO p-type Si -3 2 P 2 Er Damage 6 cm Damage 6 cm cm 17 17 cm 4 4 14 14 5 10 5 10 10 10 3 4 3 4

-3 SiO p-type Si 2 Bi Damage 6 cm cm 4 17 14 5 10 10 3 4

2 3 2 1 1

Bi concentration ( 0 0 0 10 20 30 40 50 60 70 80 90 100 Total displacements ( Depth (nm) (c)

Figure D.1: SRIM simulations of the P, Er, and Bi implanted projected range (blue curves) and displacement (red curves) profiles as a function of depth in p-type Si. The oxide surface layer is shown in gold. The fluence used to simulate the profiles is 109 ions/cm2. Appendix E

Arrhenius Plots

131 132

H H[0.28(5)] H[0.19(2)] 10-1

H[0.12(3)] H[0.11(2)] )

-2 -2

K 10

-1

/T p e 10-3

H[0.35(3)] H[0.15(2)] 10-4 H[0.21(3)]

4 5 6 7 8 9 10 1000/T (K-1) (a) 100 H[0.26(1)] Er H[0.19(2)] 10-1

H[0.18(3)] )

-2 -2

K 10

-1

(s 2

-3 /T

p 10 e

10-4 H[0.25(2)] H[0.35(2)] H[0.23(2)] 10-5 4 6 8 10 12 1000/T (K-1) (b)

Figure E.1: Arrhenius plots of the defect emission rate determined from all well-defined DLTS features of the H-implanted samples (a) and Er-implanted samples (b). Solid lines are linear fits from which the effective activation energies and hole capture cross sections are obtained. Values are quoted in Table 5.1 in Chapter 5. Appendix F

Complementary Figures for Chapter 6

133 134

I 1 2 1 2

V I

4 3 4 3 V

(a) (b)

V 1 2 1 2

I V

4 3 4 3 I

Figure F.1: Schematic examples of the van der Pauw measurement. The van der Pauw structure is represented by the square 1234. A range of currents was ﬁrst applied between 1 and 2, and the corresponding range of voltages was recorded between 3 and 4 (a). After the ﬁrst measurement, the same range of currents was then applied between 2 and 3 instead, and the corresponding range of voltages was recorded between and 1 and 4 (b). This was then repeated two more times as seen in (c) and (d). 135

5 Config. 1 Control Config. 2 Config. 3

Config. 4

-4 10

0 Voltage ( Voltage

= (1.63 0.03) 10-3 cm -5 -1 -0.5 0 0.5 1 Current ( 10-5 A) (a) 5 Config. 1 ErO Config. 2 Config. 3

Config. 4

-4 10

0 Voltage ( Voltage

= (3.96 0.07) 10-4 cm -5 -1 -0.5 0 0.5 1 Current ( 10-5 A) (b)

Figure F.2: The voltage against current plots for the control sample (a) and the sample implanted with ErO (b). Four sets of data are shown overlapping each other. Each set of data corresponds to one of the conﬁgurations in Fig. F.1. The resistivity was calculated by extracting the gradients of the linear ﬁts to the data. 136

20 μm 1 2 40 μm 3 4 80 μm

160 μm 5 320 μm 6

Figure F.3: The strip line structure from Fig. 3.2 in Chapter 3. The resistance between contacts 1 and 2 was obtained by applying a range of voltages across the two contacts and measuring the corresponding range of currents. Then the same measurement was repeated between 2 and 3, and then 3 and 4, and so on. The distance between the contacts is indicated by the arrows. 137

400 Data 350 Fitted line =(1.47 0.52) 10-5 cm2 ) 300 c R = 211.36 1.68 250 s R = 2.79 0.69 c 200 L = 2.64 0.66 m c Control 150

Total resistance ( resistance Total 100

0 0 50 100 150 200 250 300 350 Contact separation ( m) (a) 400 Data 350 Fitted line = (4.59 2.54) 10-6 cm2 ) 300 c R = 199.19 1.43 250 s R = 1.51 0.59 c 200 L = 1.52 0.59 m c 150 ErO

Total resistance ( resistance Total 100

0 0 50 100 150 200 250 300 350 Contact separation ( m) (b)

Figure F.4: Transmission line measurement for the control sample (a) and the sample implanted with ErO (b). The resistance between the contacts was plotted against their corresponding distance from each other as indicated in Fig. F.3. From the linear ﬁt (red) to the data points (blue), the contact resistivity (ρc), contact resistance (Rc), transfer length (Lc), and sheet resistance (Rs) were obtained. Bibliography

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