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Applications Des Technologies Mémoires MRAM Appliquées Aux Processeurs Embarqués Luís Vitório Cargnini

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Applications Des Technologies Mémoires MRAM Appliquées Aux Processeurs Embarqués Luís Vitório Cargnini Applications des technologies mémoires MRAM appliquées aux processeurs embarqués Luís Vitório Cargnini To cite this version: Luís Vitório Cargnini. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2013. Français. NNT : 2013MON20091. tel-01015187 HAL Id: tel-01015187 https://tel.archives-ouvertes.fr/tel-01015187 Submitted on 26 Jun 2014 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par UNIVERSITÉ MONTPELLIER 2 Préparée au sein de l’école doctorale Information, Structures et Systèmes Et de l’unité de recherche LIRMM Spécialité : Systèmes Automatiques et Microélectronique Présentée par Luís Vitório Cargnini Applications des technologies mémoires MRAM Appliquées aux processeurs embarqués Soutenue le 12/11/2013 devant le jury composé de Dr. Lionel TORRES Professeur, Université Montpellier 2 Directeur de Thèse Dr. Gilles SASSATELLI Directeur de Recherche CNRS, LIRMM UMR CNRS 5506 Co-Encadrant Dr. Guy Gogniat Professeur, Université Bretagne-Sud, Lorient Rapporteur Dr. Bertrand GRANADO Professeur, Université Pierre et Marie Curie, Paris Rapporteur Dr. Jacques-Olivier Klein Professeur, Université Paris Sud 11, Paris Président Dr. Daniel Étiemble Professeur, Université Paris Sud 11, Paris Examinateur Dr. Guillaume Prenat Ingénieur-Docteur, CEA, Laboratoire SPINTEC, Grenoble Examinateur Académie de Montpellier U n i v e r s i t é M o n t p e l l i e r II — Sciences et Techniques du Languedoc — Thèse présentée au Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier pour obtenir le grade de Docteur de l’Université Montpellier II Discipline : Génie Informatique, Automatique et Traitement du Signal Formation Doctorale : Systèmes Automatiques et Microélectronique École Doctorale : Information, Structures et Systèmes MRAM APPLIED TO EMBEDDED PROCESSORS ARCHITECTURE AND MEMORY HIERARCHY NON-VOLATILE MEMORY MRAM INTO THE MEMORY HIERARCHY par Luís Vitório Cargnini Jury composé de : Lionel Torres Professeur, Université Montpellier II/CNRS, Montpellier, France Directeur de thèse Gilles Sassatelli Directeur de recherche/CNRS, Montpellier, France Co-encadrant Guy Gogniat Professeur, Université de Bretagne Sud, Lorient, France Rapporteur Bertrand Granado Professeur, Université Pierre et Marie Curie, Paris, France Rapporteur Jacques-Olivier Klein Professeur, Institut d’Électronique Fondamentale, Université Paris Sud 11, Paris, France Président Daniel Étiemble Professeur, Lab. de Recherche en Informatique, Université Paris Sud 11, Paris, France Examinateur Guillaume Prenat Ingenieur, CEA Spintec, Grenoble, France Examinateur luís vitório cargnini MRAMAPPLIEDTOEMBEDDEDPROCESSORSARCHITECTURE ANDMEMORYHIERARCHY MRAMAPPLIEDTOEMBEDDEDPROCESSORSARCHITECTUREAND MEMORYHIERARCHY luís vitório cargnini Non-volatile Memory MRAM into the memory hierarchy Ph.D. I2S LIRMM – Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Université de Montpellier 2 November 12, 2013 – version 7.3 Luís Vitório Cargnini: MRAM applied to Embedded Processors architecture and Memory Hier- archy , Non-volatile Memory MRAM into the memory hierarchy , Ph.D., c , November 12, 2013 supervisors: Lionel Torres Gilles Sassatelli location & time frame: Montpellier,France, November 12, 2013 To my wife, that endured, my years of Ph.D., my absences. I was lucky to have found you at our Alma Mater ! Thanks for all the trust, help and support you give me everyday, we finally can go home ! To my thesis baby: now, dad have time to play ! New ideas pass through three periods: 1) It can’t be done. 2) It probably can be done, but it’s not worth doing. 3) I knew it was a good idea all along! Arthur C. Clarke Ohana means family. Family means nobody gets left behind, or forgotten. — Lilo & Stitch Ad Verum Ducit — Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) motto. ABSTRACT The Semiconductors Industry with the advent of submicronic manufacturing flows below 45nm began to face new challenges to keep evolving according with the Moore’s Law. Regarding the widespread adoption of embedded systems one major constraint became power consumption of Integrated Circuit (IC). Also, memory technologies like the current standard of integrated memory technology for memory hierarchy, the SRAM, or the FLASH for non-volatile storage have extreme intricate constraints to be able to yield memory arrays at technological nodes below 45nm. One important is up until now Non-Volatile Memory weren’t adopted into the memory hierarchy, due to its density and like flash the necessity of multi-voltage operation. This thesis has the objective to work into these constraints and provide some answers. Into the thesis will be presented methods and results extracted from this methods to corroborate our goal of delineate a roadmap to adopt a new memory technology, non-volatile, low-power, low-leakage, SEU/MEU-resistant, scalable and with similar performance as the current SRAM, physically equivalent to SRAM, or even better with a area density between 4 to 8 times the area of a SRAM cell, without the necessity of multi-voltage domain like FLASH. This memory is the MRAM (Magnetic Memory), according with the ITRS one candidate to replace SRAM in the near future. MRAM instead of storing charge, they store the magnetic orientation provided by the spin-torque orientation of the free-layer alloy in the Magnetic Tunnel Junction (MTJ). Spin is a quantical state of matter, that in some metallic materials can have the orientation or its torque switched applying a polarized current in the sense of the desired field orientation. Once the magnetic field orientation is set, using a sense amplifier, and a current flow through the MTJ, the memory cell element of MRAM, it is possible to measure the orientation given the resistance variation, higher the resistance lower the passing current, the sense will identify a logic zero, lower the resistance the SA will sense a one logic. So the information is not a charge stored, instead it is a magnetic field orientation, reason why it is not affected by SEU or MEU caused due to high energy particles. Also it is not due to voltages variations to change the memory cell content, trapping charges in a floating gate. Regarding the MRAM, this thesis has by objective address the following aspects: MRAM applied to memory Hierarchy: • By describing the current state of the art in MRAM design and use into memory hierarchy; • by providing an overview of a mechanism to mitigate the latency of writing into MRAM at the cache level (Principle to composite memory bank); • By analyzing power characteristics of a system based on MRAM on CACHE L1 and L2, using a dedicated evaluation flow • by proposing a methodology to infer a system power consumption, and performance. • and for last based into the memory banks analyzing a Composite Memory Bank, a simple description on how to generate a memory bank, with some compromise in power, but equivalent latency to the SRAM, that keeps similar performance. ix PUBLICATIONS Some ideas and figures have appeared previously in the following publications: book chapters Weisheng Zhao, Lionel Torres, Luís Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiem- ble, Dafiné Ravelosona, Claude Chappert, "High Performance SoC Design Using Mag- netic Logic and Memory", VLSI-SoC: Advanced Research for Systems on Chip, IFIP Advances in Information and Communication Technology, Volume 379, 2012, pp 10- 33, DOI: 10.1007/978-3-642-32770-4_2, Print ISBN 978-3-642-32769-8, Online ISBN 978-3- 642-32770-4, ISSN 1868-4238, Springer Berlin Heidelberg, http://link.springer.com/ chapter/10.1007%2F978-3-642-32770-4_2 international conferences Torres, L.; Brum, R.M.; Cargnini, L.V.; Sassatelli, G., "Trends on the application of emerg- ing nonvolatile memory to processors and programmable devices," Circuits and Sys- tems (ISCAS), 2013 IEEE International Symposium on , vol., no., pp.101,104, 19-23 May 2013, doi: 10.1109/ISCAS.2013.6571792, http://ieeexplore.ieee.org/stamp/stamp.jsp? tp=&arnumber=6571792&isnumber=6571764 Torres, L.; Brum, R.M.; Guillemenet, Y.; Sassatelli, G.; Cargnini, L.V., "Evaluation of hy- brid MRAM/CMOS cells for reconfigurable computing," New Circuits and Systems Conference (NEWCAS), 2013 IEEE 11th International , vol., no., pp.1,6, 16-19 June 2013, doi: 10.1109/NEWCAS.2013.6573676, http://ieeexplore.ieee.org/stamp/stamp.jsp? tp=&arnumber=6573676&isnumber=6573561 Cargnini, Luis Vitorio; Torres, Lionel; Brum, Raphael Martins; Senni, Sophiane; Sas- satelli, Gilles, "Embedded memory hierarchy exploration based on magnetic RAM," Faible Tension Faible Consommation (FTFC), 2013 IEEE , vol., no., pp.1,4, 20-21 June 2013, doi: 10.1109/FTFC.2013.6577780, http://ieeexplore.ieee.org/stamp/stamp.jsp? tp=&arnumber=6577780&isnumber=6577746 Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luís Vitório Cargnini, Yahya Lakys, Jacques-Olivier
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