Kinetis Family Issue 5 Beyond Bits Building the Industry’S Most Trusted Mcus

Designer Resource. Accelerate. Simplify. Issue 5, Version 2 Beyond Bits November 2010 Next-Generation Microcontrollers5

INTRODUCING ColdFire+ Family Kinetis Family Issue 5 Beyond Bits Building the industry’s most trusted MCUs

Welcome to the exciting fifth edition of Beyond Bits. We’re introducing two new microcontroller lines to help realize your most innovative ideas.

The Freescale ColdFire+ and Kinetis 32-bit MCU families expand your choices, regardless of core or architecture preference, and help you design more optimized products. Built from 90nm thin-film storage (TFS) flash technology, our new MCUs feature unique FlexMemory capability, a powerful array of mixed-signal analog peripherals and the latest ultra-low-power technology. Bundled with the latest Eclipse-based CodeWarrior Development Studio, MQX™ RTOS and the modular Tower System, we help you design more quickly and easily.

In addition to these two new lines, our extensive range of 8-, 16- and 32-bit MCUs offer MCU solutions you can trust. You can count on us to deliver industry-leading vertical solutions, scalable product lines, intellectual property and process technology roadmaps, outstanding technical support and a broad range of devices available for a minimum period of 10 years. We’ve worked hard to create a seamless design environment where you can easily scale from 8-bit to 32-bit, between architectures, re-using code and developing with the same tools.

This fifth edition focuses on product family details and key technical highlights of these new MCU families. And you won’t want to miss these details—we’ve packed some exciting new features onto these parts, including the best in low power, connectivity, HMI and security innovation.

Overall, we’re adding hundreds of new 32-bit MCUs to help fuel your imagination and inspire your next design.

Enjoy this edition.

Regards,

Reza Kazerounian Senior Vice President, Microcontroller Solutions Group

For Terms and Conditions and to obtain a list of available products, visit freescale.com/productlongevity. Overview Issue 5 Beyond Bits Table of Contents

Portfolio Overview 2

ColdFire+ V1 Microcontroller Family Overview 4

Kinetis Microcontrollers Overview 10

Kinetis Microcontrollers Families 12

Kinetis K10 Family ...... 16

Kinetis K20 Family ...... 19

Kinetis K30 Family ...... 22

Kinetis K40 Family ...... 25

Kinetis K60 Family ...... 28

Technical Highlights 31

Core Technology ...... 32

Compatibility and Scalability ...... 34

90nm TFS Flash and FlexMemory ...... 37

Power Management ...... 40

Xtrinsic Low-Power Touch-Sensing Interface ...... 42

Segment LCD Controller ...... 44

Precision Analog and Control ...... 46

Clocking System ...... 50

IEEE 1588 Ethernet Controller ...... 52

Universal Asynchronous Receiver/Transmitter (UART) ...... 54

USB Subsystem ...... 56

External Interfaces ...... 58

Development Tools 60

Freescale MQX Software Solutions ...... 61

Freescale Tower System ...... 64

CodeWarrior Development Studio ...... 66

IAR Embedded Workbench ...... 68

Keil Microcontroller Development Kit (MDK) ...... 70

Green Hills Software ...... 71

CodeSourcery ...... 72

P&E Micro ...... 73

Segger ...... 74

Swell ...... 75

Quick Reference 76

This document contains information on a new product. Specifications and information herein are subject to change without notice. freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 1 Overview

APPLIANCE CONSUMER GENERAL ENERGY AND MEDICAL FACTORY PURPOSE METERING AUTOMATION Robustness Low Power Precision Analog Large, Compatible Measurement Signal Processing 5V Capability USB Connectivity Portfolio Engine Ultra-Low Power High-Speed High-Performance Encryption Full Connectivity Power Line Connectivity— Peripherals Timers Offering Communication Continua Touch Sensing Integrated Analog Human-Machine Low Power Wireless Capability and Mixed Signal Interface Precision Analog

Enablement

ColdFire+ MCUs

Kinetis MCUs

Portfolio Overview Next-generation 32-bit microcontrollers

Freescale’s 32-bit industrial and consumer microcontrollers Freescale has combined its innovative IP, flash technology and platform- are evolving into a new era enabled by innovative 90nm thin-film based design capability into a portfolio storage (TFS) flash memory technology with FlexMemory. of devices that are solutions-focused The result? Hundreds of new mixed-signal MCUs with and core-agnostic. The new 32-bit ColdFire+ MCU families are built using performance, memory and feature scalability, and a market-leading the ColdFire V1 core. The new Kinetis enablement bundle that delivers a one-stop-shop solution for MCU families are built using the ARM® Cortex™-M4 core. Both families share MCUs, development tools and runtime software. the same software enablement, the same low-power flexibility and offer consistent peripherals—making it simple to pick the best solution for your end application.

2 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Overview

Built upon the ARM Cortex-M4 core, Kinetis MCUs share the same Software FlexMemory configurable EEPROM Enablement 90nm Technology capability, mixed-signal integration and Market-leading IDE, TFS ﬂash with FlexMemory low-power IP strengths as their ColdFire+ RTOS and EEPROM capability initialization tools cousins, but add additional connectivity, human-machine interface and safety and security functionality. The first phase of the Kinetis portfolio consists of five More than 40 new 90nm compatible MCU families that take ColdFire+ MCUs MCU scalability and integration to the next level. Additional families with More than 200 new 90nm application-focused peripheral sets are Kinetis MCUs currently in design and will be available throughout 2011.

Ultra-Low Comprehensive Enablement Mixed Signal Power Time to market in 32-bit MCU design 32-bit MCUs with huge Consumption performance, memory and Flexible power management increasingly depends on software feature scalability to balance performance and battery life development and the expectation that silicon vendors will provide complete enablement solutions. Freescale recognizes this and has enabled ColdFire+ Microcontrollers Kinetis Microcontrollers ColdFire+ and Kinetis MCUs with a Design Innovation. Accelerated. Design Potential. Realized. powerful set of common software and hardware development tools. Freescale Application-oriented solutions with Market-leading mixed-signal plans to deliver and support CodeWarrior increased integration, ultra-low integration, scalable performance for Microcontrollers v10.x (Eclipse™) power and optimized cost. and ultra-low power. IDE with Processor Expert, the most ColdFire+ MCUs build upon the ColdFire Complementing Freescale’s ARM based advanced tool of its kind, along with the architecture’s strong heritage and i.MX MPU products, Kinetis represents complimentary Freescale MQX™ RTOS signify the next step in the evolution of the most scalable portfolio of mixed- for both ColdFire+ and ARM Cortex-M4 ColdFire MCUs. ColdFire+ MCUs add signal ARM Cortex-M4 MCUs in the solutions. Kinetis MCUs also have the full several impressive new features: industry. By offering ARM microcontrollers support of the expansive ARM ecosystem, including IAR and Keil™. The Freescale • FlexMemory, configurable in addition to our existing ColdFire enablement offering, combined with embedded EEPROM solutions and MCUs built on Power ® the full support of the ARM ecosystem, • Additional application-specific Architecture technology, Freescale is provides a pathway for quick design peripherals for consumer goods, focused on delivering the best hardware and reduced design headaches. The appliances and smart metering and software solution available in the marketplace—regardless of Freescale Tower rapid prototyping system • High-precision, high-performance core architecture preference. completes the offering by providing mixed-signal capability unlimited quick prototyping capabilities, • Incredible low-power features, with Freescale will deliver over 200 new eliminating months of development time. run currents down to 150 µA/MHz Kinetis MCUs with scalable performance, memory and feature integration over The MCF51Qx/Jx families are the first the course of the next 18 months. The ColdFire+ products that combine cutting- benefits are obvious: designers can select edge low-power performance with a the part they need while knowing they can diverse set of analog, connectivity and also quickly adjust to market changes. security peripherals, all packaged in low Pin compatibility, peripheral compatibility cost, small footprint packages. These are and software compatibility allow only the beginning of the next round of maximum reuse while minimizing investment in the future of ColdFire. design time and cost. freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 3 ColdFire+ Microcontrollers

ColdFire+ Microcontrollers 4 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 ColdFire+ Microcontrollers

ColdFire+ Microcontrollers Design Innovation. Accelerated. freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 5 ColdFire+ Microcontrollers

ColdFire+ V1 Microcontrollers For secure ultra-low-power applications

The ColdFire+ Qx and Jx families ColdFire+ Jx/Qx Families combine cutting-edge low-power performance with a diverse set of analog, Core and System Power Memory and Clocks Management Memory Interfaces connectivity and security peripherals, all ColdFire V1 Core Phase-Locked Power Loop CPU Debug Flash RAM packaged in cost-effective, small footprint Management Enhanced Controller Frequency- Hardware Locked Loop Multiply- Divide packages. Six families are built from Accumulator 1.7V to 3.6V FlexNVM FlexRAM Voltage Low/High- Frequency 90nm thin-film storage flash technology Regulator Serial External Bus Crossbar Interrupt Oscillators Controller Programming Interface Switch I/F (EzPort) (Mini-FlexBus) with FlexMemory. Features common to Internal Direct Memory Low-Leakage Reference all six families include 32 KB–128 KB Access Wake-Up Clocks of flash, up to 32 KB of FlexMemory (2 KB EEPROM), flash programming and System Analog Timers Communication Human- Security and Interfaces Machine peripheral operation from 1.71V to 3.6V, Integrity 16-bit ADC Timers x2 Interface I2C x4 UART x2 with Smart Card (HMI) 10 low-power modes, a low-power touch- CRC 12-bit ADC Carrier Modulator SPI x2 USB OTG GPIO sensing interface, 12-bit DAC and a range Transmitter LS/FS Watchdog Analog Comparator Programmable of serial communications interfaces and I2S/SAI USB Charger Capacitive Delay Block Detect Touch Sense Hardware timers. This rich set of features makes 6-bit DAC Encryption Modulo (CAU) External the ColdFire+ Qx/Jx families ideal for Timer Interrupt 12-bit DAC Random Low-Power cost- and space-constrained consumer Number Timers x2 Generator Voltage and industrial applications ranging from Reference portable hand-held devices to wireless Only on JF, Only on Only on JF, Only on sensing nodes. LEGEND QF and QM QH and QM JU, QF and QU JF and JU

The six scalable ColdFire+ families consist of the MCF51QU, MCF51QH, Performance MCF51QF and MCF51QM, and the MCF51JU and MCF51JF devices. All • 50 MHz ColdFire V1 core + eMAC + • Independent flash banks, allowing families are software and pin-to-pin hardware divide concurrent code execution and compatible, allowing easy migration • 4-channel DMA for peripheral and firmware updating with no performance between devices to take advantage of memory servicing with reduced CPU degradation or complex coding routines additional memory and functionality. loading and faster system throughput • Cross bar switch enables concurrent multi-master bus access, increasing bus bandwidth

6 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 ColdFire+ Microcontrollers

Portable Media Player Device Accessory

Battery Power ColdFire+ V1 (chargeable by USB) Cryptography Module Performs Qx Family Accessory Authentication Internal EEPROM for to Ensure Original An incredibly cost-effective, User Settings Storage Equipment ultra-low-power, mixed-signal microcontroller family ideal for secure portable or battery-powered applications.

Codec ColdFire+ Target applications • Wireless sensor nodes Speaker or Headset USB Portable • Security control pads Media Player • Video game accessories

12:00 MCF51QH MCF51QM Encryption Smart Card Interface User Interface Real-Time Clock 16-bit ADC for Media Data Storage with Graphic Display 16-bit ADC and Touch Sensing

MCF51QU MCF51QF Encryption 12-bit ADC 12-bit ADC Ultra-Low Power Flash SRAM and FlexMemory

• 10 low-power modes with power and • 32 KB to 128 KB flash clock gating for optimal peripheral • 8 KB to 32 KB of RAM activity and recovery times. Stop • FlexMemory: Up to 2 KB of user- currents of <500 nA, run currents segmentable byte write/erase ColdFire+ V1 of 150 uA/MHz, 4 μs wake-up from EEPROM for data tables/system data. Jx Family stop mode Over 4.4M write/erase cycles with • Full flash programming and analog 100 μsec write time (brownouts without Ideal for portable consumer operation down to 1.71V for extended data loss or corruption). No user devices, the ColdFire+ Jx family battery life or system intervention to complete adds USB On-The-Go (OTG) • Low-leakage wake-up unit with up programming and erase functions capability and a serial audio to four internal modules and 16 pins as and full operation down to 1.71V. interface to the ColdFire+ wake-up sources in low-leakage stop In addition, FlexNVM up to 32 KB Qx family. (LLS)/very low-leakage stop (VLLS) for extra program code, data or modes EEPROM backup Target applications • Two low-power timers for continual Continued on next page • Secure, low-power system operation in reduced iPod accessories power state • USB audio bridges • PC peripherals • High-end remote controls

MCF51JU MCF51JF USB OTG USB OTG 12-bit ADC 12-bit ADC Encryption

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 7 ColdFire+ Microcontrollers

Continued from previous page Human-Machine Interface Timing and Control

Mixed-Signal Capability • Xtrinsic low-power touch-sensing • Up to two FlexTimers with a total of interface with up to 16 inputs. eight channels. Hardware dead-time • High-speed 12/16-bit ADC with Operates in all low power modes insertion and quadrature decoding for configurable resolution. Single or (minimum current adder when motor control differential output mode operation enabled). Hardware implementation • Carrier modulator timer generates for improved noise rejection. 500 ns avoids software polling method. High infrared waveforms for remote control conversion time achievable with sensitivity level allows use of overlay applications programmable delay block triggering surfaces and robust performance in • 12-bit DAC for analog waveform noisy environments generation for audio applications • High-speed comparators provide fast and accurate motor over-current Smart Sensor Node protection by driving PWMs to a Enhance multiply accumulate All this functionality packed into safe state is a DSP coprocessor ideal a 5 x 5 44-pin laminate QFN • Accurate on-chip voltage reference for signal processing. DSP library included eliminates need for accurate external voltage reference IC, reducing overall (Jx Only) Clock Module: system cost 50 Mhz Full-Speed Two Crystal Inputs ColdFire V1 4-ch. USB and Two Internal Core with DMA (H/D/OTG) Oscillators eMAC Connectivity and With DCD PLL and FLL Communications

• USB 2.0 OTG and device charger CrossBar Swith (XBS) detect optimizes charging current/time for portable USB devices, enabling longer battery life. Integrated USB low-voltage regulator supplies up Rapid GPIO FlexBus to 120 mA off chip at 3.3V to power external components Up to Peripheral Bridge • Two UARTs with ISO7816 smart card 128 KB Timers Analog Communications Cryptographic support. Variety of data size, format Flash Memory 2x Low-Power 12/16-bit SAR 2 x I2C, 2 x SPI Acceleration and transmission/reception settings Timers ADC 2 x UART Unit with Up to supported for multiple industrial 12-bit DAC Random 32 KB 2x FlexTimer (Jx Only) Serial Number communication protocols SRAM Programmable High-Speed Audio Interface Generator Delay Block Comparator 2 32-bit Cyclic Touch-Sensing • Inter-IC Sound (I S) interface for audio FlexMemory: Internal Voltage Carrier Redundancy Interface system interfacing Up to 2 KB Modulator Reference Check EEPROM or Timer (1.2V) Up to 48 GPIO • Two SPI and up to four I2C 32 KB Flash

On-chip Four I2C modules EEPROM capability with ADC includes enable multiple sensor unsurpassed endurance temperature inputs, including enables data log and sensor accelerometers calibration functionality SPI modules with DMA support enable Wi-Fi®, 32K SRAM outpaces Bluetooth® or connection competitive Flash/SRAM to other wireless protocols ratios, improving application performance

8 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 ColdFire+ Microcontrollers

ColdFire+ Features Options Memory Feature Options Packages

S Family C 2 2 I External Bus Interface 320FN (5x5mm) 440FN (5x5mm) 48LOFP (7x7mm) 640FN (9x9mm) 64LOFP (10x10mm) CPU Frequency (MHz) Flash (KB) FlexNVM (KB) SRAM (KB) eMAC + HDIV ADC DAC High-Speed Comparator Touch-Sensing Interface USB/OTG (LS/FS) Cryptographic Acceleration Unit FlexTimer Low-Power Timer Carrier Modulator Transmitter Programmable Delay Block UART SPI I

Up to Up Up Up to 44-pin 32 16 8 √ 12-bit optional 2 √ √ 2 2 3 √ √ 16-bit to 2 to 7 7 ch only Up to Up Qx 50 64 32 16 √ 12-bit 2 optional 7 ch 2 √ √ 2 2 3 √ √ √ 16-bit to 8 Up to Up Up to 44-pin 128 32 8 √ 12-bit 16 optional 2 √ √ 2 2 √ √ √ √ 16-bit to 4 8 ch only Up Up Up to 44-pin 32 16 16 √ 12-bit 12-bit √ optional 2 √ √ 2 2 3 √ √ √ to 2 to 7 7 ch only Up Jx 50 64 32 32 √ 12-bit 12-bit 2 √ optional 7 ch 2 √ √ 2 2 3 √ √ √ √ to 8 Up Up to 44-pin 128 32 32 √ 12-bit 12-bit 16 √ optional 2 √ √ 2 2 √ √ √ √ √ to 4 8 ch only

Reliability, Safety and External Peripheral Support º Complimentary bare-metal/no OS USB stack with PHDC, MSC, CDC, Security • Mini-FlexBus external bus interface HID class and more • Encryption coprocessor for secure provides interface options to º Complimentary Freescale data transfer and storage. Faster than peripherals such as graphics displays. Embedded GUI (eGUI) software software implementations with wide Supports up to two chip selects driver for graphics LCD panels algorithm support for DES, 3DES, AES, Complimentary bootloaders MD5, SHA-1 and SHA-256 Tools and Software º (USB, RF, serial) • Cyclic redundancy check engine • Freescale Tower System hardware º Complimentary Freescale MQX validates memory contents and development environment RTOS, USB stack and MFS communication data, increasing • Integrated development environments filesystem system reliability º CodeWarrior for Microcontrollers Micrium uC/OS-III • Independent-clocked COP guards º v10.x (Eclipse) IDE with against clock skew or code runaway º Express Logic ThreadX Processor Expert for fail-safe applications º SEGGER embOS º IAR Embedded Workbench º freeRTOS º CodeSourcery Sourcery G++ (GNU) • Runtime software and RTOS º DSP and encryption libraries

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 9 Introducing Kinetis Microcontrollers

Kinetis Microcontrollers Kinetis Microcontrollers Design Potential. Realized. Kinetis Microcontrollers

Kinetis Microcontrollers Software-enabled MCU platforms

ARM Cortex microcontrollers The Kinetis portfolio consists of multiple The platform approach offers a number hardware- and software-compatible MCU of benefits for the embedded designer: are on the move. Kinetis is families with exceptional low-power the first broad-market mixed- performance, memory scalability Match MCU capabilities to application requirements signal MCU family based on the including on-chip FlexMemory/EEPROM, and peripheral integration. Families range Select features as needed while knowing new ARM Cortex-M4 core and from entry-level to highly integrated there are paths for future expansion or the most scalable portfolio of and include a wide selection of analog, cost reduction. human-machine interface, connectivity, mixed-signal ARM Cortex-M4 Reuse hardware and software and safety and security functions. MCUs in the industry. across multiple end products With Kinetis, value isn’t confined just to Minimize development costs, the MCU. A powerful suite of enablement learning curves and time to market. software comes standard from Freescale. Add to this a large and well-established Quickly adjust to market software and tool ecosystem from changes in feature requirements numerous ARM third parties and the Create super-set or sub-set products result is a portfolio of MCU platforms that with a single MCU portfolio. delivers exceptional flexibility and value for designers of industrial and consumer end products.

12 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Mixed-Signal Capability FlexMemory: Fast, Meeting for Signal Conditioning, Flexible, High-Endurance the Needs of Conversion and Analysis On-Chip EEPROM Kinetis MCUs are rich in mixed-signal Freescale’s new FlexMemory technology the Embedded capability. Features include multiple provides an extremely versatile and high-speed, high-precision 16-bit ADCs, powerful solution for designers seeking Designer 12-bit DACs, high-speed comparators, on-chip EEPROM and/or additional and programmable gain amplifiers. With program or data flash memory. As easy Wide Selection of Scalable analog integration at this level typically and as fast as SRAM, it requires no MCUs from One Supplier requiring a multi-chip solution, Kinetis user or system intervention to complete The first phase of the Kinetis MCU MCUs offer the added benefits programming and erase functions portfolio contains five compatible MCU of reduced system cost and when used as high endurance byte- families. Five performance options are integration effort. write/byte-erase EEPROM. EEPROM available from 50 to 150 MHz with flash array size can also be configured for memory ranging from 32 KB to 1 MB Ultra-Low-Power improved endurance to suit application and high RAM-to-flash ratios throughout. Performance for requirements. FlexMemory can also Common peripherals, memory maps Extended Battery Life provide additional flash memory and packages both within and across (FlexNVM) for data or program storage in Kinetis MCUs feature the best in low- MCU families allow for easy migration to parallel with the main program flash. The power innovation, including ten flexible greater/less memory and functionality. user can configure several parameters low-power operating modes for power including EEPROM size, endurance, write profile optimization, power and clock size, and the size of additional program/ gating, back-biasing, 4µS wake up times, data flash. On larger memory variants, flash programming and analog peripheral endurance figures of over 10M write/erase operation down to 1.71V and stop and run cycles can be achieved. In comparison currents of <500 nA and <200 µA/MHz with traditional EEPROM solutions, respectively. A low-power RTC and low- FlexMemory offers a number of benefits, leakage wake-up unit add further flexibility, including greater endurance, faster write/ while a low-power timer enables continual erase times, lower voltage operation system operation in reduced power states. and user segmentation. Being on-chip it also eliminates the costs associated Kinetis Family Key Attributes with using external EEPROM ICs and the the software headaches and CPU/flash/ RAM resource impact encountered with EEPROM emulation schemes. Scalable FlexMemory Fast, Robust Flash Memory Freescale’s 90nm thin-film storage (TFS) flash memory delivers industry- leading reliability and tolerance to charge loss, full flash programming and analog peripheral operation down to 1.71V, significantly reduced run and standby currents, and fast access times. Excellent area efficiency maximizes Mixed Signal Enablement on-chip feature integration across flash densities, while independent flash banks More than 200 new parts enable simultaneous code execution Seven scalable families and firmware updating without any performance degradation or complex software routines. Continued on next page freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 13 Kinetis Microcontrollers

Continued from previous page Kinetis MCU Families

One-Stop Enablement Floating Point Unit Ethernet (IEEE® 1588) NAND Flash Controller Encryption (CAU+RNG) Offering—MCU + IDE + RTOS Segment LCD Dual CAN USB OTG (FS and HS) Hardware Tamper Detect Kinetis MCUs come with a complimentary DRAM Controller full-featured MQX RTOS and bundled CodeWarrior for Microcontrollers v10.x K60 Family, 100–150 MHz, 256 KB–1 MB (Eclipse) IDE with Processor Expert. A 100–256 pin selection of connectivity, motor control, LCD and security stacks and drivers are K40 Family 50–100 MHz, 64–512 KB also offered as well as a range of tools 64–144 pin from IAR, KEIL and other ARM third-party vendors. Kinetis MCUs are supported K30 Family 50–100 MHz, 64–512 KB by Freescale’s Tower System, a rapid 64–144 pin prototyping development platform that maximizes hardware reuse and K20 Family 50–120 MHz, 32 KB–1 MB speeds time to market. 32–144 pin

K10 Family Powerful Processing 50–120 MHz, 32 KB–1 MB Capability 32–144 pin

Kinetis MCUs feature the new ARM Common Common Common Development Cortex-M4 core. The ARM Cortex-M4 System IP Analog IP Digital IP Tools core retains all the advantages of the ® Hardware Cyclic 32-bit ARM Bundled IDE Cortex™-M4 Redundancy Check ARM Cortex-M3 core and adds new 16-bit ADC w/Processor Core w/DSP Expert digital signal processing capability in the Instructions I2C form of DSP extensions, a single cycle FlexMemory w/ Bundled OS EEPROM I2S (USB, TCP/IP, MAC unit and an optional single precision Capability Programmable Security) floating point unit. In addition, Freescale Gain Ampliﬁers Next-Generation UART/SPI Modular Tower Flash Memory has added a direct memory access (DMA) Hardware High Reliability, Development controller, cross bar switch and optional Fast Access Programmable Delay Block System 12-bit DAC on-chip cache memory which maximize Low-Voltage, Low-Power Application bus bandwidth and flash execution Multiple Operating External Bus Software Modes, Interface Stacks, performance, allowing CPU frequencies of Clock Gating Peripheral (1.71V–3.6V w/5V High-Speed Drivers and App. up to 150 MHz. Tolerant I/0) Comparators Motor Control Libraries Timers (Motor Control, Memory HMI, USB) Multiple Timers for Advanced Protection Unit Secure Digital Low-Power Host Controller DMA Motor Control Touch Sensing Broad Third-Party Ecosystem Kinetis MCUs contain multiple FlexTimer SRAM RTC modules for a wide range of control applications, including motor control with hardware dead-time insertion and quadrature decoding. A carrier modulator transmitter for generating infrared waveforms for remote control applications is standard on all devices.

14 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Connectivity and Reliability, Safety Value Communication Interfaces and Security Kinetis MCUs offer exceptional value Kinetis MCUs feature a number of Kinetis MCUs include a variety of with 10K starting prices from $0.99 connectivity peripherals, including USB data integrity and security hardware for for 32 KB flash memory devices 2.0 (full- and high-speed) device/host/ safeguarding memory, communication in a 32-pin package. On-The-Go with device charger detect and system data. A cyclic redundancy capability, Ethernet with IEEE® 1588 check module is available for validating Kinetis Product Families hardware time stamping for real-time memory contents and communication The first five general-purpose Kinetis industrial control and a multitude of serial data, while a memory protection MCU families are scheduled to sample interfaces, including UARTs with support unit provides data protection and in late 2010 with production planned for ISO7816 SIM/smart cards and increased software reliability. For fail- for early 2011. Additional families with IrDA interfaces. An Inter-IC Sound safe applications an independently application-specific peripherals sets will 2 (I S) serial interface supports the clocked watchdog offers protection follow throughout 2011. integration of audio processing hardware, against code runaway. When it comes while dual CAN modules enable industrial to security, a hardware encryption unit All Kinetis families are built around a network bridging. supports several encryption and hashing common set of system, analog and algorithms for program validation as well digital IP blocks. The level of peripheral Sophisticated Human- as authentication and securing data for integration within each family increases Machine Interfaces transfer and storage. The system security with flash memory size and pin count. module included on high-end MCU Families are distinguishable by their Human-machine interface options start families includes a unique chip identifier, performance, memory and peripheral with an Xtrinsic low-power touch-sensing secure key storage and a hardware capabilities as shown in the figure on interface (TSI). This provides a modern tamper detection system. The tamper page 12. upgrade from mechanical to touch detection system has integrated sensors keypad, rotary and slider user interfaces for voltage, frequency, temperature and and operates in all low-power modes. external sensing for physical attack A flexible low-power segment LCD detection. controller is offered on specific families with up to 512 KB flash and includes reduced power operation and segment Support for External failure detection capability. At the higher Peripherals and Memory end of the portfolio a graphics LCD Kinetis MCUs can interface to a variety controller supports up to QVGA resolution of external peripherals and memories for in single-chip configuration, or up to system expansion and data storage. A SVGA resolution using external memory. secure digital host controller supports In addition to the graphical user interface SD, SDIO, MMC or CE-ATA cards for options, the DSP capability of the ARM in-application software upgrades, media Cortex-M4 core combined with the I2S files, or adding Wi-Fi® support. For interface enable voice and audio user interfacing to external peripherals such interface options. as graphics displays, a FlexBus external bus interface is provided. NAND flash and DRAM controllers allow the connection of a wide variety of memory types.

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 15 Kinetis Microcontrollers

Kinetis K10 Family Low-power, mixed-signal MCUs

Overview Kinetis K10 Family The K10 MCU family is the entry point into the Kinetis portfolio. Devices start System Memories Clocks Core Internal and from 32 KB of flash in a small-footprint ® Program Phase-Locked ARM Cortex™-M4 External Flash RAM Loop 5 x 5 mm 32 QFN package extending up Watchdogs Frequency- Memory FlexMemory Cache to 1 MB in a 144MAPBGA package with Debug DSP Locked Loop Interfaces Protection a rich suite of analog, communication, Serial External Low/High- Frequency Interrupt Floating DMA Programming Bus timing and control peripherals.Additionally, Controller Point Unit Interface Oscillators pin compatibility, flexible low-power Low-Leakage NAND Flash Internal Wake-Up Controller Reference capabilities and innovative FlexMemory Clocks help to solve many of the major pain points for system implementation. Security Analog Timers Communication HMI

Cyclic 16-bit ADC Timers I2C x2 I2S x2 GPIO Redundancy x4 x4 (20 ch.) Check Ultra-Low Power Carrier Secure Hardware PGA x4 Modulator UART x6 Digital Touch-Sensing • 10 low-power modes with power and Transmitter Interface Analog SPI x3 Comparator x3 Programmable clock gating for optimal peripheral Delay Block

activity and recovery times. Stop 6-bit CAN x2 DAC x3 Periodic Interrupt currents of <500 nA, run currents Timers 12-bit of <200 uA/MHz, 4 µs wake-up DAC x2 Low-Power Timer from stop mode Voltage Reference Independent • Full flash programming and analog Real-Time Clock peripheral operation down to 1.71V for extended battery life • Low-leakage wake-up unit with up to eight internal modules and sixteen pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes • Low-power timer for continual system operation in reduced power state

16 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

K10 Family Summary

Memory Feature Options Packages

Part Numbers CPU (MHz) Flash (KB) FlexMemory (KB) SRAM (KB) Cache (KB) Precision Single Unit Point Floating CAN Memory Protection Unit Secure Digital Host Controller NAND Flash Controller External Bus Interface 12-bit Digital to Analog Converter Programmable Gain Amplifier 5VI/O Tolerant 32QFN (5x5 mm) 48QFN (7x7 mm) 48LQFP (7x7 mm) 64QFN (9x9 mm) 64LQFP (10x10 mm) 80LQFP (12x12 mm) 81BGA (8x8 mm) 100LQFP (14x14 mm) 104BGA (8x8 mm) 144LQFP (20x20 mm) 144BGA (13x13 mm)

MK10N32Vyy50 50 32 - 8 FM FT LF FX LH LK MB MK10N64Vyy50 50 64 - 16 FM FT LF FX LH LK MB MK10X32Vyy50 50 32 32 8 FM FT LF FX LH LK MB MK10X64Vyy50 50 64 32 16 FM FT LF FX LH LK MB MK10X128Vyy50 50 128 32 32 √ √ √ √ √ FX LH LK MB LL ML MK10X128Vyy72 72 128 32 32 √ √ √ √ √ FX LH LK MB LL ML MK10X256Vyy72 72 256 32 64 √ √ √ √ √ LK MB LL ML MK10X128Vyy100 100 128 128 32 √ √ √ √ √ √ √ LQ MD MK10X256Vyy100 100 256 256 64 √ √ √ √ √ √ √ LQ MD MK10N512Vyy100 100 512 - 128 √ √ √ √ √ √ √ LK MB LL ML LQ MD MK10X512Vyy120 120 512 512 128 16 √ √ √ √ √ √ √ √ √ LQ MD MK10N1M0Vyy120 120 1024 - 128 16 √ √ √ √ √ √ √ √ √ LQ MD

For details of peripherals offered on specific devices, please refer to the family product brief document at freescale.com. yy = package designator noted in the “Packages” column

Flash, SRAM and Mixed-Signal Capability Performance

FlexMemory • Up to four high-speed 16-bit ADCs • ARM Cortex-M4 core + DSP. • 32 KB–1 MB flash. Fast access, high with configurable resolution. Single 50–120 MHz, single cycle MAC, reliability with 4-level security protection or differential output mode operation single instruction multiple data • 8 KB–128 KB of SRAM for improved noise rejection. (SIMD) extensions, optional single 500 ns conversion time achievable with precision floating point unit • FlexMemory: 32 bytes–16 KB of programmable delay block triggering user-segmentable byte write/erase • Up to 32-channel DMA for EEPROM for data tables/system • Up to two 12-bit DACs for analog peripheral and memory servicing data. EEPROM with over 10M waveform generation for with reduced CPU loading and faster cycles and flash with 100 μsec write audio applications system throughput time (brownouts without data loss • Up to three high-speed comparators • Cross bar switch enables concurrent or corruption). No user or system providing fast and accurate motor multi-master bus accesses, increasing intervention to complete programming over-current protection by driving bus bandwidth and erase functions and full operation PWMs to a safe state • Up to 16 KB of instruction/data cache down to 1.71V. In addition, FlexNVM • Up to four programmable gain for optimized bus bandwidth and flash from 32 KB–512 KB for extra program amplifiers with x64 gain for small execution performance code, data or EEPROM backup amplitude signal conversion • Independent flash banks allowing • Accurate on-chip voltage reference concurrent code execution and eliminates need for accurate external firmware updating with no performance voltage reference IC reducing overall degradation or complex coding routines system cost Continued on next page

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 17 Kinetis Microcontrollers

Continued from previous page • Independent-clocked COP guards Tools and Software against clock skew or code runaway • Freescale Tower System hardware Timing and Control for fail-safe applications such as development environment the IEC 60730 safety standard for • Up to four FlexTimers with a total household appliances • Integrated development environments of 20 channels. Hardware dead-time º CodeWarrior for Microcontrollers insertion and quadrature decoding • External watchdog monitor drives v10.x (Eclipse) IDE with Processor for motor control output pin to safe state external components if watchdog event occurs Expert • Carrier modulator timer for infrared º IAR Embedded Workbench waveform generation in remote Keil MDK control applications External Peripheral Support º CodeSourcery Sourcery G++ (GNU) • Four-channel 32-bit periodic • FlexBus external bus interface º interrupt timer provides time base provides interface options to • Runtime software and RTOS for RTOS task scheduler or trigger memories and peripherals such º Math, DSP and encryption libraries source for ADC conversion and as graphics displays. Supports º Motor control libraries up to six chip selects programmable delay block º Complimentary bootloaders • Secure digital host controller supports (USB, Ethernet, RF, serial) Human-Machine Interface SD, SDIO, MMC or CE-ATA cards º Complimentary Freescale for in-application software upgrades, • Xtrinsic low power touch-sensing embedded GUI (eGUI) software media files or adding Wi-Fi support interface with up to 16 inputs. Operates driver for graphics LCD panels • NAND flash controller supports up to in all low-power modes (minimum º Complimentary Freescale MQX 32-bit ECC current and future NAND current adder when enabled). Hardware º Cost-effective Nano™ SSL/Nano™ types. ECC management handled implementation avoids software SSH for Freescale MQX RTOS polling method. High sensitivity level in hardware, minimizing º Micrium uC/OS-III allows use of overlay surfaces up software overhead º Express Logic ThreadX to 5 mm thick Target Applications º SEGGER embOS freeRTOS Connectivity and • Remote sensors º Mocana (security) Communications • HVAC systems º • Plus full ARM ecosystem • Up to six UARTs, with IrDA support • Gaming controllers including one UART with ISO7816 • Flow meters smart card support. Variety of data size, format and transmission/reception K10 Family: HVAC System settings supported for multiple industrial communication protocols Timers: • Drives various motor types including • Up to two Inter-IC Sound (I2S) serial DSP Hardware: stepper, BLDC and PMAC motors with • Accelerates motor control calculations interfaces for audio system interfacing sensor or sensorless algorithms DMA: • Built-in quadrature decoder detects motor speed • Up to two CAN modules • Off loads CPU from repetitive data transfers I,V FlexMemory: for industrial network bridging • Stores motor calibration data Power Stage Dive r A/C 2 • Up to three DSPI and two I C ADC Compressor Graphics SPI/FlexBus Motor LCD Kinetis Timers Reliability, Safety K10 MCU Touch-Sensing TSI Buttons ADC Auxilliary and Security Heater Timers Motor 2 • Memory protection unit provides I C, UART, SPI, CAN: I2C • Communicates memory protection for all masters with sensors I,V Optional and HMI Temperature on the cross bar switch, increasing processor Sensor 16-bit ADC and PGA: Analog Comparator: software reliability • Measures 3 phase bridge • Detects back EMF current and voltage • Monitors over current • Cyclic redundancy check engine Programmable Delay Block: validates memory contents • Schedules delayed ADC conversions relative to timer triggers and communication data, increasing system reliability

18 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Kinetis K20 Family Low-power MCUs with USB On-The-Go

Overview Kinetis K20 Family The K20 MCU family is pin, peripheral and software compatible with the K10 System Memories Clocks Core Internal and MCU family and adds full and high-speed ® Program Phase-Locked ARM Cortex™-M4 External Flash RAM Loop USB 2.0 On-The-Go with device charger Watchdogs Frequency- Memory FlexMemory Cache detect capability. Devices start from 32 Debug DSP Locked Loop Interfaces Protection KB of flash in 5 x 5 mm 32QFN packages Serial Low/High- Interrupt Floating External Frequency DMA Programming Bus extending up to 1 MB in a 144MAPBGA Controller Point Unit Interface Oscillators package with a rich suite of analog, Low-Leakage NAND Flash Internal Wake-Up Controller Reference communication, timing and control Clocks peripherals. High memory density K20 family devices include a single Security Analog Timers Communication HMI precision floating point unit and Cyclic 16-bit ADC Timers I2C x2 I2S x2 GPIO Redundancy x4 x4 (20-ch.) NAND flash controller. Check Carrier Secure Low-Power PGA x4 Modulator UART x6 Digital Xtrinsic Transmitter Touch-Sensing Interface Analog SPI x3 USB OTG Connectivity and Comparator x3 Programmable LS/FS/HS Communications Delay Block 6-bit CAN x2 USB Charger DAC x3 Periodic Detect Interrupt • USB 2.0 On-The-Go and device Timers 12-bit USB Voltage DAC x2 Regulator charger detect optimizes charging Low-Power Timer current/time for portable USB devices, Voltage Reference Independent enabling longer battery life. Integrated Real-Time USB low-voltage regulator supplies up Clock to 120 mA off chip at 3.3V to power external components from 5V input. Up to 480 Mbps with external ULPI PHY • Up to six UARTs with IrDA support, including one UART with ISO 7816 smart card support. Variety of data size, format and transmission/reception settings supported for multiple industrial communication protocols Continued on next page freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 19 Kinetis Microcontrollers

K20 Family Summary

Memory Feature Options Packages mm)

14x14 ( mm) (20x20 (8x8 mm) (7x7 mm) (10x10 mm) (12x12 mm) (13x13 mm) (8x8 mm) (5x5 mm) (7x7 mm) (9x9 mm)

Part Numbers

CPU (MHz) Flash (KB) FlexMemory (KB) SRAM (KB) Cache (KB) Precision Single Unit Point Floating CAN Memory Protection Unit Secure Digital Host Controller NAND Flash Controller External Bus Interface 12-bit Digital to Analog Converter Programmable Gain Amplifier 5VI/O Tolerant Other 32QFN 48QFN 48LQFP 64QFN 64LQFP 80LQFP 81BGA 100LQFP 104BGA 144LQFP 144BGA MK20N32Vyy50 50 32 - 8 USB OTG (FS) FM FT LF FX LH LK MB MK20N64Vyy50 50 64 - 16 USB OTG (FS) FM FT LF FX LH LK MB MK20X32Vyy50 50 32 32 8 USB OTG (FS) FM FT LF FX LH LK MB MK20X64Vyy50 50 64 32 16 USB OTG (FS) FM FT LF FX LH LK MB MK20X128Vyy50 50 128 32 32 √ √ √ √ √ USB OTG (FS) FX LH LK MB LL ML MK20X128Vyy72 72 128 32 32 √ √ √ √ √ USB OTG (FS) FX LH LK MB LL ML MK20X256Vyy72 72 256 32 64 √ √ √ √ √ USB OTG (FS) LK MB LL ML MK20X128Vyy100 100 128 128 32 √ √ √ √ √ √ √ USB OTG (FS) LQ MD MK20X256Vyy100 100 256 256 64 √ √ √ √ √ √ √ USB OTG (FS) LQ MD MK20N512Vyy100 100 512 - 128 √ √ √ √ √ √ √ USB OTG (FS) LK MB LL ML LQ MD MK20X512Vyy120 120 512 512 128 16 √ √ √ √ √ √ √ √ √ USB OTG (FS & HS) LQ MD MK20N1M0Vyy120 120 1024 - 128 16 √ √ √ √ √ √ √ √ √ USB OTG (FS & HS) LQ MD

For details of peripherals offered on specific devices, please refer to the family product brief document at freescale.com. yy = package designator noted in the “Packages” column

Continued from previous page Mixed-Signal Capability Performance

• Up to four high-speed 16-bit ADCs • ARM Cortex-M4 core + DSP. • Inter-IC Sound (I2S) serial interface with configurable resolution. Single 50–120 MHz, single cycle MAC, for audio system interfacing or differential output mode operation single instruction multiple data • Up to two CAN for industrial for improved noise rejection. (SIMD) extensions, single precision network bridging 500 ns conversion time achievable with floating point unit 2 • Up to three DSPI and two I C programmable delay block triggering • Up to 32-channel DMA for • Up to two 12-bit DACs for peripheral and memory servicing Flash, SRAM and analog waveform generation with reduced CPU loading and FlexMemory for audio applications faster system throughput • 32 KB–1 MB flash. Fast access, • Up to three high-speed comparators • Cross bar switch enables concurrent high reliability with four-level providing fast and accurate motor multi-master bus accesses, security protection over-current protection by driving increasing bus bandwidth • 8 KB–128 KB of SRAM PWMs to a safe state • Up to 16 KB of instruction/data cache • FlexMemory: 32 bytes–16 KB of • Up to two programmable for optimized bus bandwidth and flash user-segmentable byte write/erase gain amplifiers with x64 gain for execution performance EEPROM for data tables/system data. small amplitude signal conversion • Independent flash banks allowing EEPROM with over 10M cycles and • Accurate on-chip voltage reference concurrent code execution and flash with 100 μsec write time (brown- eliminates need for accurate external firmware updating with no performance outs without data loss or corruption). voltage reference IC reducing overall degradation or complex coding routines No user or system intervention to system cost complete programming and erase functions and full operation down to 1.71V. In addition, FlexNVM from 32 KB–512 KB for extra program code, data or EEPROM backup

20 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Human-Machine Interface Timing and Control External Peripheral Support

• Xtrinsic low-power touch-sensing • Up to four FlexTimers with a total • FlexBus external bus interface interface with up to 16 inputs. Operates of 20 channels. Hardware dead-time provides interface options to in all low-power modes (minimal insertion and quadrature decoding memories and peripherals such as current adder when enabled). Hardware for motor control graphics displays. Supports up to implementation avoids software • Carrier modulator timer for infrared six chip selects polling method. High sensitivity waveform generation in remote • Secure digital host controller supports level allows use of overlay control applications SD, SDIO, MMC or CE-ATA cards surfaces up to 5 mm thick • Four-channel 32-bit periodic interrupt for in-application software upgrades, timer provides time base for RTOS media files or adding Wi-Fi support Ultra-Low Power task scheduler or trigger source for • NAND flash controller supports up • 10 low-power modes with power ADC conversion and programmable to 32-bit ECC current and future and clock gating for optimal peripheral delay block NAND types. ECC management activity and recovery times. Stop handled in hardware, minimizing currents of <500 nA and run currents Reliability, Safety software overhead of <200 uA/MHz, 4 µs wake-up from and Security stop mode Tools and Software • Memory protection unit provides • Full flash programming and analog memory protection for all masters • Freescale Tower System hardware peripheral operation down to 1.71V on cross bar switch, increasing development environment for extended battery life software reliability • Integrated development environments • Low-leakage wake-up unit with up to • Cyclic redundancy check engine º CodeWarrior for Microcontrollers eight internal modules and sixteen validates memory contents v10.x (Eclipse) IDE with Processor pins as wake-up sources in low-leakage and communication data, Expert stop (LLS)/very low-leakage stop increasing system reliability º IAR Embedded Workbench (VLLS) modes • Independent-clocked COP guards º Keil MDK • Low-power timer for continual system against clock skew or code º CodeSourcery Sourcery G++ (GNU) operation in reduced power state runaway for fail-safe applications, • Runtime software and RTOS e.g. IEC 60730 º Math, DSP and encryption libraries Target Applications • External watchdog monitor drives Motor control libraries • Barcode scanners output pin to safe state external º Complimentary bootloaders • Portable media players components if watchdog event occurs º (USB, Ethernet, RF, serial) • Printers º Complimentary Freescale • Programmable logic controllers embedded GUI (eGUI) software driver for graphics LCD panels K20 Family: Universal Remote Control º Complimentary Freescale MQX FlexMemory: Touch-Sensing Low-Leakage Wake-up: º Cost-effective Nano SSL/Nano • Saves user deﬁned settings Buttons • Deep sleep wake-up controller • Stores display menus and graphics RTC: SSH for Freescale MQX RTOS • Clock source with optional TSI independent battery supply º Micrium uC/OS-III º Express Logic ThreadX Smart I2C Kinetis SEGGER embOS Battery º Charger IC K20 MCU CMT freeRTOS Infrared º USB Subsystem: º Mocana (security) • Conﬁguration and charging port to host PC ® • Plus full ARM ecosystem SDIO ZigBee • Detects type of charger and Wi-Fi® controls battery charger IC USB Bluetooth® • Firmware updates NAND RF4C Flash

NAND Flash Controller: • External storage for additional graphics/fonts freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 21 Kinetis Microcontrollers

Kinetis K30 Family Low-power MCUs with segment LCD

Overview Kinetis K30 Family The K30 MCU family is pin, peripheral and software compatible with the K10 MCU System Memories Clocks Core Internal and family and adds a flexible low-power ® Program Phase-Locked ARM Cortex™-M4 External Flash RAM Loop segment LCD controller with support Watchdogs Frequency- Memory FlexMemory for up to 320 segments. Devices start Debug DSP Locked Loop Interfaces Protection from 64 KB of flash in 64QFN packages Serial Low/High- Frequency Interrupt DMA Programming External extending up to 512 KB in a 144MAPBGA Controller Interface Bus Oscillators package with a rich suite of analog, Low-Leakage Internal Wake-Up Reference communication, timing and Clocks control peripherals. Security Analog Timers Communication HMI

Cyclic 16-bit ADC Timers x3 I2C x2 I2S GPIO Human-Machine Interface Redundancy x2 (12-ch.) Check • Xtrinsic low-power touch-sensing Carrier Secure Low-Power PGA x2 Modulator UART x6 Digital Xtrinsic Transmitter Touch-Sensing interface with up to 16 inputs. Operates Interface Analog SPI x3 Comparator x3 Programmable in all low-power modes (minimal Delay Block Segment LCD current adder when enabled). Hardware 6-bit CAN x2 DAC x3 Periodic Interrupt implementation avoids software Timers 12-bit polling method. High sensitivity DAC x2 Low-Power Timer level allows use of overlay Voltage Reference surfaces up to 5 mm thick Independent Real-Time Clock

22 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

K30 Family Summary

Memory Feature Options Packages

Part Numbers

CPU (MHz) Flash (KB) FlexMemory (KB) SRAM (KB) CAN Memory Protection Unit Secure Digital Host Controller External Bus Interface 12-bit Digital to Analog Converter Programmable Gain Amplifier 5VI/O Tolerant Other 64QFN (9x9 mm) 64LQFP (10x10 mm) 80LQFP (12x12 mm) 81BGA (8x8 mm) 100LQFP (14x14 mm) 104BGA (8x8 mm) 144LQFP (20x20 mm) 144BGA (13x13 mm) MK30X64Vyy50 50 64 32 16 N/A √ √ √ Segment LCD (up to 25x8/29x4) FX LH LK MB MK30X128Vyy50 50 128 32 32 √ √ √ √ Segment LCD (up to 36x8/40x4) FX LH LK MB LL ML MK30X128Vyy72 72 128 32 32 √ √ √ √ Segment LCD (up to 36x8/40x4) FX LH LK MB LL ML MK30X256Vyy72 72 256 32 64 √ √ √ √ Segment LCD (up to 36x8/40x4) LK MB LL ML MK30X128Vyy100 100128128 32 √ √ √ √ √ √ √ Segment LCD (40x8/44x4) LQ MD MK30X256Vyy100 100256256 64 √ √ √ √ √ √ √ Segment LCD (40x8/44x4) LQ MD MK30N512Vyy100 100512 - 128 √ √ √ √ √ √ √ Segment LCD (up to 40x8/44x4) LK MB LL ML LQ MD

For details of peripherals offered on specific devices, please refer to the family product brief document at freescale.com. yy = package designator noted in the "Packages" column

• Flexible, low-power LCD controller • Low-power timer for continual system • Independent flash banks allows with up to 320 segments (40x8 or operation in reduced power state concurrent code execution and 44x4). LCD blink mode enables firmware updating with no performance low average power while remaining Flash, SRAM and degradation or complex coding routines in low-power mode. Segment fail FlexMemory detect alerts the user to failures in Mixed-Signal Capability • 64 KB–512 KB flash. Fast the display which helps avoids the access, high reliability with • Up to two high-speed 16-bit ADCs possibility of an erroneous readout four-level security protection with configurable resolution. Single in medical applications. Frontplane/ or differential output mode operation backplane reassignment provides pin- • 16 KB–128 KB of SRAM for improved noise rejection. 500 ns out flexibility, easing PCB design, and • FlexMemory: 32 bytes–4 KB of conversion time achievable with allows LCD configuration changes via user-segmentable byte write/ programmable delay block triggering firmware with no hardware re-work. erase EEPROM for data tables/ • Up to two 12-bit DACs for Supports multiple 3V and 5V LCD panel system data. EEPROM with over analog waveform generation sizes with fewer segments (pins) than 10M cycles and flash with 100 μsec for audio applications competitive controllers and no external write time (brownouts without data components. Unused LCD pins can loss/corruption). No user or system • Up to three high-speed be configured as other GPIO functions intervention to complete programming comparators providing fast and and erase functions and full operation accurate motor over-current protection Ultra-Low Power down to 1.71V. In addition, FlexNVM by driving PWMs to a safe state from 32 KB–256 KB for extra program • Up to two programmable • 10 low-power modes with power code, data or EEPROM backup gain amplifiers with x64 gain for and clock gating for optimal peripheral small amplitude signal conversion activity and recovery times. Stop Performance • Accurate on-chip voltage reference currents of <500 nA and run currents eliminates need for accurate external of <200 uA/MHz, 4 µs wake-up • ARM Cortex-M4 core + DSP. voltage reference IC reducing overall from stop mode 50–100MHz, single cycle MAC, system cost • Full flash programming and analog single instruction multiple data Continued on next page peripheral operation down to 1.71V (SIMD) extensions for extended battery life • Up to 16-channel DMA for • Low-leakage wake-up unit with up peripheral and memory servicing to eight internal modules and sixteen with reduced CPU loading and faster pins as wake-up sources in low-leakage system throughput stop (LLS)/very low-leakage stop • Cross bar switch enables concurrent (VLLS) modes multi-master bus accesses, increasing bus bandwidth

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 23 Kinetis Microcontrollers

Continued from previous page Reliability, Safety Tools and Software and Security Timing and Control • Freescale Tower System hardware • Memory protection unit provides development environment • Up to three FlexTimers with a total memory protection for all masters • Integrated development environments of 12 channels. Hardware dead-time on cross bar switch, increasing º CodeWarrior for Microcontrollers insertion and quadrature decoding software reliability v10.x (Eclipse) IDE with for motor control • Cyclic redundancy check engine Processor Expert • Carrier modulator timer for infrared validates memory contents º IAR Embedded Workbench waveform generation in remote and communication data, increasing º Keil MDK control applications system reliability º CodeSourcery Sourcery G++ (GNU) • Four-channel 32-bit periodic • Independent-clocked COP guards • Runtime software and RTOS interrupt timer provides time base for against clock skew or code runaway RTOS task scheduler or trigger source for fail-safe applications, e.g. IEC60730 º Math, DSP and encryption libraries for ADC conversion and programmable • External watchdog monitor drives º Motor control libraries delay block output pin to safe state external º Complimentary bootloaders components if watchdog event occurs (USB, Ethernet, RF, serial) Connectivity and º Complimentary Freescale Communications External Peripheral Support embedded GUI (eGUI) software driver for graphics LCD panels • Up to six UARTs with IrDA support, • FlexBus external bus interface provides including one UART with ISO7816 interface options to memories and º Complimentary Freescale MQX smart card support. Variety of data peripherals such as graphics displays. º Cost-effective Nano SSL/Nano size, format and transmission/reception Supports up to six chip selects SSH for Freescale MQX RTOS settings supported for multiple • Secure digital host controller supports º Micrium uC/OS-III industrial communication protocols SD, SDIO, MMC or CE-ATA cards º Express Logic ThreadX • Up to two Inter-IC Sound (I2S) serial for in-application software upgrades, º SEGGER embOS interfaces for audio system interfacing media files or adding Wi-Fi support º freeRTOS • Up to two CAN for industrial Mocana (security) network bridging º • Plus full ARM ecosystem • Up to three DSPI and two I2C

Target Applications K30 Family: Bicycle Trip Computer

• Thermostats FlexMemory: • Smart meters • Saves bicycle conﬁguration data • Saves user exercise data • Heart rate monitors Cortex-M4 Core with DSP Support: Segment LCD: Segment • Blood gas analyzers • Signal processing for heart LCD • Up to 320 segments rate monitoring Touch-Sensing • Low-power “Blink” mode • 32-bit power for real-time Buttons calorie burn calculation Segment TSI LCD

Timer Speed CMT Infrared Kinetis Sensor K30 MCU ADC Heart Rate Sensor CMT: • PC data upload over infrared 16-bit ADC and PGA: • Pulse/heart rate sensor input • Ambient temperature sensor RTC: • Body temperature sensor • Very low-power time of day clock • Compass sensor • Altitude sensor Battery

24 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Kinetis K40 Family Low-power MCUs with USB and LCD

Overview Kinetis K40 Family The K40 MCU family is pin, peripheral and software compatible with the K10 System Memories Clocks Core Internal and MCU family and adds full-speed USB ® Program Phase-Locked ARM Cortex™-M4 External Flash RAM Loop 2.0 On-The-Go with device charger Watchdogs Frequency- Memory FlexMemory detect capability and a flexible low-power Debug DSP Locked Loop Interfaces Protection segment LCD controller with support Serial Low/High- Frequency Interrupt DMA Programming External for up to 320 segments. Devices start Controller Interface Bus Oscillators from 64 KB of flash in 64QFN packages Low-Leakage Internal Wake-Up Reference extending up to 512 KB in a 144MAPBGA Clocks package with a rich suite of analog, communication, timing and Security Analog Timers Communication HMI control peripherals. Cyclic 16-bit ADC Timers x3 I2C x2 I2S GPIO Redundancy x2 (12-ch.) Check Carrier Secure Low-Power PGA x2 Modulator UART x6 Digital Xtrinsic Connectivity and Transmitter Touch-Sensing Interface Analog SPI x3 USB OTG Communications Comparator x3 Programmable LS/FS Delay Block Segment LCD • USB 2.0 On-The-Go + device charger 6-bit CAN x2 USB Charger DAC x3 Periodic Detect Interrupt detect optimizes charging current/time Timers 12-bit USB Voltage DAC x2 Regulator for portable USB devices, enabling Low-Power Timer longer battery life. Integrated USB low- Voltage Reference Independent voltage regulator supplies up to 120 Real-Time mA off chip at 3.3V to power external Clock components from 5V input • Up to six UARTs with IrDA support including one UART with ISO7816 smart card support. Variety of data size, format and transmission/reception settings supported for multiple industrial communication protocols Continued on next page

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 25 Kinetis Microcontrollers

K40 Family Summary

Memory Feature Options Packages

Part Numbers

no 64 √ √ √ USB OTG (FS), Segment LCD MK40X64Vyy50 50 64 32 16 pin (up to 25x8/29x4) FX LH LK MB USB OTG (FS), Segment LCD MK40X128Vyy50 50 128 32 32 √ √ √ √ (up to 36x8/40x4) FX LH LK MB LL ML USB OTG (FS), Segment LCD 72 128 32 32 √ √ √ √ MK40X128Vyy72 (up to 36x8/40x4) FX LH LK MB LL ML USB OTG (FS), Segment LCD MK40X256Vyy72 72 256 32 64 √ √ √ √ (up to 36x8/40x4) LK MB LL ML USB OTG (FS), Segment LCD MK40X128Vyy100 100 128 128 32 √ √ √ √ √ √ √ (up to 40x8/44x4) LQ MD USB OTG (FS), Segment LCD MK40X256Vyy100 100 256 256 64 √ √ √ √ √ √ √ (up to 40x8/44x4) LQ MD USB OTG (FS), Segment LCD MK40N512Vyy100 100 512 - 128 √ √ √ √ √ √ √ (up to 40x8/44x4) LK MB LL ML LQ MD

For details of peripherals offered on specific devices, please refer to the family product brief document at freescale.com. yy = package designator noted in the "Packages" column

Continued from previous page Flash, SRAM and FlexMemory Mixed-Signal Capability

• 64 KB–512 KB flash. Fast • Up to two high-speed 16-bit ADCs • Up to two Inter-IC Sound (I2S) serial access, high reliability with with configurable resolution. Single interfaces for audio system interfacing four-level security protection or differential output mode operation • Up to two CAN for industrial network • 16 KB–128 KB of SRAM for improved noise rejection. bridging • FlexMemory: 32 bytes–4 KB of 500 ns conversion time achievable with • Up to three DSPI and two I2C user-segmentable byte write/erase programmable delay block triggering • Up to two 12-bit DACs for Human-Machine Interface EEPROM for data tables/system data. EEPROM with over 10M cycles and flash analog waveform generation • Xtrinsic low-power touch-sensing with 100 μsec write time (brownouts for audio applications interface with up to 16 inputs. Operates without data loss/corruption). No user • Up to three high-speed comparators in all low-power modes (minimal or system intervention to complete providing fast and accurate motor current adder when enabled). Hardware programming and erase functions and over-current protection by driving implementation avoids software polling full operation down to 1.71V. In addition, PWMs to a safe state method. High sensitivity level allows use FlexNVM from 32 KB–256 KB for extra • Up to two programmable of overlay surfaces up to 5 mm thick program code, data or EEPROM backup gain amplifiers with x64 gain for • Flexible, low-power LCD controller small amplitude signal conversion with up to 320 segments (40 x 8 or Performance • Accurate on-chip voltage reference 44 x 4). LCD blink mode enables • ARM Cortex-M4 core + DSP. eliminates need for accurate external low average power while remaining 50–100 MHz, single cycle MAC, voltage reference IC reducing overall in low-power mode. Segment fail single instruction multiple data system cost detect alerts the user to failures in (SIMD) extensions the display which helps avoids the possibility of an erroneous readout • Up to 16-channel DMA for peripheral in medical applications. Frontplane/ and memory servicing with reduced backplane reassignment provides pin- CPU loading and faster system out flexibility, easing PCB design and throughput allows LCD configuration changes via • Cross bar switch enables concurrent firmware with no hardware re-work. multi-master bus accesses, increasing Supports multiple 3V and 5V LCD bus bandwidth sizes with fewer segments (pins) than • Independent flash banks allow competitive controllers and no external concurrent code execution and components. Unused LCD pins can be firmware updating with no performance configured as other GPIO functions degradation or complex coding routines 26 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

Timing and Control Reliability, Safety Tools and Software

• Up to three FlexTimers with a total and Security • Freescale Tower System hardware of 12 channels. Hardware dead-time • Memory protection unit provides development environment insertion and quadrature decoding memory protection for all masters • Integrated development environments for motor control on cross bar switch, increasing º CodeWarrior for Microcontrollers • Carrier modulator timer for infrared software reliability v10.x (Eclipse) IDE with waveform generation in remote • Cyclic redundancy check engine Processor Expert control applications validates memory contents and º IAR Embedded Workbench • Four-channel 32-bit periodic communication data, increasing º Keil MDK interrupt timer provides time base system reliability º CodeSourcery Sourcery G++ (GNU) for RTOS task scheduler or trigger • Independent-clocked COP guards • Runtime software and RTOS source for ADC conversion and against clock skew or code runaway programmable delay block for fail-safe applications, e.g. IEC 60730 º Math, DSP and encryption libraries • External watchdog monitor drives º Motor control libraries Ultra-Low Power output pin to safe state external º Complimentary bootloaders (USB, Ethernet, RF, serial) • 10 low-power modes with power and components if watchdog event occurs clock gating for optimal peripheral º Complimentary Freescale activity and recovery times. Stop External Peripheral Support embedded GUI (eGUI) software driver for graphics LCD panels currents of <500 nA and run • FlexBus external bus interface provides currents of <200 uA/MHz, 4 µs interface options to memories and º Complimentary Freescale MQX wake-up from stop mode peripherals such as graphics displays. º Cost-effective Nano SSL/Nano • Full flash programming and analog Supports up to six chip selects SSH for Freescale MQX RTOS peripheral operation down to 1.71V • Secure digital host controller supports º Micrium uC/OS-III for extended battery life SD, SDIO, MMC or CE-ATA cards º Express Logic ThreadX • Low-leakage wake-up unit with up to for in-application software upgrades, º SEGGER embOS eight internal modules and sixteen pins media files or adding Wi-Fi support º freeRTOS as wake-up sources in low-leakage º Mocana (security) stop (LLS)/very low-leakage stop Target Applications (VLLS) modes • Plus full ARM ecosystem • GPS receivers • Low-power timer with continual system • Blood glucose meters operation in reduced power state • Bike computers • Currency counters

K40 Family: Thermostat

Segment FlexMemory: LCD • Saves user-deﬁned schedule • Remote update bootloader Periodic Interrupt Timers: • Stores display menus and graphics Segment • Periodically triggers ADC • Logs usage LCD conversion on sensor

Touch-Sensing TSI Kinetis ADC Temperature Buttons K40 MCU Sensor

Voltage Reference: Capacitive Touch Sensing: • Accurate voltage • Keypad buttons reference for sensor • Wake-up source

® SDIO ZigBee Wi-Fi® Battery USB Bluetooth® USB Subsystem: • Firmware updates

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 27 Kinetis Microcontrollers

Kinetis K60 Family Low-power MCUs with Ethernet and security

Overview Kinetis K60 Family The K60 MCU family includes IEEE 1588 Ethernet, full- and high-speed USB 2.0 System Memories Clocks Core Internal and On-The-Go with device charger detect ® Program Phase-Locked ARM Cortex™-M4 External Flash RAM Loop capability, hardware encryption and Watchdogs Frequency- Memory FlexMemory Cache Debug DSP Locked Loop tamper detection capabilities. Devices Interfaces Protection Serial Low/High- start from 256 KB of flash in 100LQFP Interrupt Floating External Frequency DMA Programming Bus packages extending up to 1 MB in a Controller Point Unit Interface Oscillators Low-Leakage NAND Flash DDR Internal 256MAPBGA package with a rich suite Wake-Up Controller Controller Reference Clocks of analog, communication, timing and control peripherals. High memory density Security Analog Timers Communication HMI K60 family devices include an optional Cyclic 16-bit ADC Timers I2C x2 I2S x2 GPIO Redundancy x4 x4 (20-ch.) single precision floating point unit, NAND Check Carrier Secure Low-Power PGA x4 flash controller and DRAM controller. Random Modulator UART x6 Digital Xtrinsic Number Transmitter Touch-Sensing Generator Interface Analog SPI x3 USB OTG Comparator x3 Programmable LS/FS/HS Reliability, Safety Hardware Delay Block Encryption 6-bit CAN x2 USB Charger DAC x3 Periodic Detect and Security Interrupt Tamper Timers Detect 12-bit IEEE 1588 USB Voltage • Hardware Encryption coprocessor for DAC x2 Ethernet Regulator Low-Power Timer secure data transfer and storage. Faster Voltage Reference Independent than software implementations and with Real-Time Clock minimal CPU loading. Supports a wide IEEE® 1588 variety of algorithms - DES, 3DES, AES, Timers MD5, SHA-1, SHA-256 • System security and tamper detect with secure real-time clock with independent battery supply. Secure key storage with internal/external tamper • Memory protection unit provides • Cyclic redundancy check engine detect for unsecure flash, temperature, memory protection for all masters validates memory contents and clock, and supply voltage variations on cross bar switch, increasing communication data, increasing and physical attack detection software reliability system reliability

28 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Kinetis Microcontrollers

K60 Family Summary

Memory Feature Options

Part Numbers

CPU (MHz) Flash (KB) Flex Memory (KB) SRAM (KB) Cache (KB) Precision Single Unti Point Floating CAN Memory Protection Unit Secure Digital Host Controller NAND Flash Controller External Bus Interface 12-bit Digital to Analog Converter Programmable Gain Amplifier 5VI/O Tolerant Other 100LQFP mm) (14x14 104BGA (8x8 mm) 144LQFP (20x20 mm) 144BGA (13x13 mm) 196BGA (15x15 mm) 12566BGA mm) (17x17 IEEE 1588 Eth, USB OTG (FS), MK60N256Vyy100 100 256 - 64 √ √ √ √ √ √ √ LL ML LQ MD CAU+RNG IEEE 1588 Eth, USB OTG (FS), MK60N512Vyy100 100 512 - 128 √ √ √ √ √ √ √ LL ML LQ MD CAU+RNG IEEE 1588 Eth, USB OTG (FS), MK60X256Vyy100 100 256 256 64 √ √ √ √ √ √ √ LL ML LQ MD CAU+RNG IEEE 1588 Eth, USB OTG (FS/HS), MK60X512Vyy120 120 512 512 128 16 √ √ √ √ √ √ √ √ √ LQ MD MF MJ CAU+RNG, Tamper Detect, *DRAM Ctrlr IEEE 1588 Eth, USB OTG (FS/HS), MK60X512Vyy150 150 512 512 128 16 √ √ √ √ √ √ √ √ √ LQ MD MF MJ CAU+RNG, Tamper Detect, *DRAM Ctrlr IEEE 1588 Eth, USB OTG (FS/HS), MK60N1M0Vyy120 120 1024 - 128 16 √ √ √ √ √ √ √ √ √ LQ MD MF MJ CAU+RNG, Tamper Detect, *DRAM Ctrlr IEEE 1588 Eth, USB OTG (FS/HS), MK60N1M0Vyy150 150 1024 - 128 16 √ √ √ √ √ √ √ √ √ LQ MD MF MJ CAU+RNG, Tamper Detect, *DRAM Ctrlr *256 pin packages only For details of peripherals offered on specific devices, please refer to the family product brief document at freescale.com. yy = package designator noted in the "Packages" column

• Independent-clocked COP guards External Peripheral Support • FlexMemory: 32 bytes–16 KB of user- against clock skew or code runaway for segmentable byte write/erase EEPROM • FlexBus external bus (bus interface fail-safe applications, e.g. IEC 60730 for data tables/system data. EEPROM provides interface options) provides • External watchdog monitor with over 10M cycles and flash with interface options to memories and drives output pin to safe state external 100 μsec write time (brownouts without peripherals such as graphics displays. components if watchdog event occurs data loss/corruption). No user or system Supports up to six chip selects intervention to complete programming Connectivity and • Secure digital host controller supports and erase functions and full operation SD, SDIO, MMC or CE-ATA cards Communications down to 1.71V. In addition, FlexNVM for in-application software upgrades, from 256 KB–512 KB for extra program • IEEE 1588 Ethernet MAC with media files or adding Wi-Fi support code, data or EEPROM backup hardware time stamping provides • NAND flash controller supports up precision clock synchronization for to 32-bit ECC current and future Performance real-time industrial control NAND types. ECC management • ARM Cortex-M4 core + DSP. • USB 2.0 On-The-Go + device charger handled in hardware, minimizing 100–150 MHz, single cycle MAC, detect optimizes charging current/ software overhead single instruction multiple data time for portable USB devices enabling • DRAM controller supports (SIMD) extensions, single longer battery life. Integrated USB low connection of DDR, DDR2 and precision floating point unit voltage regulator supplies up to 120 low-power DDR memories. Max. • Up to 32-channel DMA for mA off chip at 3.3V to power external frequency (clock/data) 125/250 MHz components from 5V input. Up to 480 peripheral and memory servicing Mbps with external ULPI PHY Flash, SRAM and with reduced CPU loading and faster system throughput • Up to six UARTs with IrDA support, FlexMemory including one UART with ISO 7816 • Cross bar switch enables concurrent • 256 KB–1 MB flash. Fast smart card support. Variety of data multi-master bus accesses, increasing access, high reliability with size, format and transmission/reception bus bandwidth four-level security protection settings supported for multiple • Up to 16 KB of instruction/data industrial communication protocols • 64 KB–128 KB of SRAM cache for optimized bus bandwidth • Up to two Inter-IC Sound (I2S) serial and flash execution performance interfaces for audio system interfacing • Independent flash banks allow • Two CAN for industrial concurrent code execution and network bridging firmware updating with no performance degradation or complex coding routines • Up to three DSPI and two I2C Continued on next page freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 29 Kinetis Microcontrollers

Continued from previous page Timing and Control Tools and Software

Mixed-Signal Capability • Up to four FlexTimers with a total • Freescale Tower System hardware of 20 channels. Hardware dead-time development environment • Up to four high-speed 16-bit ADCs insertion and quadrature decoding • Integrated development environments with configurable resolution. Single for motor control º CodeWarrior for Microcontrollers or differential output mode operation • Carrier modulator timer for infrared v10.x (Eclipse) IDE with for improved noise rejection. 500 ns waveform generation in remote Processor Expert conversion time achievable with control applications IAR Embedded Workbench programmable delay block triggering º • Four-channel, 32-bit periodic º Keil MDK • Up to two 12-bit DACs for analog interrupt timer provides time base º CodeSourcery Sourcery G++ (GNU) waveform generation for for RTOS task scheduler or trigger • Runtime software and RTOS audio applications source for ADC conversion and • Up to three high-speed programmable delay block º Math, DSP and encryption libraries comparators providing fast º Motor control libraries and accurate motor over-current Ultra-Low Power º Complimentary bootloaders protection by driving PWMs (USB, Ethernet, RF, serial) • 10 low-power modes with power and to a safe state clock gating for optimal peripheral º Complimentary Freescale • Up to four programmable activity and recovery times. Stop embedded GUI (eGUI) software driver gain amplifiers with x64 gain for currents of <500 nA and run currents for graphics LCD panels small amplitude signal conversion of <200 uA/MHz, 4 µs wake-up from º Complimentary Freescale MQX • Accurate on-chip voltage reference stop mode º Cost-effective Nano SSL/Nano eliminates need for accurate external • Full flash programming and analog SSH for Freescale MQX RTOS voltage reference IC, reducing overall peripheral operation down to 1.71V º Micrium uC/OS-III system cost for extended battery life º Express Logic ThreadX • Low-leakage wake-up unit with up to Human-Machine Interface º SEGGER embOS eight internal modules and sixteen pins º freeRTOS • Xtrinsic low power with up to 16 as wake-up sources in low-leakage º Mocana (security) inputs. Operates in all low-power stop (LLS)/very low-leakage stop modes (minimal current adder when (VLLS) modes • Plus full ARM ecosystem enabled). Hardware implementation • Low-power timer for continual system avoids software polling method. High operation in reduced power state sensitivity level allows use of overlay surfaces up to 5 mm thick K60 Family: Factory/Building Automation Controller Target Applications Mixed Signal: Touch-Sensing Capacitive Touch Sensing: • Sensor monitoring Buttons • Robust keypad • Building automation controllers • Load control • Robust slider input • Elevator control panels • Voltage and current measurement Graphics • Instrumentation clusters FlexBus IEEE® 1588 LCD • Surveillance cameras Distributed Ethernet Kinetis Control Network I2S (Sensors/Actuators) K60 MCU Audio Codec Speakers

Comprehensive Industrial Connectivity: ZigBee® SDIO • 10/100 Ethernet with 1588 Wi-Fi® • UARTs with RS485 and CAN ® Security Bluetooth for legacy protocols with Tamper • USB OTG Detection • SPI and I2C for peripheral systems • SDIO for wireless adaptors System Security: • IP protection • Communication protection • Tamper protection

30 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

Technical Highlights Technical Highlights

Core Technology ColdFire V1 core and ARM Cortex-M4 core

Freescale Semiconductor’s new 90nm Figure 1: ColdFire Family User Integer Programming Model 32-bit microcontroller families are built using the ColdFire V1 core and the ARM 31 0 Cortex-M4 core. Each core has attributes D0 Data Registers that make it the appropriate choice for D1 D2 many embedded application spaces. D3 D4 Version 1 ColdFire Core D5 Designed for 32-bit entry-level D6 applications, the primary focus of the D7 ColdFire V1 core is minimum core size 31 0 and power dissipation. A simplified A0 Address Registers version of the V2 ColdFire core, it A1 features improved handling of byte A2 (8-bit) and word (16-bit) operands, while A3 maintaining the same addressing modes A4 A5 and instruction definitions of the ColdFire A6 architecture. The core implements A7 Stack Pointer Revision C of the ColdFire instruction PC Program Counter set architecture. Figure 1 shows the user CCR Condition Code Register programming model, which includes: • 16 general-purpose 32-bit registers (8 data registers, D[0-7] and 8 address, A[0-7]) The enhanced multiply-accumulate gate cost. The coprocessor interface • 32-bit program counter (PC) (EMAC) unit included in the MCF51Qx/Jx allows a tightly coupled accelerator where families adds support for 16- and 32-bit the CPU fetches operands and sends • 8-bit condition code register (CCR) signed fractional numbers, compound commands to the hardware module. The ISA defines variable length operations MAC+MOVE instructions, circular Like all ColdFire processor where instructions can be 16, 32 or 48 memory queue addressing and four implementations, the ColdFire V1 core bits in length and include a powerful 48-bit accumulator registers. uses a 2-stage instruction fetch pipeline set of data memory addressing modes. The core architecture includes support (IFP) and 2-stage operand execution Supported data operand types are 1-, for generic coprocessor instructions pipeline (OEP) to provide an appropriate 8-, 16- and 32-bit integers. In addition and a hardware interface to accelerate hardware implementation to handle to memory-referencing load and store operations at the instruction or function the variable length instruction set. The operations, the ISA supports level. An example is the cryptographic core interfaces to the SoC via a single embedded load instructions and acceleration unity (CAU). The CAU 32-bit AMBA™ AHB bus. The IFP and memory-to-memory moves. provides a significant performance OEP memory interfaces are multiplexed boost to a number of security algorithms together and map directly into the popular today, including DES, AES, SHA1, 2-stage (address phase, data phase) SHA-256 and MD5 with a small hardware pipelined AHB bus.

32 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Figure 2: ARM® Cortex™-Mx Register Programming Model ARM Cortex-Mx cores are targeted at application spaces where overall size

r0 and deterministic operation are more r1 important than absolute performance. r2 As a result, the ARM Cortex-M4 r3 Low Registers core features a three-stage pipeline r4 microarchitecure: instruction fetch r5 (Fe), instruction decode (De) and, r6 r7 instruction execute (Ex). r8 The added DSP and SIMD instruction r9 High Registers r10 extensions are executed in a high-speed r11 multiply/accumulate structure; almost all r12 the multiply and optional accumulation r13 (SP) SP_process SP_main instructions have a single-cycle r14 (LR) execution time. r15 (PC) Program Status Register xPSR ARM Cortex-M4 implements multiple 32-bit bus interfaces that support a Harvard memory architecture. Specifically, the core provides a modified Harvard connection with AHB code and system buses. The code bus is typically used for instruction fetching and data accesses ARM Cortex-M4 Core Figure 2 shows the basic user of PC-relative data, while the system programming model, which includes: bus is typically used for RAM and The ARM Cortex-M4 core builds on peripheral accesses. A separate 32-bit the legacy of its ARM Cortex™-M3 • 13 general-purpose registers, r[0-12] private peripheral bus (PPB) connection predecessor and brings an intelligent stack pointer (r13 = SP), link register to several important modules (e.g, the blend of MCU and DSP features. The (r14 = LR), program counter (r15 = PC) Nested Vectored Interrupt Controller) is ARM Cortex-M4 implements the ARMv7- • Stack pointer, link register, accessible to only the core. ME™ instruction set architecture. This is program counter the ARM Thumb2 definition and provides • Multiple program status compatibility with ARM Cortex-M3 plus registers (xPSR) adds significant new capabilities with DSP and SIMD extensions. The basic The ISA defines variable length multiply-accumulate instructions support operations with 16 and 32-bit instructions. operations up to 32 x 32 + 64 –> 64. It supports data operand sizes of 8-, 16- The ARM Cortex-M4 core also supports and 32-bit integers plus fields of an optional single-precision floating-point 1–32-bit widths. unit (FPU) which includes an extension register file of 32 32-bit floating-point data registers.

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 33 Technical Highlights

Compatibility and Scalability Simplify design efforts and speed time to market

To simplify your application’s Figure 1: Compatibility of Kinetis Families hardware and software design, all the Kinetis microcontroller families have unprecedented compatibility Ethernet, Encryption, K60 Tamper Detection, and scalability. All families share DRAM Controller common characteristics spanning the features below: • Wide operating voltage range USB LCD from 1.71V to 3.6V with both flash K20 programming and analog operation down to 1.71V • Ambient operating temperature ranges K10 K40 from -40°C to +105°C • Flexible performance levels with devices rated at maximum CPU LCD K30 USB frequencies from 50 MHz to 150 MHz • Multiple package options from 32-pin QFN (5 x 5 mm body size) to

256-pin MAPBGA Table 1: Kinetis Family Differentiating Peripherals • Scalable embedded memory densities K10 Baseline from 32 KB flash/8 KB SRAM to 1 MB flash/128 KB SRAM with multiple K20 Baseline + USB flash arrays allowing read-while- write operations K30 Baseline + LCD • High-endurance, byte-writeable, embedded EEPROM from 32 bytes to K40 Baseline + USB + LCD 16 KB capable of exceeding 10 million read/write cycles Baseline + USB + Ethernet + Encryption + K60 Tamper Detect + DRAM Controller • Identical peripherals and memory maps simplifying code reuse • Powerful ARM Cortex-M4 core with built-in DSP instructions and optional single-precision FPU • Industry-standard serial wire debug, IEEE® 1149.1 JTAG, and IEEE 1149.7 compact JTAG debug interfaces along with ARM CoreSight™ architecture trace components • 10 power modes with power savings across run, wait and stop modes • Robust 5V-tolerant pin inputs

34 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Figure 2: Memory Comparison Across Kinetis Families WITHOUT FlexMemory The scalability within these options enables you to upgrade seamlessly or reduce your product costs by migrating 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB Flash/ Flash/ Flash/ Flash/ Flash/ Flash/ among the families without having to 8 KB 16 KB 32 KB 64 KB 128 KB 128 KB redesign common hardware and software. SRAM SRAM SRAM SRAM SRAM SRAM An upgrade to your product could be as K10 K10 simple as choosing a different derivative K20 K20 with augmented peripherals (see Table 1 K30 and Figure 1). K40 Another common reason to upgrade is K60 to increase the memory footprint, increase the performance level or add FlexMemory with EEPROM to your final design (see Figure 3: Memory Comparison Across Kinetis Families WITH FlexMemory Figures 2, 3 and 4). Likewise, you could reduce costs by removing similar features. 32 KB 64 KB 128 KB 256 KB 128 KB 256 KB 512 KB Flash/ Flash/ Flash/ Flash/ Flash/ Flash/ Flash/ Each family integrates both market- 32 KB 32 KB 32 KB 32 KB 128 KB 128 KB 256 KB FlexNVM FlexNVM FlexNVM FlexNVM FlexNVM FlexNVM FlexNVM focused and common embedded MCU /8 KB /16 KB /32 KB /64 KB /32 KB /64 KB /128 KB features. As pin counts increase with SRAM SRAM SRAM SRAM SRAM SRAM SRAM larger package options, more features K10 become available. Features can be K20 added while maintaining flexibility in body size, pitch and package types to best fit K30 your board manufacturing process and K40 product dimensions. K60 Continued on next page

Figure 4: Range of Maximum CPU Frequency Across Kinetis Families

50 MHz 72 MHz 100 MHz 120 MHz 150 MHz

K10 K20 K30 K40 K60

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 35 Technical Highlights

Compatibility and Scalability Continued from previous page

Packages include LQFP, QFN and Table 2: Package Types Across Kinetis Families MAPBGA options (see Table 2). Package Type Body Size Pitch Families

To provide exceptional compatibility, 32-pin QFN 5 X 5 mm 0.5 mm K10, K20 all Kinetis families were designed to be 48-pin QFN 7 X 7 mm 0.5 mm K10, K20 scalable yet pin-to-pin compatible or 48-pin LQFP 7 X 7 mm 0.5 mm K10, K20 drop-in replacements. 64-pin QFN 9 X 9 mm 0.5 mm K10, K20, K30, K40 Pin Compatibility 64-pin LQFP 10 X 10 mm 0.5 mm K10, K20, K30, K40 within an MCU Family 80-pin LQFP 12 X 12 mm 0.5 mm K10, K20, K30, K40

1. Changing your memory footprint 81-pin MAPBGA 8 X 8 mm 0.65 mm K10, K20, K30, K40 or performance tier within identical 100-pin LQFP 14 X 14 mm 0.5 mm K10, K20, K30, K40, K60 package types is a drop-in 104-pin MAPBGA 10 X 10 mm 0.65 mm K10, K20, K30, K40, K60 replacement, e.g. from a K30 family 144-pin LQFP 20 X 20 mm 0.5 mm K10, K20, K30, K40, K60 80-pin device with 128 KB of flash, 144-pin MAPBGA 13 X 13 mm 1.0 mm K10, K20, K30, K40, K60 to a K30 family 80-pin device with 256 KB of flash 196-pin MAPBGA 15 X 15 mm 1.0 mm K60 2. Changing between identical LQFP 256-pin MAPBGA 17 X 17 mm 1.0 mm K60 and QFN package types has no Figure 5: USB Figure 6: LCD Figure 7: Ethernet effect on pin ordering, e.g. from a K10 family 64LQFP device, to a K10 family I/O I/O I/O 64QFN device I/O LCD PWR I/O I/O / Ethernet I/O I/O I/O I/O 3. Features can be added with larger I/O USB I/O USB I/O I/O packages with minimal layout impact I/O I/O / LCD I/O I/O I/O I/OI/O USB

I/O I/O I/O Pin Compatibility across MCU Families 3. You can add Ethernet by migrating from 44-pin package. In addition, changing a K20 device to a K60 device in an from 64LQFP to 64QFN within a family 1. You can add USB by migrating from identical package type. The additional maintains the same pin ordering. a K10 device to a K20 device, or a Ethernet signals are multiplexed The benefit is that designs can easily K30 device to a K40 device, in an with other digital GPIO pins, so this implement dual package layouts which identical package with minimal board migration is a drop-in replacement. utilize QFN and LQFP footprints. layout changes by replacing four digital (see Figure 7) GPIO pins with four USB pins. Migrating across families (Jx to Qx) also (see Figure 5) ColdFire+ Compatibility requires a minimum set of changes. 2. You can add LCD by migrating from Only a small subset of pins (4 pins) will Coldfire+ families share the same a K10 device to a K30 device, or a K20 change when migrating between these compatibility characteristics as the device to a K40 device, in an identical devices. The benefit is that when adding Kinetis families. Within a family, changing package with minimal board layout or removing USB functionality, only your memory footprint is a drop in changes by replacing four digital minimal hardware changes are required. replacement. For example, MCF51JU32 GPIO pins with four LCD power in a 44-pin package is a drop in supply pins. The additional LCD replacement for the MCF51JU64 in a signals are multiplexed with other digital GPIO pins. (see Figure 6)

36 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

90nm TFS Flash and FlexMemory Configurable high-endurance embedded EEPROM

Freescale’s next-generation Conventional Floating Gate Bit Cell microcontrollers will offer exceptional low-power capability, performance and Polysilicon Charge Storage Medium flexibility through 90nm thin film storage (Conductor) (TFS) flash and FlexMemory technology. Control Gate TFS Flash Memory ONO Interpoly By combining split gate bit cell and Dielectric Floating Gate TFS technology, Freescale is bringing a powerful combination to the embedded market that offers several key advantages Source Drain versus competing technologies.

Split Gate Bit Cell Charges are Mobile • Flash access times of less than 30 ns. 30 to 50 percent faster than many competing technologies. ~ 100A Leakage Tunnel Path Due • Fast, low-voltage transistors Oxide to SILC, provide flash programming and analog etc. peripheral operation down to 1.71V and Substrate significantly reduced run and standby currents. Competing technologies are typically limited to 2.0V or above. • Excellent area efficiency (only a small FlexMemory as EEPROM Customer Benefits positive voltage pump is necessary Key Features for programming) enables a high level of memory and peripheral integration Programmable trade-off of EEPROM Flexibility: EEPROM size and endurance can quantity vs. endurance be customized to application needs across flash densities, while maintaining low MCU cost. Endurance of over 10M Longer EEPROM/product life Continued on next page write/erase cycles

Fast programming time allows intense Erase + write time of 1.5 ms EEPROM use with large data sets. Fast write time enables brown-out capability.

No software intervention necessary As simple as RAM from the user’s viewpoint

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 37 Technical Highlights

90nm TFS Flash and FlexMemory Continued from previous page

Silicon Nanocrystals Thin Film Storage Bit Cell

• Inherently robust design: Electrons Silicon Nanocrystal stored within the bit cell are distributed Charge Storage Medium (Isolated Conductors) among an array of silicon nanocrystals which are separated from each other Gate Poly by an insulator. • Inherently reliable: No single

nanocrystal is responsible for Source Drain maintaining the charge in the cell. If a leakage path develops beneath one nanocrystal, it may lose its stored “Immobile” Si charge, but the other nanoncrystals Charges Nanocrystal retain their charge—and the cell retains its data. 50–100A Oxide

FlexMemory 50–100A Oxide Freescale’s new FlexMemory technology Substrate provides an extremely versatile and powerful solution for designers seeking on-chip EEPROM and/or additional program or data flash memory. As easy and as fast as SRAM, it requires no user or system intervention to complete programming and erase functions Attribute Traditional EEPROM FlexMemory when used as high endurance byte- Read-while-write with Yes Yes write/byte-erase EEPROM. EEPROM program memory array size can also be configured for Granularity Byte write/erase Byte write/erase improved endurance to suit application ~100 μsec (word or byte requirements. FlexMemory can also Write time ~1–5 msec (byte write only) program, brown-outs without provide additional flash memory loss or corruption of data) (FlexNVM) for data or program storage in Erase + write time ~5–10 msec ~1.5 msec parallel with the main program flash. The SoC implementation and user user can configure several parameters Endurance 50–300K cycles (fixed) configurable, including EEPROM size, endurance, write over 10M cycles size and the size of additional program/ Minimum write voltage > 2.0V 1.71V data flash. On larger memory variants, Programmable trade-off of endurance figures of over 10M write/erase Flexibility Fixed by part number quantity vs. endurance cycles can be achieved. Additionally, designers can access the FlexRAM to expand system RAM for general application use.

38 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

FlexMemory FlexNVM • Can be used as part of the enhanced EEPROM configuration, or in addition to the main program or data flash • Can be sub-segmented into two blocks of memory. For example, a portion can Main Program Flash Array FlexNVM FlexRAM be used as flash while the rest is used for enhanced EEPROM backup and Firmware FlexController FlexRAM • Can be used as part of the EEPROM configuration FlexMemory High Endurance Byte-writeable EEPROM endurance The key features of FlexMemory include: Programmable Trade-Off is user configurable by two factors: • Configurability for designer: FlexMemory lets the user fully configure • Size of EEPROM º EEPROM array size and number of the way FlexNVM and FlexRAM blocks • Size of FlexNVM allocated to write/erase cycles are used to provide the best balance of EEPROM backup º Program or data flash size memory resources for their application. • EEPROM endurance of 10M write/erase The user can configure several Use Case Example parameters, including EEPROM size, cycles possible over full voltage and MCU has 128 KB program flash, 32 EEPROM endurance, byte-write and temperature range KB SRAM and FlexMemory has 128 read-while-write cycles, and the size of • Seamless EEPROM read/write KB FlexNVM and 4 KB FlexRAM additional program/data flash and RAM. operations: simply write or read a (maximum EEPROM size). The application In addition to this flexibility, FlexMemory memory address requires 8 KB additional program flash provides superior EEPROM performance, • High-speed byte, 16-bit, and 32-bit for a bootloader and 256 bytes of endurance and low-voltage operation write/erase operations to EEPROM high-endurance EEPROM. The user when compared to traditional • Eliminates the costs associated with would allocate 8 KB of FlexNVM for EEPROM solutions. external EEPROM ICs, and the software the additional program flash and the Enhanced EEPROM headaches and resource (CPU/flash/ remaining 120 KB for EEPROM backup. • Combines FlexRAM and FlexNVM to RAM) impact of EEPROM emulation The user would define 256 bytes of create byte write/erase, high-speed schemes EEPROM size from the FlexRAM. In this and high-endurance EEPROM example, the EEPROM endurance • Storage for large data tables or would result in a minimum of 2.32M bootloader write/erase cycles. • Read-while-write operation with main program flash memory • Minimum write voltage 1.71V

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 39 Technical Highlights

Power Management Multiple flexible low-power modes for long battery life

The power management controller Comparison of Power Modes provides the user with multiple power mode options. Ten modes of operation Typical Power Modes ColdFire+ and Kinetis ARM® Cortex™-M4 in an Embedded System Extended Power Modes Power Modes are supported to allow the user to optimize power consumption for the RUN level of functionality needed. RUN RUN VLPR There are several wake-up sources for the power modes. A low-leakage wake- WAIT up unit has up to eight internal peripheral WAIT SLEEP wake-up sources, as well as up to sixteen VLPW external pins for wake-ups. In the lowest power mode several wake-up sources STOP are available: low-power timer, real-time VLPS clock, analog comparator, DAC, capacitive touch-sensing Interface LLS and several pin interrupts. STOP DEEP SLEEP

Depending on the requirements of the VLLS3 user application, a variety of stop modes VLLS2 are available that provide state retention, partial power down or full power down of VLLS1 certain logic and/or memory. I/O states are held in all modes of operation. • Normal run mode allows the CPU to execute code with power consumption Key Features Customer Benefits as low as 200 uA/MHz. • Low-leakage stop mode reduces the Nano-amp current consumption with RAM retention Extended battery life voltage to internal logic, minimizing leakage from unused internal circuits. Wake-up time as low as 4 uS Minimize average power consumption in Keeps fast wake-up time down to 4 uS. frequent power mode change applications • Very low-leakage stop modes power Customize peripheral activity and recovery down the internal logic, and optionally Multiple low power modes times to suit application power budget RAM memory, eliminating leakage from unused circuits. This mode Device can be active with minimal 200 uA/MHz normal run mode power consumption keeps 32-byte register file content for critical application data. VLPR: Very Low Power Run VLPW: Very Low Power Wait VLPS: Very Low Power Stop VLL: Very Low Leakage

40 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Mode Brief Description Additional features for low-power/battery applications include: Run MCU can be run at full-speed. • Low-voltage detection can be Allows peripherals to function while CPU goes to sleep, reducing configured to generate a reset Wait power consumption. or interrupt to protect against CPU and peripheral clock maximum frequency is restricted. CPU/platform voltage drops. VLP Run clock is restricted to 2 MHz. Flash access is restricted to 1 MHz. LVD is off. º Supports two low-voltage detection VLP Wait Similar to VLP Run, with CPU in sleep to further reduce power. trip points Four low-voltage warning levels Stop MCU is in static state. Lowest power mode that retains all registers while º maintaining LVD protection. per trip point MCU is in static state with LVD operation off. Lowest power mode with • Programmable clock gating allows VLP Stop ADC, LPT, RTC, LCD, HSCMP, DAC and pin interrupts functional. an application to shut down unused MCU is in low-leakage state retention power mode. LLWU controls wake-up peripheral clocks to further minimize LL Stop sources including LPT, RTC, LCD, HSCMP, DAC and select pin interrupts. power consumption in run and MCU is placed in a low-leakage mode powering down most internal logic. wait modes. All system RAM contents are retained and I/O states held. LLWU controls VLL Stop3 wake-up sources, including LPT, RTC, LCD, HSCMP, DAC and select pin interrupts. Low-leakage wake-up unit: • Supports up to sixteen external input Similar to VLL Stop 3, with only partial system RAM retention. FlexRAM VLL Stop2 contents can optionally be retained. pins and up to eight internal modules with individual enable bits. VLL Stop1 Similar to VLL Stop 3, with only 32 byte register file retention. • Input sources may be external pins or Description of Power Modes from internal peripherals capable of running in LLS or VLLS modes. • Each external pin wake-up input is programmable as falling edge, rising edge or any change. • An optional low-power oscillator (LPO) cycle digital filter provided to qualify an external pin detect and RESET pin detect.

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 41 Technical Highlights

Xtrinsic Low-Power Touch-Sensing Interface Attractive user interfaces with low power appeal

Touch sensing offers a modern TSI Module Overview alternative to traditional push-button switches through the creation of touch- Control, Status and Results Registers activated push-button, slider and rotary user interfaces. Benefits include design Capacitance Window Change flexibility, low maintenance, cleanliness Compare Interrupt and the ability to support a variety of sensitivity levels and overlay surfaces. Capacitance External Value The use of touch-sensing interfaces now Pads CLK extends beyond the latest consumer Pad0 Reference 16-bit Counter Oscillator

products into domestic appliances, Pad1 Cap Switch EN portable medical devices and industrial Electrode Prescaler control panels. Oscillator /M

The touch-sensing input (TSI) module Pad15 provides capacitive touch-sensing Error Interrupt Trigger Unit Error (Overrun or Short detection with high sensitivity, enhanced Detection Detection) robustness and extreme low-power End-of-Scan Interrupt performance. The module’s key Run/Low-Power features are: Modes • Up to 16 electrodes, using a single pin per electrode, with no need for an external component Key Features Customer Benefits • Functional in all low-power modes, waking the CPU only in the event of Operational in all low power modes with only minimal current adder when Ideal for battery-powered applications electrode capacitance variations enabled • Minimal current adder when enabled • Capacitance measurement resolution down to 0.02fF Fault detection capability Robust performance in noisy environments • Electrode sampling integration: variable electrode sampling period for increased noise robustness in noisy environments High sensitivity capacitance High sensitivity allows use of thick glass, • Fault detection: detects electrode measurement resolution down to 0.02fF plastic and flexi-glass overlay surfaces short circuits and sample time misconfigurations Fully compatible with CodeWarrior IDE. • Periodic electrode scan mode requires Includes smart auto-calibration mechanisms to prevent environmental issues, noise rejection no additional MCU peripheral Fully integrated with Freescale’s algorithms, an optimized buffer structure Touch-Sensing Software (TSS) Library enabling any arrangement of electrodes and a PC GUI application for electrode characterization that includes demos and application examples

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ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Low-Power Mode Operation Low-Power Mode Operation The TSI module has programmable high and low thresholds and can be enabled in Only 1–3 uA Current Adder all low-power modes with minimum current consumption.

Threshold High An internal periodic scan module is active in all MCU power modes and has Threshold Low separate scan intervals for low-power and run modes. This allows the user to

Capacitance Electrode MCU In set longer scan intervals for minimizing Run Mode MCU In Low-Power Mode power consumption. Conversely, in run Time mode the application can set shorter scan intervals for faster touch response.

Touch-Sensing Software Library The low-power capabilities of the TSI module open up new touch-sensing Application application spaces for touch sense interfaces. Such devices are now able to be woken up from sleep states via a System Decoders Conﬁguration and touch input. Management Keypad Rotary Slider TSS Library When a touch occurs, the instantaneous electrode capacitance is detected to System Setup Key Detector be out of the threshold-defined range. This issues a TSI interrupt, which in turn

Touch Sensing Module (TSI) TSI wakes up the CPU. Module Touch-Sensing Library Integration Several applications require the implementation of keypad, rotary and slider user interfaces. Operating environment, desired response time and sensitivity to touch detection all need to be considered according to application requirements.

Freescale provides a complete touch solution with a touch-sensing module that is seamlessly integrated with the Freescale Touch Sensing Library.

Visit freescale.com/touchsensing for more information on touch-sensing software solutions. freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 43 Technical Highlights

Segment LCD Controller A configurable, low-power display

The Kinetis K30 and K40 MCU families LCD Module Overview include a flexible segment LCD controller that offer a number of benefits for cost- ALTDIV Prescaler Frame Rate Clock LCDIF effective GUI-enabled designs. Features LCLK BRATE LCDIEN include software-configurable frontplanes DUTY LADJ SOURCE and backplanes, low-power blink modes Backplane Sequencer and fault-detection capabilities as well ALT BLINK as support for a broad range of 3 and 5V BLANK BMODE Fault Detection LCD panels. Default Clock = 32.768 kHz 8 BP Phases FDPRS FDEN FDSWW FDBP The segment LCD controller is used to Alternate Clock Sequenced FP of BP Data drive monochrome LCD displays in all LCD Waveform Registers CPU modes of operation, including very MUX LCD [x] low-leakage stop modes. Key features of PxEN FP or BP V V this peripheral include: BxPEN DD IREG • Fault detection hardware alerts the user to faults in the display, the display Charge Pump VLL1 V connector, and the board connections VSUPPLY LL2 CPSEL RVEN VLL3 between the MCU and the display Vcap1 0.1uF Vcap2 • Low-power blink mode operation allows segments to be turned on and off at set intervals conserving power in stop modes • Configurable frame rate and duty cycle up to x8 • Internally regulated voltage to support contrast control • Drive for 3V or 5V LCD glass • Multi-purpose LCD pins which support backplane/COM, frontplane/SEG or GPIO functions

Key Features Customer Benefits

Avoids erroneous reading of LCD display by alerting the user to faults in the display, the display connector and the board connections between the MCU and the display. Segment fault detection Example: In medical applications, prevents the user from interpreting a potentially unsafe readout and prescribing improper treatment (dosage level)

LCD pins can be configured as frontplane Board layout can be optimized to the LCD. Changes to the LCD design can be handled or backplane by firmware, avoiding costly hardware changes

Low-power blink mode operation—blink to blank screen or blink to alternate screen at Lower average power 1/8s, 1/4s, 1/2s, 1s, 2s, 4s and 8s intervals

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ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 ••

Frontplane and Backplane The frontplane or backplane Segment Fault Detection assignment can be optimized to Reassignment The segment LCD controller has hardware match the layout of the LCD display The segment LCD control registers can support for detecting faults on the LCD by software configuration. configure any LCD pin to be a frontplane pins. Failures, where an LCD segment or a backplane LCD signal. Changes to LCD display design can be is either unexpectedly on or off, result in handled by firmware updates, reducing erroneous information that can mislead cycle time and hardware cost. the user.

Fault Detection The LCD display fault-detect circuits can be used to find faults in the LCD display, display connector and board connections between the MCU and the display.

Tsww Conﬁgure by FDSWW Hardware is used to sample and digitize generated LCD waveforms. The digitized 1 1 1 1 1 1 1 0 0 data can be analyzed for changes in LCD 0 capacitances that indicate faults. 0 0 Blink in Low-Power Modes LCD[FDPINID] The segment LCD controller supports blink to blank screen or blink to alternate

sample_clk screen while in low-power modes.

T sample Blinking to a blank screen turns all

Sample the LCD[FDPINID] segments off. Blinking to an alternate at posedge of sample clock screen allows different display data to be shown during the configurable Blink Mode Timing blink period.

78° 78° With this function, the MCU can achieve lower average power consumption Kinetis LCD controller by supporting LCD blinking without Low-Power Mode exiting the low-power mode, as shown in this diagram. Traditional LCD controller RM RM RM RM Refer to freescale.com/LCD Low-Power Mode for more information.

7:54:01 7:54:02 7:54:03 7:54:04

Kinetis LCD controller RM RM Low-Power Mode

Traditional LCD controller RM RM RM RM Low-Power Mode

RM = RUN MODE freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 45 Technical Highlights

Precision Analog and Control Rich on-chip mixed signal capability

Analog-to-Digital Converter ADC Block Diagram The 16-bit resolution analog-to-digital Channel Select converter (ADC) module uses the successive-approximation register (SAR) method, which is faster and consumes Trigger Single Ended Control less power than the sigma-delta method. It also uses averaging to enhance the resolution. Key features of the ADC Control Sequencer module include: CLK • Support for single-ended or differential inputs 16-bit Interrupt Converter Control • Averaging by 1, 4, 8, 16 or 32 Differential • Automatic compare function Offset • Triggering synchronization with DAC Control • Configurable for 8-,10-,12- or 16-bit resolution mode to manage trade- offs between speed and accuracy Averager depending on application requirements Internal Ref Formating

Data Compare Register Logic

Peripheral Key Features Customer Benefits

• Successive approximation architecture • Significantly faster and lower power than • Averaging sigma delta (SD) ADC types. Resolution • Self-test method is comparable to SD types when averaging 16-bit analog-to-digital converter is employed (ADC) • Interleaving

• Differential inputs • Improved noise rejection, dynamic range and • Offset and gain calibration measurement accuracy

• Operation in low-power modes • Increased battery life 12-bit digital-to-analog converter (DAC) • No CPU intervention required for waveform • Watermark FIFO generation–increased system performance

• Internal DAC • On-chip configurable voltage reference

High-speed comparator (HSCMP) • Input signal flexibility for monitoring multiple • Analog MUX sources

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Digital-to-Analog Converter The 12-bit digital-to-analog converter (DAC) provides a voltage output from a given digital value. Key features of the DAC module include: • Output to external pin or internal connection to other peripherals • Operation in stop modes • Multiple modes: Swing, one-time scan or normal • Multiple hardware interrupt request sources: Top or bottom HSCMP Block Diagram positions or watermark

VRSEL High-Speed Comparator V V in1 in2 (HSCMP) The on-chip high-speed analog VOSEL[5:0] MUX comparator modules provide a fast DACEN interrupt when monitoring an internal DAC Output or external signal. The modules main

MUX features include: 64-level

Enable ANMUX DAC • Operation over the entire voltage Input Pins supply range ANMUXPEN[7:0] • Programmable hysteresis control PSEL[2:0] • Internal 6-bit DAC module with External Reference 0 HSCMP External Reference 1 internal connection External Reference 2 External Reference 3 External Reference 4 • Internal input signal multiplex unit

External Reference 5 MUX External Reference 6 provides flexibility External Reference 7 Window IRQ ANMUX ACMP and Filter Continued on next page Control

ACO MUX

NSEL[2:0]

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 47 Technical Highlights

Continued from previous page Curve: VREF (V) x Temperature (ºC)

Voltage Reference 1.201 Highest The voltage reference (VREF) is intended Typ to supply an accurate voltage output 1.2 Lowest that is trimmable by an 8-bit register in 0.5 mV steps. 1.199 • Peripherals that can use VREF include 1.198 ADC, DAC and HSCMP

• Off-chip peripherals can access the 1.197 VREF output signal through the voltage (V) Voltage reference output (VREFO) pin 1.196 • High-power mode for external use 1.195 • Temperature variation less than 33 ppm/C from 0º to 50ºC 1.194 100 125 150 -50 -25 25 50 75 Programmable 0

Delay Block Temperature (ºC) The programmable delay block (PDB) enables timing synchronization between multiple internal or external peripherals. PDB Block Diagram Use case examples include: • In BLDC motor control applications, to External Pin measure the back EMF voltage with the HSCMP, the PDB synchronizes a few FlexTimer microseconds after the FlexTimer pulse width modulation (PWM) rising-edge RTC and creates a sample window mode HSCMP PIT • In general motor control applications,

the PDB measures voltages and Software PDB currents for synchronizing the FlexTimer Trigger HSCMPADC PWM and the ADC module • In metering applications, the PDB Programmable Delay Block measures both voltage and current with DAC PDB Output the ADC, synchronized with one of the (16-bit Counter) timer modules • In medical applications, the PDB (9 16-bit Registers) provides a hardware trigger for the ADC and at the same time advances the DAC buffer pointer for signal conditioning

Peripheral Key Features Customer Benefits

Higher accuracy, temperature, process and voltage deviation correction. Eliminates Voltage reference (VREF) Trimming: 8-bits register for 0.5 mV step need for external voltage reference, reducing overall system cost

Multiple peripheral integration modes for Single set of peripherals can support a wide Programmable delay block (PDB) time-sensitive applications range of applications

Hardware dead timer insertion and FlexTimer (FTM) quadarature decode Suitable for motor control applications

48 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

FlexTimer Block Diagram FlexTimer The FlexTimer module (FTM) is designed for motor control and power management Ch 0 FTM applications but also retains standard Ch 1 x4 timer features, such as output compare or

Up To 40 MHz Channel 0 input capture functions. In motor control

Capture Filter A environments, the FlexTimer provides 16-bit Counter complementary signal generation, Compare Pin Triggers to Other Timers Ch. 0 and Peripherals hardware dead time generation, mask, Fault I/O Protection Polarity n polarity and fault control capabilities— Signal Combine Channel 1 Conditioning I/O features typical of dedicated PWM

Pin modules. This flexibility makes the Dead Time Insertion Ch. 1 Compare Fault FlexTimer suitable for a wide range Protection Polarity n+1

Capture Filter B of applications.

Motor Control Example Application Example: BLDC Motor Control The peripheral sets for the ColdFire+ Qx/Jx and Kinetis microcontroller families MCU DEVICE enable 6-step vector control for brushless CH0/1 Fault DC motor control using a sensorless 6-ch. FTM0 CH2/3 algorithm. The high-speed comparator is PWM Ctrl used for back EMF detection, the 16-bit CH4/5 M 3-ph. Inverter ADC for DC bus measurements and the 3 FlexTimer in PWM mode. This enables a HSCMP list of differentiating features, including: or Speed/ Torque 3 ADC Control • Automatic dead-time insertion BLDC Motor BEMF Detect • Automatic duty-cycle load on channel pairs HSCMP • Independent control of both edges or

2 ADC • Maskable output

DC Bus Voltage and Current DCBus/Fault SCI • Hardware input fault pin • Event trigger inputs and outputs enable time-sensitive tasks Application Example: PMAC Motor Control Permanent magnet sinusoidal motors (PMAC) are popular due to their MCU DEVICE high energy efficiency and precise CH0/1 Fault control. The ColdFire+ Qx/Jx and Kinetis

CH2/3 microcontroller families offer several 6-ch. FTM0 features to enable full three-phase vector CH4/5 M Quadrature control: Encoder • FlexTimer with advanced PWM features

PHA CH0/1 • FlexTimer with quadrature decoder 2-ch. FTM1 PHB mode for speed detection Speed Vector PMAC Motor Measurement Control • Fast 16-bit SAR ADC for current and DCbus voltage measurement Voltage ADC

3-ph. • High-speed comparator for additional 3-ph. Current Currents and Voltage fault detection

Over • DSP instruction capabilities for high- HSCMP SCI Current speed calculations

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 49 Technical Highlights

Clocking System Multi-purpose clock generator

The clocking system generates the clock Clock Diagram signals necessary to drive the core, platform peripherals (USB, DMA) and 32K IRC MCG bus_clk DIV-j CG Peripheral_Clock other general-purpose peripherals. The 2M IRC ICSOUT multi-purpose clock generator (MCG) core_plat_clk DIV-k CG Platform_Clock is at the heart of the clocking system DCO FLL bus_div_clk and controls how system clocks are DIV-l CG FlexBus generated. Separate clock divider control ﬂash_clk allows individual clocks to be fractionally DIV-m CG FTFL divided and optimized for lower power PLL USB 48MHz operation. FLLCLK DIV-n CG USB PLLCLK Depending on the input clock source and SSI, eSDHC the system clock speeds required, the DIV MCG can be placed into eight different OSC modes of operation. The state diagram below highlights the different modes. For a full description, see the following table. MCG State Diagram

Each of the MCG modes can meet a different set of clocking requirements. FEI FEE This allows end applications to be optimized for cost, performance or power consumption. The MCG allows the user to easily change between modes. FBI FBE

BLPI BLPE

PBE

PEE

Key Features Customer Benefits

Lower system cost can be met with Low- and high-frequency internal references for system clock generation no crystal configurations to achieve maximum performance

Frequency-locked or phase-locked MCG can be used in FLL or PLL modes. PLL loop operation modes allow for reduced jitter

Loss-of-lock and loss-of-clock Interrupts or resets can be generated based protection circuits on the state of the MCG clock source

50 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

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Mode Description

In FEI mode, MCGOUT is derived from the FLL clock (DCOCLK), which is controlled by the 32 kHz internal FLL Engaged reference clock (32 kHz IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by Internal (FEI) the DRS[1:0] and DMX32 bits, multiplied by the internal reference frequency (32 kHz IRC). In FEI mode the PLL is disabled in a low-power state unless PLLCLKEN is set.

In FEE mode, MCGOUT is derived from the FLL clock (DCOCLK), which is controlled by the external FLL Engaged reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by the DRS[1:0] External (FEE) and DMX32 bits, multiplied by the external reference frequency, as specified by the MCGC1[FRDIV] and MCGC2[RANGE]. In FEE mode the PLL is disabled in a low-power state unless PLLCLKEN is set.

In FBI mode, the MCGOUT clock is derived either from the slow (32 kHz IRC) or fast (2 mHz IRC) internal reference clock, as selected by the IRCS bit. The FLL is operational but its output is not used. This mode FLL Bypassed is useful to allow the FLL to acquire its target frequency while the MCGOUT clock is driven from the IRCS selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow (32 kHz IRC) internal Internal (FBI) reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by the DRS[1:0] and DMX32 bits, multiplied by the 32 kHz internal reference frequency. In FBI mode the PLL is disabled in a low-power state unless PLLCLKEN is set.

In FBE mode, the MCGOUT clock is derived from the external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the FLL Bypassed MCGOUT clock is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the External (FBE) external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by the DRS[1:0] and DMX32 bits, multiplied by the internal reference frequency. In FBI mode the PLL is disabled in a low-power state unless PLLCLKEN is set.

PLL Engaged In PEE mode, the MCGOUT is derived from the PLL clock, which is controlled by the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by MCGC6[VDIV], multiplied by External (PEE) the external reference frequency, as specified by MCGC5[PRDIV]. The FLL is disabled in a low-power state.

In PBE mode, MCGOUT is derived from the external reference clock. The PLL is operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while MCGOUT PLL Bypassed is driven from the external reference clock. The PLL clock frequency locks to a multiplication factor, as External (PBE) specified by MCGC6[VDIV], multiplied by the external reference frequency, as specified by MCGC5[PRDIV]. The FLL is disabled in a low-power state.

Bypassed Low-Power In BLPI mode, MCGOUT is derived from the internal reference clock. The FLL is disabled and PLL is Internal (BLPI) disabled even if the PLLCLKEN is set to 1.

Bypassed Low-Power In BLPE mode, MCGOUT is derived from the external reference clock. The FLL is disabled and PLL is External (BLPE) disabled even if the PLLCLKEN is set to 1.

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 51 Technical Highlights

IEEE® 1588 Ethernet Controller Real-time networked measurement and control

The Ethernet controller module, Ethernet Controller Block Diagram in conjunction with an external 10/100 Ethernet PHY, is used to add Ethernet connectivity. Hardware IEEE TOE Functions MAC 1588 time stamping provides precision RX Control Receive TCP/IP MII clock synchronization for real-time Application Receive Performance Receive FIFO Interface Optimization Pause Interface control in networked automation, CRC Frame Check Terminate test and measurement applications. Features of the Ethernet TX Control controller include: Transmit TCP/IP MII Application Transmit Performance Transmit FIFO Interface Optimization Pause Interface • Full implementation of CRC Frame Generate Generate the 802.3 specification • Supports MII and RMII interfaces PHY Conﬁguration MDIO to external PHY Management Statistics Master Interface • Supports Advanced Micro Devices (AMD) Magic Packet detection Register Interface • Support for VLAN-tagged frames (IEEE 802.1Q) • IP protocol performance optimizations • Hardware time stamping support for IEEE 1588 Key Features Customer Benefits

AMD Magic AMD Magic Packet detection Lower average power consumption Packet Detection

This utility allows an external node IP protocol performance optimizations Higher Ethernet throughput to make a remote wake-up request.

When Magic Packet detection is enabled, Reduced latency vs. software IEEE 1588 hardware time stamping implementations–100 nS accuracy the Ethernet controller can be put into (network dependant) sleep mode and/or the processor can enter stop mode. In this mode: • Ethernet transmit logic is disabled • Ethernet FIFO receive/transmit functions are disabled • Ethernet receive logic is kept in normal mode, but all incoming traffic except for Magic Packets are ignored

When a Magic Packet is detected, a wake-up request is sent to the core that can be used to exit the processor from stop mode.

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ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •

IPv4 and IPv6 Checksum Calculations IP Protocol Optimization The Ethernet controller module includes IPv4 Pseudo Header for Checksum Calculation hardware logic that can handle a range of

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 common Ethernet protocol functions. Source Address This helps to decrease the software Destination Address overhead required for Ethernet stacks and Zero Protocol TCP/UDP Length can increase overall Ethernet throughput.

Features include: IPv6 Pseudo Header for Checksum Calculation • Support for TCP/IP, UDP/IP, ICMP/IP and IP header-only protocols in IPv4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 and IPv6 formats Source Address • Automatic IP header and payload (protocol specific) checksum generation and calculation Destination Address • Transparent passing of frames of other types and protocols TCP/UDP Length For TCP and UDP, the checksum is Zero Next Header calculated over the header and data sections along with some values from the IP header. The diagram below shows the Adjustable Timer IP header fields that are used for TCP and UDP checksum calculations.

Counter IEEE 1588 Support The Ethernet controller includes a hardware time-stamping module to ENETn_ATPER Mod support IEEE 1588 or similar time synchronization protocol implementations.

The adjustable timer module is used to synchronize the Ethernet controller’s

To MAC local clock to a remote master. There External Clock Input is a free running 32-bit counter and a second correction counter. The correction Correction counter increases or decreases the rate Counter ENETn_ATCR [BLAVE] of the free running counter, enabling very fine granular changes of the ENETn_ATCOR ENETn_ATINC ENETn_ATINC timer for synchronization. [INC_COR] [INC]

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 53 Technical Highlights

Universal Asynchronous Receiver/Transmitter A flexible approach to full-duplex serial communication

The universal asynchronous receiver/ UART Transmit Logic transmitter (UART) module allows for asynchronous, full-duplex serial Internal Bus communication in a variety of formats. Module Baud Rate Generator SCI Data Register (SCID) Features of the UART include: Clock

• Standard mark/space non-return-to- RTS_B SBR12:0 BRFA4:0 Variable 12-Bit Transmit zero format (NRZ) M10 Shift Register R485 Contol CTS_B Stop Start • Supports IrDA 1.4 return-to-zero- M TXINV inverted (RZI) format Shift Direction MSBF • Supports ISO 7816 protocol for TXD Pin Control PE Parity Transmitter Tx port en interfacing with SIM cards and PT Generation Tx output buffer en Control Tx input buffer en smartcards (feature supported on DMA Done one UART module only) TXDIR SBK • 13-bit baud rate selection with TE 7816 Logic TxD by-32 fractional divide IRQ/DMA DMA Requests • Programmable eight- or nine-bit Logic IRQ Requests TxD data formats Infrared Logic • Ability to select MSB or LSB to be first on the wire Loop Control To Receiver

• Hardware flow control support for LOOPS request to send (RTS) and clear to RSRC send (CTS) signals ISO 7816 Timing Diagrams • Separate transmit and receive (feature supported on two UART modules only) ISO 7816 Format without Parity Error (T=0) FIFOs with DMA request capability PARITY NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP STOP BIT BIT BIT ISO 7816 Support ISO 7816 Format with Parity Error (T=0) NACK ERROR One of the UART modules supports PARITY NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP BIT the ISO 7816 standard, allowing BIT communication with SIM cards and smartcards. This feature has the following ISO 7816 Format (T=1) PARITY NEXT characteristics: START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP BIT BIT • Supports T=0 and T=1 protocols • Automatic retransmission of NACKed packets with programmable Key Features Customer Benefits retry threshold ISO 7816 protocol support Support for SIM and smart cards • Supports 11 and 12 ETU transfers • Detects initial packet and automated Large number of communication Flexibility to implement a variety of serial transfer parameter programming formats available communication protocols • Interrupt-driven operation with seven ISO-7816 specific interrupts: FIFOs with DMA request capability Decreased CPU loading

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UART Receive Logic º Wait time violated º Character wait time violated Internal Bus º Block wait time violated º Initial character detected SBR12:0 BRFA4:0 Data Buffer º Transmit error threshold exceeded Module Baud Rate M Clock Generator Variable 12-bit Receive º Receive error threshold exceeded Shift Register M10 Stop Start Guard time violated RE Receive LBKDE º RAF Control MSBF Shift Direction RXINV Variety of Communications RxD Formats Available LOOPS Receiver RSRC Source PE Parity Wakeup Control PT Logic Logic The UART offers a number of options From Transmitter for data size, format and transmission/ reception settings. The variety of available

IRQ/DMA DMA Requests options makes the UART capable of RxD Active Edge Logic Detect IRQ Requests implementing a wide variety of serial communications protocols.

To TxD Features include: 7816 Logic • Eight- and nine-bit data formats Infrared Logic supporting parity over all nine bits • MSB or LSB first on wire • Programmable transmitter output UART Data Formats polarity

Eight Bits of Data with LSB First • Programmable receiver input polarity ADDRESS MARK START START FIFOs with DMA BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT Request Capability

Eight Bits of Data with MSB First The UART FIFOs reduce the frequency ADDRESS of CPU processing required by the UART. MARK START START BIT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT BIT The DMA can be configured to transfer an entire packet of data and then interrupt Nine Bits of Data with LSB First the CPU when all bytes are received. This ADDRESS MARK means the CPU can process the entire START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT BIT packet all at once instead of needing to stop the current program flow to move Nine Bits of Data with MSB First data bytes as they are received. ADDRESS MARK START START The size of the FIFOs vary depending BIT BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT BIT on the particular device and the specific UART. Most devices will implement an 8-byte receive and 8-byte transmit FIFO on UART0 and UART1, and no FIFOs on the remaining UARTs. freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 55 Technical Highlights

USB Subsystem Flexible USB connectivity

The USB subsystem is comprised of USB Regulator several blocks that, together, provide full, flexible USB functionality. The MCU USB subsystem includes: • USB On-The-Go (OTG) 2.0 compliant VDD controller (specific controller depends 3.3V USB Regulator on the device). Options are: 3.3V To Board º Full-speed (FS)/low-speed VOUT33 Components (LS) USB controller 5V VREGIN Vbus º High-speed (HS)-capable controller (Kinetis K20 and K60 families only). USB Transceiver HS option supported using external D+ ULPI PHY USB0_DP D+ D- º On-chip FS/LS USB transceiver USB0_DM D- USB regulator º D+ D- USB º USB device charger detect (DCD) Connector USB Device Charger Detect

FS/LS Controller HS-Capable Controller The USB FS/LS controller provides The USB HS-capable controller provides USB host and device communications USB host and device communications along with support for OTG operation. along with support for OTG operation. The FS/LS controller is USB 2.0 compliant The HS-capable controller is USB 2.0 and supports full-speed (12 Mbps) and compliant. The controller supports HS low-speed (1.5 Mbps) data transfer rates. (480 Mbps), FS (12 Mbps) device and OTG operation; the controller supports The FS/LS controller is always used HS/FS/LS host operation. with the on-chip FS/LS transceiver block. The on-chip transceiver includes internal The HS-capable controller can be used pulldown resistors on the D+ and D- lines with an optional external UTMI+ low and an internal pullup resistor on the pin interface (ULPI) PHY to support D+ line. This helps to reduce the HS mode. If HS operation is not needed, number of external components the on-chip FS/LS transceiver can be needed for USB connectivity. used instead.

56 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 • • ••

USB Device Charger Detect

VBUS System Interrupt System VBUS_detect Software

Standard D- Control Host Port Pulldown and or USB D- Enable Status Bus USBDCD Dedicated Module Charger Charge or Rate Charging Connector Host Port D+ Pull Down Battery Pull Up Enable Comm Charger D+ Enable USB Command Module Control USB Transceiver IC Controller

Device

USB Regulator can now control the battery charging IC requesting higher current draw from The USB regulator generates a 3.3V USB VBUS, making the product a smart supply from the USB VBUS or a charging device. Traditionally, a USB rechargeable battery supply. subsystem without USBDCD hardware The USB regulator is an LDO linear would only receive the minimal current voltage regulator module that provides draw for charging from USB VBUS. The 3.3V from an input power supply varying advantage is that the charging current/ from 2.7 to 5.5V. The 3.3V output from time is optimized. the regulator is used to power the on-chip Features include: USB transceiver and device charger detect. The output pin (VOUT33), capable • Complies with the latest industry- of sourcing up to 120 mA, can be used standard specification, USB Battery to power external board components Charging Specification, Revision 1.1 and/or the MCU main power supply. • Programmable timing parameters This eliminates the cost of external LDO. default to values required by industry standards: USB Device Charger Detect º Standard default values allow The USB device charger detect minimal configuration (USBDCD) module works with the º Programmability allows the flexibility USB transceiver to detect if the USB to meet future standards updates device is attached to a charging port • Compatible with systems (either a dedicated charging port or powered from: a charging host). By properly identifying º Rechargeable battery the type of charging port, the MCU º Non-rechargeable battery º External 3.3V LDO regulator powered from USB or directly from USB using internal regulator

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 57 Technical Highlights

External Interfaces System expansion and off-chip data storage

The Kinetis MCU families support a wide DRAM Controller variety of external interfaces, including a DRAM controller, FlexBus external bus interface and NAND flash controller. Command AHB Port 1 Queue ColdFire+ Qx and Jx families include a DDR Mini FlexBus external bus interface. DDR2 Write DRAM AHB Port 2 PHY DRAM Controller Queue LPDDR Chip

Port Arbiter Transaction The DRAM controller enables users to Processing connect large amounts of DRAM to the Read AHB Port 3 Queue MCU. This means that applications are not limited to internal SRAM, opening the doors for new use cases. The main FlexBus Modes of Operation features of this block are:

• Enables the MCU family to be used in Non Muxed Mode applications that require access to large amounts of memory—supports up to Data Data Data Data 512 MB of external memory • 8- and 16-bit external data bus Address Address Address Address interfaces • Maximum frequency (clock/data) Data and Address Have Separate Ports

150/300 MHz Muxed Mode • Supports DDR, DDR2 and LPDDR Address Data Data Address memory types • Fully asynchronous operation with Data and Address Are Interleaved on the Same Port an independent PLL • Supports dynamic on-die termination Smart LCD Mode both in the host device and in the DRAM Data Data Data Data • Supports one chip select and up to eight bank devices Data Is Sent Sequentially on One Port • Supports bursts of 16 and 32 bytes, version has 8-, 16- and 32-bit port sizes º Optional secondary wait independent byte lane timing and very with configuration for multiplexed or non- state counter robust timing recovery for simplified multiplexed addresses and data buses. board routing º Useful for interfacing to burst Features include: memories that have a long access • Supports low-power modes • Byte-, word-, longword- and 16-byte time for the first chunk of data, but Mini FlexBus/FlexBus line-sized transfers can deliver subsequent data faster • Programmable burst and burst-inhibited • Programmable address setup time with The Mini FlexBus interface on the transfers selectable for each chip select respect to the assertion of chip select ColdFire+ family devices is designed to and transfer direction connect with up to two external devices. • Programmable address hold time with The FlexBus interface on the Kinetis • Auto-acknowledge feature respect to the negation of chip select family devices is designed to connect º Primary wait state counter and transfer direction with up to six external devices. Each up to 63 clocks

58 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Technical Highlights

ColdFire+ Kinetis* Qx Jx K10 K20 K30 K40 K60 •• •••••

Peripheral Key Features Customer Benefits FlexBus supports the connection to: • Flash 8-, 16-, 32- and 128-bit line Maximize throughput according to the specific • Smart LCDs sized transfers application • FPGAs Programmable burst and burst-inhibited transfers selectable for each chip select Optimized traffic patterns for • SRAM FlexBus and transfer direction each client in the bus • PROM Auto-acknowledge feature Increased flexibility and • EPROM Programmable address-setup time lower BOM costs in glueless external device connections • EEPROM Programmable address-hold time NAND Flash Controller Supports DDR, DDR2 and LPDDR The power vs performance trade-off can be optimized for memory types the application The NAND flash controller (NFC) enables a glueless connection to MLC NAND Fully asynchronous operation with an DRAM operating frequecy can be set independently of the memories. The heavy load of error independent PLL DRAM system frequency correction code (ECC) calculations are Controller Supports bursts of 16 and 32 bytes with Reduced complexity in board handled in hardware and up to 32-bit ECC independent byte lane timing and very routing and component robust timing recovery selection helps ensure that current and foreseeable generations of MLC NAND memories Minimizes overall system Supports low-power modes power consumption are supported. The main features of this block are: NAND Flash Controller Block Diagram • 8-/16-bit NAND flash interface • Memory mapped registers boot_done boot_fail irq and SRAM buffer boot_after_reset Boot boot_mode Control • Supports all NAND flash products NFC_IO[15:0] lpg_clk lps_clk CMD Residue regardless of density/organization reset_b DATA Generation (with page sizes of 512+16B/2 KB+ Control Control NFC_CLE 64B/4 KB+128B/4 KB+218B/8 KB) Register Conﬁg BCH Encoder NFC_ALE • Supports flash device commands 7 ECC Modes NFC_CEn such as page read, page program, reset, block erase, read status, read ID, NFC_RE Addr copy-back, multiplane read/program, Dec. SRAM NFC_WE Control interleaved read/program, random ECC Control NFC_R/Bn input/output and read in EDO mode

NAND FLASH CONTROL • In bypassable ECC mode, the NFC

IPM BUS CPU Access Bus DMA BCH Control SRAM supports 4-, 6-, 8-, 12-, 16-, 24- Decoder Buffer REQ BUS and 32-bit error correction IDLE GRT • Two configurable DMA channels: Use EMB IF SRAM Buffer DMA channel 1 to read/write the main 9 KB area of a page, and DMA channel 2 IPM DMA Bus for the spare area. Use DMA channel 1 *External interfaces are offered on the following families: only to read/write a page for both main DRAM Controller: Kinetis K60 Mini FlexBus: ColdFire+ Qx/Jx and spare areas of a page FlexBus: Kinetis K10/K20/K30/K40/K60 NAND Flash Controller: Kinetis K10/K20/K60 freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 59 Software and Development Tools

Software and Development Tools Software and Development Tools

Freescale MQX™ Software Solutions Complimentary full-featured RTOS

Freescale streamlines Freescale Comprehensive Solution embedded design with a complimentary real-time CodeWarrior Development Demo Code Applications operating system and Environment Customized Application (MQX™ OS Applications software stacks Application Tasks and Aware) Industry-Speciﬁc Libraries The increasing complexity of industrial CodeWarrior applications and expanding functionality Processor Expert Ethernet of semiconductors are driving embedded USB MQX RTOS (RTCS) Discrete developers toward solutions that combine MQX Design Optional Driver, and Services Third Enablement proven hardware and software platforms. File System CAN Development Party Layer To help accelerate time to market Tools and Freescale and improve application development Core Services MQX RTOS Third Party: success, Freescale is offering the MQX IAR (MQX OS real-time operating system (RTOS) with Aware) TCP/IP and USB software stacks and BSP/PSP HAL peripheral drivers to ColdFire, ColdFire+ and Kinetis MCU customers at no Open Source BDM and BDM/JTAG Microcontroller Hardware additional charge. The combination of Third Party: Freescale MQX software solutions and our Emulator/Probe On Device silicon portfolio creates a comprehensive PC Hosted

source for hardware, software, tools and Freescale MQX Software Solutions services.

Reducing Cost, MQX RTOS: Customizable Component Set Accelerating Success

By providing complimentary Freescale Name Services MQX software solutions with its silicon Queues Interrupts products, Freescale helps alleviate much of the initial software investment Partitions Utilities Messages hurdle faced by embedded developers. Task Errors Initialization Comparable full-featured software Task Events offerings may cost developers as much Management Lightweight Core Memory as $95,000 (USD) in licensing fees. Semaphores Services CORE Continued on next page Watchdogs Mutexes Task Queue Automatic Scheduling Task Creation Timers IPCs RR and FIFO Scheduling Exception Formatted I/O Software and Handling I/O Subsystems Kernel Log Logs Development Tools AS-NEEDED

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 61 Software and Development Tools

Freescale MQX Software Solutions Continued from previous page

According to recent research, RTCS TCP/IP Stack development teams spend approximately

*SNMP 60 percent of their resources on RPC *SSH *XML *SMTP *POP3 HTTP (v3) software. Embedded projects based on SNMP XDR Telnet FTP TFTP DNS SNTP Web Server 32-bit devices have a greater need for (v1, v2) software reuse to manage development costs. The Freescale MQX RTOS and *SSL software stacks address these developer needs by providing a scalable, reusable Sockets BootP DHCP RIP platform that works across a wide range of Freescale processor architectures, TCP UDP development tools and third-party ICMP IGMP software environments. NAT IP CIDR Freescale MQX is deployed as production-ready source code, including IP-E IPCP PAP CHAP CCP LCP communications software stacks and peripheral drivers, at no additional cost. ARP PPP Freescale MQX is provided with a commercial-friendly software licensing model, enabling developers to keep their source modifications while being able Ethernet Serial HDLC to distribute the required binary code. *Denotes optional products Application Presentation Session Transport Network Data Link Physical Full Featured, Proven and Scalable The Freescale MQX RTOS offers sophisticated applications. For designs a straightforward application that do have a formal certification process The MQX RTOS has been the programming interface (API) with a to follow, MQX is an excellent choice. backbone of embedded products based modular, component-based architecture Past licensees have certified MQX-based on Freescale silicon for more than 15 that makes it very scalable. Components applications to medical specifications years. MQX software deployment spans are linked in only if needed, preventing (CFR 820.30 Part 21, IEC 60601-1) and a broad range of market segments and unused functions from bloating the the aerospace requirements listed under leading manufacturers worldwide. memory footprint. Plug-ins, such as DO-178b. Safety critical applications The Freescale MQX RTOS offers security, industrial protocols and graphical based on MQX include eye surgery powerful, preemptive real-time interfaces from Freescale’s strong network equipment, drug injection equipment, performance with optimized context of partners, can also be added. radiation dose monitoring equipment, switch and interrupt time, enabling aircraft braking systems and aircraft fast, highly predictable response times. Certifiable to Medical and navigation equipment. Its small, configurable size conserves Aerospace Standards memory space for embedded applications Even if your application does not require and it can be configured to take as formal certification, the robustness of little as 6 KB of ROM, including kernel, MQX provides a trusted platform that has interrupts, semaphores, queues and been proven in thousands of time-critical, memory manager.

62 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Software and Development Tools

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Freescale MQX Add-on Software Freescale MQX

• Network management: Support for SNMP version Real-Time TCP/IP 1 and 2 is built into RTCS. EAI offers MQX SNMPv3 Communication Suite Real-Time TCP/ • XML parsing and framing: The MQX XML component IP Communication The Freescale MQX real-time Suite (RTCS) Optional enables your device to accept data in XML, as well Components as send data packaged in XML communication suite (RTCS) is a fast, Available from • e-Mail communication: The MQX SMTP module provides efficient and low-footprint embedded Embedded Access Inc. your device with outbound e-mail communication and MQX POP3 provides the capability to accept incoming Internet stack that supports a rich set e-mail communication of standard TCP/IP protocols. It comes complete with a number of application NanoSSL™ and • NanoSSH: Provides privacy, authentication and ensures layer protocols such as Telnet, FTP, SNMP NanoSSH™ software by data integrity between a secure server and its clients Mocana available from • NanoSSL: Cyptographic protocols that provide security v1 and SNMP v2. A number of optional, Freescale Semiconductor for communications over networks such as the Internet pre-integrated protocols and products are also available from third parties. • Portable embedded GUI library designed PEG + Graphics Library to provide a professional-quality GUI for embedded The Freescale MQX RTCS is scalable, Available from Embedded systems applications allowing you to easily define the feature Access Inc. • Small, fast and easily ported to virtually any hardware configuration capable of supporting graphical output set you want to accommodate your ROM and RAM memory budgets. SEGGER emWin • emWin is designed to provide an efficient, LCD Graphics Library/GUI For more information about the controller-independent GUI for any application Available from SEGGER Freescale MQX platform, please visit Microcontroller that operates with a graphical LCD freescale.com/MQX. • CANopen is a CAN-based higher layer protocol • Developed as a standardized embedded network CANOpen Master/Slave for Embedded Devices with highly flexible configuration capabilities Available from IXXAT, Inc. • Unburdens the developer from dealing with CAN-specific details such as bit-timing and implementation-specific functions

• Profinet RT for I/O device Industrial Network • EtherNet/IP for adapter and scanner and Field • Ethernet powerlink for managing and controlled nodes Bus Protocols • EtherCAT for slave nodes Available from IXXAT, Inc. • SERCOS III for slave devices • Precision time protocol IEEE 1588-2008 (v2)

• SFFS is a safe flash file system that can support almost any NOR or NAND flash device • Provides a high degree of reliability and complete protection against unexpected SFFS Flash File System power failure or reset events Available from Embedded • Provides wear leveling, bad block handling and Access Inc. ECC K30C algorithms to ensure you get optimal use out of a flash device • Pre-integrated with the MQX RTOS: allows you to create a robust file system quickly for an embedded device using on-chip or on-board flash devices

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 63 Software and Development Tools

Freescale Tower System A modular development platform

Overview The Freescale Tower System The Freescale Tower System is a Controller Module Primary Elevator modular development platform for • Tower MCU/MPU • Common serial 8-, 16- and 32-bit microcontrollers that board and expansion bus signals enables advanced development through • Works stand-alone rapid prototyping. Featuring multiple or in Tower System • Two 2x80 connectors on development boards or modules, the • Features integrated backside for easy debugging interface signal access and Tower System provides designers for easy programming side-mounting and run-control via board (LCD module) with building blocks for entry-level to standard USB cable advanced microcontroller development. • Power regulation circuitry

Secondary Elevator • Standardized Modular and Expandable • Additional and signal secondary serial and assignments • Controller modules provide easy-to- expansion bus signals • Mounting holes use, reconfigurable hardware • Standardized signal assignments • Interchangeable peripheral modules— Board Connectors • Mounting holes and serial, memory and graphical LCD— expansion connectors • Four card-edge for side-mounting connectors make customization easy peripheral boards • Uses PCI Express® • Open-source hardware and connectors Size Peripheral Module (x16, 90 mm/ standardized specifications promote the 3.5” long, 164 pins) • Tower is approx. 3.5” H x 3.5” W • Examples include serial interface module, development of additional modules for x 3.5” D when fully assembled memory expansion module and Wi-Fi® added functionality and customization

Speeds Development Time Controller Modules Features • Open source hardware and software Kinetis K40 Family: • 256 KB flash MCU, 256 KB FlexMemory in allows quick development with TWR-K40X256 (K40 MCU module) 144 MAPBGA package proven designs TWR-K40X256-KIT (K40 MCU • On-board JTAG debug interface module + elevator modules + serial • Access to all features, including segment • On-board debug hardware for easy module) LCD and USB programming and debugging using only a standard USB cable Kinetis K60 Family: • 512 KB flash MCU, non FlexMemory in TWR-K60N512 (K60 MCU module) 144 MAPBGA package TWR-K60N512-KIT (K60 MCU • On-board JTAG debug interface module + elevator modules + serial • Access to all features, including Ethernet module) and USB

• 128 KB flash MCU in \64 LQFP package ColdFire+ JF Family MCU Module • On-board BDM debug interface • Access to all features, including USB

• 128 KB flash MCU in 64 LQFP package ColdFire+ QM Family MCU Module • On-board BDM debug interface • Access to all features, including 16-bit ADC

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ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Tower System Modules Cost Effective Features Benefits • Peripheral modules can be re-used with Controller Modules (8-, 16-, 32-bit) all Tower System controller modules, Works stand-alone or as part of Tower System Allows rapid prototyping eliminating the need to purchase Provides easy programming and debugging Features on-board debug interface via mini-B USB cable redundant hardware for future designs Peripheral Modules • Enabling technologies like LCD, serial Can be re-used with all Tower System Eliminates the need to buy/develop and memory interfacing are offered MCU/MPU modules redundant hardware off-the-shelf at a low cost to provide Interchangeable peripheral modules—serial, Enables advanced development and memory, graphical LCD, prototyping and more broad functionality a customized enablement solution Elevator Boards Provides easy signal access and enables Software Enablement Two 2x80 connectors side-mounting modules (i.e. LCD module) and Support Power regulation circuitry Provides power to all boards The increasing complexity of industrial Allows for customized peripheral Standardized signal assignments module development applications and expanding functionality Allows easy expansion using PCI Express of semiconductors are driving embedded Four card-edge connectors available connectors (x16, 90 mm/3.5” long, 164 pins) developers toward solutions that require the integration of proven hardware and Available Tower System Modules software platforms. Freescale, along Controller Modules Price Features with a strong alliance network, offers TWR-MCF51CN $39 MCF51CN ColdFire V1 Ethernet module comprehensive solutions including TWR-MCF5225X $49 MCF5225X ColdFire V2connectivity module development tools, debuggers, TWR-S08LL64 $69 MC9S08LL64 8-bit segment LCD module MC9S08LH64 8-bit segment LCD module programmers and software. TWR-S08LH64 $69 with integrated 16-bit ADC TWR-MPC5125 $119 MPC5125 e300c4 Power Architecture® module Take Your Design MCF51MM ColdFire V1microcontroller module TWR-MCF51MM $59 designed for medical applications to the Next Level MC9S08MM128 8-bit microcontroller module TWR-S08MM128 $59 designed for medical applications For a complete list of development TWR-MCF51JE $69 MCF51JE ColdFire V1 USB microcontroller module kits and modules offered as part of the Peripheral Modules Price Features Freescale Tower System, please visit TWR-SER $49 Serial module with RS232/RS485, Ethernet, CAN, USB freescale.com/Tower. TWR-ELEV $29 Elevator modules: Primary and Secondary TWR-PROTO $14.99 Prototyping module Join the online community of Tower TWR-LCD $99 Graphical LCD module with 3.2” QVGA display Geeks. Interact. Explore. Create. Memory module with serial flash, MRAM, SD card and TWR-MEM $89 towergeeks.org compact flash interfaces Swappable sensor module with accelerometer, barometer TWR-SENSOR-PAK $149 and touch-sensing controller Complete Kits Price Includes TWR-MCF51CN-KIT $99 TWR-MCF51CN, TWR-SER and TWR-ELEV modules TWR-MCF5225X-KIT $119 TWR-MCF5225X, TWR-SER and TWR-ELEV modules TWR-S08LL64-KIT $99 TWR-S08LL64, TWR-PROTO and TWR-ELEV modules TWR-S08LH64-KIT $99 TWR-S08LH64, TWR-PROTO and TWR-ELEV modules TWR-MPC5125-KIT $169 TWR-MPC5125, TWR-SER and TWR-ELEV modules TWR-MCF51MM, TWR-SER, TWR-ELEV and TWR-MCF51MM-KIT $149 MED-EKG modules TWR-S08MM128, TWR-SER, TWR-ELEV and TWR-S08MM128-KIT $149 MED-EKG modules TWR-MCF51JE-KIT $119 TWR-MCF51JE-KIT, TWR-SER and TWR-ELEV modules freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 65 Software and Development Tools

CodeWarrior Development Studio Based on the Eclipse open development platform

Freescale’s CodeWarrior Development C/C++ Perspective Studio for Microcontrollers v10.x integrates the development tools for the RS08, HCS08, ColdFire, ColdFire+ and Kinetis architectures into a single product based on the Eclipse open development platform. Eclipse offers an excellent framework for building software development environments and is becoming a standard framework used by many embedded software vendors. • Eclipse IDE 3.4 • Build system with optimizing C/C++ compilers for HCS08, RS08, ColdFire, ColdFire+ and Kinetis processors • Extensions to Eclipse C/C++ development tools (CDT) to provide sophisticated features to troubleshoot MCU Change Wizard and repair embedded applications

MCU Change Wizard The MCU Change Wizard allows a project to be re-targeted to a new processor in as few as six mouse clicks. Simply select a new device (from the same or a different architecture—RS08, HCS08, ARM or ColdFire), select the default connection and the CodeWarrior tool suite will automatically reconfigure the project for the new device with the correct build tools and support files. • Compiler • Assembler • Linker CodeWarrior Key Features Key Benefits • Header files Ability to easily retarget project MCU Change Wizard to a new processor • Vector tables • Libraries Trace and profile support Sophisticated emulator-like debug capability for on-chip trace buffers without additional hardware • Linker configuration files Ability to monitor registers, memory and global LiveView variables without stopping the processor

Problems in hardware layer can be resolved Freescale Processor Expert during initial design phase

66 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Software and Development Tools

ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

Debug Perspective Profiling and Analysis The CodeWarrior profiling and analysis tools provide visibility into an application as it runs on the processor to identify operational problems. • Supports architectures with on-chip trace buffers (HCS08, ColdFire V1, ColdFire+ and Kinetis) • Allows tracepoints to be set to enable and disable trace output • Able to step through trace data and the corresponding source code simultaneously • Allows trace data to be exported into a Microsoft® Excel® file Processor Expert Processor Expert Freescale’s Processor Expert is a rapid application design tool that combines easy-to-use component-based application creation with an expert knowledge system. • CPU, on-chip peripherals, external peripherals and software functionality are encapsulated into embedded components • Each component’s functionality can be tailored to fit application requirements by modifying the component’s properties, methods and events • When the project is built, Processor Processor Expert Key Features Key Benefits Expert automatically generates highly Allows an application to be specified optimized embedded C-code and Graphical user interface by the functionality needed places the source files into the project Creates tested, optimized C code tuned Automatic code generator to application needs and the selected Freescale device

Immediately flags resource conflicts and Built-in knowledge base incorrect settings so errors are caught early in the design cycle

Allows for the creation of user-specific Component wizard hardware-independent embedded components freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 67 Software and Development Tools

IAR Embedded Workbench Powerful, reliable development tools

IAR Embedded Workbench is a set IAR Embedded Workbench IDE of development tools for building and debugging embedded applications using assembler, C and C++. It is available for various Freescale MCU and MPU families, including ColdFire+ and Kinetis.

IAR Embedded Workbench provides a completely integrated development environment, including project manager, editor, build tools and debugger. In a continuous workflow, you can create source files and projects, build applications and debug them in a simulator or on hardware.

Regardless of which Freescale device you have chosen to work with, you will experience the same intuitive user interface coupled with target-specific support for each device. Reuse of code and migration to new microcontroller architectures is made easy as each IAR C/C++ Compiler uses the same naming convention.

Key Components

• Integrated development environment • Code coverage and function profiling • Ready-made code and project with project management tools and analysis utilities examples for supported evaluation editor • Support for RTOS-aware debugging on boards • Highly optimizing C and C++ compiler hardware • User and reference guides in PDF • C-SPY® simulator and hardware • Freescale MQX Software Solutions format debugger systems integration • Context-sensitive online help • IAR J-Trace and IAR J-Link debug • Information Center provides quick probes access to user guides, examples and • Timeline window visualizes call stack, other useful information interrupts and variable values over time • Configuration files for all supported • Power debugging devices

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ColdFire+ Kinetis Qx Jx K10 K20 K30 K40 K60 •• •••••

IAR Embedded Workbench Timeline Window

Timeline Power Debugging MQX Integration IAR Embedded Workbench provides IAR Embedded Workbench supports Freescale MQX Software Solutions has you with advanced features for powerful power debugging on Kinetis been integrated with IAR Embedded trace debugging. The timeline window microcontrollers. Power debugging allows Workbench. A ready-made port which graphically displays correlated information you to optimize your system for lower can be compiled and linked using IAR about various properties on a single power consumption. Embedded Workbench is available and timeline. • Visualization of the power consumption ready for use. There are also project • Visualization of the call stack provides over time in the timeline window templates that make it easy to create an information about depth of stack and • Simultaneous visualization of the call MQX-based project. length of each function call stack, interrupts and variable values • Interrupt graph displays events taking gives you a high-level view of the IAR C-SPY Debugger provides kernel place in the application system’s power consumption awareness for the MQX RTOS, as well as other operating systems. Kernel • Variable values are plotted over time • Power log provides high-resolution awareness in the debugger allows power data the user to examine operating system • Power consumption is correlated to properties during a debug session. the source code. Click in the power • Operating system properties such as graph and the corresponding source tasks, semaphores and mailboxes can code is highlighted be monitored • Power profiling utility • Execution control can be kernel dependent. For instance, it is possible to set breakpoints on conditions for specific operating system properties

For more information, visit IAR.com.

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 69 Software and Development Tools

Keil Microcontroller ColdFire+ Kinetis Development Kit Qx Jx K10 K20 K30 K40 K60 ARM MCU development environment •••••

The Keil micocontroller development kit Microcontroller Development Kit (MDK) MDK supports all ARM and Cortex-M Microcontroller Development Kit (MDK) ULINK® USB Adapters processor-based MCUs, including • Best-in-class ARM C/C++ Compilation Tools • JTAG and Serial Wire Interface Freescale’s new Kinetis family. It • Genuine Keil µVision®4 IDE/Debugger/Simulator • Flash Programming • Royalty-free RTX Real-Time Operating System • On-the-ﬂy Target Debugging combines the μVision™ 4 IDE/debugger • Easy device conﬁguration with Device Database support • Real-Time Data Trace with ARM compilation tools to provide for more than 700 ARM-Powered devices • ETM Instruction Trace (ULINKpro) developers with an easy to use, Evaluation Boards A/D Converter I/O Ports Debug Run-Control • Keil provides a wide range of evaluation feature-rich environment. boards for ARM and Cortex-M devices Timer/Counter Interrupt Debug MDK provides many unique features System Channel RTOS and Middleware designed to help you quickly develop your • RTX Real-Time OS with Source Code PWM Flash ROM • TCP/IP Suite with Server Applications • File System for ROM and Memory Cards project. CPU • Direct support for USB and CAN interfaces • Device database: Automatically UART RAM configures device and project parameters I2C/SPI DMA Real-Time • Trace and analysis tools: Optimizes and Clock verifies the application by measuring Ethernet SD/MMC USB CAN performance and code coverage Interface • Fully functional RTX™ real-time operating system: Add resource • Debugger: Provides code coverage information while your system is running, management to the application statistics to verify applications that re- including a trace window, debug viewer, The MDK consists of the several powerful quire certification testing and validation. exceptions window, event counters and a components for debugging and analysis: • Performance analyzer: Displays the logic analyzer. execution time recorded for functions • ARM compilation tools: Deliver All Cortex-M devices with ETM provide including the time spent in a function optimized, high-performance code for instruction trace. The Keil ULINKpro is and the number of calls to it. all ARM-powered devices. Further code the only trace adapter which streams size savings can be gained by selecting • Execution profiler: Records execution instruction trace directly to your PC. the MicroLib library. statistics for each CPU instruction, This enables debugging of historical • Debugger: Can be configured as a including the execution count and sequences, execution profiling and simulator or target debugger and execution time for each instruction. code coverage analysis. provides a single environment for All Cortex-M-based devices feature ARM The virtually unlimited stream of trace application testing. CoreSight technology with advanced information enables MDK to provide • System viewer: Provides an advanced debug and trace capabilities. Together complete code coverage of your program. method of viewing and modifying with a ULINK adapter it allows the user to Code coverage identifies every instruction peripheral registers. control the CPU, single step one source that has been executed, ensuring • Analysis tools: Work with the simulator or assembler line, set breakpoints while thorough testing of your application. This or with target hardware via the ULINK™ the processor is running, and read/write is an essential requirement for complete pro streaming trace adapter. memory and peripheral registers on the fly. software verification and certification. • Configurable logic analyzer: Provides a All Cortex-M3 and Cortex-M4 devices For more information, visit keil.com. graphical display of signals and variables. provide data and event trace. MDK Users can display the specific instructions provides a number of ways to analyze this that caused variable changes.

70 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Software and Development Tools

Development Tools, ColdFire+ Kinetis RTOS and Middleware Qx Jx K10 K20 K30 K40 K60 ARM Embedded Software Solutions •• •••••

Green Hills Software offers solutions for TimeMachine™ Debugging Suite Kinetis MCUs based on ARM Cortex-M4 technology. Real-Time Operating System • μ-velOSity™ royalty-free RTOS is a small, fast, easy-to-learn operating system for the most cost-sensitive and resource-constrained devices Software Development Tool • MULTI® and AdaMULTI™ development environments allow to quickly develop, debug, test and optimize embedded and real-time applications The TimeMachine suite extends • TimeMachine™ debugging suite allows the range of the MULTI IDE by the user to find the most outrageously providing a window into the complex difficult bugs—in minutes interactions in software that can • DoubleCheck™ integrated static result in bugs, performance problems analyzer easily pinpoint bugs early in and testing nightmares. development

• Green Hills optimizing compilers Green Hills C/C++ Compilers fully detected by compilers during standard generate the smallest and fastest code conform to ANSI/ISO industry standards, builds and often go undetected during from C, C++, Ada 95 and Fortran and include optional enforcement of run-time testing or typical field operation. MISRA C programming guidelines. Processor Probes The MULTI TimeMachine debugging • SuperTrace™ Probe allows for fast MULTI Development suite offers a wide variety of trace trace, download and debug Environment analysis tools that enable embedded • Green Hills Probe for high- software developers to find and fix bugs MULTI provides a host-based (Windows, performance real-time debugging faster, optimize with ease and test with Linux or UNIX workstation) graphical confidence. By presenting the information environment for ARM target development. ARM Optimizing Compilers in easy-to-understand displays, Host-target connectivity is provided The Green Hills Compiler for ARM TimeMachine enables developers to through a variety of means, depending on generates architecture-specific and even quickly navigate through trace data and the target environment. MULTI supports processor-specific optimizations to use the produce better code in less time. many ARM targets. pipeline and instruction set characteristics Learn more at ghs.com/products/ of each supported ARM processor model. The DoubleCheck integrated static arm_development.html. Green Hills offers further optimization analyzer finds code sequences that may through CodeFactor, a link-time result in buffer overflows, resource leaks optimization which reduces overall program and many other security and reliability size by identifying and removing redundant problems. It is effective at locating a segments of code from object files. significant class of defects that are not freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 71 Software and Development Tools

CodeSourcery: Sourcery G++ ColdFire+ Kinetis Tools for professional ColdFire Qx Jx K10 K20 K30 K40 K60 •• ••••• and Kinetis developersSourcery G++ Components

Sourcery G++ is CodeSourcery’s Sourcery G++ Components comprehensive tools solution for professional embedded C and C++ developers. Sourcery G++ has all the Sourcery G++ IDE Eclipse, CDT, Plug-Ins CS3 tools a developer needs to build and CodeSourcery debug embedded applications, including Common Start-up Code Sequence Run Build an IDE, optimizing C/C++ compilers, Debug JTAG runtime libraries, source-and assembly- GCC/G++ Sprite GNU C and GDB JTAG/BDM Libraries (E)GLIBC level debugger with hardware debug C++Compilers GNU

Debugger Application uClibc support, simulator, BSPs and utilities for Newlib Libstdc++ Linux developers. QEMU Simulation Binutils Simulator Sourcery G++ supports Freescale’s GNU Assembler and GNU Linker TCP/IP ColdFire, Kinetis, i.MX and Power GDB Server Architecture-based processor families. Host System Target System Sourcery G++ runs on Linux and Windows host systems and targets Linux, uClinux, Sourcery G++ offers peripheral multiple processes, at once. At the RTOS or bare metal systems. Support for register browsing and integrated flash deployment stage, the Prelinker can the MQX RTOS is coming soon. programming. reduce application startup time and the Sourcery G++ is based on the GNU Library Optimizer can reduce library Sourcery G++ includes the CodeSourcery Toolchain and the Eclipse IDE, so it footprint. Common Start-up Code Sequence (CS3), comes with all of the advantages of which provides a basic board support these powerful open-source tools with Availability package for many popular boards with additional features available only from linker scripts, start-up code and debugger Sourcery G++ is available in Professional, CodeSourcery. interface files. And for new boards, the Standard and Personal Editions. Sourcery Sourcery G++ Board Builder allows G++ Professional and Standard Editions Bare Metal and RTOS include direct access to CodeSourcery’s Development developers to create a custom board definition file. engineering team—the same team Developers working with a bare metal responsible for contributing over 10,000 system can take advantage of the Linux Application and Kernel changes to the official versions of the GNU Sourcery G++ Debug Sprite for running Development Toolchain. All Sourcery G++ customers and debugging applications on target also receive access to regular semi- Sourcery G++ offers a complete Linux hardware via a JTAG or BDM probe. annual Sourcery G++ updates, as well as build and debug environment for Linux Supported probes include P&E, Axiom any intermediate updates produced for applications, Linux kernel or Linux kernel BDM, Abatron, Freescale CCS devices, Professional Edition customers. Download modules. The Sysroot Utilities and the Macraigor, RealView ICE, SEGGER J-Link a free 30-day evaluation. Remote System Explorer make it easy and ULINK2. Sourcery G++ also includes to get an application running on the For more information, visit an instruction set simulator for ColdFire target system. Sourcery G++ supports codesourcery.com/sgpp. and Kinetis systems. debugging on the target hardware or in the simulator with a debugger that displays multiple threads, and even

72 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Software and Development Tools

Multilink Universal ColdFire+ Kinetis A single interface for Freescale Qx Jx K10 K20 K30 K40 K60 development •• •••••

The Multilink Universal represents the next Multilink Universal Supported Architectures step forward for P&E’s successful line of Multilink hardware interfaces. It combines support, in a single interface, for many Freescale architectures, including HCS08, RS08, HC(S)12, ColdFire/ColdFire+ V1, ColdFire V2–V4, Power Architecture MPC55xx/56xx and Kinetis MCUs based on ARM. It will be available in November 2010, and will be followed by a high- speed version in early 2011.

P&E’s Multilinks are affordable, development-oriented interfaces that allow access to BDM/JTAG on a target microcontroller from the user’s PC. The Multilink Universal offers this same Supported Architectures Cyclone Production reliability and affordability while combining Programmers support, in a single interface, for many • HCS08 Freescale architectures. It includes several • RS08 P&E has added support for Freescale’s ColdFire+ V1 to its Cyclone PRO stand- ribbon cables to allow connections to • HC(S)12 alone programmer, and support for the proper header for each architecture, • ColdFire/ColdFire+ V1 and is designed to make its broad the Kinetis ARM to the Cyclone MAX • ColdFire V2–V4 support of Freescale architectures simple stand-alone programmer. These Cyclone • Power Architecture MPC55xx/56xx to implement. The user can simply flip products are geared towards production open the Multilink case and install the • Kinetis ARM programming, including automated appropriate ribbon cable. and high-volume programming. P&E is Software Support also developing a Cyclone stand-alone programmer that will include support for Universal Multilink Features • Freescale’s CodeWarrior many Freescale architectures in a single, • P&E Software (including programmers • Draws power from USB interface—no production-oriented interface. separate power supply required and debuggers) • Target voltage of 1.6V–5.25V • Third-party software For more information, visit • Includes a ribbon cable for each pemicro.com/universal. supported architecture

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 73 Software and Development Tools

SEGGER: J-Link and Flasher ColdFire+ Kinetis Convenient development and Qx Jx K10 K20 K30 K40 K60 production programming •••••

Designed using SEGGER’s industry-leading SEGGER Debug Probes and Production Flash Programmers embedded software, J-Link debug probes offer a wide array of advanced features J-Linktm and boast support for a broad spectrum of microcontrollers and microprocessors, Intelligent including Freescale’s complete i.MX, Kinetis and ColdFire V2–V4 lines. Many popular Debugging via IDEs, such as CodeWarrior, IAR, Keil, Code JTAG/SWD Sourcery V2–V4 and more have built-in support for the J-Link. • Robust communication

The J-Link debug line offers high • Very high performance download speed into RAM* and flash (download speed up to memory. Each hardware model of these 1.5 MB)* JTAG debuggers has its own unique • Unlimited flash breakpoints attributes to offer and there are a number (license required) of available software add-on modules which enhance the J-Link’s functionality. For more details, please see segger.com/ jlink.html. J-Flash is a comprehensive J-Link ULTRA for high performance Flasher for production flash user interface for flash programming. J-Link ULTRA is based on the highly programming and in the field services The flash breakpoint add-on allows for optimized and proven J-Link, it offers Our in-circuit programmer (Flasher ARM) an unlimited number of breakpoints even higher speed as well as target is a superset of our J-Link DDL. It contains while debugging in flash memory. The power measurement capabilities due to all of the debug probe features, while J-Link SDK is a standard Windows the faster CPU, built-in FPGA and High- being designed for use in a production DLL typically used from C. It makes the Speed USB interface. This permits you environment. Different interfaces, like the entire functionality of the J-Link available to take full advantage of the low power command line interface or the optionally through the exported functions and allows features offered by today’s modern cores. available SDK allow an easy integration into to write your own program using J-Link. J-Link Ultra raises the bar, aiming to be any production environment. the fastest emulator available. Hardware Models The Flasher ARM has on-board memory to J-Link Pro for connectivity J-Trace for Cortex-M for store your binary image permitting simple J-Link Pro is an enhanced version of the post-mortem-analysis stand-alone flash programming. This is J-Link. It incorporates an on-board Ethernet J-Trace for Cortex-M is a JTAG probe particularly useful for support teams which interface in addition to the USB, as well which includes trace (ETM) support. have to upgrade devices out in the field. as two LED hardware status indicators. It J-Trace assists the developer in analyzing They only need to carry a small box which comes with licenses for all J-Link related his target system’s behavior. The 4 MB is readily configured to perform the update, SEGGER software products, including flash trace memory provides plenty of space once it is connected to the target system. breakpoints, RDI, J-Flash and GDB Server, to store the last executed functions. For more details, please visit segger.com/ providing the optimum debugging solution This allows to find out how the program flasherarm.html. for the professional developer. arrived at a certain position in code which

*The regular J-Link performs with an already high is either not expected or wanted. 750 KBps, J-Link Ultra allows an even faster peak download speed of 1.5 MBps 74 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2 Software and Development Tools

ColdFire+ Kinetis Swell PEG Product Line Qx Jx K10 K20 K30 K40 K60 Any LCD. Anywhere. PEG software. •• •••••

Swell Software provides graphical user interface (GUI) solutions for embedded PEG Pro PEG+ C/PEG devices. Swell’s PEG Pro, PEG+ and C/PEG • Screen transitions • Multiple window updates • Designed for small LCDs product offering includes a GUI library • Multiple alpha-blended • Alpha-blended images (QVGA) • • for embedded development that works windows Run-time image decoders Low color-depth • True anti-aliasing and language resources • Very small footprint tightly with real-time operating systems. • Gradient manager • Custom widget integration • Single window update The development tool allows developers • Open GL support • Dynamic themes • Multi-language capable to layout user interface screens and • Written in C++ • Written in C++ • Written in ANSI C controls using the PEG library and external resources to generate C/C++ code. One of the smallest footprints and most efficient code bases available. Starting 225 KB Starting at 160 KB Starting at 90 KB PEG software accelerates GUI design Typical 225–250 KB Typical 160–175 KB Typical 90–110 KB for embedded devices by allowing Pricing starts as low as $4995 for a developer project license with three seats. developers to create prototypes on a Windows® or Linux® based PC by providing a complete visual layout and Window Builder Technology design tool to enable GUI design to take place in parallel to the embedded software/hardware development.

The PEG WindowBuilder automatically generates C++ source code that is ready to be compiled and linked into any application, further accelerating the deployment of the final product.

Swell’s GUI software products work hand in hand with Freescale customers’ real- time operating systems to incorporate LCD screens and display interfaces into future products.

GUI Interface Technology

Application Layer

PEG Library PEG WindowBuilder for Runs on PC/Linux/X11 to allow proof PEG Library Rapid Development of concept development LCD Driver RTOS RTOS Driver WindowBuilder allows a designer to layout Enables hardware/software LCD Driver each of the screens for a project through development to happen in parallel a simple-to-use interface, providing a Made available for free evaluation GUI Interface Technology “What You See Is What You Get” display. PEG’s modular form enables a rapid • Full WYSIWYG development development process. Simulation environment for PEG+ • The core library interfaces to different and PEG Pro RTOSs, input devices and LCD controllers by replacing the underlining driver

freescale.com/ColdFire+ | freescale.com/Kinetis Next-Generation Microcontrollers 75 ReferencesOverview

Quick Reference List of Next-Generation, 32-bit MCU Resources

Resource URL

ColdFire+ Microcontrollers freescale.com/ColdFire+

Kinetis Microcontrollers freescale.com/Kinetis

Thin Film Storage (TFS) with FlexMemory Technology freescale.com/TFS

Xtrinsic Sensing Solutions freescale.com/sensors

Freescale Tower System freescale.com/Tower

Tower Geeks Community towergeeks.org

MQX Software Solutions freescale.com/MQX

CodeWarrior Development Tools freescale.com/CodeWarrior

Processor Expert freescale.com/ProcessorExpert

IAR Embedded Workbench iar.com/Freescale

Keil Microcontroller Development Kit keil.com

Green Hills Software ghs.com/products/arm_development.html

CodeSourcery: Sourcery G++ codesourcery.com/sgpp

Multilink Universal pemicro.com/universal

SEGGER: J-Link and Flasher segger.com

76 Next-Generation Microcontrollers Beyond Bits, Issue 5, Version 2

Freescale, the Freescale logo, ColdFire and CodeWarrior are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. ColdFire+, Kinetis, Processor Expert and Xtrinsic are trademarks of Freescale Semiconductor, Inc. ARM is the registered trademark of ARM Limited. Arm Cortex-M3, ARM Cortex-M4, ARMv7-ME and CoreSight are trademarks of ARM Limited. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. PEG is a trademark of Swell Software LLC, Reg. U.S. Pat. & Tm. Off. C/PEG, PEG Pro, PEG+ and PEG WindowBuilder are trademarks of Swell Software LLC. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

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