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MC68HC05RC9 MC68HC05RC18

General Release Specification

M68HC05 Microcontrollers

HC05RC18GRS/D Rev. 2.1 08/2005

freescale.com

General Release Specification — MC68HC05RC18

List of Sections

Section 1. General Description ...... 15

Section 2. Memory ...... 29

Section 3. Central Processing Unit ...... 35

Section 4. Interrupts...... 39

Section 5. Resets ...... 47

Section 6. Parallel Input/Output (I/O) ...... 55

Section 7. Low-Power Modes ...... 59

Section 8. Core Timer ...... 63

Section 9. Carrier Modulator Transmitter (CMT) ...... 69

Section 10. Instruction Set...... 87

Section 11. Electrical Specifications ...... 105

Section 12. Mechanical Specifications...... 113

Section 13. Ordering Information...... 117

Appendix A. MC68HC05RC9 ...... 121

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor List of Sections 3 NON-DISCLOSURE AGREEMENT REQUIRED List of Sections List of 4 List of Sections Freescale Semiconductor Freescale Sections of List 4 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Table of Contents

Section 1. General Description 1.1 Contents ...... 15 1.2 Introduction...... 16 1.3 Features ...... 16 1.4 Mask Options ...... 19 1.5 Signal Description...... 21 1.5.1 VDD and VSS ...... 23 1.5.2 IRQ (Maskable Interrupt Request) ...... 23 1.5.3 OSC1 and OSC2...... 23 1.5.4 RESET ...... 26 1.5.5 LPRST...... 26 1.5.6 IRO ...... 26 1.5.7 PA0–PA7...... 27 1.5.8 PB0–PB7...... 27 1.5.9 PC0–PC3 (PC4–PC7)...... 27

Section 2. Memory 2.1 Contents ...... 29 2.2 Introduction...... 29 2.3 Memory Map...... 29 2.3.1 ROM ...... 32 2.3.2 ROM Security ...... 32 2.3.3 RAM ...... 33

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Table of Contents 5 NON-DISCLOSURE AGREEMENT REQUIRED Table ofContents 6 Table of Contents Freescale Semiconductor Freescale Contents of Table 6 General Release Specif cto MC68HC05RC18 ication 3.7 Program Counter (PC) . Program Counter(PC) 3.7 .. External Interrupt(IRQ 4.6.1 . Stack Pointer(SP) 3.6 4.6 Hardware Interrupts . Interrupts Hardware 4.6 Condition CodeRegister 3.5 Index Register(X). 3.4 5.5.3 Illegal Address. . Illegal Address. Computer Operating 5.5.3 . (POR). Reset Power-On 5.5.2 . Resets Internal 5.5.1 5.5 Low-PowerExte 5.4 Reset(RESET External . 5.3 Introduction. . . 5.2 Contents 5.1 . Core TimerInterrupt Carrier ModulatorTr 4.7 External InterruptTiming 4.6.3 4.6.2 Software Interrupt(SWI). 4.5 Reset InterruptSequence. . 4.4 CPU InterruptProcessing. . 4.3 Introduction. . . 4.2 Contents 4.1 . . Accumulator (A) . 3.3 Introduction. . . 3.2 Contents 3.1 Section 3.CentralProcessingUnit Section 4.Interrupts rnal Reset (LPRST rnal Reset Section 5.Resets Section ...... ). . . ). ansmitter Interrupt(CMT rpryRst(OR . (COPR) Reset Properly . (CCR) . . . (CCR) . . . . . Pr esa). Keyscan) B /Port . . . . ) . . . .36 . .50 . .48 . .47 . .39 . .35 . .47 . .39 . .35 . .38 . .45 . .41 . .36 . .38 . .53 . .36 . .44 . .41 ) ..45 ) . .43 . .50 . .40 . .51 . .43 . .50 — Rev. 2.1 Table of Contents

Section 6. Parallel Input/Output (I/O) 6.1 Contents ...... 55 6.2 Introduction...... 55 6.3 Port A ...... 55 6.4 Port B ...... 56 6.5 Port C ...... 57 6.6 Input/Output Programming ...... 57

Section 7. Low-Power Modes 7.1 Contents ...... 59 7.2 Introduction...... 59 7.3 Stop Mode ...... 59 7.4 Stop Recovery ...... 60 7.5 Wait Mode...... 61 7.6 Low-Power Reset ...... 61

Section 8. Core Timer 8.1 Contents ...... 63 8.2 Introduction...... 63 8.3 Core Timer Control and Status Register...... 65 8.4 Core Timer Counter Register ...... 67 8.5 Computer Operating Properly (COP) Reset ...... 67 8.6 Timer During Wait Mode...... 68

Section 9. Carrier Modulator Transmitter (CMT) 9.1 Contents ...... 69 9.2 Introduction...... 69 9.3 Overview...... 70

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Table of Contents 7 NON-DISCLOSURE AGREEMENT REQUIRED Table ofContents 8 Table of Contents Freescale Semiconductor Freescale Contents of Table 8 General Release Specif cto MC68HC05RC18 ication 05IsrcinStSmay. Instruction Set Summary 10.5 045CnrlIsrcin . Control Instructions Bit Manipulation Instru 10.4.5 Instructions Jump/Branch 10.4.4 10.4.3 10.4.2 Read-Modify-Write Instructions. . Read-Modify-Write Instructions. 10.4.2 10.4.1 Register/Memory Instructions . Register/Memory Instructions 10.4.1 Stop ModeOperation. . 9.7 ModeOperation Wait 9.6 Modulator Peri . Extended SpaceOperation 9.5.4 9.5.3 04IsrcinTps. Instruction Types . . Relative 10.4 . Indexed,16-Bit Offset. 10.3.8 10.3.7 . FSK Mode 9.5.2 10.3.6 Indexed, 8-Bit Offset . Indexed, 8-BitOffset 10.3.6 . Time Mode . . Modulator 9.5.1 9.5 035Idxd oOfe . Indexed, No Offset 10.3.5 Carrier GeneratorDataRegisters 9.4.2 034Etne . . Extended . Direct. 10.3.4 . Immediate 10.3.3 . . Inherent 10.3.2 10.3.1 . Addressing Modes 10.3 . Introduction. 10.2 . . Contents 10.1 . Time Counter. . Carrier Generator 9.4.1 9.4 MR,MR,adMR). MDR3) (MDR1, MDR2,and (CHR1, CLR1, CHR2, and CLR2) . (CHR1, CLR1,CHR2,andCLR2) Section 10.InstructionSet od DataRegisters ...... tos. ctions ...... 91 . .76 . .89 . .88 . .88 . .89 . .87 . .97 . .85 . .91 . .79 . .90 . .77 . .74 . .89 . .73 . .90 . .89 . .98 . .94 . .96 . .85 . .90 . .80 . .84 . .72 . .93 . .92 — Rev. 2.1 Table of Contents

Section 11. Electrical Specifications 11.1 Contents ...... 105 11.2 Introduction...... 105 11.3 Maximum Ratings...... 106 11.4 Operating Temperature Range...... 107 11.5 Thermal Characteristics ...... 107 11.6 DC Electrical Characteristics (5.0 Vdc)...... 108 11.7 DC Electrical Characteristics (2.2 Vdc)...... 109 11.8 Control Timing (2.2 Vdc to 5.0 Vdc) ...... 111

Section 12. Mechanical Specifications 12.1 Contents ...... 113 12.2 Introduction...... 113 12.3 28-Pin Plastic Dual-In-Line Package (Case 710-02) ...... 114 12.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04)...... 114 12.5 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02)...... 115

Section 13. Ordering Information 13.1 Contents ...... 117 13.2 Introduction...... 117 13.3 MCU Ordering Forms ...... 117 13.4 Application Program Media...... 118 13.5 ROM Program Verification ...... 119 13.6 ROM Verification Units (RVUs)...... 120 13.7 MC Order Numbers ...... 120

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Table of Contents 9 NON-DISCLOSURE AGREEMENT REQUIRED Table ofContents 10 Table of Contents Freescale Semiconductor Freescale Contents of Table 10 General Release Specif cto MC68HC05RC18 ication A.1 Contents . . . Contents A.1 A.3 Memory Map. . Memory Map. A.3 . Introduction. A.2 Appendix A.MC68HC05RC9 . . . . .121 . .121 . .121 — Rev. 2.1 General Release Specification — MC68HC05RC18

List of Figures

Figure Title Page

1-1 MC68HC05RC18 Block Diagram ...... 18 1-2 28-Pin DIP Pinout...... 21 1-3 28-Pin SOIC Pinout ...... 22 1-4 44-Pin PLCC Pinout ...... 22 1-5 Crystal Connections ...... 24 1-6 2-Pin Ceramic Resonator Connections ...... 25 1-7 3-Pin Ceramic Resonator Connections ...... 25 1-8 External Clock Source Connections...... 26

2-1 MC68HC05RC18 Memory Map ...... 30 2-2 I/O Registers ...... 31

3-1 Programming Model ...... 35 3-2 Stacking Order ...... 36

4-1 Interrupt Processing Flowchart...... 42 4-2 IRQ Function Block Diagram ...... 43

5-1 Reset Block Diagram ...... 48 5-2 Reset and POR Timing Diagram ...... 49 5-3 COP Watchdog Timer Location ...... 53

6-1 Port B Pullup Options ...... 56 6-2 I/O Circuitry ...... 58

7-1 Stop Recovery Timing Diagram ...... 60 7-2 Stop/Wait Flowchart ...... 62 8-1 Core Timer Block Diagram ...... 64 8-2 Core Timer Control and Status Register (CTCSR) ...... 65

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor List of Figures 11 NON-DISCLOSURE AGREEMENT REQUIRED List ofFigures 2Ls fFgrsFreescale Semiconductor ListFigures of 12 General Release Specif cto MC68HC05RC18 ication - C8C5C eoyMp . MemoryMap MC68HC05RC9 Page A-1 Maximum SupplyCurrentversusInternal Modulator DataRegisters(M 11-1 Modulator Controland . Extended SpaceOperation 9-8 9-7 . Modulator BlockDiagram 9-6 Title Carrier DataRegister(CHR1 9-4 9-3 Timer CounterRegister 8-3 Figure - M prto nTm oe. CMT OperationinTimeMode 9-5 Carrier GeneratorBlock Carrier ModulatorTransmitter 9-2 9-1 lc rqec . Clock Frequency Status Register(MCSR) Diagram. . Diagram. (CTCR). . (CTCR). . , CLR1, CHR2, and CLR2) . ..74 . , CLR1,CHR2,andCLR2) DR1, MDR2, and M MDR2,and DR1, . . Mdl lc iga ..71 ModuleBlockDiagram . . .122 . .110 . .77 . .67 . .72 . .80 ..81 . .78 DR3) ..84 DR3) — Rev. 2.1 General Release Specification — MC68HC05RC18

List of Tables

Table Title Page

4-1 Vector Address for Interrupts and Reset ...... 41

5-1 COP Watchdog Timer Recommendations ...... 52

6-1 I/O Pin Functions ...... 58

8-1 RTI and COP Rates at 4.096-MHz Oscillator...... 66

10-1 Register/Memory Instructions...... 92 10-2 Read-Modify-Write Instructions ...... 93 10-3 Jump and Branch Instructions ...... 95 10-4 Bit Manipulation Instructions ...... 96 10-5 Control Instructions ...... 97 10-6 Instruction Set Summary ...... 98 10-7 Opcode Map...... 104

13-1 MC Order Numbers ...... 120

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor List of Tables 13 NON-DISCLOSURE AGREEMENT REQUIRED List ofTables 14 List of Tables Freescale Semiconductor Freescale Tables of List 14 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 1. General Description

1.1 Contents

1.2 Introduction...... 16 1.3 Features ...... 16 1.4 Mask Options ...... 19 1.5 Signal Description...... 21 1.5.1 VDD and VSS ...... 23 1.5.2 IRQ (Maskable Interrupt Request) ...... 23 1.5.3 OSC1 and OSC2...... 23 1.5.3.1 Crystal Resonator ...... 24 1.5.3.2 Ceramic Resonator ...... 25 1.5.3.3 External Clock Signal...... 26 1.5.4 RESET ...... 26 1.5.5 LPRST...... 26 1.5.6 IRO ...... 26 1.5.7 PA0–PA7...... 27 1.5.8 PB0–PB7...... 27 1.5.9 PC0–PC3 (PC4–PC7)...... 27

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 15 NON-DISCLOSURE AGREEMENT REQUIRED General Description 16 General Description Freescale Semiconductor Freescale Description General 16 General Release Specif Features 1.3 Introduction 1.2 cto MC68HC05RC18 ication Features oftheMC count packages. (PLCC). FouradditionalI/Olinesare 29-pin dual-in-linepackage available ina28-pinsmalloutline and pullups)alow-powerre RAM. Thereare20 Kbyte memorymaphas15,936byte chip peripheralsincludeacarrier (RTI) andcomputeroperatingpr (CPU) core,includingth remote controlapplications.Itcontai M68HC05 Familyofmicr The MC68HC05RC18isagene Carrier ModulatorTr • 14-StageCoreTimerwithR • 352BytesofOn-ChipRAM • 64Bytes ofBurn-InROM • 15,936 Bytes ofUserROM • FullyStaticOperation • 4.2-MHz MaximumOscillatorFr • On-Chip Oscillatorwith • 28-PinSOIC,DIP, • HC05 Core • LowCost • Protocols Length Modulator(PLM), and Computer OperatingProper input-output(I/O)lines 68HC05RC18 include: e 14-stagecoretimerwi ocontroller units(MCUs) ansmitter (CMT)Support (DIP),ora44-pinpl Crystal/CeramicResonator or44-PinPLCCPackages ral-purpose, low-co set pin.TheMC68HC05RC18is operly (COP)watchdogsystems.On- modulator transmitter(CMT).The16- integrated circuit(SOIC)package,a ly (COP)WatchdogCircuits eal-Time Interrupt(RTI)and ns theHC05centralprocessingunit Frequency ShiftKeying (FSK) s ofuserROMand352bytes available forbond equency at2.2to (eight havingkeyscanlogic astic leadedchipcarrier th real-timeinterrupt andissuitablefor ing Baseband,Pulse st additiontothe out inhigherpin 5.0 VoltSupply — Rev. 2.1 General Description

• Low-Power Reset Pin • 20 Bidirectional Input/Output (I/O) Lines (Four Additional I/O Lines Available for Bond Out in Higher Pin Count Packages) • Mask Programmable Interrupts and Pullups on Eight Port Pins (PB0–PB7) • High-Current Infrared (IR) Drive Pin • High-Current Port Pins (PC0–PC3) • Power-Saving Stop and Wait Modes • Mask Selectable Options: – COP Watchdog Timer – STOP Instruction Disable – Edge-Sensitive or Edge- and Level-Sensitive Interrupt Trigger – Port B Interrupts for Keyscan, with Two Optional Pullup Strengths

NOTE: A line over a signal name indicates an active-low signal. For example, RESET is active low.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 17 NON-DISCLOSURE AGREEMENT REQUIRED General Description 18 General Description Freescale Semiconductor Freescale Description General 18 General Release Specif LPRST RESET OSC1 OSC2 * Marked pinsareavailable only V IRQ V DD SS IRQEN SYSTEM COP OSCILLATOR CONDITION CODEREGISTER 0 cto MC68HC05RC18 ication CPU REGISTERS 0 CONTROL in higher pincount (>28)packages. CPU iue1-1.MC68HC Figure 0 0 SYSTEM BURN-IN ROM—64BYTES RTI ROM — 15,936ROM — BYTES 0 SRAM — 352BYTES SRAM PROGRAM COUNTER PROGRAM 0 M68HC05 CPU 0 ÷ 2 1 1 1 1 INDEX REGISTER CORE TIMER ACCUMULATOR SYSTEM 1 PROCESSOR STACK POINTER INTERNAL H CLOCK 05RC18 BlockDiagram ALU I N Z C IRQEN TRANSMITTER MODULATOR

DATA DIRECTION REGISTER DATA DIRECTION REGISTER DATA DIRECTION REGISTER CARRIER

PORT B PORT A PORT C KEYSCAN PULLUPS — PC5* PC4* PC3 PC2 PC1 PC0 PC7* PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PA7 Rev. 2.1 IRO PC6* PB5 PB4 PB3 PB2 PB1 PB0 PA6 General Description

1.4 Mask Options

The MC68HC05RC18 has a total of 13 mask options, including:

• Eight Port B Interrupt Enables (one for each pin) • Port B Pullup Enable • Port B Strong/Weak Pullup Select • IRQ Sensitivity • COP Enable/Disable • STOP Enable/Disable

The following are nonprogrammable options in that they are selected at the time of code submission when masks are made:

PB7IE — Port B7 Interrupt Enable This option enables or disables the interrupt generation on port B bit 7. 1 = Enables the interrupt 0 = Disables the interrupt

PB6IE — Port B6 Interrupt Enable This option enables or disables the interrupt generation on port B bit 6. 1 = Enables the interrupt 0 = Disables the interrupt

PB5IE — Port B5 Interrupt Enable This option enables or disables the interrupt generation on port B bit 5. 1 = Enables the interrupt 0 = Disables the interrupt

PB4IE — Port B4 Interrupt Enable This option enables or disables the interrupt generation on port B bit 4. 1 = Enables the interrupt 0 = Disables the interrupt

PB3IE — Port B3 Interrupt Enable This option enables or disables the interrupt generation on port B bit 3. 1 = Enables the interrupt 0 = Disables the interrupt

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 19 NON-DISCLOSURE AGREEMENT REQUIRED General Description 20 General Description Freescale Semiconductor Freescale Description General 20 General Release Specif cto MC68HC05RC18 ication PULLEN —PullupEnable Enable PB0IE —PortB0Interrupt Enable PB1IE —PortB1Interrupt Enable PB2IE —PortB2Interrupt STOPEN —STOPIn COPEN —COPEnable SWPUSEL —Strong This optionselectsbetweeneithert This optionwilldisable This optionenablesordisablesthe This optionenablesordisablesthe This optionenablesordisablesthe instruction isdisabled. When theSTOPoption isdeselec instruction isenabled. When theSTOPoptionissele timer isdisabled. When theCOPoptionisdeselecte timer isenabled. When theCOPoptionisselected for anyofthepo pin thathasits 0 =Disablestheinterrupt 1 =Enablestheinterrupt 0 =Disablestheinterrupt 1 =Enablestheinterrupt 0 =Disablestheinterrupt 1 =Enablestheinterrupt 0 =Selectsthestrongpullups 1 =Selectstheweakpullups 0 =Disablesallpullups 1 =Enablespullupsforenabled interrupt enabled. rt Bpullupsthatareenabled. /Weak PullupSelect struction Enable all pullupsorenablethe cted (STOPEN=1),theSTOP ted (STOPEN=0),the STOP (COPEN =1),th d (COPEN=0),theCOPwatchdog he strongpullupor interrupt generationonportBbit0. interrupt generationonportBbit1. interrupt generationonportBbit2. interrupts,othersdisabled. pullups ofanyportB e COPwatchdog the weakpullup — Rev. 2.1 General Description

NOTE: When the STOP instruction is disabled, executing a STOP instruction is equivalent to executing a WAIT instruction, except that the core timer is reset.

IRQ — IRQ sensitivity When the IRQ option is selected (LEVEL = 1), edge- and level- sensitive IRQ is enabled. When the IRQ option is deselected (LEVEL = 0), edge-only sensitive IRQ is enabled.

1.5 Signal Description

The MC68HC05RC18 is available in

1. 28-pin dual-in-line package (DIP) see Figure 1-2 2. 28-pin small outline integrated circuit (SOIC) package see Figure 1-3 3. 44-pin plastic leaded chip carrier (PLCC) package see Figure 1-4

The signals are described in the following subsections.

PB0 1 28 OSC1 PB1 2 27 OSC2 PB2 3 26 VDD PB3 4 25 IRQ PB4 5 24 RESET PB5 6 23 IRO

PB6 7 22 VSS PB7 8 21 LPRST PA0 9 20 PC3 PA1 10 19 PC2 PA2 11 18 PC1 PA3 12 17 PC0 PA4 13 16 PA7 PA5 14 15 PA6

Figure 1-2. 28-Pin DIP Pinout

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 21 NON-DISCLOSURE AGREEMENT REQUIRED General Description 22 General Description Freescale Semiconductor Freescale Description General 22 General Release Specif cto MC68HC05RC18 ication PC7 PC6 PA1 PA0 PB7 PB6 PB5 PB4 NC NC NC NOTE: NC = No Connect NC=No NOTE: Figure 1-4.44-PinPLCCPinout Figure 1-3.28-PinSOICPinout 17 16 15 14 13 12 11 10 9 8 7 level (either V logic appropriate should betiedtoan All noconnects NC 18 6 NC PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA2 19 5 PB3

PA3 20 4 PB2 14 13 12 11 10 9 8 7 6 5 4 3 2 1

DD PA4 21 3 PB1 orV PA5 22 2 PB0 SS NC 23 1 NC ). PA6 24 44 OSC1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PA7 25 43 OSC2

PC0 26 42 VDD PA6 PA7 PC0 PC1 PC2 PC3 LPRST V IRO IRQ V OSC2 OSC1 RESET PC1 27 41 IRQ SS DD NC 28 40 NC 31 32 33 34 35 36 37 38 39 29 30 NC PC2 PC3 PC4 PC5 NC LPRST V IRO RESET NC SS — Rev. 2.1 General Description

1.5.1 VDD and VSS Power is supplied to the microcontroller’s digital circuits using these two

pins. VDD is the positive supply and VSS is ground.

1.5.2 IRQ (Maskable Interrupt Request)

This pin has a user-specified mask option that provides one of two different choices of interrupt triggering sensitivity. The options are: 1. Negative edge-sensitive triggering only 2. Both negative edge-sensitive and level-sensitive triggering The MCU completes the current instruction before it responds to the

interrupt request. When IRQ goes low for at least one tILIH, a logic 1 is latched internally to signify that an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic 1 and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence.

If the option is selected to include level-sensitive triggering, the IRQ input

requires an external resistor to VDD for wired-OR operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.

Refer to Section 4. Interrupts for more detail.

1.5.3 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the 2-pin on- chip oscillator. The oscillator can be driven by any of the following:

• Crystal resonator • Ceramic resonator • External clock signal

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 23 NON-DISCLOSURE AGREEMENT REQUIRED General Description 24 General Description Freescale Semiconductor Freescale Description General 24 General Release Specif 1.5.3.1 CrystalResonator NOTE: NOTE: cto MC68HC05RC18 ication mount thecrystalandca account forallstraylayo load capacitancevaluesusedinth internal oscillatorbytwotoprod or tuningfork crystal. might overdriveorhaveth Use anAT-cutcrystaland values requiredtoprovidereliabl because thecrystalparametersdeter parallel resonantcrystal.Followt The circuitin of f The frequencyoftheinter op . iue1-5 Figure * Starting value only. Follow crystal supplier’srecommenda- crystal only.Follow value Starting * . startup and maximumstability. and startup . values regardingcomponent tions . iue1-5. CrystalConnections Figure 30 pF* showsacrystaloscillat ut capacitances.Tomini pacitors asclosepossibletothepins. e incorrectcharacterist nal oscillatorisf notastriportuning S1OSC2 OSC1 4.2 MHz 4.2 10 M 10 MCU uce theinternalclockwithafrequency he crystalsupplier’srecommendations, XTAL e startupandmaximu Ω e oscillatorcircui * mine theexter thatwillpr osc 30 pF* . TheMCUdividesthe fork crystal.TheMCU ovide reliable ovide reliable or circuit for an AT-cut, anAT-cut, for or circuit ic impedanceforastrip mize outputdistortion, t designshould nal component m stability.The — Rev. 2.1 General Description

1.5.3.2 Ceramic Resonator

To reduce cost, use a ceramic resonator instead of a crystal. Use the circuit shown in Figure 1-6 for a 2-pin ceramic resonator or the circuit shown in Figure 1-7 for a 3-pin ceramic resonator and follow the resonator manufacturer’s recommendations.

MCU OSC1 OSC2

CERAMIC RESONATOR C C

Figure 1-6. 2-Pin Ceramic Resonator Connections

MCU OSC1 OSC2

CERAMIC RESONATOR C C

Figure 1-7. 3-Pin Ceramic Resonator Connections

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 25 NON-DISCLOSURE AGREEMENT REQUIRED General Description 26 General Description Freescale Semiconductor Freescale Description General 26 1.5.6 IRO General Release Specif 1.5.5 LPRST 1.5.4 RESET 1.5.3.3 ExternalClock Signal

cto MC68HC05RC18 ication biasing logic.See modulator transmitter subsystem whic The IRO pinis the high-cu immunity. See contains aninternalSchmitttriggeras with allprocessorclocksandcr power resetmode.Inlo The LPRST as partofitsinputtoim RESET pulling This active-lowpinisusedtoreset 1-8 Figure resonator andcapacitorsasclose stray layoutcapacitances.Tomini capacitance valuesusedintheoscill reliable startingdepend The externalcomponentvaluesr iue1-8.External Figure .) pinisanactive-low low. The RESET low.The Section 5.Resets Section 9.CarrierModul prove noiseimmunity.See w-power resetmode,the upon theresonatorpar OSC1 rrent sourceandsink MCU pinandisusedto ystal oscillator pincontainsaninternalSchmitttrigger Clock SourceConnections equired formaximu . mize outputdistor OSC2 as possibletothepins.(See the MCUtoaknownstartupstateby < ator circuitdesi EXTERNAL CLOCK partofitsinputtoimprovenoise h issuitablefo UNCONNECTED ator Transmitter(CMT) halted.TheLP ameters. Theload output ofthecarrier MCU isheldinreset put theMCUintolow- Section 5.Resets gn shouldincludeall tion, mountthe m stabilityand r drivingIRLED RST — Rev. 2.1 pin . . General Description

1.5.7 PA0–PA7

These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as inputs during power-on or reset. For detailed information on I/O programming, see 6.6 Input/Output Programming.

1.5.8 PB0–PB7

These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as inputs during power-on or reset. Each port B I/O line has a mask optionable interrupt/pullup for keyscan. For detailed information on I/O programming, see 6.6 Input/Output Programming.

1.5.9 PC0–PC3 (PC4–PC7)

These eight I/O lines comprise port C. PC0–PC3 are high-current pins. PC4–PC7 are standard drive pins and are available only in higher pin count (>28) packages. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. For detailed information on I/O programming, see 6.6 Input/Output Programming.

NOTE: Only four bits of port C are bonded out in 28-pin packages for the MC68HC05RC18, although port C is truly an 8-bit port. Since pins PC4–PC7 are unbonded, software should include the code to set their respective data direction register locations to outputs to avoid floating inputs.

NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC05RC18 do not require termination, termination is recommended to reduce the possibility of static damage.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor General Description 27 NON-DISCLOSURE AGREEMENT REQUIRED General Description 28 General Description Freescale Semiconductor Freescale Description General 28 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 2. Memory

2.1 Contents

2.2 Introduction...... 29 2.3 Memory Map...... 29 2.3.1 ROM ...... 32 2.3.2 ROM Security ...... 32 2.3.3 RAM ...... 33

2.2 Introduction

This section describes the organization of the on-chip memory.

2.3 Memory Map

The MC68HC05RC18 has a 16-Kbyte memory map consisting of user ROM, RAM, burn-in ROM, control registers, and input/output (I/O).

Figure 2-1 is a memory map of the MCU. Figure 2-2 is a more detailed memory map of the I/O register section.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Memory 29 NON-DISCLOSURE AGREEMENT REQUIRED Memory 30 Memory Freescale Semiconductor Freescale Memory 30 General Release Specif $3FEF $3FAF $3FFF $3FB0 $00C0 $00BF $3FF0 $00FF $017F $001F $0180 $0100 $0020 $0000 USER VECTORS BURN-IN ROM & VECTORS 15,920 BYTES 128 BYTES 160 BYTES 16 BYTES 64 BYTES 32 BYTES cto MC68HC05RC18 ication USER ROM RAM RAM I/O 64 BYTES STACK iue2-1.MC68HC05RC18Memory Map Figure 16,383 16,368 16,367 16,304 16,303 0384 0383 0256 0255 0192 0191 0032 0031 0000 CORE TIMER CONTROLCORE TIMER&STATUSREG. PORT C DATA DIRECTION REGISTERPORT CDATADIRECTION PORT B DATA DIRECTION REGISTERPORT BDATADIRECTION REGISTERPORT ADATADIRECTION CORE TIMERVECTOR(HIGHBYTE) CORE TIMER COUNTER REGISTER CORE TIMER VECTOR (LOW BYTE) TIMER VECTOR(LOW CORE IR TIMER VECTOR(HIGHBYTE)IR IR TIMER VECTOR (LOWBYTE) IR TIMER RESET VECTORRESET (HIGH BYTE) RESET VECTORRESET (LOWBYTE) IRQ/PTB KEYSCANPULLUPS IRQ/PTB KEYSCAN PULLUPSIRQ/PTB KEYSCAN SWI VECTOR (HIGHBYTE) SWI PORT C DATAREGISTER PORT SWI VECTOR (LOW BYTE) PORT BDATAREGISTER PORT ADATAREGISTER VECTOR (HIGHBYTE) VECTOR (LOW BYTE) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CMT MDR1 CMT CLR2 CMT MDR3 CMT MDR2 RESERVED CMT MCSR CMT CHR1 CMT CLR1 CMT CHR2 UNUSED UNUSED ...... $3FFB $0A $3FFF $3FFE $3FFD $3FFC $09 $08 $07 $06 $05 $04 $03 $02 $01 $00 $15 $1F $18 $17 $3FF0 $3FF8 $1E $13 $16 $0F $3FFA $3FF6 $11 $10 $14 $12 $3FF9 $3FF7 $3FF5 ...... — Rev. 2.1 Memory

AddrRegister NameBit 7654321Bit 0

$00 Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

$01 Port B Data Register PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

$02 Port C Data Register PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

$03 ReservedRRRRRRRR

$04 Port A Data Direction Register DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

$05 Port B Data Direction Register DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0

$06 Port C Data Direction Register DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

$07 ReservedRRRRRRRR

$08 Timer Control and Status Register CTOF RTIF TOFE RTIE TOFC RTFC RT1 RT0

$09 Timer Counter Register

$0A ReservedRRRRRRRR

$0B ReservedRRRRRRRR

$0C ReservedRRRRRRRR

$0D ReservedRRRRRRRR

$0E ReservedRRRRRRRR

$0F ReservedRRRRRRRR

Carrier Generator High $10 IROLN CMTPOL PH5 PH4 PH3 PH2 PH1 PH0 Data Register 1 (CHR1)

Carrier Generator Low $11 IROLP 0 PL5 PL4 PL3 PL2 PL1 PL0 Data Register 1 (CLR1)

Carrier Generator High $12 0 0 SH5 SH4 SH3 SH2 SH1 SH0 Data Register 2 (CHR2)

Carrier Generator Low $13 0 0 SL5 SL4 SL3 SL2 SL1 SL0 Data Register 2 (CLR2)

Modulator Control and $14 EOC 0 EIMSK EXMRK BASE MODE EOCIE MCGEN Status Register (MCSR)

$15 Modulator Data Register 1 (MDR1) MB11 MB10 MB9 MB8 SB11 SB10 SB9 SB8

$16 Modulator Data Register 2 (MDR2) MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0

R= Reserved Figure 2-2. I/O Registers

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Memory 31 NON-DISCLOSURE AGREEMENT REQUIRED Memory 32 Memory Freescale Semiconductor Freescale Memory 32 General Release Specif 2.3.2 ROMSecurity 2.3.1 ROM Addr Register Name Bit 7654321Bit 0 $1D ReservedRRRRRRRR$1C ReservedRRRRRRRR $1E ReservedRRRRRRRR$1B$1A ReservedRRRRRRRR ReservedRRRRRRRR 1 ouao aaRgse MR)S7S6S5S4S3S2S1SB0 SB1 SB2 SB3 SB4 SB5 SB6 $19 ReservedRRRRRRRR SB7 $18 ReservedRRRRRRRR Modulator DataRegister3(MDR3) $17 cto MC68HC05RC18 ication 1. No security feature is absolutely secure. Howe secure. 1. security feature is absolutely No software remainsproprietary. Security hasbeenincorporated locations. $3FF2, $3FF3,$3FF4,and and interruptvectors.Thesix Ten oftheuservectors, The burn-inROMisloca $3FAF and16bytesof The userROMconsistsof15,920byte values atlocations prevent externalviewingoftheRO copying the ROM difficult for unauthorized users. ROMdifficultforunauthorized the copying iue2-2.I/OR Figure R= Reserved $2000–$2008, customerscan egisters (Continued) user vectorslocate $3FF6through$3F ted from$3FB0to$3FEF. $3FF5 —aregeneral- 1 remaining locati into theMC68HC M contents.Byhavinguniquedata ver, Freescale’s strategy s ofROMlocatedfrom$0180to d from$3FF0to$3FFF. FF, arededicatedtoreset ons —$3FF0,$3FF1, 05RC18 tohelp help ensurethattheir purpose userROM is to make reading or — Rev. 2.1 Memory

2.3.3 RAM

The user RAM consists of 352 bytes of a shared stack area. The RAM starts at address $0020 and ends at address $017F. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.

NOTE: Using the stack area for data storage or temporary work locations requires care to prevent the area from being overwritten due to stacking from an interrupt or subroutine call.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Memory 33 NON-DISCLOSURE AGREEMENT REQUIRED Memory 34 Memory Freescale Semiconductor Freescale Memory 34 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 3. Central Processing Unit

3.1 Contents

3.2 Introduction...... 35 3.3 Accumulator (A) ...... 36 3.4 Index Register (X)...... 36 3.5 Condition Code Register (CCR) ...... 36 3.6 Stack Pointer (SP) ...... 38 3.7 Program Counter (PC) ...... 38

3.2 Introduction

This section describes the registers of the MC68HC05RC18 central processor unit (CPU). The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2.

A ACCUMULATOR

X INDEX REGISTER

13 0

PC PROGRAM COUNTER

13 70

0 0 0 0 0 0 11 SP STACK POINTER

CCR

HINZC CONDITION CODE REGISTER

Figure 3-1. Programming Model

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Freescale Semiconductor Central Processing Unit 35 NON-DISCLOSURE AGREEMENT REQUIRED Central Processing Unit 36 Central Processing Unit Freescale Semiconductor Freescale Unit Processing Central 36 General Release Specif 3.5 ConditionCodeRegister(CCR) 3.4 IndexRegister(X) (A) Accumulator 3.3 cto MC68HC05RC18 ication The CCRisa5-bitregister used asatemporarystoragearea. value tocreateaneffectiveaddress. The indexregisterisan operands andresultsof The accumulatorisageneral-purpose to enableordisableinte indicate theresultsofinstructio NOTE: Since the stack pointer decrements decrements pointer stack Since the NOTE: INCREASING ADDRESSES MEMORY followed by PCH, etc.Pullingfrom followed byPCH, UNSTACK R N R U E T 70 70 70 111 iue3-2. StackingOrder Figure arithmeticcalculations rrupts. Thesebitscan 8-bit registerusedfo inwhichtheH,N,Z, INDEX REGISTER ACCUMULATOR CONDITION CODE REGISTER PCH PCL the stack is in the reverseorder. the stackisin n justexecuted,andtheIbitisused during pushes, the PCL X A Theindexregister 8-bit registerusedtohold r theindexedaddressing be individuallytestedby ordatamanipulations. andCbitsareusedto U R R N P E T T I is stacked first, is stacked STACK mayalsobe DECREASING ADDRESSES MEMORY — Rev. 2.1 Central Processing Unit

a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs.

CCR

HINZC

Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared.

Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative.

Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.

Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.

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Freescale Semiconductor Central Processing Unit 37 NON-DISCLOSURE AGREEMENT REQUIRED Central Processing Unit 38 Central Processing Unit Freescale Semiconductor Freescale Unit Processing Central 38 General Release Specif (PC) ProgramCounter 3.7 (SP) Pointer Stack 3.6 NOTE: cto MC68HC05RC18 ication Kbyte memorymap. implementation, however, The HC05CPUcoreiscapa next bytetobefetched. The programcounterisa13-bitregister two locationsonthestack;anin and losesthepreviouslystoredinform locations. If64locati to $00C0.Subroutinesandinterr significant registerbits set to00000011.Theseeightbits When accessingmemory,theeightmost is pulledfromthestack. decremented asdataispushedonto the stackpointerissettoloca stack. DuringanMCUresetorthere The stackpointercontains 30 13 370 7 13 0001SP 00000011 ons areexceeded,thest toproduceanaddresswi theaddressingregister theaddressofnext ble ofaddressing16-bit tion $00FF.Thestackpointeristhen terrupt usesfivelocations. upts mayuseupto64(decimal) areappendedto PC set stackpointer(R the stackandincrementedasdata ation. Asubroutinecalloccupies thatcontainstheaddressof significantbitsarepermanently ack pointerwrapsaround thin therangeof$00FF s arelimitedtoa16- freelocationonthe the sixleast locations. Forthis SP) instruction, — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 4. Interrupts

4.1 Contents

4.2 Introduction...... 39 4.3 CPU Interrupt Processing...... 40 4.4 Reset Interrupt Sequence...... 41 4.5 Software Interrupt (SWI)...... 41 4.6 Hardware Interrupts ...... 43 4.6.1 External Interrupt (IRQ/Port B Keyscan) ...... 43 4.6.2 External Interrupt Timing...... 44 4.6.3 Carrier Modulator Transmitter Interrupt (CMT) ...... 45 4.7 Core Timer Interrupt ...... 45

4.2 Introduction

The MCU can be interrupted four different ways, which are discussed in this section. They are:

1. Nonmaskable Software Interrupt Instruction (SWI) 2. External Asynchronous Interrupt (IRQ/Port B Keyscan) 3. Internal Carrier Modulator Transmitter Interrupt 4. Internal Core Timer Interrupt

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Freescale Semiconductor Interrupts 39 NON-DISCLOSURE AGREEMENT REQUIRED Interrupts 40 Interrupts Freescale Semiconductor Freescale Interrupts 40 General Release Specif InterruptProcessing CPU 4.3 cto MC68HC05RC18 ication the currentCPUregist interrupt occurs,theprocessorcomple processing. Otherwise,thenextinst receives aninterruptrequest,thepr processing. 4-1 Figure overhead. must includethe firstinstruct latencytothe maximum The M68HC05CPUdoesnot the appropriateinterruptso When aninterruptistobeprocess state. is executedthesameasanyotherin highest vectorlocationshownin interrupt ispendingafterthestacking and finallychecksthep If interruptsarenotma complete. next instructionthatwastobeexec be recoveredfromthe routine iscompleted.The An RTIinstructionisusedtosignif locations $3FF6–$3FFFasdefinedin to behalted,but notca interruptsdo hardware reset, and tosettheinterruptmask Interrupts causetheprocessorto Latency =(Longestinstruction showsthesequenceofevents are consideredpendinguntilth longest instructionexecut er state,setstheIbitto sked (I bit in theCCRis sked (Ibitin stack andnormalprocessi ending hardwareinterr RTI instructioncausest ftware serviceroutinefr (I bit)topreventaddi support interruptible al 4-1 Table execution time+10)xt save registerco y whentheinterruptsoftwareservice ed, theCPUfetchesaddressof use thecurrentinst ruction isfetchedandexecuted.Ifan uted whentheinterr ocessor willproceedwithinterrupt ion oftheinterrup struction, regardlessoftheI-bit operation,thein tes thecurrentinstruction,stacks al 4-1 Table will be serviced first. The SWI The first. serviced be will that occursduringinterrupt ion timeplusstacking inhibitfurtherinterrupts, upts. Ifmorethanone clear) whentheCPU clear) e currentinstructionis . tional interrupts.Unlike he registercontentsto ng toresumeatthe ntents onthestack om thevectortableat instructions.The t serviceroutine ruction execution terrupt withthe upt tookplace. cyc seconds — Rev. 2.1 Interrupts

4.4 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-1. A low-level input on the RESET pin or an internally generated RST signal, causes the program to vector to its starting address, which is specified by the contents of memory locations $3FFE and $3FFF. The I bit in the condition code register is also set. The MCU is configured to a known state during this type of reset.

Table 4-1. Vector Address for Interrupts and Reset

Flag Vector Register Name Interrupt CPU Interrupt Address

N/A N/A Reset RESET $3FFE–$3FFF

N/A N/A Software Interrupt SWI $3FFC–$3FFD

N/A N/A External Interrupts* IRQ $3FFA–$3FFB

MCSR EOC End of Cycle Interrupt CMT $3FF8–$3FF9

CTOF, Real Time Interrupt CTCSR CORE TIMER $3FF6–$3FF7 RTIF Core Timer Overflow

*External interrupts include IRQ and port B keyscan sources.

4.5 Software Interrupt (SWI)

The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after interrupts that were pending before the SWI was fetched or before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Interrupts 41 NON-DISCLOSURE AGREEMENT REQUIRED Interrupts 42 Interrupts Freescale Semiconductor Freescale Interrupts 42 General Release Specif FROM STACK: CCR, A, X, PC. RESTORE REGISTERS cto MC68HC05RC18 ication iue4-1 Figure Y Y IRQ /PORT B KEYSCAN INTERRUPTS? INSTRUCTION. INSTRUCTION. INSTRUCTION INSTRUCTION INTERRUPT? CORE TIMER INTERRUPT? FETCH NEXT EXTERNAL INTERNAL INTERNAL EXECUTE RESET IN CCR N FROM . SET? I BIT CMT SWI RTI Interrupt Processing Flowchart ? ? N N N N N Y Y Y Y CLEAR? EIMSK N Y CLEAR IRQ REQUEST LATCH LOAD PCFROM APPROPRIATE CC REGISTER. PC, X, A,CCR. PC, SET I BIT IN SET IBIT VECTOR. STACK — Rev. 2.1 Interrupts

4.6 Hardware Interrupts

All hardware interrupts except RESET are maskable by the I bit in the CCR. If the I bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts.

The three types of hardware interrupts, which are explained in the following sections, are: 1. External interrupt 2. Core timer interrupt 3. Carrier modulator transmitter interrupt

4.6.1 External Interrupt (IRQ/Port B Keyscan)

The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ function is shown in Figure 4-2.

NOTE: The BIH and BIL instructions will apply to the level on the IRQ pin itself and to the output of the logic OR function with the port B IRQ interrupts. The states of the individual port B pins can be checked by reading the appropriate port B pins as inputs.

TO BIH & BIL INSTRUCTION V DD SENSING

IRQ PIN IRQ PORT B LATCH TO IRQ PROCESSING IRQ CLEAR R IN CPU

EIMSK

LEVEL (MASK OPTION)

Figure 4-2. IRQ Function Block Diagram

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Freescale Semiconductor Interrupts 43 NON-DISCLOSURE AGREEMENT REQUIRED Interrupts 44 Interrupts Freescale Semiconductor Freescale Interrupts 44 4.6.2 ExternalInterruptTiming General Release Specif cto MC68HC05RC18 ication Data Registers(M the IRQ the The interruptrequestislatchedimmedi (internal andexternal)ar ofth maskbit(Ibit) If theinterrupt processing theexternalinterrupt. Reset clearstheinterruptlatch, point, theexternalinterruptwillbefo pending withintheinterrupt any externalinterrupt MSCR registerofthe External interruptscanalsobema pin. sensitive tothreecases: When edgeandlevelsensitivityisselect only triggerisavailabl Either alevel-sensit serviced asspecifiedbyt two cases: When edgesensitivityisselectedforthe feature isenabledass (PB0–PB7) actasotherexternalin The IRQ .Fallingedgeorlowle 3. FallingedgeontheIRQ 2. LowlevelontheIRQ 1. Fallingedgeonany 2. .FallingedgeontheIRQ 1. source.Theinterruptrequestis pinisonesourceofanexter DR1, MDR2,andMDR3) ive andedge-sensitivetri IR remote timer. See See timer. remote IR e viathemaskprogramm received setstheinte pecified bytheuser. e disabled.Clearin he contentsof$3FFAand$3FFB. portBpinwith pin module untiltheEIMSKbi vel onanyportBpin pin pin as willtheCPUw e CCR is set, all maskable interrupts e CCRisset,allmaskableinterrupts sked bysettingtheEIMSKbitin terrupt sources if their interrupt interrupt their sourcesif terrupt rwarded totheCPUforprocessing. nal interrupt.All ately followingthefallingedgeof then synchronizedinternallyand ed fortheIRQin interruptenabled IRQ interrupt,itissensitiveto g theIbitenablesinterrupts. 9.5.4 Modulat rrupt latchandremains fordetails.Whenmasked, gger oranedge-sensitive- able optionfortheIRQ with interruptenabled hen itfinishes t iscleared,atthat portBpins terrupt, itis or Period — Rev. 2.1

Interrupts

4.6.3 Carrier Modulator Transmitter Interrupt (CMT)

A CMT interrupt is generated when the end of cycle flag (EOC) and the end of cycle interrupt enable (EOCIE) bits are set in the modulator control and status register (MCSR). This interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $3FF8 and $3FF9. Note that the CMT will not generate any new interrupts while the chip is in wait mode, regardless of the state of the status register (MCSR).

4.7 Core Timer Interrupt

This timer can create two types of interrupts. A timer overflow interrupt occurs whenever the 8-bit timer rolls over from $FF to $00 and the enable bit TOFE is set. A real-time interrupt occurs whenever the programmed time elapses and the enable bit RTIE is set. Either of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory locations $3FF6 and $3FF7.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Interrupts 45 NON-DISCLOSURE AGREEMENT REQUIRED Interrupts 46 Interrupts Freescale Semiconductor Freescale Interrupts 46 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 5. Resets

5.1 Contents

5.2 Introduction...... 47 5.3 External Reset (RESET)...... 48 5.4 Low-Power External Reset (LPRST) ...... 50 5.5 Internal Resets ...... 50 5.5.1 Power-On Reset (POR)...... 50 5.5.2 Computer Operating Properly Reset (COPR) ...... 51 5.5.2.1 Resetting the COP ...... 51 5.5.2.2 COP During Wait Mode ...... 51 5.5.2.3 COP During Stop Mode ...... 51 5.5.2.4 COP Watchdog Timer Considerations...... 52 5.5.2.5 COP Register...... 53 5.5.3 Illegal Address...... 53

5.2 Introduction

The MCU can be reset from five sources: two external inputs and three internal restart conditions. The RESET and LPRST pins are inputs as shown in Figure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Resets 47 NON-DISCLOSURE AGREEMENT REQUIRED Resets 48 Resets Freescale Semiconductor Freescale Resets 48 General Release Specif 5.3 ExternalReset(RESET RESET LPRST ADDRESS ADDRESS IRQ DATA OSC V DD NOTE: COP WATCHDOG cto MC68HC05RC18 ication POWER-ON RESET ILLEGAL ADDRESS (COPR) (ILLADDR) place theMCUinanonuserope the internalCOPwatchdogresetar operating mode. the CPUandperiphera MCU inusermodewhile threshold. Thisactive-lowinputwi threshold andremainsin device, unlessotherwisespecified. Activation oftheRSTsi external resetoccurswhenevertheRESET threshold voltageseparatedbyami connected toaSchmitttriggerinpu The RESET (POR) Figure 5-1. ResetBlockDiagram 5-1. Figure ) pinisoneofthetwo ls. Terminationof gnal isgenerallyreferredtoasresetofthe resetuntiltheRESET the illegaladdressre CLOCKED rating mode. external sourcesof PH2 ll generatetheRS t gatetoprovideanupperandlower e theonlyresetsourcesthatcan nimum amountof D D LATCH LATCH the externalRESET S R pinispulledbelowthelower POR andLPRST TO OSCILLATOR MODULETO OSCILLATOR pinrisesabovetheupper set hasnoeffecton RST CPU T signalandreset a reset.Thispinis hysteresis. This SELECT PERIPHERALS TO IRQ TO LOGIC MODE TO OTHER input or input placethe — Rev. 2.1 Resets 1 2 1 1 DD OSC1 V BUS DATA BUS CLOCK RESET INTERNAL INTERNAL ADDRESS INTERNAL PROCESSOR 0 V CYC 4064 t 4064 NEW 3FFE CYC t NEW 3FFF . DD NEW PC OP CODE PCL PCH NEW PC initiates the reset sequence. RL 3 t and POR Timing Diagram 3FFE PCH 3FFE 3FFE 3FFE to be recognized as a power-on reset on the next rise of V equency. It is only used to represent time. ation is not available externally. POR PCL Figure 5-2. Reset NEW PC 3FFF OP CODE NEW PC 4 POR must fall to a level lower than V > V DD 2. OSC1 line is not meant to represent fr 1. Internal timing signal and bus inform 3. following edge of RESET the rising edge of the clock The next rising internal processor 4. V NOTES:

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Resets 49 NON-DISCLOSURE AGREEMENT REQUIRED Resets 50 Resets Freescale Semiconductor Freescale Resets 50 General Release Specif 5.5.1 Power-OnReset(POR) Internal Resets 5.5 Low-PowerExternalReset(LPRST 5.4 cto MC68HC05RC18 ication (t the MCUremaininginre upper threshold.Thisacti This externalresetoccurswhenevertheLPRST signal remainsinthere reset functionisacti The PORgeneratestheRSTsignalthat cycles (PH2)aftertheo an oscillatorstabilizationdelayof able todetectadropin to stabilize.ThePORis The internalPORisgeneratedonpower- illegal addressresethas operating mode.PORandLPRST timer aretheonlyresetsourcesthat Termination ofthe function, theCOPwatchdog The threeinternallygener remains inthere function isactiveat a logic1isappliedtoLP asl resetcondition low-power processor clocksandthecr RST signalandresetting lower thresholdandremainsinresetuntiltheLPRST hysteresis. TheLPRST and lowerthresholdvoltageseparat This pinisconnectedtoaSchmitttri ends. cyc ) oscillatorstabilizationdelayis set conditionunti external RESET theendofthis4064-cycl ve attheendofthis4064-cycle delay,theRST ) pinisoneofth set conditionuntiltheot scillator becomesactive. the powersupplyvoltage set untilthe4064internal strictly forpowerturn RST no effectonoperatingmode. the CPUandperipherals ve-low inputwill,in ated resetsaretheinitialpower-onreset ystal oscillator.TheM timer reset,andtheill , processorclocks wil ong asalogic0remainsonLP placetheMCUinus 4064 internalprocessorbusclock l theotherresetcondition(s)end. inputortheinte completed.Ifanyotherreset canplacetheMC ed byaminimumamountof gger inputgatetoprovideanupper e twoexternalsourcesofareset. resetstheCPU.Ifanyother up toallowtheclockoscillator e delay,theRSTsignal addition togeneratingthe -on conditionsandisnot her resetcondition(s) pinispulledbelowthe egal addressdetector. processorclockcycle (brown-out). Thereis CU willremaininthis l bere-enabled with , haltallinternal rnal COPwatchdog pinrisesabovethe er mode while the the while er mode U intoanon-user RST — . When Rev. 2.1 Resets

CAUTION: The VDD voltage should rise sufficiently fast to reach the minimum operating voltage for the given oscillator frequency before the 4064- cycle internal processor clock timeout period expires. If VDD rises too slowly, then either the RESET or LPRST pin should be driven low (less than VIL) until VDD reaches the minimum operating level for the oscillator frequency.

5.5.2 Computer Operating Properly Reset (COPR)

The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU.

The COP reset function is enabled or disabled by a mask option and is verified during production testing.

5.5.2.1 Resetting the COP

Writing a zero to the COPF bit prevents a COP reset. This action resets the counter and begins the timeout period again. The COPF bit is bit 0 of address $3FF0. A read of address $3FF0 returns user data programmed at that location.

5.5.2.2 COP During Wait Mode

The COP continues to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset.

5.5.2.3 COP During Stop Mode

When STOP is executed, the COP counter will be cleared and held in that state until the STOP state is exited. This is true whether STOP is enabled and the chip enters an actual STOP state (when all clocks are stopped) or if STOP is disabled and only the internal PH1 and PH2 are stopped (a wait-like state). If a reset is used to exit stop mode, the COP counter is held in reset until 4064 POR cycles are completed, at which

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Resets 51 NON-DISCLOSURE AGREEMENT REQUIRED Resets 52 Resets Freescale Semiconductor Freescale Resets 52 General Release Specif 5.5.2.4 COPWatchdog cto MC68HC05RC18 ication watchdog timerisselectedbyamask halt andpreventstheCO inadvertently duetothe option, anyexecutionoftheSTOPin by amaskoption.If The COPwatchdogtimeris but doescountthesecycles. COP counterdoesnotwaitforthe time countingwillbegi summarized in watchdog timer,STOPinstructi The recommendedinteractionsandc mode forperiodslongert be when ittimesout.Therefore,is IF the Following Conditions Exist: TimerConsiderations disabled Wait Time Wait Time Time Wait al 5-1. COPWatchdog Table Any Length Wait Time Disable COPbyMask Disable Option Time Wait Any Length forasystemthatmu More than Less than Less Wait Time Wait al 5-1 Table the COPwatchdogtimerisselectedbyamask CPTmotEnable orDisable COPOption byMask Timeout COP COP Timeout Disable COPbyMask Disable Option COPTimeout n. IfanexternalIRQisusedtoexitstopmode,the CPU beingdisturbed)caus P watchdogtimerfrom . han theCOPtimeoutperiod. active inallmodes on, andWAITinstructionare recommendedthat st haveintentional completion ofth Timer Reco struction (eitherintentionallyor onsiderations fortheCOP option, theCOP THENCOP Watchdog the Timer ShouldBe: of operationifenabled mmendations timing out.IftheCOP e 4064PORcycles es theoscillatorto the COPwatchdog uses ofthewait resets theMCU — Rev. 2.1 Resets

5.5.2.5 COP Register

The COP register is shared with the LSB of the unimplemented user interrupt vector at location $3FF0 as shown in Figure 5-3. Reading this location returns whatever user data has been programmed at this location. Writing a 0 to the COPR bit in this location clears the COP watchdog timer.

Address: $3FF0

Bit 7654321Bit 0

Read: XXXXXXXX

Write: COPR

Reset:———————0

= Unimplemented Figure 5-3. COP Watchdog Timer Location

5.5.3 Illegal Address

An illegal address reset is generated when the CPU attempts to fetch an instruction from I/O address space ($0000 to $001F).

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Freescale Semiconductor Resets 53 NON-DISCLOSURE AGREEMENT REQUIRED Resets 54 Resets Freescale Semiconductor Freescale Resets 54 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 6. Parallel Input/Output (I/O)

6.1 Contents

6.2 Introduction...... 55 6.3 Port A ...... 55 6.4 Port B ...... 56 6.5 Port C ...... 57 6.6 Input/Output Programming ...... 57

6.2 Introduction

In user mode, 24 lines (four of which are unavailable in the standard 28- pin package) are arranged as three 8-bit I/O ports. These ports are programmable as either inputs or outputs under software control of the data direction registers.

NOTE: To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register.

6.3 Port A

Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the data direction register (DDR) is at $0004. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Parallel Input/Output (I/O) 55 NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output(I/O) 56 Parallel Input/Output (I/O) Freescale Semiconductor Freescale (I/O) Input/Output Parallel 56 General Release Specif B Port 6.4 WEAK PB7 STRONG V DD V DD cto MC68HC05RC18 ication careful whenusingportBpinst or theIbitofc preconditioned toalogic1prev enabled. Beforeswitchingfromanoutput corresponding portbitto returning theportstoinputs.Wr such generatedinterruptfrom whether toenablethepull either of which maybe pullup resistorenabled.Thereisac enabled. Whenaninterruptoptionis mask programmableinte not affectthedataregist and thedatadirectionre with othersubsystems.Theaddressof Port Bisan8-bitbidire same forallenabledin sensitivity oftheIRQ FROM ALLOTHERPORTBPINS NORMAL PORT CIRCUITRY AS SHOWNIN iue6-1. Port Figure FIGURE 2-4 ondition coderegistershoul pinwillalsopertainto terrupts circuits.The ctional portwhichdoesnot B PullupOptions active fortheenabledinte er, butclearsthedatadire gister (DDR)isat rrupt generationoption, output mode.EachoftheportBpinshasa ups andwhichstrengthto IRQ takingimmediateeffect. MASK OPTION(PULLUP DDR BIT MASK OPTION(STRONG MASK OPTION(PB7IE) hat havetheinte iting aonetoDDRbitsetsthe ent aninterruptfrombeinggenerated hoice betweentwo enabled, thispinmayalsohavea theportBdataregisteris$0001 IRQEN toaninput,thedatashouldbe address $0005.Resetdoes theenabledportBpins.Be edgeorandlevel / ENABLE /WEAK SEL) d besettopreventany rrupt generation any ofwhichcanbe rrupts. Thechoiceof ) ction regist share anyofitspins choosewillbethe LOGIC TO INTERRUPT pullup strengths, er, thereby — Rev. 2.1 Parallel Input/Output (I/O)

6.5 Port C

Port C is an 8-bit bidirectional port (PC0–PC7) which does not share any of its pins with other subsystems. The port C data register is at $0002 and the data direction register (DDR) is at $0006. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to output mode. Port C pins PC4–PC7 are available only in higher pin count (>28 pin) packages.

6.6 Input/Output Programming

Port pins can be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each I/O port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0.

At power-on or reset, all DDRs are cleared, which configures all pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Parallel Input/Output (I/O) 57 NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output(I/O) 58 Parallel Input/Output (I/O) Freescale Semiconductor Freescale (I/O) Input/Output Parallel 58 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 Parallel Input/Output (I/O)

Table 6-1. I/O Pin Functions

Access DDR I/O Pin Functions

Write 0 The I/O pin is in input mode. Data is written into the output data latch.

Write 1 Data is written into the output data latch and output to the I/O pin.

Read 0 The state of the I/O pin is read.

Read 1 The I/O pin is in an output mode. The output data latch is read.

DATA DIRECTION REGISTER BIT

INTERNAL LATCHED HC05 I/O OUTPUT OUTPUT CONNECTIONS DATA BIT PIN

INPUT REG BIT

INPUT I/O

Figure 6-2. I/O Circuitry

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Parallel Input/Output (I/O) 59 NON-DISCLOSURE AGREEMENT REQUIRED Parallel Input/Output(I/O) 60 Parallel Input/Output (I/O) Freescale Semiconductor Freescale (I/O) Input/Output Parallel 60 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 7. Low-Power Modes

7.1 Contents

7.2 Introduction...... 59 7.3 Stop Mode ...... 59 7.4 Stop Recovery ...... 60 7.5 Wait Mode...... 61 7.6 Low-Power Reset ...... 61

7.2 Introduction

This section describes the low-power modes, which are stop mode and wait mode.

7.3 Stop Mode

The STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer operation.

When stop mode is entered, all core timer counter bits are cleared. The I bit in the CCR is cleared to enable interrupts, but all interrupts are held pending until the device is brought out of stop mode. All other registers and memory remain unaltered. All input/output lines remain unchanged.

NOTE: If an external interrupt is pending when stop mode is entered, then stop mode will be exited immediately.

The EIMSK bit is not cleared automatically by the execution of a STOP instruction. Care should be taken to clear this bit before entering stop mode.

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Freescale Semiconductor Low-Power Modes 59 NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes Low-Power 0LwPwrMdsFreescale Semiconductor Low-Power Modes 60 General Release Specif StopRecovery 7.4 NOTES: .IRQ 3. .IRQ 2. of theOSC1pin Representstheinternalgating 1. pin level- and edge-sensitive mask option level- andedge-sensitive pin edge-sensitive maskoption pin INTERNAL INTERNAL ADDRESS CLOCK RESET OSC1 LPRST cto MC68HC05RC18 ication IRQ IRQ BUS 1 3 2 interrupt, LPRST interrupt, The processorcanbebroughtoutof iue7-1.StopRec Figure t LPRL t t LIH RL t ILCH , orRESET overy TimingDiagram . Referto FE3F FE3F 3FFF 3FFE 3FFE 3FFE 3FFE 4064 t stopmodeonlybyanexternal CYC iue7-1 Figure . RESET OR INTERRUPT VECTOR FETCH — Rev. 2.1 Low-Power Modes

7.5 Wait Mode

The WAIT instruction places the MCU in a low power-consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the core timer, the oscillator, and any enabled module remain active. Any interrupt or reset will cause the MCU to exit wait mode. The user must shut off subsystems to reduce power consumption. Wait current specifications assume CPU operation only and do not include current consumption by any other subsystems.

During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous states. The timer can be enabled to allow a periodic exit from wait mode.

7.6 Low-Power Reset

Low-power reset mode is entered when a logic 0 is detected on the LPRST pin. When in this mode (as long as LPRST is held low), the MCU is held in reset and all internal clocks and the crystal oscillator (if used) are halted. Applying a logic 1 to LPRST will cause the part to exit low- power reset mode and begin counting out the 4064-cycle oscillator stabilization period. Once this time has elapsed, the MCU will begin operation from the reset vectors ($3FFE–$3FFF).

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Low-Power Modes 61 NON-DISCLOSURE AGREEMENT REQUIRED Low-Power Modes Low-Power 2LwPwrMdsFreescale Semiconductor Low-Power Modes 62 General Release Specif N (PTB KEYSCAN INTERRUPT) INTERRUPT EXTERNAL (IRQ Y )? N TURN ON OSCILLATOR.TURN ON .SERVICE 2. FETCH RESET 1. DELAY TO STABILIZE. cto MC68HC05RC18 ication STOP OSCILLATOR AND ALL CLOCKS. WAIT FOR TIME FOR WAIT C. VECTORTO B. SET IBIT A. STACK INTERRUPT VECTOR OR CLEAR IBIT. LPRST? ROUTINE INTERRUPT RESET STOP OR Y Figure 7-2. Stop/WaitFlowchart 7-2. Figure CORE TIMERCLOCKACTIVE. CMT TIMER CLOCK ACTIVE. PROCESSOR CLOCKS .SERVICE 2. FETCH RESET 1. OSCILLATOR ACTIVE. PROCESSOR CLOCK. C. VECTOR TO B. SET I BIT A. STACK INTERRUPT VECTOR OR STOPPED. RESTART ROUTINE INTERRUPT LPRST? RESET WAIT OR Y (PTB KEYSCAN INTERRUPT) INTERRUPT EXTERNAL (IRQ N )? Y Y INTERRUPT? CMT TIMER INTERNAL N Y INTERRUPT? CORE TIMER INTERNAL N Y — Rev. 2.1 N General Release Specification — MC68HC05RC18

Section 8. Core Timer

8.1 Contents

8.2 Introduction...... 63 8.3 Core Timer Control and Status Register...... 65 8.4 Core Timer Counter Register ...... 67 8.5 Computer Operating Properly (COP) Reset ...... 67 8.6 Timer During Wait Mode...... 68

8.2 Introduction

The core timer for this device is a 14-stage multifunctional ripple counter. Features include timer overflow, power-on reset (POR), real-time interrupt (RTI), and COP watchdog timer.

As seen in Figure 8-1, the internal peripheral clock is divided by four and then drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the core timer counter register (CTCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral clock (E)/1024. This point is then followed by three more stages, with the resulting clock (E/4096) driving the real- time interrupt circuit (RTI). The RTI circuit consists of three divider stages with a one-of-four selector. The output of the RTI circuit is further divided by eight to drive the mask optional COP watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are located in the timer control and status register at location $08.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Core Timer 63 NON-DISCLOSURE AGREEMENT REQUIRED Core Timer 64 Core Timer Freescale Semiconductor Freescale Timer Core 64 General Release Specif 8 CTCSR CTCR 8 OVERFLOW CIRCUIT DETECT TFRI OERI RT1 RTIE TOFE RTIF CTOF E cto MC68HC05RC18 ication INTERRUPT CIRCUIT ÷ TO INTERRUPT 2 $09COUNTER CORETIMER REGISTER (CTCR) 10 LOGIC E iue8-1. CoreTimer BlockDiagram Figure ÷ RTI SELECT CIRCUIT 2 15 5-BIT COUNTER E ÷ 2 14 TOFC E ÷ 2 13 INTERNAL BUS RTFC E ÷ 2 12 RT0 INTERNAL PERIPHERAL CLOCK (E) $08 STATUS REGISTER TIMER CONTROL& TCBP E ÷ ÷ 2 4 2 COP WATCHDOG TIMER ( TIMER TO RESET E LOGIC ÷ 2 2 3 RTI 12 ÷ OUT 8) POR CLEAR COP — Rev. 2.1 Core Timer

8.3 Core Timer Control and Status Register

The CTCSR contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. Figure 8-2 shows the value of each bit in the CTCSR when coming out of reset.

Address: $0008

Bit 7654321Bit 0

Read: CTOF RTIF 00 TOFE RTIE RT1 RT0 Write: TOFC RTFC

Reset:00000011

= Unimplemented Figure 8-2. Core Timer Control and Status Register (CTCSR)

CTOF — Core Timer Overflow CTOF is a read-only status bit set when the 8-bit ripple counter rolls over from $FF to $00. Clearing the CTOF is done by writing a one to TOFC. Writing to this bit has no effect. Reset clears CTOF.

RTIF — Real-Time Interrupt Flag The real-time interrupt circuit consists of a 3-stage divider and a one- of-four selector. The clock frequency that drives the RTI circuit is E/212 (or E ÷ 4096) with three additional divider stages giving a maximum interrupt period of 16 milliseconds at a bus rate of 2.024 MHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. Clearing the RTIF is done by writing a one to RTFC. Writing has no effect on this bit. Reset clears RTIF.

TOFE — Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears this bit.

RTIE — Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Core Timer 65 NON-DISCLOSURE AGREEMENT REQUIRED Core Timer 66 Core Timer Freescale Semiconductor Freescale Timer Core 66 General Release Specif cto MC68HC05RC18 ication RT1–RT0 —Real-TimeInterruptRateSelect RTFC —Real-Time TOFC —TimerOverflowFlagClear 6m 2 16 ms problems, theCOPshouldbe could bemissedoranadditionalone is modifiedduringacycleinwhich RT1 ifthetimeoutperiod these bitsifnecessary.Caresh lowest periodicrateandgivesthe circuit. Referto These twobitsselectoneoffourt effect ontheRTIFbit.Thi When aoneiswrittentoth no effectontheCTOF When aoneiswrittentothisbit,CT s2 2 8 ms 4 ms s2 2 ms 2.048-MHz Bus 2.048-MHz RTI Rate al 8-1. RTI andCOPRates Table 15 14 13 12 ÷ ÷ ÷ ÷ E11(2E10(2E01(2E00(2 al 8-1 Table RT1–RT0 Interrupt FlagClear bit.Thisbitalwaysreadsaszero. . Resetsetsthesetwobitswhichselectsthe is imminentoruncertain s bitalwaysreadsaszero. is bit,RTIFcleared. Minimum COP Rates cleared beforechangingRTItaps. 18 17 16 15 ould betakenwhenalteringRT0and 2.048-MHz Bus 2.048-MHz –2 –2 –2 –2 aps fromthereal maximum time in which toalter inwhich time maximum the counterisswitching,anRTIF 15 14 13 12 OF iscleared.Writingazerohas / 1 s(2 (2 112 ms (2 56ms )/E (2 28ms )/E 14ms )/E )/E at 4.096-MHzOscillator could begenerated.Toavoid Writingazerohasno . Iftheselectedtap -time interrupt 2.048-MHz Bus Maximum COP 18 17 16 15 )/E 128 ms 128 64ms )/E 32ms )/E 16ms )/E )/E Rates — Rev. 2.1 Core Timer

8.4 Core Timer Counter Register

The timer counter register is a read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked by the CPU clock (E/4) and can be used for various functions, including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter.

Address $0009

Bit 7654321Bit 0

Read: D7 D6 D5 D4 D3 D2 D1 D0

Write:

Reset:00000000

= Unimplemented Figure 8-3. Timer Counter Register (CTCR)

The power-on cycle and the low-power reset both serve to clear the entire counter chain and begin clocking the counter. After 4064 cycles, the power-on/low-power reset circuit is released, which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up from zero and normal device operation begins. When a reset other than POR and low- power reset is asserted any time during operation, the counter chain is cleared but the 4064-cycle stabilization period is not invoked.

8.5 Computer Operating Properly (COP) Reset

The COP watchdog timer function is implemented on this device by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Figure 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP timeout, or clearing the COP is accomplished by writing a zero to bit 0 of address $3FF0. When the COP is cleared, only the final divide-by-eight stage (output of the RTI) is cleared.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Core Timer 67 NON-DISCLOSURE AGREEMENT REQUIRED Core Timer 68 Core Timer Freescale Semiconductor Freescale Timer Core 68 General Release Specif 8.6 TimerDuringWaitMode cto MC68HC05RC18 ication wait mode.TheCOPisalways interrupts areenabled,atimerinterr The CPUclockhaltsduring stop modebedisabledindevicesthat mode isexited,theCOPtimercl as ifawaitmodeinstructionha execution ofSTOPinstructioncauses all associatedoperations The COPremainsenabledafterexecuti generated torese If theCOPwatchdogtimeris behavior. Thisfuncti any situationwhereitmightentr stuck orlockedupandto This COP’sobjectiveistomakeit prevent theCOPfrombeingdis t theMCU. on isamaskoption. be suretheCOPisable be apply. IftheSTOPin wait mode,butthetime allowedtotimeout, enabledwhileinusermode. d beenexecuted(exceptthatwhenstop abled bytheSTOPinstruction. ap itselfinabnormalorunintended eared). Thus,itisrecommendedthat impossible forthisdevicetobecome upt willcausethepr havetheCOPenabled theCPUtoenterwaitmodejust on oftheWAITinstructionand struction isdisabled, torescuet an internalresetis r remainsactive.If ocessor toexit he partfrom , asthiswill — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 9. Carrier Modulator Transmitter (CMT)

9.1 Contents

9.2 Introduction...... 69 9.3 Overview...... 70 9.4 Carrier Generator ...... 72 9.4.1 Time Counter...... 73 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) ...... 74 9.5 Modulator ...... 76 9.5.1 Time Mode ...... 77 9.5.2 FSK Mode ...... 79 9.5.3 Extended Space Operation ...... 80 9.5.3.1 End Of Cycle (EOC) Interrupt ...... 81 9.5.3.2 Modulator Control and Status Register ...... 81 9.5.4 Modulator Period Data Registers (MDR1, MDR2, and MDR3) ...... 84 9.6 Wait Mode Operation ...... 85 9.7 Stop Mode Operation ...... 85

9.2 Introduction

The carrier modulator transmitter (CMT) module provides a means to generate the protocol timing and carrier signals for a wide variety of encoding schemes. The CMT incorporates hardware to off-load the critical and/or lengthy timing requirements associated with code generation from the CPU, releasing much of its bandwidth to handle other tasks such as code data generation, data decompression, or keyboard scanning. The CMT does not include dedicated hardware configurations for specific protocols but is intended to be sufficiently programmable in its function to handle the timing requirements of most

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 69 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 0CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 70 General Release Specif Overview 9.3 cto MC68HC05RC18 ication the modulatoroutpu for self-clockedprotocol system clockstoprovidere generate signalswith signal todeterminebothperiodanddut modulator hasa example, a400-kHzsign the numberofcountsr kHz) instepsof500ns.Thepo The userindependentlymay The carriergeneratorhasaresolutionof The modulatorprovides Carrier Generator continuously toallowforthegener register (MCSR)isset, intervention. WhentheB dynamically switchbetweentwo two setswheninstructed FSK (frequencyshiftkey) referred toastimemode),just cycles arepossible.Theca periods, higherresolution(asaperce 80% (fourhigh,onelow).Forlowe high, fourlow),40%(twothr between highandlowtimessothedut require 5x500nscount output blocks.Theblock The moduleconsistsofcarriergener future protocolsnotr infrared outpin(IRO)directly.Thisf disabled, certainCMTr protocols withminimalCPUinterv of highandlowtimes. resolution of4 . t (TIME),controlthelogi eadily produciblebythe periods between1 When operatinginnorm equired tocompletet egisters canbeusedto the carrieroutputto s. Themodulatorcaneit asimplemethodtocont s togenerate. todosobythemodulat ASE bitinthe al hasaperiodof2.5 diagram isshownin mode,thegeneratorwi rrier generatormaysele al-time controlorit define thehighandlowti ssible dutycycleoptionswilldependupon one setwillbeused. µ carrier frequencieswithoutCPU s witha2-MHzoscilla ee low),60%(threehigh,twolow)and ention. Whent ation ofbaseband r frequencysignals eature allowsfor ator, modulator,andtransmitter y cyclesavailablewillbe20%(one ntage ofthetotalperiod)duty y cycle.Thecarriergeneratorcan Thesecounts modulator controlandstatus 500nswitha2-MHzoscillator. µ s (1MHz)and64 he carrierperiod.For c levelofthemodulator current architecture. iue9-1 Figure can countcarrierclocks µ al mode(subsequently her gatethecarrieronto change thestateof modulator isheldhigh rol protocoltiming.The s andwilltherefore or, allowingtheuserto he modulatoris ll togglebetweenthe ct betweentwosets When operatingin protocols. See may besplit the generationof mes ofthecarrier with larger tor. Itcancount . µ s (15.6 — Rev. 2.1 9.4 Carrier Modulator Transmitter (CMT)

output (baseband), or directly route the carrier to the modulator output while providing a signal to switch the carrier generator between high/low time register buffers (FSK). See 9.5 Modulator.

The transmitter output block controls the state of the infrared out pin (IRO). The modulator output is gated on to the IRO pin when the modulator/carrier generator is enabled. Otherwise, the IRO pin is controlled by the state of the IRO latch, which is directly accessible to the CPU by means of bit 7 of the carrier generator data registers CHR1 and CLR1. The IRO latch can be written to on either edge of the internal bus clock (fosc/2), allowing for IR waveforms which have a resolution of twice the bus clock frequency (fosc). See 9.4.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2).

PRIMARY/SECONDARY SELECT

MODE

BASE

MODULATOR CARRIER OUT IRO CARRIER OUT TRANSMITTER GENERATOR MODULATOR PIN fOSC . OUTPUT

MODULATOR/

CARRIER ENABLE EOC INTERRUPT ENABLE EOC FLAG

CPU INTERFACE fOSC ÷ 2

DB AB EOC INTERRUPT

Figure 9-1. Carrier Modulator Transmitter Module Block Diagram

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 71 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 2CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 72 General Release Specif CarrierGenerator 9.4 CARRIER GENERATOR CARRIER OUT MODULATOR/ ENABLE BASE f cto MC68HC05RC18 ication OSC

block diagramisshownin clocks counted.Thedutyc and thecarrierlowtime. input clocks(500nsfora2-MHzoscill The carriersignalisge in theMCSRmustbeclearedto intervention. The MCGENbitint intervention. The dual frequencyFSK(frequencyshift count valuesisheldinanothersetof programmable andareheldin clocks tototalcounted.Thehi Figure 9-2. CarrierGenerator BlockDiagram 9-2. Figure

CLOCK AND OUTPUT CONTROL SECONDARY HIGH COUNTREGISTER SECONDARY SECONDARY LOW COUNT REGISTER PRIMARY HIGH COUNT REGISTER PRIMARY HIGHCOUNT PRIMARY LOWCOUNTREGISTER CLR CLK 6-BIT UPCOUNTER nerated bycountingapredeterminednumberof =? =? The periodisdeterminedby iue9-2 Figure ycle isdeterminedbyt tworegisters.Anal he MCSRmustbeset enablecarriergeneratorclocks.The registerstoallowthegenerationof keying) protocolswithoutCPU gh andlowtime . ator) forboththecarrierhightime ternate setofhigh/low COUNT REGISTER SELECT CONTROL he ratioofhightime thetotalnumberof values areuser and the BASE bit and the MODE SECONDARY PRIMARY/ SELECT — Rev. 2.1 Carrier Modulator Transmitter (CMT)

9.4.1 Time Counter

The high/low time counter is a 6-bit up counter. After each increment, the contents of the counter are compared with the appropriate high or low count value register. When this value is reached, the counter is reset and the compare is redirected to the other count value register. Assuming that the high time count compare register is currently active, a valid compare will cause the carrier output to be driven low. The counter will continue to increment and when reaching the value stored in the selected low count value register, it will be cleared and will cause the carrier output to be driven high. The cycle repeats, automatically generating a periodic signal which is directed to the modulator. The lowest frequency (maximum period) and highest frequency (minimum period) which can be generated are defined as:

fmax = fosc ÷ (2 x 1) Hz 6 fmin = fosc ÷ (2 x (2 – 1)) Hz

In the general case, the carrier generator output frequency is:

fout = fosc ÷ (Highcount + Lowcount) Hz

Where: 0 < Highcount < 64 and 0 < Lowcount < 64

NOTE: These equations assume the DIV2 bit (bit 6) of the MCSR is clear. When the DIV2 bit is set, the carrier generator frequency will be half of what is shown in these equations.

The duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. As the input clock period is fixed, the duty cycle resolution will be proportional to the number of counts required to generate the desired carrier period.

Highcount Duty Cycle = ------Highcount+ Lowcount

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 73 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 4CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 74 General Release Specif 9.4.2 CarrierGeneratorDataRegisters(CHR1,CLR1,CHR2,andCLR2) cto MC68HC05RC18 ication iue9-3. Carrier DataRegister Figure (CLR2). Bit7ofCHR1 data registers:secondary (CHR1); one7-bitda The carriergeneratorcontainsone8-bit Reset:0Reset:0 0UUUUUU 0UUUUUU Reset:0Reset:0 0UUUUUU 0UUUUUU CHR2 CHR1 Read: Read: Read: Read: Write: CLR2 Write: Write: CLR1 Write: U = Unaffected U = Unaffected U = U = Unaffected U = Unaffected U = RL MPLP5P4P3P2P1PH0 PH1 PH2 PH3 PH4 PH5 CMTPOL IROLN IROLP0 PL5PL4PL3PL2PL1PL0 Bit 7654321BitBit 7654321Bit 0 0 Bit 7654321BitBit 7654321Bit 0 0 Address $0013Address $0012Address Address $0011Address $0010Address H H H H H SH0 SH1 SH2 SL5SL4SL3SL2SL1SL0 0 SH3 0 SH4 SH5 0 0 ta register:primarylowti and CHR2isusedtoread hightime(CHR2)and (CHR1, CLR1, CHR2, and CLR2) (CHR1,CLR1,CHR2, and data register:primaryhightime me (CLR1);andtwo6-bit secondarylowtime and writetheIROlatch — Rev. 2.1 . Carrier Modulator Transmitter (CMT)

PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data Values When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is always selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the secondary register pair are alternately selected under control of the modulator. The primary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled to avoid spurious results.

NOTE: Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear, the IRO latch value appears on the IRO output pin. Care should be taken that bit 7 of the data to be written to CHR1 or CHL1 should contain the desired state of the IRO latch.

Additionally, writing to CHR1 to update PH0–PH5 will also update the CMT polarity bit. Care should be taken that bit 6 of the data to be written to CHR1 should contain the desired state of the polarity bit.

SH0–SH5 and SL0–SL5 — Secondary Carrier High and Low Time Data Values

When selected, these bits contain the number of input clocks required to generate the carrier high and low time periods. When operating in time mode (see 9.5.1 Time Mode), this register pair is never selected. When operating in FSK mode (see 9.5.2 FSK Mode), this register pair and the primary register pair are alternately selected under control of the modulator. The secondary carrier high and low time values are undefined out of reset. These bits must be written to nonzero values before the carrier generator is enabled when operating in FSK mode.

CMTPOL — CMT output Polarity

This bit controls the polarity of the CMT output (IRO). When this bit is a zero, then the CMT output is active high. When this bit is set to one the CMT output is active low, in other words inverted. The reset state of this bit is zero.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 75 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 6CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 76 General Release Specif 9.5 Modulator NOTE: cto MC68HC05RC18 ication the modulatorcountscl The modulatorcanoperate intwomodes bit modulatorperiodregister The 12-bitMBUFFandS The MCGENbitintheMCSR reloaded withthecontents occurs, thecounterisreloadedwith require successiveburstsofdiff space periodwillbegenerated(forinst opened again.Shoul register, SREG.When decrementing counterwiththecontent continually comparesthelogicalcomple modulator gateisclos mark bufferregister, detection whichisloaded The modulatorconsists update theprimarycarrierhighand Writing toCHR1update IROLN andIROLP—IROLatchControl taken thatbits5–0of In addition,writing contain thedesiredval CHR1 shouldcontainthedesired polarity bit.Careshould reset. clock; forexample,onef updates theIROlatchonpositive negative edgeoftheinter IROLN updatestheIROlatchwith Reading IROLNorIROLP to CHR1updateIROL d SREG=0,thematch MBUFF. Whenthisc the datatobewritten ed anda12-bitcomparatorisenabledwhich a matchisobtained,them ues fortheprimaryca ocks derivedfromthe of a12-bitdownc be takenthatbit6oft BUFF registersarea from themodulationma ofitsbuffer,SBUFF, osc IROLN ortoCLR1 nal processorclock(f s, MDR1,MDR2,andMDR3. reads thestateoft mustbesettoenabl periodlater.TheIROla erent frequencies).Whenthematch values forthepolaritybit. low datavalues. thedatabeing the contentsofMBUFF,SREGis s ofthemodulationspaceperiod ance, forFSKprotocolswhich ment ofthecontents(still) edge oftheinte , timeandFSK. ounter underflows,the ounter withunderflow N willupdatetheCMT rrier highorlowdata. will beim CHR1orCHL1should system oscillatorand ccessed throughthree8- he datatobewritten he IROlatch.Writing andthecyclerepeats. update IROLPwillalso odulator controlgateis osc e themodulatortimer. rk periodfromthe written onthe /2). Writing IROLP Care shouldbe tch isclearoutof mediate andno rnal processor In timemode, — Rev. 2.1 Carrier Modulator Transmitter (CMT)

modulates a single-carrier frequency or no carrier (baseband). In FSK mode, the modulator counts carrier periods and instructs the carrier generator to alternate between two carrier frequencies whenever a modulation period (mark + space counts) expires.

12 BITS

0 MBUFF

³ 8 fOSC CLOCK CONTROL 13-BIT DOWN COUNTER * . CARRIER OUT

12 LOAD MBUFF/SBUFF . MODULATOR GATE MODULATOR OUT COUNTER

MS BIT =? SYSTEM CONTROL PRIMARY/SECONDARY SELECT

SREG * MODULATOR/ CARRIER GENERATOR. ENABLE EOC FLAG SET EXTENDED SPACE EXTENDED SBUFF EOC FLAG MODULATOR CONTROL/STATUS REGISTER 12 BITS EOC INTERRUPT ENABLE

MODE BASE * DENOTES HIDDEN REGISTER DIV2

Figure 9-4. Modulator Block Diagram

9.5.1 Time Mode

When the modulator operates in time mode, the modulation mark and space periods consist of zero or an integer number of fosc ÷ 8 clocks (= 250 kHz @ 2 MHz osc). This provides a modulator resolution of 4 µs and a maximum mark and space periods of about 16 ms (each). However, to prevent carrier glitches which could affect carrier spectral purity, the modulator control gate and carrier clock are synchronized. The carrier signal is activated when the modulator gate opens. The modulator gate can only close when the carrier signal is low (the output

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 77 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 8CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 78 General Release Specif CARRIER FREQUENCY TIME MODE OUTPUT BASEBAND OUTPUT MODULATOR GATE f OSC ÷ 8 cto MC68HC05RC18 ication AKSAEMR MARK MARK SPACE MARK Setting theDIV2bitin The markandspacetimeequationsare: duration ofas be at alogic 1for theduration oft baseband mode(BASEbi logic levelduringspaceperiodsis Figure 9-5. CMTOperat 9-5. Figure pace period.See t mark theMCSRwill t space t inMCSRis = ion inTimeMode () ------BF 1 MBUFF = iue9-5 Figure BF 8 ------SBUFF he markperiodandat SPACE low). Ifthecarriergeneratorisin ------f f osc doublemarkandspacetimes. osc ------s ------+ high), themodulatoroutputwill × ------. × sec 8 -s sec alogic0forthe — Rev. 2.1 Carrier Modulator Transmitter (CMT)

9.5.2 FSK Mode

When the modulator operates in FSK mode, the modulation mark and space periods consist of an integer number of carrier clocks (space period can be zero). When the mark period expires, the space period is transparently started (as in time mode); however, in FSK mode the carrier switches between data registers in preparation for the next mark period. The carrier generator toggles between primary and secondary data register values whenever the modulator mark period expires. The space period provides an interpulse gap (no carrier), but if SBUFF = 0, then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches (zero space).

Using timing data for carrier burst and interpulse gap length calculated by the CPU, FSK mode can automatically generate a phase-coherent, dual-frequency FSK signal with programmable burst and interburst gaps.

The mark and space time equations for FSK mode are:

MBUFF+ 1 tmark = ------sec s fcg

SBUFF tspace = ------ssec fcg

Where fcg is the frequency output from the carrier generator, setting the DIV2 bit in the MCSR will double mark and space times.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 79 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 0CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 80 General Release Specif 9.5.3 ExtendedSpaceOperation NOTE: SET EXSPC cto MC68HC05RC18 ication standard operationatt with nomarkperiods.Cl modulation periodswill elapsed whiletheEX Where thesubscripts1,2,...nre equation: calculate thelengthofanextended equal inlengthtoth The EXSPCfeaturecanbeusedto example ofextended Where f the equation: Similarly, tocalculatethelengthofanextendedspaceinFSKmode,use (beginning withthenext MCSR willforcethemodul the maximumpossiblevalueofSBUF In eithertimeorFS t exspace t exspace iue9-6.Extended SpaceOperation Figure = cg = isthefrequencyoutputfrom ((SBUFF ((SBUFF 1 )+(MBUFF 1 K mode,thespaceperiod e markandspacecount )+(MBUFF CLEAR EXSPC SPC bitwasset. space operation,see he beginningofthenext consist entirelyofthes earing EXSPCwill load ofMBUFF/SBUFF) ator totreatthe 2 +1+SBUFF 2 +1+SBUFF fer tothemodulationperiodsthat f osc f cg space intimemode,usethe emulate azeromarkevent. F. SettingtheEX 2 ) +... (MBUFF +... ) 2 the carriergenerator.Foran )+... (MBUFF )+... returnthe next modulationperiod iue9-6 Figure s combined.Subsequent e extendedspaceperiods can bemadelongerthan modulation per asaspaceperiod n n +1+SBUFF +1+SBUFF modulator to . SPC bit in the in SPC bit n n )) x8 — )) )) iod. To secs Rev. 2.1 secs Carrier Modulator Transmitter (CMT)

9.5.3.1 End Of Cycle (EOC) Interrupt

At the end of each cycle (when the counter is reloaded from MBUFF), the end of cycle (EOC) flag is set. If the interrupt enable bit was previously set, an interrupt will also be issued to the CPU. The EOC interrupt provides a means for the user to reload new mark/space values into the MBUFF and SBUFF registers. As the EOC interrupt is coincident with reloading the counter, MBUFF does not require additional buffering and may be updated with a new value for the next period from within the EOC interrupt service routine (ISR). To allow both mark and space period values to be updated from within the same ISR, SREG is buffered by SBUFF. The contents written to SBUFF are transferred to the active register SREG at the end of every cycle irrespective of the state of the EOC flag. The EOC flag is cleared by a read of the modulator control and status register (MCSR) followed by an access of MDR2 or MDR3. The EOC flag must be cleared within the ISR to prevent another interrupt being generated after exiting the ISR. If the EOC interrupt is not being used (IE = 0), the EOC flag need not be cleared.

9.5.3.2 Modulator Control and Status Register

The modulator control and status register (MCSR) contains the modulator and carrier generator enable (MCGEN), interrupt enable (IE), mode select (MODE), baseband enable (BASE), extended space (EXSPC), and external interrupt mask (EIMSK) control bits, divide-by- two prescaler (DIV2) bit, and the end of cycle (EOC) status bit.

Address: $0014

Bit 7654321Bit 0

Read: EOC DIV EIMSK EXSPC BASE MODE IE MCGEN Write:

Reset:00000000

= Unimplemented Figure 9-7. Modulator Control and Status Register (MCSR)

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 81 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 2CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 82 General Release Specif cto MC68HC05RC18 ication EXSPC —ExtendedSpaceEnable Mask —ExternalInterrupt EIMSK EOC —EndOfCycleStatusFlag DIV2 —Divide-by-twoprescaler Extended SpaceOperation For adescriptionofthe interrupts. Thisbitisclearedbyreset. The externalinterruptmaskbit bit isnotdoublebuffered,its EOC issetwhenamatchoccursbet with the(possiblynew)contentsof the endofmodul period register,SREG, and thespaceperiodregist rate whenenabledand2xthebu The divide-by-twoprescalercauses flag isclearedbyreset. read oftheMCSRfollowedbyan contents ofthespaceper 0 =Extendedspacedisabled 1 =Extendedspaceenabled 0 =IRQandkeyscaninterruptsenabled 1 =IRQandkeyscaninterruptsmasked 0 =Currentmodulatio 1 =Endofmodulatorcycle(c 0 =Divide-by-two 1 =Divide-by-two ation cycle.Atthis prescalerenabled prescaler disabled and thedowncounter.Thi extended spaceenablebit,see n cycleinprogress iod buffer,SBUFF.This er, SREG,isloadedwith . Thisbitisclearedbyreset. hould notbesetduringatransmission. is usedtomaskIRQandkeyscan s ratewhendisabled(f ounter =SBUFF)hasoccurred access ofMDR2orMDR3.TheEOC themarkperiod the CMTtobeclockedatbus ween thecontents time,thecounterisinitialized flagisclearedbya s isrecognizedas the(possiblynew) buffer, MBUFF, MBUFF, buffer, osc ofthespace 9.5.3 ). Sincethis — Rev. 2.1 Carrier Modulator Transmitter (CMT)

BASE — Baseband Enable 1 = Baseband enabled 0 = Baseband disabled When set, the BASE bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. When BASE is clear, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. See 9.5.1 Time Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission.

MODE — Mode Select 1 = CMT operates in FSK mode. 0 = CMT operates in Time mode. For a description of CMT operation in time mode, see 9.5.1 Time Mode. For a description of CMT operation in FSK mode, see 9.5.2 FSK Mode. This bit is cleared by reset. This bit is not double buffered and should not be written to during a transmission.

IE — Interrupt Enable 1 = CPU interrupt enabled 0 = CPU interrupt disabled A CPU interrupt will be requested when EOC is set if IE was previously set. If IE is clear, EOC will not request a CPU interrupt.

MCGEN — Modulator and Carrier Generator Enable 1 = Modulator and carrier generator enabled 0 = Modulator and carrier generator disabled Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks. Once enabled, the carrier generator and modulator will function continuously. When MCGEN is cleared, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled (to save power) and the modulator output is forced low. To prevent spurious operation, the user should initialize all data and control registers before enabling the system. This bit is cleared by reset.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 83 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 4CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 84 General Release Specif 9.5.4 ModulatorPeriodDataRegisters(MDR1,MDR2,andMDR3) cto MC68HC05RC18 ication to clearMDR1andgenerat contains thetwomost least significanteightbitsof bit registers,MDR1,MDR2,andM The 12-bitMBUFFandS not berequired.Splitting many applications,per iue9-8.ModulatorDataRegi Figure ee:UnaffectedbyReset UnaffectedbyReset Reset: UnaffectedbyReset Reset: Reset: MDR3 MDR2 MDR1 Read: Read: Read: Write: Write: Write: B1M1 B B B1S1 B SB8 SB9 SB10 SB11 MB8 MB9 MB10 MB11 B B B B B B B MB0 MB1 MB2 MB3 MB4 MB5 MB6 MB7 BitBit 7654321BitBit 7654321Bit 0 7654321Bit 0 0 B B B B B B B SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 Address $0017Address $0016Address $0015Address iods greaterthanthoseobt significant nibblesof the registersupinthis BUFF registersarea e 8-bitperiodswithju MBUFF andSBUFFresp DR3. MDR2andMDR3containthe sters (MDR1,M MBUFF and SBUFF.In and MBUFF ccessed throughthree8- manner allowstheuser st twodatawrites. ained byeightbitswill DR2, andMDR3) ectively. MDR1 — Rev. 2.1 Carrier Modulator Transmitter (CMT)

9.6 Wait Mode Operation

During wait mode the CMT, if enabled, will continue to operate normally. However, there will be no new codes or changes of pattern mode while in wait mode, as the CPU is not operating. In addition, the CMT will not generate any new interrupts while the chip is in wait mode, although if it has one pending when wait mode is entered then that pending interrupt will serve to pull the chip out of WAIT mode.

NOTE: Although the CMT will not generate any new interrupts while wait mode is active, a previously generated CMT interrupt that is still pending will bring the MCU out of wait mode.

9.7 Stop Mode Operation

During stop mode, the CMT halts all operation. No registers are affected.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Carrier Modulator Transmitter (CMT) 85 NON-DISCLOSURE AGREEMENT REQUIRED Carrier ModulatorTransmitter (CMT) 6CrirMdltrTasitr(M)Freescale Semiconductor Carrier Modulator Transmitter (CMT) 86 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 10. Instruction Set

10.1 Contents

10.2 Introduction...... 88 10.3 Addressing Modes ...... 88 10.3.1 Inherent ...... 89 10.3.2 Immediate ...... 89 10.3.3 Direct...... 89 10.3.4 Extended ...... 89 10.3.5 Indexed, No Offset ...... 90 10.3.6 Indexed, 8-Bit Offset ...... 90 10.3.7 Indexed,16-Bit Offset...... 90 10.3.8 Relative ...... 91 10.4 Instruction Types ...... 91 10.4.1 Register/Memory Instructions ...... 92 10.4.2 Read-Modify-Write Instructions...... 93 10.4.3 Jump/Branch Instructions ...... 94 10.4.4 Bit Manipulation Instructions ...... 96 10.4.5 Control Instructions ...... 97 10.5 Instruction Set Summary ...... 98

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 87 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 88 Instruction Set Freescale Semiconductor Freescale Set Instruction 88 General Release Specif 10.3 AddressingModes 10.2 Introduction cto MC68HC05RC18 ication are: the datarequiredtoexecuteaninst The addressingmodesprovideeightdi The CPUuseseightaddre accumulator. stored intheindexregist accumulator (A)andtheindexregi instruction allowsun plus onemore:theunsignedmultip modes. Theinstructions The MCUinstructionsethas62inst Relative • Indexed, 16-bitoffset • Indexed, 8-bitoffset • Indexed, nooffset • Extended • •Direct Immediate • Inherent • signed multiplicationof include allthoseof er, andthelow-orderpr ssing modesforflexibi ster (X).Thehigh-orderproductis ruction. Theeightaddressingmodes ly (MUL)instruction.TheMUL ructions anduseseightaddressing fferent waysfortheCPUtofind the M146805CMOSFamily the contentsof oduct isstoredinthe lity inaccessingdata. — Rev. 2.1 Instruction Set

10.3.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.

10.3.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.

10.3.3 Direct

Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address.

10.3.4 Extended

Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address.

When using the Freescale assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 89 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 90 Instruction Set Freescale Semiconductor Freescale Set Instruction 90 General Release Specif 10.3.6 Indexed,8-BitOffset 10.3.5 Indexed,NoOffset 10.3.7 Indexed,16-BitOffset cto MC68HC05RC18 ication Indexed 8-bitoffsetinstru These instructionscana following theopcode.Thesumist CPU addstheunsig data withvariableaddresseswithin Indexed, 8-bitoffsetinstructionsare a tableortoholdthe Indexed, nooffsetinstructionsare byte, sotheseinstructions address oftheoperand. locations. Theindexregistercontai access datawithvariableaddresse with instructions Indexed memory locationsandcoul in ann-elementtable.Thetablecan determines theshortest fo As withdirectandextended addressi in ann-elementtable Indexed, 16-bitoffsetinstructionsare second byteisthelowofoffset. The firstbyteaftertheopc following theopcode.Thesumist the unsignedbyteinindexregi data withvariableaddressesatany Indexed, 16-bitoffsetinst of thetableisin k valueistypicallyintheindexregi ned byteintheindexregist byte followingtheopcode. address ofafrequentlyus anywhere inmemory. ccess locations$0000–$01FE. The CPUautomatically ructions are3-byteinstructionsthatcanaccess nooffsetare1-byte ctions areusefulforse rm ofindexedaddressing. ode isthehighbyteof d extendasfarlo can addresslocations$0000–$00FF. ster, andtheaddress he effectiveaddress he effectiveaddress often usedtomoveapointerthrough ster tothetwounsignedbytes ns thelowbyteofeffective s withinthefirst256memory the first511memorylocations.The location inmemory.TheCPUadds 2-byte instructions begin anywherewithin useful forselecti ng, theFreescaleassembler instructions thatcan cation 510($01FE).The er totheunsignedbyte ed RAMorI/Olocation. lecting thekthelement uses $00asthehigh the16-bitoffset; ng thekthelement thatcanaccess of thebeginning of theoperand. of theoperand. thefirst256 — Rev. 2.1 Instruction Set

10.3.8 Relative

Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next location after the branch instruction.

When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch.

10.4 Instruction Types

The MCU instructions fall into the following five categories:

• Register/Memory Instructions • Read-Modify-Write Instructions • Jump/Branch Instructions • Bit Manipulation Instructions • Control Instructions

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 91 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 92 Instruction Set Freescale Semiconductor Freescale Set Instruction 92 General Release Specif 10.4.1 Register/MemoryInstructions cto MC68HC05RC18 ication memory. accumulator ortheindexregister Most ofthemusetw These instructionsoperateonCPU utpyMUL STX STA SUB ORA Accumulator from Byte Memory Subtract LDX Store IndexRegister inMemory CMP LDA BIT Store Accumulator inMemory Byte andSubtract Ca Memory Byte OR Accumulator with Memory CPX Multiply EOR Load Index Byte Registerwith Memory AND ADD Byte Load Accumulatorwith Memory Byte Accumulator Memory OR with EXCLUSIVE Byte Memory with IndexRegister Compare Compare Accumulator Bit TestAccumulator withAccumulator Byte Memory AND to Accumulator Byte Add Memory Add Memory Byte and Byte Carr Add Memory Table 10-1. Register/Memory Instructions 10-1.Register/Memory Table o operands.Oneoperand ntuto Mnemonic Instruction i oAcmltrADC Accumulator to y Bit r i rmAcmltrSBC Bit fromAccumulator rry . TheCPUfindst registers andmemorylocations. is in either the the either in is he otheroperandin — Rev. 2.1 Instruction Set

10.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register.

NOTE: Do not use read-modify-write operations on write-only registers.

Table 10-2. Read-Modify-Write Instructions

Instruction Mnemonic

Arithmetic Shift Left (Same as LSL) ASL

Arithmetic Shift Right ASR

Bit Clear BCLR(1)

Bit Set BSET(1)

Clear Register CLR

Complement (One’s Complement) COM

Decrement DEC

Increment INC

Logical Shift Left (Same as ASL) LSL

Logical Shift Right LSR

Negate (Two’s Complement) NEG

Rotate Left through Carry Bit ROL

Rotate Right through Carry Bit ROR

Test for Negative or Zero TST(2)

1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.

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Freescale Semiconductor Instruction Set 93 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 94 Instruction Set Freescale Semiconductor Freescale Set Instruction 94 General Release Specif 10.4.3 Jump/BranchInstructions cto MC68HC05RC18 ication of thecondition instruction. TheCPUalso from –128to+127t condition (setorcl program counterifthesp finds theeffectivebranchdestination following theopcode.The addressing. Thedirectaddressoftheby instructions useacombination of anyreadablebit The BRCLRandBRSETinstructionsc thebranch met, program counterwhenatest instructions allowthe jump-to-subroutine instru program counter.Theunconditional Jump instructionsallo code register. is notperformed. ear) ispartoftheopcode. in thefirst256memory w theCPUtointerrupt CPU tointerruptthe he addressofthenextlo ecified bitteststrue.T ction (JSR)havenoregi transfersthetestedbit third byteisthesigned conditionismet.Ifth of directaddressingandrelative jumpinstruction(JMP)andthe by addingthethirdbyteto ause abranchbasedonthestate te tobetestedisinthebyte normal sequenceofthe locations. These3-byte the normalse The spanofbranchingis he bittobe cation afterthebranch to the carry/borrow bit bit carry/borrow to the ster operand.Branch offset byte.TheCPU e testconditionisnot quence ofthe tested andits — Rev. 2.1 Instruction Set

Table 10-3. Jump and Branch Instructions

Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear BRCLR Branch Never BRN Branch if Bit Set BRSET Branch to Subroutine BSR Unconditional Jump JMP Jump to Subroutine JSR

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 95 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 96 Instruction Set Freescale Semiconductor Freescale Set Instruction 96 General Release Specif 10.4.4 BitManipulationInstructions cto MC68HC05RC18 ication CPU canalsotest memory, whichincludesI/Oregister The CPUcansetorclearanywritabl first 256memorylocations. i e BSET BRSET BCLR BRCLR Bit Set BranchSet ifBit BranchClear ifBit Bit Clear al 10-4.BitMani Table and branchbasedont ntuto Mnemonic Instruction pulation Instructions s andon-chipRAMlocations.The e bitinthefirst256bytesof he stateofanybi t inanyofthe — Rev. 2.1 Instruction Set

10.4.5 Control Instructions

These instructions act on CPU registers and control CPU operation during program execution.

Table 10-5. Control Instructions

Instruction Mnemonic

Clear Carry Bit CLC

Clear Interrupt Mask CLI

No Operation NOP

Reset Stack Pointer RSP

Return from Interrupt RTI

Return from Subroutine RTS

Set Carry Bit SEC

Set Interrupt Mask SEI

Stop Oscillator and Enable IRQ Pin STOP

Software Interrupt SWI

Transfer Accumulator to Index Register TAX

Transfer Index Register to Accumulator TXA

Stop CPU Clock and Enable Interrupts WAIT

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 97 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 98 Instruction Set Freescale Semiconductor Freescale Set Instruction 98 General Release Specif 10.5 InstructionSetSummary ADC ,X ADC ADC ADC ADC ADC # ADD ,X ADD ADD ADD ADD ADD # AND ,X AND AND AN AND AND # ASL ,X ASL ASLX ASLA ASL ASR ASRX ASRA ASR ASR ,X BCLR BCC BEQ BCS BHCC BHCS BHS BHI D opr Source opr opr rel opr opr rel rel opr opr opr opr opr opr opr opr opr opr opr rel rel Form nopr rel rel opr opr opr ,X ,X ,X ,X ,X ,X ,X ,X Add with Carry A A Carry with Add Add without Carry A A Carry without Add Logical AND A A Logical AND rtmtcSitLf Sm sLL — — as LSL) ShiftLeft(Same Arithmetic rtmtcSitRgt—— — Right Shift Arithmetic Clear Bit n Mn Mn n Bit Clear rnhi ar i la PC Branch BitClear ifCarry rnhi qa PC PC Branch ifEqual (Same asBLO) BitSet Branch ifCarry rnhi afCryBtCerPC BitClear Branch ifHalf-Carry rnhi ihro aePC PC Branch ifHigherorSame BitSet Branch ifHalf-Carry rnhi ihrPC Branch ifHigher cto MC68HC05RC18 ication prto Description Operation al 10-6. InstructionSetSummary Table C ← ← ← ← ← ← ← (PC) + 2 + (PC)+2 b7 b7 (PC) +2 (PC) +2 (PC) +2 (PC) +2 (PC) +2 (PC)+2 ← (A) + (M) +(C) +(M) (A) ← ← (A) (A)+(M) ← rel ∧ 0————— 0 ()—— — (M) rel rel rel rel rel rel ?C b0 b0 ? C = 0———RL2 r3 rr 24 REL ? ————— C = 0 ? C = 1———RL2 r3 rr 25 REL ? ————— C = 1 ? H = 0———RL2 r3 rr 28 REL ? ————— H = 0 ? C = 0———RL2 r3 rr 24 REL ? ————— C = 0 3 rr 29 REL ? ————— H = 1 ? Z = 1———RL2 r3 rr 27 REL ? ————— Z = 1 ∨ Z = 0———RL2 r3 rr 22 REL Z ————— = 0 0 C HINZC ↕ ↕ Þ Þ Effect on — — CCR ↕ ↕ ↕ ↕ ↕ Þ Þ Þ Þ Þ ↕ ↕↕ ↕ ↕↕ ↕↕ Þ — ↕ Þ DIR (b7) DIR (b6) DIR (b5) DIR (b4) DIR (b3) DIR (b2) DIR (b1) DIR (b0) DIR EXT IMM EXT IMM EXT IMM DIR DIR DIR INH INH DIR INH INH DIR IX1 IX2 IX1 IX2 IX1 IX2 IX1 IX1 IX IX IX IX IX Address Mode — DB CB BB AB EB D9 C9 FB D4 C4 1D B9 A9 E9 B4 A4 E4 1B F9 F4 1F 78 68 58 48 38 77 67 57 47 37 19 17 15 13 11 Opcode Rev. 2.1 ee ff ee ff ee ff hh ll hh ll hh ll dd dd dd dd dd dd dd dd dd dd dd dd dd ff ff ff ff ff ii ii ii Operand 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 2 5 6 3 3 5 5 6 3 3 5 5 5 5 5 5 5 5 5 Cycles Instruction Set

Table 10-6. Instruction Set Summary (Continued)

Effect on Source CCR Form Operation Description Mode

HINZC Cycles Opcode Address Operand BIH rel Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ————— REL 2F rr 3 BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ————— REL 2E rr 3 BIT #opr IMM A5 ii 2 BIT opr DIR B5 dd 3 BIT opr ↕ EXT C5 hh ll 4 Bit Test Accumulator with Memory Byte (A) ∧ (M) — — ↕ — BIT opr,X Þ IX2 D5 ee ff 5 BIT opr,X IX1 E5 ff 4 BIT ,X IX F5 3 BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? C ∨ Z = 1————— REL 23 rr 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? I = 0 ————— REL 2C rr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 ————— REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? I = 1 ————— REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 ————— REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 ————— REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel ? 1 = 1 ————— REL 20 rr 3 DIR (b0) 01 dd rr 5 DIR (b1) 03 dd rr 5 DIR (b2) 05 dd rr 5 ↕ DIR (b3) 07 dd rr 5 BRCLR n opr rel Branch if Bit n Clear PC ← (PC) + 2 + rel ? Mn = 0 ———— Þ DIR (b4) 09 dd rr 5 DIR (b5) 0B dd rr 5 DIR (b6) 0D dd rr 5 DIR (b7) 0F dd rr 5 BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 ————— REL 21 rr 3 DIR (b0) 00 dd rr 5 DIR (b1) 02 dd rr 5 DIR (b2) 04 dd rr 5 Þ DIR (b3) 06 dd rr 5 BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 ———— ↕ DIR (b4) 08 dd rr 5 DIR (b5) 0A dd rr 5 DIR (b6) 0C dd rr 5 DIR (b7) 0E dd rr 5 DIR (b0) 10 dd 5 DIR (b1) 12 dd 5 DIR (b2) 14 dd 5 DIR (b3) 16 dd 5 BSET n opr Set Bit n Mn ← 1 ————— DIR (b4) 18 dd 5 DIR (b5) 1A dd 5 DIR (b6) 1C dd 5 DIR (b7) 1E dd 5 PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) BSR rel Branch to Subroutine ————— REL AD rr 6 SP ← (SP) – 1 PC ← (PC) + rel CLC Clear Carry Bit C ← 0 ———— 0 INH 98 2

CLI Clear Interrupt Mask I ← 0 — 0 ——— INH 9A 2

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 99 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 100 Instruction Set Freescale Semiconductor Freescale Set Instruction 100 General Release Specif CLR CLRX CLRA CLR CLR ,X CLR CPX CPX CPX CPX # CPX CPX ,X DEC ,X DEC DECX DECA DEC CMP CMP # CMP ,X CMP CMP CMP COM ,X COM COMX COMA COM EOR ,X EOR EOR EOR EOR EOR # INC ,X INC INC INCX INCA INC JMP JMP JMP JMP JMP ,X Source opr opr opr opr opr opr opr opr opr opr opr opr opr opr Form opr opr opr opr opr opr opr opr opr opr opr opr opr ,X ,X ,X ,X ,X ,X ,X ,X ,X ,X ,X ,X Clear Byte Clear opr ne eitrwt eoyBt X M — — (X)–(M) Index Byte Compare RegisterwithMemory Decrement Byte opr cuuao ihMmr ye()–()—— — –(M) (A) Byte AccumulatorCompare withMemory Complement Byte (One’sComplement Byte Complement) EXCLUSIVE OR Accumulator with Memory Accumulator OR withMemory EXCLUSIVE Increment Byte nodtoa upPC Jump Unconditional Byte cto MC68HC05RC18 ication al 10-6.Instruction Table prto Description Operation Set Summary (Continued) Set Summary M M M A X ← ← ← ← ← A ← M M M M M M A X (M (M A X (M (A (X ← M M M Jump Address ————— A X ← ← ← ← ← ← ← ← ← ← (A) ) = $FF –(X) ) =$FF –(A) ) =$FF ) = $FF –(M) ) =$FF –(M) ) =$FF ) = $FF –(M) ) =$FF ← ← ← ← ← (M)+1 (A)+1 (M)+1 (M)+1 (X)+1 (M) –1 (A) –1 (X) –1 (M) –1 (M) –1 $00 $00 $00 $00 $00 ⊕ ()—— — (M) —— —01— 1 0 —— —— —— HINZC Effect on CCR ↕ ↕ ↕ ↕ ↕ ↕ Þ Þ Þ Þ Þ Þ ↕ ↕ ↕↕ ↕ ↕ ↕ Þ Þ Þ Þ — — — ↕ 1 Þ EXT IMM EXT IMM EXT IMM EXT INH INH DIR DIR INH INH DIR DIR INH INH DIR DIR INH INH DIR DIR IX1 IX1 IX2 IX1 IX1 IX2 IX1 IX1 IX2 IX1 IX1 IX2 IX IX IX IX IX IX IX IX Address Mode — DC CC BC EC FC D3 C3 D1 C1 D8 C8 7C 6C 5C 4C 3C B3 A3 E3 B1 A1 E1 7A 6A 5A 4A 3A B8 A8 E8 F3 7F 6F 5F 4F 3F F1 F8 73 63 53 43 33 Opcode Rev. 2.1 ee ff ee ff ee ff ee ff hh ll hh ll hh ll hh ll dd dd dd dd dd dd dd dd ff ff ff ff ff ff ff ff ii ii ii Operand 5 6 3 3 5 3 4 5 4 3 2 5 6 3 3 5 3 4 5 4 3 2 5 6 3 3 5 3 4 5 4 3 2 5 6 3 3 5 2 3 4 3 2 Cycles Instruction Set

Table 10-6. Instruction Set Summary (Continued)

Effect on Source CCR Form Operation Description Mode

HINZC Cycles Opcode Address Operand JSR opr DIR BD dd 5 PC ← (PC) + n (n = 1, 2, or 3) JSR opr EXT CD hh ll 6 Push (PCL); SP ← (SP) – 1 JSR opr,X Jump to Subroutine ————— IX2 DD ee ff 7 Push (PCH); SP ← (SP) – 1 JSR opr,X IX1 ED ff 6 PC ← Effective Address JSR ,X IX FD 5

LDA #opr IMM A6 ii 2 LDA opr DIR B6 dd 3 LDA opr ↕ EXT C6 hh ll 4 Load Accumulator with Memory Byte A ← (M) — — ↕ — LDA opr,X Þ IX2 D6 ee ff 5 LDA opr,X IX1 E6 ff 4 LDA ,X IX F6 3

LDX #opr IMM AE ii 2 LDX opr DIR BE dd 3 LDX opr ↕ ↕ EXT CE hh ll 4 Load Index Register with Memory Byte X ← (M) — — — LDX opr,X Þ Þ IX2 DE ee ff 5 LDX opr,X IX1 EE ff 4 LDX ,X IX FE 3

LSL opr DIR 38 dd 5 LSLA ↕ INH 48 3 LSLX Logical Shift Left (Same as ASL)C 0 — — ↕↕ INH 58 3 Þ LSL opr,X b7 b0 IX1 68 ff 6 LSL ,X IX 78 5

LSR opr DIR 34 dd 5 LSRA INH 44 3 LSRX Logical Shift Right0 C — — 0 ↕↕ INH 54 3 LSR opr,X b7 b0 IX1 64 ff 6 LSR ,X IX 74 5

MUL Unsigned Multiply X : A ← (X) × (A) 0 ——— 0 INH 42 11

NEG opr M ← –(M) = $00 – (M) DIR 30 dd 5 NEGA A ← –(A) = $00 – (A) ↕ INH 40 3 NEGX Negate Byte (Two’s Complement) X ← –(X) = $00 – (X) —— ↕↕ INH 50 3 Þ NEG opr,X M ← –(M) = $00 – (M) IX1 60 ff 6 NEG ,X M ← –(M) = $00 – (M) IX 70 5

NOP No Operation ————— INH 9D 2

ORA #opr IMM AA ii 2 ORA opr DIR BA dd 3 ORA opr ↕ EXT CA hh ll 4 Logical OR Accumulator with Memory A ← (A) ∨ (M) — — ↕ — ORA opr,X Þ IX2 DA ee ff 5 ORA opr,X IX1 EA ff 4 ORA ,X IX FA 3

ROL opr DIR 39 dd 5 ROLA ↕ INH 49 3 ROLX Rotate Byte Left through Carry BitC — — ↕↕ INH 59 3 Þ ROL opr,X b7 b0 IX1 69 ff 6 ROL ,X IX 79 5

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 101 NON-DISCLOSURE AGREEMENT REQUIRED Instruction Set 102 Instruction Set Freescale Semiconductor Freescale Set Instruction 102 General Release Specif ROR ,X ROR ROR RORX RORA ROR SBC SBC SBC SBC # RTS Return fromSubroutine Return RTS S ee tc one SP fromInterrupt Return Stack Reset Pointer RTI RSP SBC SBC ,X E e nerp akI C andE StopOscillator STX STX STX STOP STA ,X Mask Interrupt Set STA STA Bit Carry Set STA STA SEI SEC STX SUB SUB SUB SUB # STX ,X SUB SUB ,X W Software Interrupt SWI A rnfrAcmltrt ne eitrX Transfer Accumulator toIndex Register TAX Source opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr Form opr opr opr opr ,X ,X ,X ,X ,X ,X ,X ,X ,X oaeBt ih hog ar i — — Bit Rotate ByteRightthroughCarry Subtract Memory Byte and Carry Bit from and Carry Byte SubtractMemory tr cuuao nMmr M Store Accumulator inMemory tr ne eitrI eoyM Store Index InMemory Register Subtract Memory Byte from Accumulator A A Byte from Accumulator Subtract Memory Accumulator cto MC68HC05RC18 ication al 10-6.Instruction Table prto Description Operation al R i N E2 8E INH — — — 0 — nable IRQPin PCH PCH PCL Set Summary (Continued) Set Summary SP SP SP PC PC SP SP SP SP SP SP SP SP SP SP SP ← ← SP SP ← ← ← b7 ← A ← ← ← ← Interrupt Vector Interrupt HighByte Interrupt Vector Interrupt Low Byte ← ← (SP) –1;Push(CCR) (SP)–1;Push(PCH) ← ← (PC) +1;Push(PCL) (PC) ← (SP) +1;Pull (CCR) (SP) + 1; Pull (PCH) Pull (SP)+1; (SP) + 1; Pull (PCH) Pull (SP)+1; (SP) + 1; Pull (PCL) Pull + 1; (SP) (SP) + 1; Pull (PCL) Pull + 1; (SP) ← (SP) –1;Push (A) (SP) –1;Push (X) (SP)+1;Pull (X) (SP)+1;Pull (A) ()–()–()—— — –(C) –(M) (A) (SP) –1;I (SP) ← ← ()–()—— — (A)–(M) ← ← ← ← ← $ 0 F———IH9 2 9C INH ————— $00FF ( )———IH9 2 97 INH ————— (A) ()—— — (A) ()—— — (X) 1—1——IH9 2 9B INH ——— 1 — 1 1—— N 92 99 INH 1 ———— 1 b0 ← 1 C —— N 16 81 INH ————— — N 310 83 INH ——— 1 — HINZC ↕ Þ Effect on ↕↕↕↕ CCR ↕ ↕ ↕ ↕ ↕↕↕ Þ Þ Þ Þ ↕↕ ↕↕ ↕ ↕ — — EXT IMM EXT EXT EXT IMM INH INH DIR N 09 80 INH DIR DIR DIR DIR IX1 IX1 IX2 IX1 IX2 IX1 IX2 IX1 IX2 IX IX IX IX IX Address Mode — DF CF D2 C2 D7 C7 EF BF D0 C0 B2 A2 E2 B7 E7 FF B0 A0 E0 F2 F7 F0 76 66 56 46 36 Opcode Rev. 2.1 ee ff ee ff ee ff ee ff hh ll hh ll hh ll hh ll dd dd dd dd dd ff ff ff ff ff ii ii Operand 5 6 3 3 5 4 5 6 5 4 3 4 5 4 3 2 4 5 6 5 4 3 4 5 4 3 2 Cycles Instruction Set

Table 10-6. Instruction Set Summary (Continued)

Effect on Source CCR Form Operation Description Mode

HINZC Cycles Opcode Address Operand

TST opr DIR 3D dd 4 TSTA INH 4D 3 TSTX Test Memory Byte for Negative or Zero (M) – $00 — — ↕↕— INH 5D 3 TST opr,X IX1 6D ff 5 TST ,X IX 7D 4

TXA Transfer Index Register to Accumulator A ← (X) ————— INH 9F 2 0 WAIT Stop CPU Clock and Enable Interrupts — ——— INH 8F 2 Þ A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Instruction Set 103 Instruction Set LSB 0 1 2 3 4 5 6 7 8 9 F E A B C D MSB 3 3 3 3 4 3 3 4 2 3 3 3 3 3 3 5 BIT STA JSR LDA LDX STX JMP SUB SBC CPX ADD AND ADC EOR ORA CMP 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 4 4 4 4 5 4 4 5 3 4 4 4 4 4 4 6 BIT STA JSR LDA LDX STX JMP SUB SBC CPX ADD AND ADC EOR ORA CMP 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 5 5 5 5 6 5 5 6 4 5 5 5 5 5 5 7 BIT STA JSR LDA LDX STX JMP SUB SBC CPX ADD AND ADC EOR ORA CMP 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 3IX2 4 4 4 4 5 4 4 5 3 4 4 4 4 4 4 6 BIT STA JSR LDA LDX STX JMP SUB SBC CPX ADD AND ADC EOR ORA CMP MSB of Opcode in Hexadecimal MSB Number of Cycles of Number Mnemonic Opcode Mode Bytes/Addressing of Number 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3EXT 3 3 3 3 4 2 4 5 3 3 3 3 3 3 3 3 5 0 BIT STA JSR LDA LDX STX JMP SUB SBC CPX ADD AND ADC EOR ORA CMP BRSET0 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 3DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR MSB 2 2 2 2 2 2 2 2 2 2 2 6 2 0 BIT LDA LDX SUB SBC CPX BSR ADD AND ADC EOR ORA CMP LSB 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2IMM 2REL 2 2 2 2 2 2 2 2 CLI SEI TAX TXA CLC SEC RSP NOP 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 6 2 9 2 10 RTI SWI RTS WAIT STOP 1INH 1INH 1INH 1INH 1INH 5 5 5 5 5 5 5 4 5 5 5 INC TST LSR CLR ROL ASR DEC NEG ROR COM ASL/LSL 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX 1IX LSB of Opcode in Hexadecimal 6 6 6 6 6 6 6 6 5 6 6 INC TST LSR CLR ROL ASR DEC NEG ROR COM Table 10-7. Opcode Map ASL/LSL 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 2IX1 y-Write Control Register/Memory 3 3 3 3 3 3 3 3 3 3 3 INCX TSTX LSRX CLRX ROLX ASRX DECX NEGX RORX COMX ASLX/LSLX 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 3 3 11 3 3 3 3 3 3 3 3 3 MUL INCA TSTA LSRA CLRA ROLA ASRA DECA NEGA RORA COMA ASLA/LSLA 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 1INH 5 5 5 5 5 5 5 5 5 4 5 INC TST LSR CLR ROL ASR DEC NEG ROR COM ASL/LSL 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 BIL BHI BIH BMI BPL BLS BRA BNE BCC BRN BEQ BMS BMC BHCS BHCC BCS/BLO 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 2REL 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 BSET0 BSET1 BSET2 BSET3 BSET4 BSET5 BSET6 BSET7 BCLR0 BCLR1 BCLR2 BCLR3 BCLR4 BCLR5 BCLR6 BCLR7 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 2DIR 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 0123456789ABCDEF DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX Bit Manipulation Branch Read-Modif BRSET0 BRSET1 BRSET2 BRSET3 BRSET4 BRSET5 BRSET6 BRSET7 BRCLR0 BRCLR1 BRCLR2 BRCLR3 BRCLR4 BRCLR5 BRCLR6 BRCLR7 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR 3DIR INH = InherentIMM = ImmediateDIR = DirectEXT = Extended No Offset REL = Relative = Indexed, IX 16-Bit Offset IX2 = Indexed, Offset 8-Bit IX1 = Indexed, MSB 0 1 2 3 4 5 6 7 8 9 F E A B C D LSB

General Release Specification MC68HC05RC18 — Rev. 2.1 NON-DISCLOSURE AGREEMENT REQUIRED 104 Instruction Set Freescale Semiconductor General Release Specification — MC68HC05RC18

Section 11. Electrical Specifications

11.1 Contents

11.2 Introduction...... 105 11.3 Maximum Ratings...... 106 11.4 Operating Temperature Range...... 107 11.5 Thermal Characteristics ...... 107 11.6 DC Electrical Characteristics (5.0 Vdc)...... 108 11.7 DC Electrical Characteristics (2.2 Vdc)...... 109 11.8 Control Timing (2.2 Vdc to 5.0 Vdc) ...... 111

11.2 Introduction

This section contains MCU electrical specifications and timing information.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Electrical Specifications 105 NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications 106 Electrical Specifications Freescale Semiconductor Freescale Specifications Electrical 106 General Release Specif 11.3 MaximumRatings NOTE: cto MC68HC05RC18 ication voltage level,eitherV V conditions. DC ElectricalCharact ratings. This deviceisnotguar shown inthetablebelow.KeepV high staticvoltages;however,do The MCUcontainscircuitrytopr exposed withoutperman aret ratings Maximum Storage Temperature Range Operating Temperature Range CurrentDrain Per PinExcluding V VoltageInput Supply Voltage SS MC68HC05RC18 (Standard) MC68HC05RC18 ≤ (V

Refer to IN rV or OUT 11.6 DCElectrical ) aigSmo au Unit Value Symbol Rating ≤ V SS DD he extremelimitstowhichtheMCUcanbe anteed tooperateproperly eristics (2.2Vdc) orV . Connectunusedinputstotheappropriate ently damagingit. DD DD . and V otect theinputsagainstdamagefrom not applyvoltages IN andV Characteristics(5.0Vdc) SS forguaranteedoperating OUT withintherange T V V T STG I25mA DD IN A atthemaximum higher thanthose 03t 70V –0.3 to +7.0 –65 to+150 –65 V V 0 to +70 0 to SS T DD L –0.3to to T to +0.3 H and — Rev. 2.1 11.7 o o V C C Electrical Specifications

11.4 Operating Temperature Range

Characteristic Symbol Value Unit

Operating Temperature Range T to T T L H °C MC68HC05RC18 (Standard) A 0 to +70

11.5 Thermal Characteristics

Characteristic Symbol Value Unit

Thermal Resistance PDIP θJA 60 °C/W SOIC 60

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Electrical Specifications 107 NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications 108 Electrical Specifications Freescale Semiconductor Freescale Specifications Electrical 108 General Release Specif 11.6 DCElectricalCh Output Low VoltageOutput Supply Current (see Notes) (see Current Supply LowInput Voltage Output High Voltage High Output NOTES: VoltageOutput Capacitance Current Input Input High High VoltageInput I/O Ports Hi-Z Leakage Current I/O PortsHi-Z Leakage (I Stop Wait Run IRQ C, Port B, Port A, Port (I (I (I (I (I PB0–PB7 with Strong Pullups Enabled Pullups PB0–PB7 withStrong (V I PB0–PB7 withWeak Enabled Pullups (V PB0–PB7 withWeak Enabled Pullups (V Enabled Pullups PB0–PB7 withStrong (V I RESET orOutput) Ports (as Input RESET Port A, Port B, Port C, IRQ C, Port B, Port A, Port Port A, Port B, Port C Port B, Port A, Port LOAD LOAD LOAD LOAD LOAD LOAD LOAD LOAD 9. Strong pullups are designed to be capable of pulling to to V of pulling to be capable aredesigned pullups Strong 9. I Wait 8. I (Operating) Run 5. I Wait 4. 3. Typical values at midpoint of voltage range, range, 25 of midpoint voltage values at Typical 3. reflectaverage measurements. Allvalues shown 2. V 1. 6. Wait, Stop Stop I Wait, 6. 7. Stop I Stop 7. 25 0 o = –10.0 =–10.0 =10.0 C to+70 o = 20 mA) Port C (Bits 0–3) 20 mA)Port C = =35 mA) IRO 4–7) (Bits C Port B, Port A, Port mA) 6 = (Bits 0–3) –4 mA)Port C = mA)IRO =–20 Port mA)Port A, B,–4 4–7) = Port (Bits C C from rail; no dc loads; less than 50 pF on all outputs; C outputs; all pF on 50 than less loads; dc no rail; from , LPRST , LPRST DD =5.0Vdc µ DD DD DD A µ o is affected linearly by theOSC2 capacitance. isaffectedlinearly : only coretimer active is measured with OSC1 withOSC1 = V measured is A C , IRQ , IRQ DD : all ports configured as inputs, V asinputs, configured : all ports hrceitcSmo i y a Unit Max Typ Min Symbol Characteristic , OSC1 ± 10%, V 10%, cto MC68HC05RC18 ication DD , Wait I , RESET , RESET SS =0Vdc,T DD aracteristics (5.0Vdc) : Measured using external square waveclocksource(f square using : external Measured , LPRST , LPRST IN IN IN IN IN IN SS A = 0.7x V = 0.2x V , OSC1 , OSC1 = 0.7x V = 0.2x V = 0 . ° C to +70 C to DD DD DD DD IL o =0.2V, V ) ) C only ) ) 9 ° C, unless otherwise noted otherwise C, unless L =20pF OSC2 on IH within within 1 IH C C V V V V V =V I V I I DD OUT OZ OH OH IN INT OL OL IH IL DD

–0.2 V µ s for pF,4-k a 100 0.7 x V 0.7 x V V V V DD DD DD DD –15 –40 –70 1 10 — –10 V –5 –1 — — — — — — — — — — – 0.1

SS –0.8 –0.8 –0.8 DD OSC V V V DD DD DD –136 –20 –48 –79 0.2 0.4 0.2 0.5 0.5 0.3 2.4 = 4.2 MHz), all inputs 0.2 V allinputs 0.2 =4.2MHz), Ω V 0.2 x — —V — — — — —

–0.2 –0.4 –0.2 load. –130 –210 20.0 10.0 –60 –80 0.5 0.8 0.5 0.1 1.0 4.0 12 — — — — 1 8 DD DD — Rev. 2.1 mA mA µ µ µ µ pF V V V V V A A A A Electrical Specifications

11.7 DC Electrical Characteristics (2.2 Vdc)

Characteristic Symbol Min Typ Max Unit

Output Voltage

ILOAD = 10.0 µA VOL — — 0.1 V ILOAD = –10.0 µA VOH VDD– 0.1 — — Output High Voltage (I = –1.2 mA) Port A, Port B, Port C (Bits 4–7) V V – 0.3 V – 0.1 — LOAD OH DD DD V (ILOAD = –6 mA) IRO VDD– 0.8 VDD– 0.3 — (ILOAD = –1.2 mA) Port C (Bits 0–3) VDD– 0.3 VDD– 0.1 — Output Low Voltage (I = 2.0 mA) Port A, Port B, Port C (Bits 4–7) V — 0.1 0.3 LOAD OL V (ILOAD = 11 mA) IRO — 0.2 0.8 (ILOAD = 7.0 mA) Port C (Bits 0–3) — 0.1 0.3 Input High Voltage V 0.7 x V —V V Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 IH DD DD

Input Low Voltage V V — 0.2 x V V Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1 IL SS DD

Supply Current (see Notes)

Run IDD — 0.75 1.0 mA Wait IDD — 0.1 0.3 mA Stop o 25 C IDD — 0.1 1.0 µA o o 0 C to +70 C IDD — 0.1 4.0 µA I/O Ports Hi-Z Leakage Current I –4 — 4 µA Port A, Port B, Port C OZ

Input Current RESET, LPRST, IRQ, OSC1 –0.4 — 0.4 9 PB0–PB7 with Strong Pullups Enabled (VIN = 0.4 x VDD) –8 –21 –35 IIN µA PB0–PB7 with Strong Pullups Enabled (VIN = 0.7 x VDD) –5 –16 –28 PB0–PB7 with Weak Pullups Enabled (VIN = 0.4 x VDD) –2 –6 –15 PB0–PB7 with Weak Pullups Enabled (VIN = 0.7 x VDD –1 –2 –12 Capacitance

Ports (as Input or Output) COUT — — 12 pF RESET, LPRST, IRQ CINT — — 8 NOTES:

1. VDD = 2.2 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted 2. All values shown reflect average measurements. 3. Typical values at midpoint of voltage range, 25 oC only

4. Wait IDD: only core timer active 5. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source (fOSC = 4.2 MHz), all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 6. Wait, Stop IDD: all ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V 7. Stop IDD is measured with OSC1 = VSS. 8. Wait IDD is affected linearly by the OSC2 capacitance. 9. Strong pullups are designed to be capable of pulling to VIH within 25 µs for a 100 pF, 4-kΩ load.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Electrical Specifications 109 NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications 110 Electrical Specifications Freescale Semiconductor Freescale Specifications Electrical 110 General Release Specif Figure 11-1.MaximumSupplyCurr cto MC68HC05RC18 ication

SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 1.0 2.0 3.0 4.0 0.2 0.3 0.4 0.6 0.8 1.0 0 0 02.5 02.5 V V T T A A DD DD = –0 = –0 = 2.4 V = 5.5 V = ° ° C to 70 C to 70 C to . 2.0 0.5 . 2.0 0.5 INTERNAL(MHz) CLOCKFREQUENCY INTERNAL(MHz) CLOCKFREQUENCY R U

° N °

C I C D D . 1.5 1.0 . 1.5 1.0 ent versusInternalClockFrequency W XTAL XTAL A W I

STOP I T A R U I I STOP I ÷ T N ÷ D 2 I D I D 2 D D D

DD DD (20 (4 µ µ A) A) 2.1 2.1 — Rev. 2.1 Electrical Specifications

11.8 Control Timing (2.2 Vdc to 5.0 Vdc)

Characteristic Symbol Min Max Unit Frequency of Operation

Crystal fOSC — 4.2 MHz External Clock fOSC dc 4.2 MHz Internal Operating Frequency

Crystal (fOSC /2) fOP — 2.1 MHz External Clock (fOSC /2) fOP dc 2.1 MHz

Cycle Time tCYC 480 — ns

Crystal Oscillator Startup Time (see Note 3) tOXOV —100ms

Stop Recovery Startup Time (Crystal Oscillator) ( see Note 3) tILCH —100ms

RESET Pulse Width tRL 1.5 — tCYC

Interrupt Pulse Width Low (Edge-Triggered) tILIH 125 — ns

Interrupt Pulse Period tILIL see Note 2 — tCYC

OSC1 Pulse Width tOH, tOL 90 — ns NOTES: o o 1. VDD = 2.2 to 5.5 Vdc, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tCYC. 3. These features, are not tested.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Electrical Specifications 111 NON-DISCLOSURE AGREEMENT REQUIRED Electrical Specifications 112 Electrical Specifications Freescale Semiconductor Freescale Specifications Electrical 112 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 General Release Specification — MC68HC05RC18

Section 12. Mechanical Specifications

12.1 Contents

12.2 Introduction...... 113 12.3 28-Pin Plastic Dual-In-Line Package (Case 710-02) ...... 114 12.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) ...... 114 12.5 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02) .115

12.2 Introduction

This section describes the dimensions of the dual-in-line package (DIP), small outline integrated circuit (SOIC), and plastic leaded chip carrier (PLCC) MCU packages.

The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, please visit the Freescale website at http://freescale.com. Follow wwweb on-line instructions to retrieve the current mechanical specifications.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Mechanical Specifications 113 NON-DISCLOSURE AGREEMENT REQUIRED Mechanical Specifications 114 Mechanical Specifications Freescale Semiconductor Freescale Specifications Mechanical 114 General Release Specif 12.4 28-PinSmallOutlineIntegrat 12.3 28-PinPlasticDual-I -T- 28 114 HG 28 114 28X 26X 26X .1 02)TAB A T (0.25) 0.010 D G cto MC68HC05RC18 ication -A- A F M S D 15 n-Line Package(Case710-02) PLANE SEATING N S B 15 K -B- K C C PLANE SEATING -T- R ed CircuitPackage(Case751F-04) 14X X 45 .1 (0.25) 0.010 P ° M L M J B M M J F NOTES: .DMNINBDE O INCLUDE NOT DOES B DIMENSION 3. LEADS OF CENTER TO L DIMENSION 2. (D), LEADS OF TOLERANCE POSITIONAL 1. ODFLASH. MOLD PARALLEL. FORMED WHEN OTHER. EACH AND PLANE SEATING TO RELATION IN CONDITION, MATERIAL ATMAXIMUM (0.010) 0.25mm WITHIN BE SHALL DIM M G N K H D C B A L F J NOTES: .DMNINDDE O INCLUDE NOT DOES D DIMENSION 5. 0.15 PROTRUSION MOLD MAXIMUM MOLD 4. INCLUDE NOT DO B AND A DIMENSION MILLIMETER. 3. DIMENSION: CONTROLLING 2. PER TOLERANCING AND DIMENSIONING 1. ILMTR INCHES MILLIMETERS CONDITION. MATERIAL MAXIMUM AT DIMENSION D OF EXCESS IN TOTAL (0.005) 0.13 BE SHALL PROTRUSION DAMBAR PROTRUSION. DAMBAR SIDE. PER (0.006) PROTRUSION. 1982. Y14.5M, ANSI 13.72 36.45 I MIN MIN 0.51 2.92 0.20 1.65 1.02 0.36 3.94 52 BSC 15.24 DIM 0 .4BSC 2.54 M G ° K D C B A R P F J 14.22 37.21 10.05 17.80 A MAX MAX ILMTR INCHES MILLIMETERS I MIN MIN 1.02 3.43 0.38 2.16 1.52 0.56 5.08 15 0.25 0.13 0.23 0.41 0.35 2.35 7.40 .7BC000BSC 0.050 BSC 1.27 0 ° ° 10.55 18.05 0.020 0.008 0.065 0.040 0.014 0.155 0.540 1.435 0.115 A MAX MAX 0.75 0.29 0.32 0.90 0.49 2.65 7.60 .0 BSC 0.600 BSC 0.100 0 8 ° °

ALLOWABLE 0.010 0.395 0.005 0.009 0.016 0.014 0.093 0.292 0.701 0.040 0.135 0.015 0.085 0.060 0.022 0.200 0.560 1.465 15 0 ° ° — 0.029 0.415 0.013 0.035 0.019 0.104 0.299 0.011 0.711 8 ° Rev. 2.1 Mechanical Specifications

12.5 44-Pin Plastic Leaded Chip Carrier Package (Case 777-02)

B 0.007(0.180)M T L-M S N S D -N- YBRK U 0.007(0.180)M T L-M S N S

Z -L- -M-

V X G1 44 1 W D 0.010 (0.25)S T L-M S N S VIEW D-D

A 0.007(0.180)M T L-M S N S

M S S R 0.007(0.180)T L-M N H 0.007(0.180)M T L-M S N S Z

J K1 E

0.004 (0.10) G C K -T- SEATING PLANE G1 F VIEW S 0.010 (0.25)S T L-M S N S 0.007(0.180)M T L-M S N S

VIEW S

NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED INCHES MILLIMETERS WHERE TOP OF LEAD SHOLDERS EXITS DIM MIN MAX MIN MAX PLASTIC BODY AT MOLD PARTING LINE. A 0.685 0.695 17.40 17.65 2. DIMENSION G1, TRUE POSITION TO BE B 0.685 0.695 17.40 17.65 MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSION R AND U DO NOT INCLUDE MOLD C 0.165 0.180 4.20 4.57 FLASH. ALLOWABLE MOLD FLASH IS 0.010 E 0.090 0.110 2.29 2.79 (0.25) PER SIDE. F 0.013 0.019 0.33 0.48 4. DIMENSIONING AND TOLERANCING PER ANSI G 0.050 BSC 1.27 BSC Y14.5M, 1982. H 0.026 0.032 0.66 0.81 5. CONTROLLING DIMENSION: INCH. J 0.020 0.51 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 K 0.025 0.64 (0.300). DIMENSIONS R AND U ARE DETERMINED R 0.650 0.656 16.51 16.66 AT THE OUTERMOST EXTREMES OF THE U 0.650 0.656 16.51 16.66 PLASTIC BODY EXCLUSIVE OF THE MOLD V 0.042 0.048 1.07 1.21 FLASH, TIE BAR BURRS, GATE BURRS AND W 0.042 0.048 1.07 1.21 INTERLEAD FLASH, BUT INCLUDING ANY X 0.042 0.056 1.07 1.42 MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. Y 0.020 0.50 7. DIMINSION H DOES NOT INCLUDE DAMBAR Z 2° 10° 2° 10° PROTRUSION OR INTRUSION. THE DAMBAR G1 0.610 0.630 15.50 16.00 PROTUSION(S) SHALL NOT CAUSE THE H K1 0.040 1.02 DIMINSION TO BE GREATER THAN 0.037 (0.940116). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMINISION TO SMALLER THAN 0.025 (0.635).

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Mechanical Specifications 115 NON-DISCLOSURE AGREEMENT REQUIRED Mechanical Specifications 116 Mechanical Specifications Freescale Semiconductor Freescale Specifications Mechanical 116 General Release Specif cto MC68HC05RC18 ication — Rev. 2.1 Design Specification — MC68HC05RC18

Section 13. Ordering Information

13.1 Contents

13.2 Introduction...... 117 13.3 MCU Ordering Forms ...... 117 13.4 Application Program Media...... 118 13.5 ROM Program Verification ...... 119 13.6 ROM Verification Units (RVUs)...... 120 13.7 MC Order Numbers ...... 120

13.2 Introduction

This section contains instructions for ordering custom-masked ROM MCUs.

13.3 MCU Ordering Forms

To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Freescale representative. Submit the following items when ordering MCUs:

• A current MCU ordering form that is completely filled out (Contact your Freescale sales office for assistance.) • A copy of the customer specification if the customer specification deviates from the Freescale specification for the MCU • Customer’s application program on one of the media listed in 13.4 Application Program Media

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Ordering Information 117 NON-DISCLOSURE AGREEMENT REQUIRED Ordering Information 118 Ordering Information Freescale Semiconductor Freescale Information Ordering 118 General Release Specif 13.4 ApplicationProgramMedia cto MC68HC05RC18 ication 3. PC-DOS is a trademark of International Business Machines Corporation. Machines Business International of trademark is a 3. PC-DOS ofMicrosoft 2. trademark Corporation. MS-DOS aregistered is isa tr 1. registered Macintosh generated byM6805crossa format (S1andS9records),achar On diskettes,theapplic diskette withthefo When submittingtheappl fo logic Use positive following media: Please delivertheapp Then pressthereturnkeyto 891-FREE. Aftermaking Freeware BulletinBoardService(B The currentMCUorderingformisalso MS-DOS • Formattedcapacityofdiskette • Name ofoperating system • •Date File nameofobjectcode • Project orproductname • Customer partnumber • Customer name • MS-DOS • •Macintosh K ordouble-sidedhi double-sided high-density1.4M) double-density 360Kordoubl ®2 ® ®1 orPC-DOS orPC-DOS llowing information: 31/2-inchdiskette(double-sided800Kor r dataandaddresses. ademark of Apple Computer, Inc. Computer, ofApple ademark lication programtoFr ation programmustbein the connection,type ication programonadi gh-density 1.44M) starttheBBSsoftware. TM ssemblers andlinkers. TM 51/4-inchdiske 3 31/2-inchdiskett that formatteddiskette acter-based objectfileformat BS). Thetelephonenu e-sided high-density1.2M) availablethroughtheFreescale eescale inoneofthe bbs tte (double-sided skette, clearlylabelthe Freescale’s S-record Freescale’s in lowercase letters. inlowercaseletters. e (double-sided720 mber is(512) — Rev. 2.1 Ordering Information

NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all non-user ROM locations or leave all nonuser ROM locations blank. Refer to the current MCU ordering form for additional requirements. Freescale may request pattern re-submission if nonuser areas contain any nonzero code.

If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames.

In addition to the object code, a file containing the source code can be included. Freescale keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code.

13.5 ROM Program Verification

The primary use for the on-chip ROM is to hold the customer’s application program. The customer develops and debugs the application program and then submits the MCU order along with the application program.

Freescale inputs the customer’s application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain nonuser ROM code, such as self-check code. Freescale sends the customer a computer printout of the listing verify file along with a listing verify form.

To aid the customer in checking the listing verify file, Freescale will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned.

Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Freescale. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor Ordering Information 119 NON-DISCLOSURE AGREEMENT REQUIRED Ordering Information 120 Ordering Information Freescale Semiconductor Freescale Information Ordering 120 General Release Specif 13.7 MCOrderNumbers 13.6 ROMVerificationUnits(RVUs) cto MC68HC05RC18 ication RVUs arenotguaran quantity. Theseunitsare implemented. The10 demonstrate thatthecu not testedtoenvironmental unmarked ceramicandtestedto5Vd sends theRVUstocustomer mask begins.Freescale application programcannotbecha application programandisusedto custom photographicmask.Themask types. 13-1 Table After receivingthesigned 28-Pin Plastic Dual In-Line Package 28-Pin Small Out 44-Pin Plastic Leaded Chip Chip Leaded Plastic 44-Pin (DIP) Circuit Package(SOIC) Carrier (PLCC) Carrier Package Type showstheMCor line Integrated Table 13-1. MCOrder 13-1. Numbers Table teed byFreescale RVUsarefreeofcharge stomer’s userROMpatternwasproperly then produces10MC not tobeusedforqualif listing verifyform,Fr extremesbecausethei der numbersfortheavailablepackage . RVUsareusuallypackagedin processsiliconwafers.The nged afterthemanufactureof Temperature 0 0 0 Operating ° ° ° C to 70C to C to 70C to C to 70C to c atroomtemper Range contains thecustomer’s Quality Assurance. ° ° ° MC68HC05RC18P C MC68HC05RC18DW C MC68HC05RC18FN C Us, calledRVUs,and eescale manufacturesa with theminimumorder ication orproduction. r solepurposeisto MC Order Number ature. RVUsare — Rev. 2.1 General Release Specification — MC68HC05RC18

Appendix A. MC68HC05RC9

A.1 Contents

A.2 Introduction...... 121 A.3 Memory Map...... 121

A.2 Introduction

Appendix A introduces the MC68HC05RC9. The technical data applying to the MC68HC05RC18 applies to the MC68HC05RC9 with the exceptions given in this appendix.

A.3 Memory Map

Both the MC68HC05RC9 and the MC68HC05RC18 have 16-Kbyte memory maps consisting of user ROM, RAM, burn-in ROM, and input/output (I/O). However, the user ROM for the MC68HC05RC9 consists of only 8112 bytes of ROM.

Figure A-1 shows the MC68HC05RC9 memory map in user mode.

MC68HC05RC18 — Rev. 2.1 General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED

Freescale Semiconductor 121 NON-DISCLOSURE AGREEMENT REQUIRED 122 General Release Specif $1FFF $3FEF $3FAF $3FFF $3FB0 $00C0 $00BF $2000 $3FF0 $00FF $017F $001F $0180 $0100 $0020 $0000 USER VECTORS BURN-IN ROM cto MC68HC05RC18 ication & VECTORS 128 BYTES 8112 BYTES 160 BYTES 16 BYTES 64 BYTES 32 BYTES USER ROM UNUSED RAM RAM I/O 64 BYTES Figure A-1.MC68HC05RC9 MemoryMap STACK 16383 16368 16367 16304 16303 0384 0383 0256 0255 0192 0191 0032 0031 0000 CORE TIMER CONTROL & STATUS REG. CORE TIMERCONTROL&STATUS PORT C DATA DIRECTION REGISTERPORT CDATADIRECTION PORT B DATA DIRECTION REGISTERPORT BDATADIRECTION REGISTERPORT ADATADIRECTION CORE TIMER VECTOR (HIGH BYTE) CORE TIMER COUNTER REGISTER CORE TIMER VECTOR (LOW BYTE) CMT TIMER VECTOR (LOW BYTE) TIMER VECTOR(LOW CMT CMT TIMERVECTOR (HIGHBYTE) RESET VECTOR(HIGH BYTE) RESET VECTORRESET (LOW BYTE) IRQ/PTB KEYSCANPULLUPS IRQ/PTB KEYSCAN PULLUPSIRQ/PTB KEYSCAN SWI VECTOR (HIGHBYTE) SWI PORT C DATA REGISTER SWI VECTOR (LOWBYTE) SWI PORT B DATAREGISTER PORT A DATAREGISTER PORT VECTOR (HIGHBYTE) VECTOR (LOW BYTE) CMT TIMER MDR1 CMT TIMERCLR2 CMT TIMER MDR3 CMT TIMER MDR2 CMT TIMER MCSR CMT TIMER CHR1 CMT TIMERCLR1 CMT TIMER CHR2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED UNUSED UNUSED ...... Freescale Semiconductor Freescale $3FFB $0A $3FFF $3FFE $3FFD $3FFC $15 $09 $08 $07 $06 $05 $04 $03 $02 $01 $00 $1F $18 $17 $3FF0 $3FF8 $13 $16 $1E $0F $3FFA $3FF6 $11 $10 $14 $12 $3FF9 $3FF7 $3FF5 ...... — Rev. 2.1

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Rev. 2.1 HC05RC18GRS/D 08/2005