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Computer Architecture 1DT016: About Microcode with Examples About µCode Examples: 8-bit vN CPU Computer Architecture 1DT016 distance Fall 2017 http://xyx.se/1DT016/index.php Per Foyer Mail: [email protected] [email protected] 20172017 1 Microcoded Control Units In assignment 4 you will design your own 8-bit microcoded von Neumann CPU in LogiSim -Hey, I can’t do that!? -Yes you can! -No, it must be too complicated! -Absolutely not. It’s easier than you think! -Ok…(?) [email protected] 2017 2 Control Unit: Execution states Look at the control unit as a sequencer generating control signals for: -Realizing the ISA -Controling the data flow within the CPU Almost like a self-playing piano - What is to be done in each state? - Do we need more states? [email protected] 2017 3 CPU components [email protected] 2017 4 CPU: Registers (High level) • This is registers that are available to the user as part of the ISA • General purpose (GP) registers can consist of descrete (separate individual) registers or of a register bank. • Status registers typically contain flags that are set depending of results after ALU instructions (Z, N, C, …) [email protected] 2017 5 CPU Assembly (user) level • A user doesn’t know anything about whether a CPU is microcoded or not. • What is available to a user is, simply put, a set of machine code instructions together with a set of registers to work with. • The instructions can have different formats and addressing modes [email protected] 2017 6 CPU: Registers (low level) - Not visible to the user (ISA) - Do we need more registers? The memory data register (MDR), the memory address register (MAR) and the I/O control register are the buffer registers closest to the outside world - the data, address and control buses. [email protected] 2017 7 CPU: External interface signals • The clock is, for example, used for clocking the control unit • MREQ (memory request), RD (read) and WR (write) are interface signals to memory and memory mapped I/O • You can of course name the signals to anything you want [email protected] 2017 8 CPU: ALU Status is fed, or taken from, the status register. If the result of an ALU operation is zero the Z-flag is set, if negative the N flag and so forth. [email protected] 2017 9 µControl Unit: Horizontal µ-code Note: This is only an example showing the fundamental principles • Maximum parallelism, given the number of bits from the µROM • Many control lines make it easier to modify the ISA • µROM acts as a sequencer of arbitrary control signals • Easily expanded by adding parallel ROMs • Large ROMs costs expensive silicon die space • Sometimes called Wide µ-code [email protected] 2017 10 µControl Unit: Vertical µ-code Note: This is only an example showing the fundamental principles • Must carefully group signals together so partial parallelism can be guaranteed • Uses less high speed ROM which frees upp space on silicon die • Less flexibility to enhance the ISA • Sometimes called narrow µ-code [email protected] 2017 11 µControl Unit with Lookup table Note: This is only an example showing the fundamental principles • The machine instruction in IR is an index to the Lookup ROM • The value in the Lookup ROM is the start address (set in µPC) for the µ-code corresponding to the machine code in IR [email protected] 2017 12 CPU: microCoded Control Unit [email protected] 2017 13 Sketch: 8-bit vN CPU: Overview [email protected] 2017 14 Sketch: 8-bit vN CPU: Registers This is just an example. You can choose any number of registers and configurations. You are the designer! [email protected] 2017 15 Sketch: 8-bit vN CPU: Buses The external buses have to be Tri-state. High (ones), low (zeroes) or high impedance (”don’t care”, Hi-Z). The latter important so the CPU don’t interfere with other things that are connected to the buses. [email protected] 2017 16 Sketch: 8-bit vN CPU: ISA modes If variable format instructions are used, the first byte may be used as opcode followed by instruction parameters [email protected] 2017 17 Sketch: 8-bit vN CPU: Control Unit Gives an average of 4 micro instructions per Assembly instruction [email protected] 2017 18 Sketch: 8-bit vN CPU: PM This is just an example of a possible memory configuration. Remember that the CPU is to follow the von Neumann architecture which means that program and data can reside anywhere in the ROM: same memory map. •Interrupt and Trap vectors - Easiest to implement as jump instructions to absolute addresses •Resident (non volatile) program and data RAM: Program and Data (Volatile) Unused memory space: Can be used for memory mapped I/O Endian order? Big or Little? (actually doesn’t matter but needs to be decided) [email protected] 2017 19 Sketch: 8-bit vN CPU: ROM Memory Bank 0 0x0000 JMP RESET H …if big endian order L 0x0003 JMP TRAP No need for byte H aligning addresses L - Why? 0x0006 JMP INT H L TRAP can be used for ”software emergencies”, … such when trying to execute an illegal (undefined) 0x1FFF instruction [email protected] 2017 20 Sketch: 8-bit vN CPU: RAM Bank 0 (ROM) 0x2000 … Bank 1 0x3FFF 0x4000 … Bank 2 0x5FFF 0x6000 … Bank 3 0x7FFF 0x8000 … Bank 4 0x9FFF [email protected] 2017 21 Sketch: 8-bit vN CPU: PM: Bank Select Can be used for memory mapped I/O [email protected] 2017 22 Sketch: 8-bit vN CPU: The ISA One way to develop a simple processor ISA is to invent it as one go along writing an initial assembler program. Remember that we are the CPU designers who are free to design an 8-bit processor any way we want! In the hardware world, the equivalent to a ”Hello world” program is to blink a LED to see that a machine code program really can do something. [email protected] 2017 23 Sketch: 8-bit vN CPU: ”Hello world” hardware Remember that the buses ”have no memory” in themself. Therefore we need a latch to store the LED-bit. [email protected] 2017 24 Sketch: 8-bit vN CPU: ISA design Lets say that the following registers will be used in the CPU ISA design. These registers are visible to the user. A and B: 8-bit general purpose (GP) registers I and X: 8-bit registers that can either be used as general purpose registers or combined as a 16-bit index register IX PC: 16-bit program counter F: 8-bit flag register. Stores result bits from ALU operations: Z(ero), N(egative), P(ositive), C(arry) etc. Now mnemonics have to be invented for use in assembler programs. Keep it simple. As the CPU is microcoded, more instructions can be added later without re-designing the hardware. [email protected] 2017 25 Sketch: 8-bit vN CPU: We have no assembler, so the translation from mnemonics to machine code must be done by hand. Decision: Let the CPU work in big endian order Now let’s start creating the program that will blink the LED. Mnemonics and machine code operations are invented and defined as we go along, just as the CPU already existed! [email protected] 2017 26 Sketch: 8-bit vN CPU: Blink LED (1) We need assembly language instructions for writing a program. For now it’s enough to define only 12 machine code instructions. Later we will probably need more CPU registers and instructions. [email protected] 2017 27 Sketch: 8-bit vN CPU: Blink LED (2) First define the trap and interrupt table in our own assembly language [email protected] 2017 28 Sketch: 8-bit vN CPU: Blink LED (3) Only one byte needs to be allocated in RAM for storing LED data [email protected] 2017 29 Sketch: 8-bit vN CPU: Blink LED (4) The program LED-blinking program itself [email protected] 2017 30 Sketch: 8-bit vN CPU: Blink LED (5) Traps and interrupt are probably not designed yet so program execution will then never get here. But it looks good [email protected] 2017 31 Sketch: 8-bit vN CPU: Blink LED (6) Opcodes were defined on a previous slide. It doesn’t matter in what order they are defined. The only thing that is important is that individual instructions have unique opcodes so there will be a one-to-one mapping between opcodes and instructions (mnemonics). Later in the design work, the assembly language opcodes will be used as indexes to the microcode jump table ROM, which in turn will contain indexes to the microcode program ROM inside the control unit like e.g.: Op (8-bit opcode) index to JT ROM (10-bit) address to microcode ROM that contain (16-bit or so) wide microcode words – the actual dimensions are entirely up to the designer! Time to assemble the LED-blinking program into machine code. [email protected] 2017 32 Sketch: 8-bit vN CPU: Blink LED (7) Only 9 bytes of memory necessary for the trap/interrupt vector table… [email protected] 2017 33 Sketch: 8-bit vN CPU: Blink LED (8) …and only 1 byte of RAM for reading and writing temporary data… [email protected] 2017 34 Sketch: 8-bit vN CPU: Blink LED (9) …and 21 bytes of memory for the main program… [email protected] 2017 35 Sketch: 8-bit vN CPU: Blink LED (10) …and finally 6 bytes of memory for the trap/interrupt routines This makes a grand total of a only 37 bytes for everything! Wow! [email protected] 2017 36 Sketch: 8-bit vN CPU: Opcodes As we have seen, our instructions have already a number of properties: •Variable length (1 to 3 bytes) •Different addressing modes: This far: • Jump absolute (3bytes) • Jump absolute on condition (3 bytes) • Register load immediate (2 bytes) • Register load register indirect (1 byte) • Register store register indirect (1 byte) • Register store to absolute address (3 bytes) • ALUop immediate (2 bytes) The first byte in a machine code instruction - the opcode - will be fed as an index to the microcode jump table ROM which points to the corresponding microcode.
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