DOCSLIB.ORG

An Overview of Compilation and GCC

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
An Overview of Compilation and GCC Workshop on Essential Abstractions in GCC An Overview of Compilation and GCC GCC Resource Center (www.cse.iitb.ac.in/grc) Department of Computer Science and Engineering, Indian Institute of Technology, Bombay 29 June 2013 29 June 2013 Overview: Outline 1/42 Outline • Introduction to Compilation • An Overview of Compilation Phases • An Overview of GCC Essential Abstractions in GCC GCC Resource Center, IIT Bombay Part 1 Introduction to Compilation 29 June 2013 Overview: Introduction to Compilation 2/42 Implementation Mechanisms Source Program Translator Target Program Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 2/42 Implementation Mechanisms Source Program Input Data Translator Target Program Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 2/42 Implementation Mechanisms Source Program Source Program Input Data Translator Interpreter Target Program Machine Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 3/42 Implementation Mechanisms as “Bridges” • “Gap” between the “levels” of program specification and execution Program Specification Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 3/42 Implementation Mechanisms as “Bridges” • “Gap” between the “levels” of program specification and execution Program Specification Translation Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 3/42 Implementation Mechanisms as “Bridges” • “Gap” between the “levels” of program specification and execution Program Specification Translation Interpretation Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 3/42 Implementation Mechanisms as “Bridges” • “Gap” between the “levels” of program specification and execution State : Variables Program Specification Operations: Expressions, Control Flow Translation Interpretation State : Memory, Registers Machine Operations: Machine Instructions Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 4/42 High and Low Level Abstractions Input C statement a = b<10?b:c; Spim Assembly Equivalent lw $t0,4($fp) ; t0<-b # Is b smaller slti $t0, $t0, 10 ; t0 <- t0 < 10 # than 10? not $t0,$t0 ; t0<-!t0 bgtz $t0, L0: ; if t0>0 goto L0 lw $t0,4($fp) ; t0<-b # YES b L1: ; gotoL1 L0: lw $t0, 8($fp) ;L0: t0 <- c # NO L1: sw 0($fp), $t0 ;L1: a <- t0 Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 5/42 Implementation Mechanisms • Translation = Analysis + Synthesis Interpretation = Analysis + Execution Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 5/42 Implementation Mechanisms • Translation = Analysis + Synthesis Interpretation = Analysis + Execution Equivalent • Translation Instructions Instructions Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 5/42 Implementation Mechanisms • Translation = Analysis + Synthesis Interpretation = Analysis + Execution Equivalent • Translation Instructions Instructions Actions Implied Interpretation Instructions by Instructions Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 6/42 Language Implementation Models Synthesis Compilation Analysis Execution Interpretation Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: Introduction to Compilation 7/42 Language Processor Models Back End C,C++ Front Optimizer End Virtual Java, C# Machine Essential Abstractions in GCC GCC Resource Center, IIT Bombay Part 2 An Overview of Compilation Phases 29 June 2013 Overview: An Overview of Compilation Phases 8/42 The Structure of a Simple Compiler Parser Semantic Symtab Scanner Analyser Handler Source Program Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 8/42 The Structure of a Simple Compiler Instruction Assembly Parser AST Selector Insn Emitter Assembly Semantic Symtab Register Program Scanner Analyser Handler Allocator Source Program Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 8/42 The Structure of a Simple Compiler FrontEnd BackEnd Instruction Assembly Parser AST Selector Insn Emitter Assembly Semantic Symtab Register Program Scanner Analyser Handler Allocator Source Program Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 9/42 Translation Sequence in Our Compiler: Parsing a=b<10?b:c; Input Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 9/42 Translation Sequence in Our Compiler: Parsing a=b<10?b:c; AsgnStmnt Input ; Lhs = E name E ? E : E E < E name name name num Parse Tree Issues: • Grammar rules, terminals, non-terminals • Order of application of grammar rules eg. is it (a = b<10?) followed by (b:c)? • Values of terminal symbols eg. string “10” vs. integer number 10. Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 10/42 Translation Sequence in Our Compiler: Semantic Analysis a=b<10?b:c; AsgnStmnt Input ; Lhs = E name E ? E : E E < E name name name num Parse Tree Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 10/42 Translation Sequence in Our Compiler: Semantic Analysis a=b<10?b:c; AsgnStmnt = Input name ; ?: (int) Lhs = E (a,int) < name E E : E name name ? (bool) (b,int) (c,int) E < E name name name num name num (b,int) (10,int) Parse Tree Abstract Syntax Tree (with attributes) Issues: • Symbol tables Have variables been declared? What are their types? What is their scope? • Type consistency of operators and operands The result of computing b<10? is bool and not int Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 11/42 Translation Sequence in Our Compiler: IR Generation a=b<10?b:c; AsgnStmnt = Input name ; ?: (int) Lhs = E (a,int) < name E E : E name name ? (bool) (b,int) (c,int) E < E name name name num name num (b,int) (10,int) Parse Tree Abstract Syntax Tree (with attributes) Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 11/42 Translation Sequence in Our Compiler: IR Generation a=b<10?b:c; AsgnStmnt = Input name ; (a,int) ?: (int) Tree List Lhs = E = < name E E : E name name ? (bool) (b,int) (c,int) T0 Not < E < E name name name num 10 b name num (b,int) (10,int) IfGoto Parse Tree Abstract Syntax Tree (with attributes) T0 L0: = Issues: T1 b • Convert to maximal trees which can be Goto implemented without altering control flow L1: Simplifies instruction selection and scheduling, L0: = register allocation etc. T1 c L1: = • Linearise control flow by flattening nested a T1 control constructs Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 12/42 Translation Sequence in Our Compiler: Instruction Selection a=b<10?b:c; AsgnStmnt = Input name ; (a,int) ?: (int) Tree List Lhs = E = < name E E : E name name ? (bool) (b,int) (c,int) T0 Not < E < E name name name num 10 b name num (b,int) (10,int) IfGoto Parse Tree Abstract Syntax Tree (with attributes) T0 L0: = T1 b Goto L1: L0: = T1 c L1: = a T1 Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 12/42 Translation Sequence in Our Compiler: Instruction Selection a=b<10?b:c; AsgnStmnt = Input name ; (a,int) ?: (int) Tree List Lhs = E = < name E E : E name name ? (bool) (b,int) (c,int) T0 Not < E < E name name name num 10 b name num (b,int) (10,int) IfGoto Parse Tree Abstract Syntax Tree (with attributes) T0 L0: = Instruction List Issues: ← T1 b T0 b • Cover trees with as few T ← T < 10 Goto 0 0 machine instructions as T0 ← ! T0 L1: possible if T0 > 0 goto L0: L0: = ← T1 b • Use temporaries and local T c 1 goto L1: registers L1: = L0: T1 ← c ← a T1 L1: a T1 Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 12/42 Translation Sequence in Our Compiler: Instruction Selection a=b<10?b:c; AsgnStmnt = Input name ; (a,int) ?: (int) Tree List Lhs = E = < name E E : E name name ? (bool) (b,int) (c,int) T0 Not < E < E name name name num 10 b name num (b,int) (10,int) IfGoto Parse Tree Abstract Syntax Tree (with attributes) T0 L0: = Instruction List Issues: ← T1 b T0 b • Cover trees with as few T ← T < 10 Goto 0 0 machine instructions as T0 ← ! T0 L1: possible if T0 > 0 goto L0: L0: = ← T1 b • Use temporaries and local T c 1 goto L1: registers L1: = L0: T1 ← c ← a T1 L1: a T1 Essential Abstractions in GCC GCC Resource Center, IIT Bombay 29 June 2013 Overview: An Overview of Compilation Phases 13/42 Translation Sequence in Our Compiler: Emitting Instructions a=b<10?b:c; AsgnStmnt = Input name ; (a,int) ?: (int) Tree List Lhs = E = < name E E : E name name ? (bool) (b,int) (c,int) T0 Not < E < E name name name num 10 b name num (b,int) (10,int)
Load more

Recommended publications
  • Comparison of Contemporary Real Time Operating Systems
    ISSN (Online) 2278-1021 IJARCCE ISSN (Print) 2319 5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 4, Issue 11, November 2015 Comparison of Contemporary Real Time Operating Systems Mr. Sagar Jape1, Mr. Mihir Kulkarni2, Prof.Dipti Pawade3 Student, Bachelors of Engineering, Department of Information Technology, K J Somaiya College of Engineering, Mumbai1,2 Assistant Professor, Department of Information Technology, K J Somaiya College of Engineering, Mumbai3 Abstract: With the advancement in embedded area, importance of real time operating system (RTOS) has been increased to greater extent. Now days for every embedded application low latency, efficient memory utilization and effective scheduling techniques are the basic requirements. Thus in this paper we have attempted to compare some of the real time operating systems. The systems (viz. VxWorks, QNX, Ecos, RTLinux, Windows CE and FreeRTOS) have been selected according to the highest user base criterion. We enlist the peculiar features of the systems with respect to the parameters like scheduling policies, licensing, memory management techniques, etc. and further, compare the selected systems over these parameters. Our effort to formulate the often confused, complex and contradictory pieces of information on contemporary RTOSs into simple, analytical organized structure will provide decisive insights to the reader on the selection process of an RTOS as per his requirements. Keywords:RTOS, VxWorks, QNX, eCOS, RTLinux,Windows CE, FreeRTOS I. INTRODUCTION An operating system (OS) is a set of software that handles designed known as Real Time Operating System (RTOS). computer hardware. Basically it acts as an interface The motive behind RTOS development is to process data between user program and computer hardware.
    [Show full text]
  • Historical Perspective and Further Reading 162.E1
    2.21 Historical Perspective and Further Reading 162.e1 2.21 Historical Perspective and Further Reading Th is section surveys the history of in struction set architectures over time, and we give a short history of programming languages and compilers. ISAs include accumulator architectures, general-purpose register architectures, stack architectures, and a brief history of ARMv7 and the x86. We also review the controversial subjects of high-level-language computer architectures and reduced instruction set computer architectures. Th e history of programming languages includes Fortran, Lisp, Algol, C, Cobol, Pascal, Simula, Smalltalk, C+ + , and Java, and the history of compilers includes the key milestones and the pioneers who achieved them. Accumulator Architectures Hardware was precious in the earliest stored-program computers. Consequently, computer pioneers could not aff ord the number of registers found in today’s architectures. In fact, these architectures had a single register for arithmetic instructions. Since all operations would accumulate in one register, it was called the accumulator , and this style of instruction set is given the same name. For example, accumulator Archaic EDSAC in 1949 had a single accumulator. term for register. On-line Th e three-operand format of RISC-V suggests that a single register is at least two use of it as a synonym for registers shy of our needs. Having the accumulator as both a source operand and “register” is a fairly reliable indication that the user the destination of the operation fi lls part of the shortfall, but it still leaves us one has been around quite a operand short. Th at fi nal operand is found in memory.
    [Show full text]
  • Motorola 68000 Opcodes
    Motorola 68000 CPU Opcodes Mnemonic Size Single Effective Address Operation Word Data Mnemonic Size Single Effective Address Operation Word Data Addressing Mode Format M Xn ORI to CCR B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 B I RTE 0 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 Data register Dn 0 0 0 reg ORI to SR W 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 W I RTS 0 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 Address register An 0 0 1 reg ORI B W L 0 0 0 0 0 0 0 0 S M Xn I TRAPV 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 0 Address (An) 0 1 0 reg ANDI to CCR B 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 B I RTR 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 Address with Postincrement (An)+ 0 1 1 reg ANDI to SR W 0 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 W I JSR 0 1 0 0 1 1 1 0 1 0 M Xn Address with Predecrement -(An) 1 0 0 reg ANDI B W L 0 0 0 0 0 0 1 0 S M Xn I JMP 0 1 0 0 1 1 1 0 1 1 M Xn Address with Displacement (d16, An) 1 0 1 reg SUBI B W L 0 0 0 0 0 1 0 0 S M Xn I MOVEM W L 0 1 0 0 1 D 0 0 1 S M Xn W M Address with Index (d8, An, Xn) 1 1 0 reg ADDI B W L 0 0 0 0 0 1 1 0 S M Xn I LEA L 0 1 0 0 An 1 1 1 M Xn Program Counter with Displacement (d16, PC) 1 1 1 0 1 0 EORI to CCR B 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 B I CHK W 0 1 0 0 Dn 1 1 0 M Xn Program Counter with Index (d8, PC, Xn) 1 1 1 0 1 1 EORI to SR W 0 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 W I ADDQ B W L 0 1 0 1 Data 0 S M Xn Absolute Short (xxx).W 1 1 1 0 0 0 EORI B W L 0 0 0 0 1 0 1 0 S M Xn I SUBQ B W L 0 1 0 1 Data 1 S M Xn Absolute Long (xxx).L 1 1 1 0 0 1 CMPI B W L 0 0 0 0 1 1 0 0 S M Xn I Scc B 0 1 0 1 Condition 1 1 M Xn Immediate #imm 1 1 1 1 0 0 BTST B L 0 0 0 0 1 0 0
    [Show full text]
  • Computer Architectures
    Computer Architectures Motorola 68000, 683xx a ColdFire – CISC CPU Principles Demonstrated Czech Technical University in Prague, Faculty of Electrical Engineering AE0B36APO Computer Architectures Ver.1.10 1 Original Desktop/Workstation 680X0 Feature 68000 'EC000 68010 68020 68030 68040 68060 Data bus 16 8/16 16 8/16/32 8/16/32 32 32 Addr bus 23 23 23 32 32 32 32 Misaligned Addr - - - Yes Yes Yes Yes Virtual memory - - Yes Yes Yes Yes Yes Instruct Cache - - 3 256 256 4096 8192 Data Cache - - - - 256 4096 8192 Memory manager 68451 or 68851 68851 Yes Yes Yes ATC entries - - - - 22 64/64 64/64 FPU interface - - - 68881 or 68882 Internal FPU built-in FPU - - - - - Yes Yes Burst Memory - - - - Yes Yes Yes Bus Cycle type asynchronous both synchronous Data Bus Sizing - - - Yes Yes use 68150 Power (watts) 1.2 0.13-0.26 0.13 1.75 2.6 4-6 3.9-4.9 at frequency of 8.0 8-16 8 16-25 16-50 25-40 50-66 MIPS/kDhryst. 1.2/2.1 2.5/4.3 6.5/11 14/23 35/60 100/300 Transistors 68k 84k 190k 273k 1,170k 2,500k Introduction 1979 1982 1984 1987 1991 1994 AE0B36APO Computer Architectures 2 M68xxx/CPU32/ColdFire – Basic Registers Set 31 16 15 8 7 0 User programming D0 D1 model registers D2 D3 DATA REGISTERS D4 D5 D6 D7 16 15 0 A0 A1 A2 A3 ADDRESS REGISTERS A4 A5 A6 16 15 0 A7 (USP) USER STACK POINTER 0 PC PROGRAM COUNTER 15 8 7 0 0 CCR CONDITION CODE REGISTER 31 16 15 0 A7# (SSP) SUPERVISOR STACK Supervisor/system POINTER 15 8 7 0 programing model (CCR) SR STATUS REGISTER 31 0 basic registers VBR VECTOR BASE REGISTER 31 3 2 0 SFC ALTERNATE FUNCTION DFC CODE REGISTERS AE0B36APO Computer Architectures 3 Status Register – Conditional Code Part USER BYTE SYSTEM BYTE (CONDITION CODE REGISTER) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1 T0 S 0 0 I2 I1 I0 0 0 0 X N Z V C TRACE INTERRUPT EXTEND ENABLE PRIORITY MASK NEGATIVE SUPERVISOR/USER ZERO STATE OVERFLOW CARRY ● N – negative ..
    [Show full text]
  • RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (Built 15Th February 2018)
    RTEMS CPU Supplement Documentation Release 4.11.3 ©Copyright 2016, RTEMS Project (built 15th February 2018) CONTENTS I RTEMS CPU Architecture Supplement1 1 Preface 5 2 Port Specific Information7 2.1 CPU Model Dependent Features...........................8 2.1.1 CPU Model Name...............................8 2.1.2 Floating Point Unit..............................8 2.2 Multilibs........................................9 2.3 Calling Conventions.................................. 10 2.3.1 Calling Mechanism.............................. 10 2.3.2 Register Usage................................. 10 2.3.3 Parameter Passing............................... 10 2.3.4 User-Provided Routines............................ 10 2.4 Memory Model..................................... 11 2.4.1 Flat Memory Model.............................. 11 2.5 Interrupt Processing.................................. 12 2.5.1 Vectoring of an Interrupt Handler...................... 12 2.5.2 Interrupt Levels................................ 12 2.5.3 Disabling of Interrupts by RTEMS...................... 12 2.6 Default Fatal Error Processing............................. 14 2.7 Symmetric Multiprocessing.............................. 15 2.8 Thread-Local Storage................................. 16 2.9 CPU counter...................................... 17 2.10 Interrupt Profiling................................... 18 2.11 Board Support Packages................................ 19 2.11.1 System Reset................................. 19 3 ARM Specific Information 21 3.1 CPU Model Dependent Features..........................
    [Show full text]
  • Software De Sistemas Introduccion
    SOFTWARE DE SISTEMAS INTRODUCCION • EL CONCEPTO DE SOFTWARE VA MAS ALLA DE LOS PROGRAMAS DE COMPUTACION EN SUS DISTINTOS ESTADOS QUE ABARCA TODO LO INTANGIBLE RELACIONADO Algodesl.wordpress.com t i ¿QUE ES? p o s d e s o f t w a r e . c o m • Parte esencial para clasificar sistemas operativos • Conocido como software base • Conjunto de programas de software que permite interactuar con el hardware y operarlo junto con configuraciones y funciones de entrada y salida ¿Que hace? • Permite utilizar sistema operativo e informático, incluyendo herramientas de diagnostico • Su propósito es aislar un programa o hardware de aplicaciones tanto como sea posible proyectoova.webcindario.com Ejemplos de programas de software de sistema a d • Potenciales ejemplos: r ia n ▪ cargadores a l is s e ▪ Enlazadores t .b lo ▪ Utilidad de software g s p o ▪ Interfaz grafica t ▪ Celdas ▪ Bios ▪ Hipervisores ▪ Gestores de arranque losejemplos.com *si el software del sistema se almacena en memoria volátil se denomina firware Tipos • Como tal no existen varios tipos de software de sistema pero se pueden dividir en 3; O k • Sistema operativo h o s • t Controladores i n g • . Programas de utilería c o m Tipos; SISTEMA OPERATIVO • Parte que se encarga de administración de hardware como los componentes de computadora y encargado de que todos se unan para funcionar en 1 solo objetivo m i n d 4 2 . c o m SISTEMAS OPERATIVOS • MICROSOFT WINDOWS ▪ Núcleo: monolítico (versiones basadas en MS­DOS) e hibrido (versiones basadas en Windows NT) ▪ Plataformas: ARM, arquitectura Intel, MIPS, Alpha, Power PC SISTEMAS OPERATIVOS • MAC OS ▪ Núcleo: XNU basado en mach y BSD, es tipo hibrido ▪ Plataformas; power PC SISTEMAS OPERATIVOS • LINUX: ▪ Núcleo: núcleo Linux ▪ Plataformas; DEC Alpha, ARM, POWER PC, superH, SPARC, ETRAX CRIS, MIPS, MN103… etc.
    [Show full text]
  • Designing PCI Cards and Drivers for Power Macintosh Computers
    Designing PCI Cards and Drivers for Power Macintosh Computers Revised Edition Revised 3/26/99 Technical Publications © Apple Computer, Inc. 1999 Apple Computer, Inc. Adobe, Acrobat, and PostScript are Even though Apple has reviewed this © 1995, 1996 , 1999 Apple Computer, trademarks of Adobe Systems manual, APPLE MAKES NO Inc. All rights reserved. Incorporated or its subsidiaries and WARRANTY OR REPRESENTATION, EITHER EXPRESS OR IMPLIED, WITH No part of this publication may be may be registered in certain RESPECT TO THIS MANUAL, ITS reproduced, stored in a retrieval jurisdictions. QUALITY, ACCURACY, system, or transmitted, in any form America Online is a service mark of MERCHANTABILITY, OR FITNESS or by any means, mechanical, Quantum Computer Services, Inc. FOR A PARTICULAR PURPOSE. AS A electronic, photocopying, recording, Code Warrior is a trademark of RESULT, THIS MANUAL IS SOLD “AS or otherwise, without prior written Metrowerks. IS,” AND YOU, THE PURCHASER, ARE permission of Apple Computer, Inc., CompuServe is a registered ASSUMING THE ENTIRE RISK AS TO except to make a backup copy of any trademark of CompuServe, Inc. ITS QUALITY AND ACCURACY. documentation provided on Ethernet is a registered trademark of CD-ROM. IN NO EVENT WILL APPLE BE LIABLE Xerox Corporation. The Apple logo is a trademark of FOR DIRECT, INDIRECT, SPECIAL, FrameMaker is a registered Apple Computer, Inc. INCIDENTAL, OR CONSEQUENTIAL trademark of Frame Technology Use of the “keyboard” Apple logo DAMAGES RESULTING FROM ANY Corporation. (Option-Shift-K) for commercial DEFECT OR INACCURACY IN THIS purposes without the prior written Helvetica and Palatino are registered MANUAL, even if advised of the consent of Apple may constitute trademarks of Linotype-Hell AG possibility of such damages.
    [Show full text]
  • Pwny Documentation Release 0.9.0
    pwny Documentation Release 0.9.0 Author Nov 19, 2017 Contents 1 pwny package 3 2 pwnypack package 5 2.1 asm – (Dis)assembler..........................................5 2.2 bytecode – Python bytecode manipulation..............................7 2.3 codec – Data transformation...................................... 11 2.4 elf – ELF file parsing.......................................... 16 2.5 flow – Communication......................................... 36 2.6 fmtstring – Format strings...................................... 41 2.7 marshal – Python marshal loader................................... 42 2.8 oracle – Padding oracle attacks.................................... 43 2.9 packing – Data (un)packing...................................... 44 2.10 php – PHP related functions....................................... 46 2.11 pickle – Pickle tools.......................................... 47 2.12 py_internals – Python internals.................................. 49 2.13 rop – ROP gadgets........................................... 50 2.14 shellcode – Shellcode generator................................... 50 2.15 target – Target definition....................................... 79 2.16 util – Utility functions......................................... 80 3 Indices and tables 83 Python Module Index 85 i ii pwny Documentation, Release 0.9.0 pwnypack is the official CTF toolkit of Certified Edible Dinosaurs. It aims to provide a set of command line utilities and a python library that are useful when playing hacking CTFs. The core functionality of pwnypack
    [Show full text]
  • The Mc68020 32-Bit Microprocessor by Paul F
    NEW C HIPS THE MC68020 32-BIT MICROPROCESSOR BY PAUL F. GROEPLER AND JAMES KENNEDY The latest member of Motorola's 68000 family includes on-board cache and virtual memory THE MC68020, the newest addition to the chip managers. They control inter- ate control for the micromachine. the Motorola M68000 family of micro- nal buses, registers, and the execution The instruction prefetch and decode processors, is a full 32-bit processor unit. unit fetches and decodes an instruc- with separate 32-bit data and address The execution unit contains the pro- tion for execution by the execution buses, an on-board instruction cache, gram counter (PC), the address, and unit. The prefetch is a three-word- dynamic bus sizing, and a coproces- the data . The PC section calculates in- deep on-chip instruction store. It elim- sor interface. It is object-code com- struction addresses and manages inates the need for the processor to patible with the earlier members of pointers. The address section calcu- sequentially fetch an instruction from the M68000 family but has new ad- lates operand addresses and stores external memory, decode and ex- dressing modes in support of high- the registers available to the user. The ecute it, and fetch another. level languages. data section performs all data opera- Instead, because of the sequential The MC68020 is an HCMOS (high- tions, such as immediate data value nature of instruction accesses, the speed complementary metal-oxide moves . It also contains the barrel prefetch can anticipate the next ac- semiconductor) microprocessor with shifter, which performs one-cycle cess and make it before it is needed.
    [Show full text]
  • Improving Performance of Virtual Machines by Virtio Bridge Bypass
    www.ijecs.in International Journal Of Engineering And Computer Science ISSN:2319-7242 Volume 6 Issue 4 April 2017, Page No. 20931-20937 Index Copernicus value (2015): 58.10 DOI: 10.18535/ijecs/v6i4.24 Improving performance of Virtual Machines by Virtio bridge Bypass for PCI devices 1Shirley Kotian, 2Kirti Menon, 3Kirti Menon, 4Utsav Mundada, 5Neeraj Vilas Auti 1234PICT, 5PICT [CS] ABSTRACT Inspired by the Virtio module of virtualization, we propose an alternate method to directly communicate with PCI devices such as NIC without the use of any kernel modules. This method uses a specialized module written by us which will avoid the mechanism of bridges like the ones used in Virtio that increase latency. This module will be present in the userspace of the guest OS and we are specifically targeting the e1000 device for this purpose and later plan to make it generic for all PCI devices. Our motivation is to avoid unnecessary communication with the kernel which slows down the system. For the first step. we do resource mapping to map the PCI device memory into userspace. Then, we expose PCI configuration space through a userspace module using ACPI cables. Thus, we create a userspace PCI driver which will decrease the latency in access time and increase speed of execution. The applications in the Guest OS that request communication with the PCI devices will be redirected to our application. This will take some load off the kernel and reduce its overhead. Finally, we boot a VM that actually talks to our PCI device emulator. GENERAL TERMS Virtio, UPCI, e1000, QEMU, virt-manager, UIO.
    [Show full text]
  • Virtualization for Embedded Software
    JETS VIRTUALIZATION FOR EMBEDDED SOFTWARE Seasoned aerospace organizations have already weathered the VIRTUALIZATION WITH JETS: change from bespoke systems and proprietary languages to COTS A KEY ENABLER OF DEVOPS TRANSFORMATION and open-source, as well as paradigm shifts from high-overhead FOR AEROSPACE AND DEFENSE waterfall and spiral development models to lightweight and agile methodologies and are considering moving to scalable agile Like all companies in the technology industry, aerospace and defense methods. As with previous seismic shifts in the industry, most suppliers are facing increased pressure to reduce cost and increase defense and aerospace firms will have to follow, especially as best-of- productivity, while meeting their market’s demand for higher breed tools, talent and processes are all refactored to take advantage overall quality and rapid adoption of new platforms, development of DevOps’ unique productivity and quality improvements. DevOps paradigms and user experiences. is a collective term for a range of modern development practices that combines loosely-coupled architectures and process automation In recent years, the rapid pace of innovation for consumer tech, with changes to the structure of development, IT and product teams. together with a new generation of ‘digital native’ users that demand Adoption of DevOps (See Figure 1). more capability than previous generations, has left many in the industry playing constant catch-up. Adoption of DevOps includes a shift from long, structured release cycles to continuous delivery, and relies on heavy use of automation to improve productivity and quality. This can be complicated by The commercial software world is shifting again, several factors common to the defense and aerospace industry.
    [Show full text]
  • Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
    Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy
    [Show full text]