Resistive Switching in Core-Shell Nanowires for Applications in Neuromorphic Architectures

RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES FOR APPLICATIONS IN NEUROMORPHIC ARCHITECTURES

SHANGRADHANVA ESWARA VASISTH

A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

UNIVERSITY OF FLORIDA

2021

To family and friends

ACKNOWLEDGMENTS

Primarily, I would like to express my sincerest gratitude towards my graduate advisor, Dr. Juan C. Nino. With his understanding, guidance, and constant support, I have been able to complete this work and earn my degree. High standards in safety and work set by him has made me a better academic scholar and researcher. Leading by example, the work ethic he has instilled in me will stay the course of my life. I would also like to thank Dr. Anthony Brennan, Dr. Christopher Batich, Dr. Brent Gila, and Dr. David

Mazyck, for being on my adivisory committee and providing me their time and advice.

At the Nino Research Group, I have been glad to have worked and interacted with some of the smartest, kind, and diverse group of people. I would like to thank all the past and present members of the group for their support and help when I needed it. I would like to specially thank Dr. Hiraku Maruyama for constantly motivating me to work, Amalie

Atassi and Marshall Frye for taking the initiative to help complete the work on functionalized nanocellulose, Marc Martorell for helping me build the setup for noise amplification, and Mustafa Siddiqi for the many hours he has spent in sample preparation.

I would also like to thank Andres Trucco and other engineers at the Nanoscale

Research Facility at the University of Florida for their assistance with e-beam lithography and overall guidance towards the fabrication of the core-shell nanowires.

I would like to thank my family the most as they have played a significant role in making me the person I am today. Finally, I would like to thank my roommates (past and present) and friends who are in different parts of the world, for beilieving in me and helping me unwind.

A part of this dissertation is based upon work supported by the National Science

Foundation Grant No. ECCS-1709641. Any opinions, findings, conclusions, or

recommendations expressed in this publication are those of the author and do not necessarily reflect the views of the National Science Foundation.

TABLE OF CONTENTS

page

ACKNOWLEDGMENTS ...... 4

LIST OF TABLES ...... 9

LIST OF FIGURES ...... 10

LIST OF ABBREVIATIONS ...... 14

ABSTRACT ...... 16

CHAPTER

1 INTRODUCTION ...... 20

1.1. Statement of Problem and Motivation ...... 20 1.2. Scientific Approach ...... 22 1.3. Organization of Dissertation ...... 24 1.4. Contributions to the Field ...... 25

2 BACKGROUND ...... 27

2.1. Memristive or Resistive Switching...... 27 2.1.1. Types of Resistive Switching ...... 30 2.2.2. Mechanisms of Resistive Switching in Metal Oxides ...... 32 2.2. Resistive Switching in HfO2...... 35 2.3. Charge Transport Mechanisms ...... 40 2.4. Organic and Inorganic Synapses ...... 43 2.5. Noise in Networks ...... 47 2.6. Impedance Spectroscopy ...... 50

3 EXPERIMENTAL PROCEDURES AND TECHNIQUES ...... 54

3.1 Fabrication Techniques ...... 54 3.1.1. Lithography ...... 54 3.1.1.1. Resist coat (spinners) ...... 55 3.1.1.2. Bake ...... 56 3.1.1.3. Exposure by e-beam ...... 56 3.1.1.4. Development ...... 58 3.1.2. Deposition Techniques ...... 58 3.1.2.1. Sputter deposition ...... 58 3.1.2.2. Atomic layer deposition (ALD) ...... 59 3.1.3. Other Techniques Used ...... 60 3.1.3.1. Reactive ion etching (RIE) ...... 60 3.1.3.2. PR stripping and plasma ashing ...... 60

3.2. Electrical Characterization ...... 61 3.2.1. Setup ...... 61 3.2.2. DC I-V Measurement ...... 62 3.2.2.1. I-V sweep mode ...... 62 3.2.2.2. I-V pulse mode and synaptic pulse modes ...... 62 3.2.3. AC Impedance Measurement ...... 63 3.2.4. Low-frequency Noise (LFN) Measurement ...... 63 3.3. Microstructural Characterization ...... 64

4 FABRICATION OF CORE-SHELL NANOWIRES ...... 66

4.1. Prototypes Fabricated ...... 66 4.1.1. Prototype 1 ...... 67 4.1.2. Prototype 2 ...... 67 4.1.3. Prototype 3 ...... 69 4.1.4. Crossbar Architectures ...... 69 4.1.5. Prototype 4 ...... 70 4.1.5.1. Layer 1 ...... 70 4.1.5.2. Layer 2 ...... 71 4.1.5.3. Layer 3 ...... 72 4.1.5.4. Layer 4 ...... 73

5 COMPLEMENTARY RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES ... 77

5.1. Electroforming ...... 77 5.2. Bipolar Resistive Switching (BRS) ...... 78 5.2. Complementary Resistive Switching (CRS) ...... 84 5.3. Conclusion ...... 90

6 IMPLICATIONS OF RESISTIVE SWITCHING MECHANISMS IN CORE-SHELL NANOWIRES ...... 91

6.1. TEM of Core-shell Nanowires ...... 91 6.2. Bipolar Resistive Switching ...... 96 6.3. Complementary Resistive Switching ...... 99 6.4. Conclusion ...... 103

7 ARTIFICIAL SYNAPTIC RESPONSE AND EFFECT OF TEMPERATURE ON BIPOLAR RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES ...... 104

7.1. Artificial Synaptic Response in BRS and CRS Mode ...... 104 7.1.1. Potentiation and Depression in BRS Mode ...... 104 7.1.2. Synaptic Behavior in CRS Mode ...... 110 7.2. Effect of Temperature on Bipolar Resistive Switching ...... 113 7.3. Conclusion ...... 118

8 TYPES OF NOISE AND IMPEDANCE SPECTROSCOPY IN CORE-SHELL NANOWIRES ...... 119

8.1. Low-frequency and Telegraph Noise ...... 119 8.2. Impedance Spectroscopy ...... 124 8.3. Conclusion ...... 129

9 SUMMARY AND FUTURE WORK ...... 130

9.1. Summary ...... 130 9.1.1. Complementary Resistive Switching in Core-shell Nanowires ...... 130 9.1.2. Implications of Resistive Switching Mechanisms in Core-shell Nanowires ...... 130 9.1.3. Artificial Synaptic Response and Effect of Temperature on Bipolar Resistive Switching in Core-shell Nanowires ...... 131 9.1.4. Types of Noise and Impedance Spectroscopy in Core-shell Nanowires ...... 131 9.2. Future Work ...... 132

APPENDIX

A LESSONS LEARNED ...... 134

B LOW-FREQUENCY NOISE AMPLIFIER ASSEMBLY ...... 136

C FABRICATION DETAILS OF PRELIMINARY PROTOTYPES ...... 138

C.1. Prototype 1 ...... 138 C.2. Prototype 2 ...... 140 C.3. Prototype 3 ...... 143 C.4. Crossbar Architectures ...... 146

LIST OF REFERENCES ...... 148

BIOGRAPHICAL SKETCH ...... 162

LIST OF TABLES

Table page

2-1 Active layer thickness, SET/RESET potential, cyclic endurance and resistance retention of binary and complex oxides in crossbar/thin-film architectures ...... 29

2-2 List of basic charge transport mechanisms in insulators ...... 41

4-1 List of tools used to fabricate prototype 4...... 74

6-1 Summary of stoichiometry at various interfaces ...... 94

6-2 Summary of CRS states based on the state of both memristors in a core- shell nanowire...... 100

7-1 Summary of CRS states based on the state of both memristors in a core- shell nanowire...... 111

C-1 List of tools used to fabricate prototype 1 ...... 138

C-2 List of tools used to fabricate prototype 1 ...... 140

C-3 List of tools used to fabricate prototype 4 ...... 143

C-4 List of tools used to crossbar architectures...... 146

LIST OF FIGURES

Figure page

1-1 Moore’s law through the years...... 20

2-1 Example of I-V sweep for a bipolar resistive switch ...... 28

2-2 Operation modes of resistive switching...... 32

2-3 Schematic representations for mechanisms of thermochemical switching ...... 33

2-4 Schematic representations for mechanisms of electrochemical switching ...... 33

2-5 Growth of Ag filaments (scale bar is 200 nm) ...... 34

2-6 Schematic representations for mechanisms of interface-type switching ...... 34

2-7 Formation of oxygen vacancies and movement of Zn ...... 35

2-8 Modes of operation ...... 36

2-9 Modes of operation ...... 37

2-10 Dissolution of Ta active electrode into active HfO2 layer ...... 39

2-11 Movement of Ca2+ ions during synaptic transmission ...... 45

2-12 Comparison of synaptic response in HfO2 and AlOx/HfO2 based ReRAM devices ...... 46

2-13 Power spectral density of an isolated switch vs one in a network...... 48

2-14 Power spectral density of HfOx/AlOx system...... 49

2-15 Evidence of noise ...... 50

2-16 Schematic of various components of the ITO/TiO2/ITO system affecting impedance...... 52

2-17 Impedance spectroscopy of Pt/NiO/Pt thin-film resistive switches ...... 53

3-1 Schematic for the fabrication of nanowires...... 54

3-2 Spin curves for 950 PMMA resist (A3, A4, and A7) ...... 55

3-3 Laurell spinner used to spin PMMA PR ...... 56

3-4 RAITH 150 ...... 57

3-5 Kurt J. Lesker multi target sputter tool used to deposit HfO2, Pt and Ti...... 58

3-6 Fiji 200 ALD system ...... 59

3-7 Probe station setup for electrical characterization of nanowires ...... 61

3-8 Example of I-V sweep on a single memristive node ...... 62

3-9 Examples of pulse schemes used ...... 63

3-10 LFN measurement setup...... 64

4-1 Schematics of fabricated core-shell nanowires...... 66

4-2 Preliminary prototypes ...... 68

4-3 Crossbar architectures with order and amount of deposition...... 69

4-4 Layer 1 of prototype 5 showing core-shell nanowires...... 71

4-5 Layer 2 of prototype 4 where wires intersecting with those of Layer 1 were exposed...... 72

4-6 Layer 3 of prototype 4 with electrode circles (6 μm diameter) before etching 40 nm of Al2O3...... 73

4-7 Final device image of prototype 4...... 74

5-1 Fabricated core-shell nanowire...... 78

5-2 Electrical characterization in BRS mode ...... 79

5-3 Electrical characterization in BRS mode (sweep and pulse schemes) ...... 81

5-4 Current conduction mechanism in HRS ...... 83

5-5 Current conduction mechanism in LRS ...... 83

5-6 Core-shell nanowires structural schematic ...... 84

5-7 Types of observed BRS curves ...... 85

5-8 Electrical characterization in CRS mode ...... 86

5-9 Current conduction mechanisms in CRS mode ...... 88

5-10 Effect of compliance current during initial BRS forming on peak current in CRS mode ...... 89

6-1 STEM analysis of core-shell nanowires ...... 93

6-2 Schematics detailing switching mechanism in BRS mode under one node of a core-shell nanowire ...... 98

6-3 Schematics detailing switching mechanism in BRS mode under the other node of a core-shell nanowire...... 99

6-4 CRS behavior observed in core-shell Pt/HfO2 system with “0” and “1” as two defined states to store information...... 100

6-5 Schematics detailing switching mechanism in CRS mode utilizing both nodes of a core-shell nanowire ...... 101

6-6 Schematics detailing switching mechanism in CRS mode utilizing both nodes of a core-shell nanowire ...... 103

7-1 8W BRS switch under investigation...... 105

7-2 Determination of bias for synapses ...... 106

7-3 Potentiation and depression in an 8W switch ...... 107

7-4 Potentiation using 0.9 V for 50 pulses and depression using -0.8 V for 40 pulses in a C8W switch...... 108

7-5 Schematic for potentiation and depression in BRS mode ...... 110

7-6 CRS behavior observed in core-shell Pt/HfO2 system with “0” and “1” as two defined states to store information...... 111

7-7 Synaptic response when operated in CRS mode...... 113

7-8 Impact of temperature ranging from 297K – 358K in an 8W BRS switch ...... 115

7-9 HRS segment of I-V ...... 115

7-10 Current conduction plot based on thermionic emission...... 116

7-11 Reduced trap barrier height at different electric fields...... 117

7-12 Current conduction plot based on ohmic conduction ...... 118

8-1 Low-frequency noise ...... 120

8-2 Random telegraph noise ...... 122

8-3 Stimulated telegraph noise driven by constant pulse trains with the state of the system read at 0.12 V after every pulse...... 123

8-4 Resistance in BRS mode in the frequency domain at different temperatures ... 125

8-5 Impedance spectroscopy ...... 126

A-1 S/TEM image of a core-shell nanowire ...... 134

B-1 Low-frequency noise amplifier assembled by Marc Martorell of the Nino Research Group...... 136

B-2 Flowchart of the stages within the LFNA ANF124 replica...... 137

LIST OF ABBREVIATIONS

AAO Anodic Aluminum Oxide

AC Alternating Current

ALD Atomic Layer Deposition

ANN Artificial Neural Network

BRS Bipolar Resistive Switching

CMOS Complementary Metal Oxide Semiconductor

CRS Complementary Resistive Switching

CVD Chemical Vapor Deposition

DAD Diligent Analog Discovery

DC Direct Current

DI Water De-ionized Water

E-beam Electron-beam

EDS Energy Dispersive Spectroscopy

EELS Electron Energy Loss Spectroscopy

FeRAM Ferroelectric Random Access Memory

HRS High Resistance State

HRTEM High Resolution Transmission Electron Microscopy

ICP Inductively Coupled Plasma

IPA Isopropyl Alcohol

ITO Indium Tin Oxide

I-V Current-Voltage

LFN Low-frequency Noise

LRS Low Resistance State

LTD Long-term Depression

LTP Long-term Potentiation

MIBK Methyl Isobutyl Ketone

MRAM Magnetoresistive Random Access Memory

NRF Nanoscale Research Facility

PCM Phase Change Memory

PIA Precision Impedance Analyzer

PMMA Poly Methyl Methacrylate

PR Photoresist

PSD Power Spectral Density

PSPA Precision Semiconductor Parameter Analyzer

PVD Physical Vapor Deposition

RAM Random Access Memory

ReRAM Resistive Random Access Memory

RF Radio Frequency

RIE Reactive Ion Etching

S/TEM Scanning Transmission Electron Microscopy

SEM Scanning Electron Microscopy

STDP Spike Time Dependent Plasticity

STP Short-term Potentiation

URS Unipolar Resistive Switching

Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES FOR APPLICATIONS IN NEUROMORPHIC ARCHITECTURES

Shangradhanva Eswara Vasisth

May 2021

Chair: Juan C. Nino Major: Materials Science and Engineering

Metal-oxide nanowires are rapidly gaining importance as non-volatile elements in neuromorphic architectures. Non-volatile memory devices, specifically those exhibiting resistive (or memristive) switching have been proposed to replicate the synaptic contact artificially. Nanowires exhibiting resistive switching behavior play an important role in fabricating highly dense, energy efficient, fast-parallel computing systems. Additionally, the use of core-shell nanowires especially is advantageous as they provide greater control of active area thickness, either with control of active layer deposition over the conductive core or by controlling the growth of the active layer around the core. The conductive core offers multibit memory capabilities and helps in establishing connections in architectures beyond crossbar arrays. Therefore, memristive nanowires offer an opportunity to ultimately increase the synaptic density beyond the current state-of-the-art

6 8 2 systems (10 to 10 connections/cm ). HfO2 has proven to be a viable candidate as an active layer due to its compatibility with complementary metal-oxide semiconductor

(CMOS) fabrication techniques, endurance of >1011 cycles with an extrapolated memory retention of 10 years. However, techniques of fabrication and electrodes in contact can cause significant variation in resistive switching type, mode, operating voltages,

endurance, and retention of states and therefore must be evaluated before device integration. Additionally, identifying sources of noise and determination of multiple synaptic states is necessary to use the devices in neuromorphic architectures. In this work, core (Pt) – shell (HfO2) nanowires with Ti top electrodes are fabricated via e-beam lithography. This enables the investigation of resistive switching characteristics, current conduction mechanisms in different states, synaptic potentiation and depression and sources of noise in core-shell nanowires for implementation in neuromorphic architectures.

The wires patterned on SiO2/Si substrate using e-beam lithography while Pt and

Ti, and the shell, HfO2, were sputtered on with additional lithography, deposition, and liftoff techniques. To determine resistive switching characteristics electrically, I-V sweep and pulse schemes were employed. After the initial electroforming step, both eightwise and counter eightwise bipolar resistive switching (BRS). Remarkably, for the first time along with BRS complementary resistive switching (CRS) was also demonstrated in core- shell nanowires. The cycling endurance in BRS mode was at least 1000 cycles with an off-on ratio ~ 13 and resistance was retained for 104 s. Additionally, compliance current used to form the nanowire in BRS mode influenced the CRS operation by lowering the peak operating current. The mechanism of switching in HfO2 has generally been attributed to be via oxygen vacancy filaments. Preliminary current density – electric field analysis performed to determine charge conduction mechanisms revealed that the wires exhibit thermionic emission mechanism in high resistance state (HRS) and ohmic conduction mechanism in low resistance (LRS) during BRS mode of operation and

hopping conduction mechanism in state 0 and space-charge-limited conduction mechanism in state 1 during CRS mode of operation.

Synaptic potentiation and depression can be obtained with gradual change in resistance by the application of pulses. These pulses, however, are not high enough to cause change in the resistance but are low enough to cause potentiation and depression.

In this work, when operated in BRS mode, non-linear weight update was observed with at least 3 distinct states each in potentiation and depression. In addition, changing the pulse scheme resulted in 3 synaptic states in the CRS mode.

To assess the impact of temperature on resistive switching, I-V sweep measurements were performed at temperatures between 297K and 358K. With increase in temperature, the SET voltage reduced, RESET process became more gradual and increase in RESET current was observed. This can be attributed to increased movement of vacancies forming the filament due to heat. Additionally, Arrhenius plot was extracted for HRS from the I-V curves at several potentials. A linear behavior was observed further confirming thermionic emission dominating charge conduction in HRS. This plot was later used to determine a barrier height of 0.23 eV from the conduction band.

Power spectral density (PSD) is calculated from low-frequency noise current that corresponds to spatio-temporal correlations in the device. These dynamic processes are observed in brain waves which may help in optimizing the system. When the wire was in

LRS in BRS mode, 1/fα like behavior was observed in the PSD α=1.24 which indicates a metallic behavior of charge movement as compared to semiconductive. Therefore, further confirming ohmic conduction behavior in LRS. However, in HRS, a low voltage pulse stimulation resulted in random telegraph noise that can be attributed to electrons

moving in and out of trap states. Further, a high voltage pulse stimulation resulted in stimulated telegraph noise that can be attributed to vacancy migration in the active HfO2 layer. Finally, impedance spectroscopy is performed to help understand the variation of dielectric properties with frequency in BRS and CRS modes. Here when the wire was in

HRS in BRS mode, a negative capacitance was observed at low frequencies at room temperature and as temperature increased in higher frequencies, the reactance of the device became less negative. This combined behavior is attributed to inductive dispersion due to electron movement in trapped states. This observed versatility in the mode of operation between BRS and CRS makes these core-shell nanowires of significant interest for use as synaptic elements in neuromorphic network architectures.

CHAPTER 1 INTRODUCTION

1.1. Statement of Problem and Motivation

Gordon Moore, Intel’s co-founder in 1975, predicted that the density of transistors on a fixed chip area doubles every two years [1]. The semi-log Figure 1-1 detailing the exponential growth of transistors confirms his prediction still holds true today as it did in the 1970s. However, he later suggested that this exponential increase cannot continue indefinitely [2]. The increased scaling down, memory and computing devices are headed towards a technological and physical limit, where transistors become unreliable as quantum uncertainties govern electron behavior.

Figure 1-1. Moore’s law through the years (Reprinted from Technological Progress,” Our World in Data, https://ourworldindata.org/technological-progress (March 23, 2021) [3]).

Additionally, current computational systems are reliant on von Neumann architectures in combination with complementary metal oxide semiconductor (CMOS) technology. This basic architecture used to build computing systems has a central processing unit and a separate storage unit. A common path shared between these units to communicate instructions and to store data has led to delay in speed of computation due to slow rate of data transfer. John Backus called this delay as the von Neumann bottleneck, where the majority of traffic present in this connecting channel details to the address/location of the data than the data itself [4].

A potential solution to alleviate this bottleneck is to fabricate parallel computing systems where the processing and storage units are present on the same chip [5]. The human brain is presently the fastest, parallel processing system known to us. With greater computing power and speed than even the largest supercomputers, the human brain consumes an equivalent of 20 W of electricity to performing similar tasks [6], [7]. As the brain is better understood, silicon systems are simultaneously simulating the connections of the brain to create artificial neural networks (ANNs). For example, current state-of-the-art neuromorphic systems like DeepSouth, IBM TrueNorth, Intel Loihi, and

Neurogrid, digitally simulate neuronal synapses to process tasks [8]. These systems, however, are built using classical circuit elements like resistors, capacitors, inductors, and transistors. Therefore, they will eventually succumb to the limits of CMOS technologies.

In the past two decades, non-volatile memory devices especially devices exhibiting resistive switching have been proposed to act as synapses in neuromorphic systems.

These are two-terminal electrical components have a metal-insulator (typically a metal oxide)-metal structure and the resistance is a function of the amount and direction of the

current [9]. These devices have already been incorporated into resistive random access memories (ReRAMs) and as described by Shimeng Yu [10], they have high on-chip density (4 – 12 F2 per bit, where F is the minimum feature size), increased energy efficiency (approximate consumption of <100 pJ per programming pulse compared to <10 fJ for biologicals synapses) and low leakage power consumption while performing fast- parallel computing [11].

However, limitations of these crossbar architectures include the presence of current sneak-paths [12], complex circuits and quadratic scaling with number of neurons.

To address these limitations Nino and Kendall [13] have proposed a patented architecture that utilizes core-shell nanowires to create large, random, and sparse neural networks.

Simulations have shown that these networks perform better than conventional architectures for digit speech recognition tasks when used as a reservoir [14].

Additionally, core-shell nanowires are advantageous as they provide access to the active layer in the radial direction than in the axial direction and the conductive core assists in obtaining multibit memory capabilities [15], [16]. With the majority of literature discussing integration of crossbars in neuromorphic hardware, there is a clear gap in understanding the dynamics involved in resistive switching of core-shell nanowires.

Therefore, this work focuses on fabricating core-shell nanowires to examine their switching dynamics and synaptic behavior for potential application in neuromorphic architectures.

1.2. Scientific Approach

Hafnium oxide (HfO2) is actively used in CMOS devices as a gate dielectric, is compatible with semiconductor fabrication methods and has a resistive switch (in crossbar [17]–[20] and core-shell architectures [15], [21]). The current state-of-the-art

crossbar device with HfO2 memristive layer has low programming voltage, switching speed of <5 ns, a record endurance of 1.2×1011 cycles with retention that can be extrapolated to 10 years. Additionally, 24 resistance levels have also been programmed

[22]. As a result, HfO2 is a viable candidate to be used as the active layer (shell) in this work. Additionally, tuning factors like thickness of the oxide [15], [23] and electrodes (core and top) at the interface [20], [24] desirable resistive switching characteristics can be obtained.

Once designed, e-beam lithography is used to pattern the substrates during fabrication due to greater control over the width of channel when used in conjunction with a positive photoresist. RF sputtering is used to deposit HfO2 as it coats the walls of the channels too thereby facilitating an enclosing shell.

HfO2 resistive switching devices have shown all types of resistive switching across prior works in literature, where one or multiple types have been observed in the same device. The fabricated core-shell structures are characterized electrically by probing just the top electrodes which potentially gives two devices, one under each electrode.

Therefore, the combined effect of these two memristors on resistive switching will be determined.

Charge transport mechanisms will be determined by fitting I-V data to semiconductor charge transport models. To determine the underlying mechanism a cross-section of the nanowire will be viewed under a scanning transmission electron microscope. Based on the analysis, atomistic schematic views will be used to explain different states of resistive switching that relates to filamentary conduction. By controlling the growth of the filaments, the conductance (synaptic weights) can be varied in steps.

These multilevel synaptic states in BRS and CRS will be determined by applying various pulse schemes. The impact of temperature on conduction is significant, therefore resistive switching will be analyzed over the range of 297K – 358K. Barrier height and activation energy will also be determined from Arrhenius plots.

Additionally, various sources of noise due to the presence of vacancies and traps will be identified and analyzed to assist with potential electronic integration. Finally, AC impedance spectroscopy will provide insight into the variation of dielectric properties with frequency.

1.3. Organization of Dissertation

Following this introduction, Chapter 2 presents a brief background regarding types and mechanisms of resistive switching in metal oxide active layers, conduction mechanism models, synapses (biological and artificial), noise in networks, and impedance analysis in memristors.

Chapter 3 introduces the methods and techniques used in fabrication, electrical and morphological characterization of core-shell nanowires.

Chapter 4 provides detailed steps involved in the fabrication different prototypes in a class 1000 cleanroom.

Chapter 5 discusses the resistive switching characteristics of core-shell nanowires.

Here, BRS and CRS are demonstrated while simultaneously fitting data to models to determine current conduction mechanisms.

Chapter 6 provides insight into resistive switching mechanism in both BRS and

CRS mode by analyzing TEM-EDS micrographs.

Chapter 7 begins by determining bias required to induce synaptic potentiation and depression. Synaptic potentiation and depression is determined in both BRS modes and

in CRS modes. This chapter also discusses the impact of temperature on resistive switching.

Chapter 8 presents various types of noise in different resistance states and discusses their source. Finally, impedance spectroscopy is performed to understand the variation of dielectric properties with frequency.

Chapter 9 summarizes this work and provides an outlook for the future.

In addition to the above content the author has provided additional information pertaining to this work in the appendices.

1.4. Contributions to the Field

As part of this work, a protocol was developed initially to fabricate core-shell nanowires by utilizing CMOS compatible techniques like e-beam lithography, sputtering and liftoff. Next, when individual wires were probed electrically to determine the resistive switching characteristics, depending on the applied bias both eight wise and counter eight wise bipolar resistive switching (BRS) behavior was obtained on a single nanowire. This unique behavior of the core-shell nanowires investigated in this work, is attributed to the presence of two memristors connected in an anti—serial manner. Remarkably, by combining both types, a new type known as complementary resistive switching (CRS) was observed for the first time in core-shell nanowire systems.

The resistive switching behavior in both BRS and CRS can be attributed to conduction of charge via oxygen vacancy filaments [25], [26]. When a positive bias is applied on the top Ti electrode, oxygen atoms diffuse into the electrode and the vacancies formed drift towards the inert Pt electrode leading to the formation of filaments. It is the control of this filament by the application of the desired threshold bias, resistive switching can be controlled. Apart from observing a 1-bit synapse in the BRS mode, the use of

pulse trains has resulted in multiple synaptic states. Each applied pulse causes gradual change in conduction due to a gradual formation or breaking of the conducting filament.

This phenomenon has been observed in both 8W and C8W bipolar resistive switch with the observance of at least 3 synaptic states each in potentiation and depression.

The analysis of various types of noise in BRS mode revealed that, the low- frequency noise due to the filament in LRS follow a 1/fα power law distribution. In HRS however, pulse stimulated noise is observed. A behavior attributed to the release of charge trapped in vacancies or trap sites in the oxide resulting in noise current.

Impedance spectroscopy in BRS mode revealed negative capacitance in lower frequency regimes when the wire was in HRS. This can be attributed to the accumulation and movement of charge between trap sites leading to an inductive dispersion.

Finally, by varying temperatures of the nanowire in BRS mode, in HRS thermionic emission was the dominant charge conduction mechanism and the resultant barrier height was ~0.23 eV. However, despite initial analysis suggesting the presence of ohmic conduction in LRS, a decrease in resistance was observed with increase in temperature.

A contrasting result that can be attributed to the presence of either hopping conduction on the other memristor in the nanowire.

CHAPTER 2 BACKGROUND

A brief review of related topics is provided here to assist in building an intellectual foundation for the understanding of topics covered in the following chapters. The background provided here is merely an introduction to topics like, resistive switching in oxides and then specifically in HfO2, charge transport mechanisms detailing various models considered, organic and artificial synapses, noise in networks and impedance spectroscopy.

2.1. Memristive or Resistive Switching

The classic two terminal circuit elements namely are resistor, capacitor, and inductor. However, another two terminal element called memristor, a contraction of memory and resistor was proposed [27]. The memristor is combination of resistance with memory that unlike volatile devices retains memory operation if left unperturbed [9], [28].

These non-volatile devices have the unique ability to modify their resistance based on the magnitude and direction of applied bias/current. A variety of physical mechanisms like ion migration, redox reactions spin-polarized tunneling, phase transitions, ferroelectric polarization govern the charge transport in these devices. This facilitates the development of novel, dense and energy efficient devices to break past the von Neumann bottleneck. Several new technologies have been developed with CMOS techniques to fabricate large arrays for memory and neuromorphic architectures, namely phase change memory (PCM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), and resistive random access memory (ReRAM) [8].

To understand memristive performance, devices are initially characterized in I-V sweep mode as shown in Figure 2-1. This enables the determination of the voltage and

current thresholds and the operation mode of switching between a high resistance state

(HRS) and a low resistance state (LRS). Most devices must undergo the process of electroforming before the first write-read operation. Usually, a higher voltage and current is employed to activate the device. To change the resistance states in these devices, the devices have to be SET and RESET. During the SET process when the threshold voltage exceeds VSET, the device is relatively turned ON, implying that the device has transitioned into the LRS from HRS. Subsequently, during the RESET process when the threshold voltage exceeds VRESET, the device is relatively turned OFF, implying that the device has transitioned into HRS from LRS.

150

100

50 LRS A)

µ SET

0 HRS

-50 Current ( -100 RESET V V -150 RESET SET -2 -1 0 1 2 Voltage (V)

Figure 2-1. Example of I-V sweep for a bipolar resistive switch

Memristive or resistive switching behavior has been observed in numerous binary and complex oxides, some examples of state-of-the-art crossbar/thin-film architectures of binary oxides and complex oxides are listed in Table 2-1. These devices are capacitor- like and are experimentally fabricated with a metal-insulator-metal (MIM) structure.

Table 2-1. Active layer thickness, SET/RESET potential, cyclic endurance and resistance retention of binary and complex oxides in crossbar/thin-film architectures Active layer VSET VRESET Endurance Memristive oxide thickness Retention (V) (V) (cycles) (nm) 11 6 HfO2 [22] 5 1.3 -3.05 1.2×10 >2.6×10 s 12 Ta2O5-x/TaO2-x [29] 40 6 -4.5 10 10 years ZnO [30] 60 -6.2 6.3 250 106 s 5 6 5 Nb:SrTiO3 [31] 5×10 2.5 -3.5 10 10 s 4 Pr0.7Ca0.3MnO3 [32] 100 -5 5 100 10 s Here, the component ‘M’ can be any compound or metal with high conductivity, and ‘I’ is the intermediate layer/s of oxides or other switching material present between two electrodes [9]. These structures have been widely been fabricated as crossbar arrays which were originally proposed to establish electrical connection for switching systems

(e.g.: telecommunication switching systems) [33]. The systems have straight electrode bars arranged perpendicularly in a grid-like pattern with the switching material sandwiched between the electrodes at the intersection. The goal of these structures was to not only connect a single pair of circuits but also connect pairs from various circuits (in- plane or stacked). Highly dense crossbar memories must have the eclectic set of characteristics: repeatable and reliable switching between at least two states, require less power and survive billions of switching cycles.[9] Also, during device operation, excellent thermal stability is imperative. Stacked crossbar structures fabricated by Kim et al. [34] with NbO2 switching material displayed reproducible I-V for over 100 cycles.

The device also showed exceptional thermal stability of up to 160°C when compared to VO2 devices with extremely thin film thickness, simple processing and with the ability to scale down the area to 10 nm. Therefore, these crossbars showed potential for vertical high-density integration.

2.1.1. Types of Resistive Switching

There are three main operation modes in resistive switching (Figure 2-2) with differing I-V sweep: a) unipolar (URS) Figure 2-2a and b, b) bipolar (BRS) Figure 2-2c and d, and c) complementary (CRS) Figure 2-2e and f. URS behavior is mainly known for its SET and RESET operation occurring with one voltage polarity. Initially, from HRS the devices are SET, and the process occurs when a threshold potential is reached while the current is being limited. A compliance current is usually applied to prevent excessive current flow leading to dielectric breakdown of the device. To RESET the devices the compliance current must be removed for a complete transition back into HRS.

A majority of systems in literature operate in BRS mode. Initially, devices in HRS are triggered to SET at a threshold voltage, often in the presence of a compliance current.

To read the state of the system, potentials much smaller than the threshold is applied.

The device is RESET back to HRS at certain potential threshold in the opposite polarity.

A complementary resistive switch is obtained by connecting two memristors exhibiting BRS in an anti-serial manner as suggested by Linn et al. [35] as a solution to the sneak path problem in crossbar arrays, where there is a presence of two BRS curves: one counter-eightwise and the other eightwise. They evidenced this phenomenon by using two GeSe memristive active layers connected back-to-back in series with an electrode in between the two active layers. This phenomenon was later observed in several other oxides namely: SiO2 [36], TaOx [37]–[39], TiOx [40], HfOx [41]–[43], and

GdOx [44]. However, in some cases this behavior can also be observed by controlling processing and operation of a random access memory (RAM) [45]. To program and store information in these devices, states 0 and 1 are defined. Here, state 0 is when memristor

A is in HRS and memristor B is in LRS and state 1 is when memristor A is in LRS and

memristor B is in HRS. Since one memristor is in HRS, the device is effectively in HRS in both these cases. The device is ON when both the memristors are in LRS which results in increase in current. The read voltage must be greater than V1, the first threshold voltage and smaller than V2. Since during every read operation the state written is erased, a pulse VV2 must be applied to restore state 0.

Therefore, depending on the applied bias and geometry, one or more types of resistive switching can be observed in metal oxide memristors.

-4 RESET RESET 10 LRS

10-7

LRS

Current SET Current(A) 10-10 HRS SET HRS 10-13 Voltage 0.0 0.5 1.0 1.5 Voltage (V) a) b)

150

LRS 100 LRS 50 SET A) µ SET

HRS HRS

Current -50 Current(

RESET -100 RESET

-150 Voltage -2 -1 0 1 2 Voltage (V) c) d)

300 RESET RESET 1 ON 200 ON 100 SET A) SET 1 OFF µ V V

4 3

OFF OFF 0 SET OFF V V Current 1 2 SET 2 Current( -100 ON ON RESET -200 RESET 2

Voltage -2 -1 0 1 2 Voltage (V) e) f)

Figure 2-2. Operation modes of resistive switching: a), b) ideal unipolar resistive switching and unipolar resistive switching observed in four layers of alternating ZrO2/HfO2 nanolaminates; c), d) ideal bipolar resistive switching and bipolar resistive switching observed in Pt/HfO2 core-shell nanowire; e), f) ideal complementary resistive switching and complementary resistive switching observed in Pt/HfO2 core-shell nanowire.

2.2.2. Mechanisms of Resistive Switching in Metal Oxides

The overarching switching mechanism of memristors involves either an interface- type path or filamentary conducting path, with the latter making the majority of memristors.

These mechanisms are only described briefly here. For additional details and fundamentals of memristors, the reader is directed to reference [9].

In the interface-type path, the memristive switching occurs at the boundary between the metal electrode and the oxide. In a filamentary conducting path, a conducting filament forms in between the metal electrodes. A rupturing and reforming of the filament path results in the switching mechanism [25]. The conducting filament path can be influenced through thermochemical switching whereby thermal effects can influence the rupturing and forming of filaments through Joule heating (Figure 2-3a, b and c). [26]

a) b) c)

Figure 2-3. Schematic representations for mechanisms of thermochemical switching: a) growth of oxygen vacancy, b) forming of filament, and c) breaking of filament in the metal oxide (blue atoms represents the metal oxide sandwiched between similar electrodes (gray atoms) and yellow atoms represents oxygen vacancies).

The memristive switching mechanisms can be further organized into electrochemical metallization, valence change, or purely electronic. Electrochemical metallization (Figure 2-4a, b and c), also known as cation migration, involves an electrochemically active electrode and an inert counter electrode whereby the cation (eg.

Cu or Ag) becomes oxidized and migrates toward the counter electrode forming a filament conducting path.

a) b) c)

Figure 2-4. Schematic representations for mechanisms of electrochemical switching: a) deposition of atoms from the active electrode, b) forming of filament, and c) breaking of filament in the metal oxide (blue atoms represents the metal oxide sandwiched between an active electrode (teal atoms) and an inert electrode (gray atoms) the teal atoms indicate dissolution of active electrode into the metal oxide).

This has been demonstrated by Yang et al. [46] in a Ag/SiO2/Pt system and can be observed in Figure 2-5. Here, upon application of bias, Ag dissolved from the Ag

electrode to form a conductive filament between the electrodes to enable resistive switching. The filament would dissolve once the device was RESET.

Figure 2-5. Growth of Ag filaments (scale bar is 200 nm) (Reprinted from Yang et al. 2012 [46]).

Valence change, or anion migration, primarily involves oxygen anions and is described through oxygen vacancies. An interface-type path (Figure 2-6g, h and i) can form due to the accumulation of oxygen vacancies at the boundary or a filament conducting path can form via migration of the oxygen vacancies leading to a compositional change in the memristor and ultimately a conducting filament [26].

g) h) i)

Figure 2-6. Schematic representations for mechanisms of interface-type switching: a) growth of oxygen vacancies, b) forming of filament, and c) breaking of filament in the metal oxide (blue atoms represents the metal oxide sandwiched between dissimilar electrodes (gray and brick red atoms) and yellow atoms represents oxygen vacancies).

It is important to note that these two types of pathways are not mutually exclusive as demonstrated by [47]. This was previously observed by Chen et al. [48] in their

Pt/ZnO/Pt system as seen in Figure 2-7. In their work, the oxygen vacancies formed when biased allowed the Zn atoms to migrate into the vacancy to form a Zn metallic filament. Therefore, this movement of oxygen and Zn ions enabled phase transition between Zn-rich ZnO1-x and ZnO that resulted in a unipolar resistive switch.

Figure 2-7. Formation of oxygen vacancies and movement of Zn (Reprinted from Chen et al. 2013 [48]).

2.2. Resistive Switching in HfO2

Hafnium oxide has been extensively studied and is currently employed in CMOS devices as a gate dielectric. Due to compatiblility with semiconductor fabrication methods, this metal oxide has proven to be a viable candidate to produce resistive switching devices [49]–[51]. The performance of these devices vary based on growth conditions, electrode in contact at the interface of the active layer and the thickness of the active layer. Current state-of-the-art systems fabricated by Jiang et al. [17] and Li et al.

[52] that have low programming voltages (<1 V) switching speed of <5 ns and 20 ns, an on-off endurance of 1.2×1011 and 109 cycles , and a resistance retention that can be extrapolated to 10 years. Simultaneously, multiple resistance states was also achieved in each device.

Hafnium oxide is also versatile and displays all three types of resistive switching in oxide memristors; URS [53], [54], BRS [17], [24], [55], and CRS [41]–[43]. The proposed conduction mechanism however, for most devices operating in any mode is filamentary.

Where, a filament grows from one electrode to the other (either metal ions or oxygen vacancies) to enable the flow of charge. In some instances, both URS and BRS modes of switching have been observed as shown in Figure 2-8 [24]. Lee et al. [24] noticed that despite having thin films (~12 nm), in the URS mode HRS resistance was high and the resistance ratio at 0.5 V was 104 – 109. When the device was operated in the BRS mode, the switching was unstable with a lower resistance ratio. This was attributed to a higher bandgap of HfO2 when compared to TiO2 or ZrO2.

b) a)

Figure 2-8. Modes of operation: URS (a) and BRS (b) in HfO2 (Reprinted from Lee et al. 2007 [24]).

Similarly, some HfO2 systems have displayed CRS along with BRS [41]–[43]. This behavior has been primarily seen when the same material is used as cathode and anode

[41], [42] however, Chen et al. [43] has observed CRS (Figure 2-9) with dissimilar electrodes. Initially, low compliance currents are utilized to form the devices and operate them in BRS mode. This was done intentionally to keep the filament size thin and

asymmetric. By repeating this operation at a slightly higher bias the device evolves from

BRS to CRS mode of operation.

b) a)

Figure 2-9. Modes of operation: BRS (a) and CRS (b) in HfO2 (Reprinted from Chen et al. 2016 [43]).

Alternatively, interface type of resistive switching has also been observed in HfO2

[56], [57]. In this type, switching occurs by regulating the resistance at the electrode- oxide interface by the oxygen vacancies present at the interface. The devices transition into LRS or HRS by the accumulation or depletion of oxygen vacancies at the interface.

The governing conduction mechanism was determined to be Fowler-Nordheim tunneling, where a depletion layer is created due to the oxygen vacancies created by the active electrodes. The vacancies provide n-type doping to the active layer and if the depletion layer is thin enough, electrons will tunnel through the electrode into the active layer.

The effect of electrode on the electrical transport characteristics of HfO2 are significant. The conduction mechanism, type and other resistive switching properties are highly dependent on the electrode in contact. For example, a recent study performed by

Saylan et al. [58] compared resistive switching properties with two different top electrodes. In their work, the HfO2 active layer had p-type Si as the bottom electrode and

an active electrode (Ag) was compared with an inert electrode (Au). With Ag as the top electrode, the devices exhibited BRS with the help of Ag filaments. However, with Au as the top electrode the devices exhibited an unstable URS with the help of oxygen vacancy filaments. Additionally, the SET and RESET potentials were lower for devices with Ag top electrode. Some electrodes also result in multiple types of resistive switching in HfO2 as shown by Lin et al. [59] when examining effects of other top electrodes. The devices with Ta, Pt, Cu, and Ni as top electrodes exhibited BRS with oxygen vacancies dominating the conduction mechanism. However, when the potentials were lowered and the polarity was reversed, the devices with Cu and Ni as top electrodes displayed URS in addition to

BRS. This was attributed to the diffusion of Cu and Ni in the active HfO2. This phenomenon of active electrode diffusion was also analyzed by Jiang et al. [17], where an active Ta top electrode diffused into the oxide resulting in BRS (Figure 2-10).

However, when Lee et al. [51] added a thin Ti buffer layer adjacent to HfO2 resulted in the absorption and movement of oxygen from the oxide into the Ti layer. Also, another work performed by Lee et al. [24] on resistive switching in HfO2 with Au and Pt electrodes suggested that when the device is biased, at the Pt/HfO2 interface, a dearth of oxygen was observed. Given that resistive switching in HfO2 is predominantly based on movement of oxygen vacancies to form a conductive filament, Pt and Ti were chosen as the electrodes for this thesis. Additionally, previous work done by Sharath et al. [60] on effect of HfO2 thickness on resistive switching has suggested that with increasing thickness the forming voltage increases. Where, 4.7 V was required to form 10 nm of

HfO2 and there was increase of 0.26 V for every 1 nm of oxide added. As a result, the thickness of HfO2 is also a factor to be considered. Additionally, Hou et al. also evidenced

the effect of bottom electrode on resistive switching. In their work with the

TiN/HfO2/Hf/TiN system, the Hf at the bottom electrode acted as a buffer layer for oxygen and induced oxygen vacancies into the active layer.

Figure 2-10. Dissolution of Ta active electrode into active HfO2 layer (Reprinted from Jiang et al. 2016 [17]).

HfO2 nanowires have only been explored as core-shell structures. Huang et al.[61]

Sn-doped In2O3 (ITO) core and HfO2 shell by depositing hafnia on ITO nanowires. The wires displayed BRS with SET and RESET occurring at 1 and -1 V for a 5 nm thick HfO2 shell. The device remained stable for 103 cycles and ON-OFF ratio of 10 with retention of resistance up to 104 s. However, as predicted, for a thicker shell of 10 nm SET and

RESET voltages were larger, 1.85 and -1.35 V respectively. With a thicker shell, ON-

OFF ratio increased to 102 but endurance reduced to 30 cycles. This was attributed to higher voltages leading to breakdown of devices.

On the other hand, Huang et al. [62] from Wen-Wei Wu’s group took functioning

Ni/NiO core-shell wires and coated them with 20 nm of HfO2 using atomic layer deposition

(ALD) due to its excellent resistive switching characteristics. When probed, the devices could be operated in both directions. The SET potential was constant at 2 V with a

compliance current of 10 μA. However, the device could be RESET in two different ways: a) by sweeping to 1.7 V at a higher compliance current or b) by sweeping to -1.6 V.

Thereby, displaying both URS and BRS type of switching behavior. The devices were stable for 200 cycles and retained resistance for 106 s. HRTEM and STEM analysis reveals switching occurs due to the migration of Hf4+, Ni2+ and O2- ions in the nanowires between the core and the top electrode. Therefore, the addition HfO2 to the nanowire array the density was improved.

2.3. Charge Transport Mechanisms

In ideal insulating metal oxides, the conductance is assumed to be zero. However, there is transport of charge through real insulators when temperature of electric field is high enough. Among several charge transport mechanisms in insulators, the processes under consideration for this thesis are listed in Table 2-2. From the expressions in Table

2-2, temperature and electric field are used to detect the transport mechanism experimentally. Among these transport mechanisms, each may dominate for a specific insulator depending on bias and temperature.

When the insulators are placed under high electric fields, charge is commonly transported by tunneling. This emission is independent of temperature but is highly dependent on the amount of applied field. This is a product of quantum mechanics where, the potential barrier is penetrated by the electron wave function. Tunneling can be categorized as direct tunneling where charge tunnels through the entire barrier width; or

Fowler-Nordheim tunneling where the charge tunnels through only a part of the barrier width.

Schottky emission here is based on thermionic emission theory which assumes that a) barrier height qϕB is larger than kT, b) at the plane that determines emission, a

thermal equilibrium exists, and c) this equilibrium is not affected by the net current flow and therefore, two current fluxes can be superimposed. As a result of these assumptions, barrier height is the only factor affecting current flow in this process. For example, Hsu and Chou [63] observed this behavior when their Au/Ga2O3 core-shell nanowire was in

HRS.

Table 2-2. List of basic charge transport mechanisms in insulators [64], [65].

Process Expression

3⁄2 4√2m*(qϕ ) Tunneling J∝E2exp [- B ] (2-1) 3qhE

-q(ϕ -√qE/4πε) Schottky emission J=A**T2exp [ B ] (2-2) kT

Frenkel-Poole -q(ϕ -√qE/πε) J∝Eexp [ B ] (2-3) emission kT

-ΔE Ohmic J∝Eexp [ ac] (2-4) kT

E -ΔE Ionic conduction J∝ exp [ ac] (2-5) T kT

Space-charge-limited 9εμV2 J= (2-6) conduction 8d3

qλE-ΔE Hopping conduction J=qnλfexp [ ac] (2-7) kT

** A is effective Richardson constant, ϕB is the barrier height, E is the electrical field, ε is the permittivity if * the insulator, m is the effective mass, d is the insulator thickness, ΔEac is the activation energy of electrons/ions, k is the Boltzmann’s constant, T is the absolute temperature, μ is the carrier mobility, q is

the electron charge, h is the Planck’s constant, n is the electron concentration in the conduction band, f is the thermal vibration frequency of trapping sites, and λ is the mean hopping distance.

Frenkel-Poole emission is through movement of thermally excited electrons from trap sites into the conduction band. The expression for Frenkel-Poole is similar to that of

Schottky emission, however, the barrier height in this case is the depth of the trap potential well. Since the positive charge is immobile in the oxide, barrier lowering is twice as large and therefore, barrier reduction is larger than in Schottky emission. For example,

Jana et al. [44] observed this behavior when their device (IrOx/GdOx/Al2O3/TiN) was in state 1 of CRS mode.

In ohmic conduction, thermally excited electrons carry current by hopping from one state into the next. This mechanism is exponentially dependent on temperature.

In ionic conduction, ions are either removed from or introduced into the insulator under an applied field, akin to a diffusion process. Charges build up at the interface when the current flows resulting in altered potential distribution. However, some ions return to their equilibrium position due residual internal fields that persist once applied field is removed.

When no compensating charge is present in the insulator as carriers are injected, space-charge-limited current flows in the device. In this mechanism, carrier concentrations are increased above equilibrium under bias and as a result electric field profile is controlled by these injected charge carriers. Therefore, a feedback mechanism is created, where field drives current which then sets up the field. For example, Hsu and

Chou [63] observed this behavior when their Au/Ga2O3 core-shell nanowire was in LRS.

Finally, in hopping conduction mechanism the electrons that are thermally excited and travel by hopping through subsequent isolated states to enable current flow. Jana et al.

[44] observed this behavior when their device (IrOx/GdOx/Al2O3/TiN) was in state 0 of

CRS mode. For additional details, works of Sze and Ng [64] and Mott and Davis [65] can be referred.

It has been noted previously that temperature is a factor affecting charge transport through insulators. This, however, also affects SET/RESET operation in resistive switching devices. This was initially observed by Fang et al. [66] in their TiN/HfOx/Pt

RRAM system. They observed with increase in temperature a) high oxygen vacancy trap density enhanced trap assisted tunneling caused increase in leakage current in HRS; b)

SET and RESET voltages were reduced; and c) multibit memory was not retained.

Walczyk et al. [18] also observed this in their system (Ti/TiN/HfO2/TiN) where, OFF-ON ratio dropped to ~5 from 20 when the temperature was varied from 213K to 413K. The authors attributed this to significant increase of current in the OFF state while the current in the ON state decreased.

2.4. Organic and Inorganic Synapses

Present state-of-the-art CMOS neuromorphic hardware are broadly classified as either digital or analog and mixed signal [8]. Digital CMOS hardware are consistent and well-studied where the algorithms are mapped into fixed circuits for efficiency or software for flexibility. Prominent examples include, IBM’s TrueNorth [67], Intel’s Loihi [68],

SpiNNaker [69], etc.. Analog and mixed signal hardware combine the strength and low latency of digital circuits and the low power characteristics of analog circuits. Prominent examples include DYNAP [70], Neurogrid [71], etc.. However, biological systems consume at least 8 orders of magnitude lesser power for computation than present CMOS neuromorphic architectures. It is proposed that a 10 nm node can potentially achieve the same level of efficiency in analog circuits but that technology is still under development

[6]. Non-volatile devices like memristors, have been proposed as potential artificial/inorganic synapses in neuromorphic hardware to reduce power consumption and increase density. Therefore, the driving force behind the fabrication of these devices is to emulate the computational abilities of the human.

Healthy human brains consists of approximately 200 billion neurons where the neurons are linked to one another through over a trillion connections known as synapses.

These micrometer sized synapses are responsible for the transport of electrical impulse from one neuron to the other. The number of synapses may vary over time, but regardless learning and memory storage are enabled through the dynamic changes synaptic strength between neurons [72], [73]. These weights are modified by impulse spikes in the brain’s neural network resulting in synaptic plasticity [74]. Plasticity of two types, short-term plasticity (STP) and long-term plasticity (LTP) perform on different time scales [75], [76]. Transition from STP to LTP can be enabled by recurring stimuli at brief intervals [77]. As summarized by Wang et al. [78] STP and LTP in the synapses of the brain are extremely dependent on movement of Ca2+ ions at the pre- and post- synaptic terminals. The influx of these ions induces stronger synaptic connection and an outflux of these ions leads to instantaneous decay of the connection. A schematic of various movements of pre-synaptic Ca2+ ions during synaptic transmission is shown in Figure 2-

11.

With regards to neuronal connection, the brain is determined to be a typical small world network that has high clustering and short path lengths [79]. The brains also show power law following degree distributions and a modular hierarchical structure with smaller networks within larger modules of networks. It is this network of neuronal connections

current neuromorphic architectures are trying to emulate. These architectures have emulated and modelled the Ca2+ ion dynamics to obtain a new learning scheme known as spike time dependent plasticity (STDP) [80]. In this scheme, every neuron integrates all the input signals and when it crosses the threshold, a spiking pulse is fired to modify the weight based on the pulse timing of the pre- and post- synapse [81].

Figure 2-11. Movement of Ca2+ ions during synaptic transmission (Reprinted from Zucker 1999 [82]).

In artificial memristive synapses, the control over resistance based on electric stimuli and multi-level resistance response can be used to perform in-memory computing

[8], [81]. In-memory computing is a solution to the von Neumann bottleneck where computation of tasks and storage of memory is done in the same unit. The systems’ peripheral circuitry, array-level organization, and logic control are exploited with memory playing an active role in computation to achieve in-memory computing [83]. Large arrays of non-volatile memories are used where weights are updated in parallel by changing the potential at the corresponding row and column. Depending on the case and algorithms used, a different weight update non-ideality is obtained that affects the convergence

speed and final training results. Device to device and cycle to cycle variations may also affect convergence speed [81].

Resistive random access memories (ReRAMs) are one among the several non- volatile memories that possess favorable characteristics like scalability, moderate switching speed and low power consumption, for neuromorphic implementation [11], [81].

In ReRAMs long term state retention of >10 years is desired [11], but this is not true in all as some can display based on programming conditions, both volatile and non-volatile retention. Ohno et al. [75] observed STP and LTP in their Ag2S based ReRAM devices.

The volatility of the high ON state enabled STP and the non-volatile permanent conductance state enabled LTP. This transition was controlled by changing the inter pulse time delay. As the inter pulse time delay was reduced from 20 s to 2 s, STP transitioned into LTP.

Figure 2-12. Comparison of synaptic response in HfO2 and AlOx/HfO2 based ReRAM devices (Reprinted from Woo et al. 2016 [84]).

However, apart from long- and short- term retention, multilevel conductance states using identical pulse schemes has been observed previously by Woo et al. [84]. Since for direct mapping of weights a linear response is desired [11], Woo et al. [84] added Al at the HfO2 interface which led to the formation of an interfacial AlOx layer to improve vacancy distribution when compared to devices without Al. As seen in Figure 2-12, the addition of Al improved linearity when a constant pulse train was applied. This was due to the gradual accumulation of vacancy in the interfacial AlOx layer. However, a resistance ratio did drop significantly from ~10 to ~3.

2.5. Noise in Networks

Since neuromorphic architectures are endeavoring to emulate the computational abilities of the brain, including the synaptic plasticity, correlated memory in the brain in dynamic synapses have hierarchical structures like amplifying loops [85] and feedforward transmission subassemblies [86]. Thus, making learning a dynamic process in the brain.

The brain’s network oscillates periodically between subcritical and critical boundary during operation to facilitate a fast and correlated reaction to stimulation during computation and learning. This is has been attributed to the self-organized criticality of the system [87]; where, a dynamic non-linear system will organize itself to a critical condition (maximum correlated state), when exposed to external stimulation with fast internal relaxations [88].

In artificial synapses, non-linear response to stimulus leads to short- and long-term memory. However, when these systems are connected to each other on a large scale, the power spectral density (PSD) (2-8) of white noise in the network will start to obey the

1/fα (where 0<α<3) power law distribution as shown in Figure 2-13 [88], [89]. This indicates presence of long-range correlations caused due to the network of synapses.

The correlated activity in synapses of the network originate from an applied bias independent of frequency at a particular synapse. As a result, akin to the brain, this represents the system organizing itself as dynamic circuit, where a local Hebbian style strengthening of connections has global dynamical effect. Therefore, the synaptic networks are in a critical state and transition between several metastable states that follow the power law. For a given current response in the time domain, PSD can be obtained by performing fast Fourier transformation of the data.

∞ ∞ 1 * -i2πfτ PSD(f)= ∫ [ lim ∫ xT(t-τ)xT(t)dt] e dτ (2-8) -∞ T→∞ T -∞

Figure 2-13. Power spectral density of an isolated switch vs one in a network (Reprinted from Stieg et al. 2019 [88]).

Current fabrication techniques are more than capable to produce dynamic circuits non-linear synapses. However, the utility of these dynamic events has not been exploited yet. These systems are highly malleable and device physics governs the learning rate and not the complexity of algorithms. Yu et al. [90] analyzed the behavior of noise in a

TiN/HfOx/AlOx/Pt ReRAM and discovered a bias dependance of PSD (Figure 2-14). The

PSD was linear in LRS (α~1) and super-linear in HRS (α~2) which suggested that during the RESET process, the conductive filaments ruptured and a tunneling gap was formed.

a) b)

Figure 2-14. Power spectral density of HfOx/AlOx system in a) LRS and b) HRS (Reprinted from Yu et al. 2011 [90]).

Another type of noise in ReRAMs that has come under scrutiny over the past decade is random telegraph noise (RTN). In a majority of ReRAMs, defects/traps accumulate to form conductive filaments that carry charge between the electrodes.

However, if charges are trapped in these defects they can affect the flow of current when bias and hence produce RTN [91]–[96]. Higher voltages are rarely used to scrutinize as this can cause resistance instabilities and/or switching of states. Therefore, low voltages are employed where only electronic effects are observed [97]. When the device is intentionally exposed to trains of higher voltage pulses, the resistance gradually changes and saturates. If the pulse train persists, zero-average stimulated telegraph noise (STN) will be observed instead of resistance change. It has been previously suggested that this pulsed stimulated noise has similar physics to non-volatile switching. Therefore, ionic effects might be the source of STN [91]. As a result, when identical pulse trains are

applied, RTN impacts reading and STN impacts the programming of a resistance state.

In Figure 2-15a, at a constant low voltage, current fluctuations are limited and can be attributed to RTN. In Figure 2-15b, at a bias high enough to change the resistive state is applied, the current fluctuations observed are attributed to STN. Additionally, Brivio et al.

[91] also observed STN dependance on applied voltage pulse where STN amplitude increased with bias.

Figure 2-15. Evidence of noise: a) RTN and b) STN (Reprinted from Brivio et al. 2019 [91]).

2.6. Impedance Spectroscopy

To study dynamics of charges in liquids and solids, and to analyze the electrical and dielectric properties of electroceramic materials impedance spectroscopy is performed. This technique involves analyzing the response of a material to an electrical stimulus in the time or frequency domain [98], [99]. Originally used by Bauerle [100] to

measure conductivity in ionic solids, impedance spectroscopy has gained importance in examining electrochemical systems, as a direct correlation exists between the impedance behavior of a material and the physics governing the material.

Typically, impedance is measured by applying an oscillating current or voltage across the nodes of a material and subsequently measuring the amplitude or the shift in phase of the output current frequency as the independent variable. On the other hand, if the output current response is measured with time as the independent variable, frequency dependance of impedance can be extracted from transformation techniques like Laplace or Fourier transformation [98]. For analysis depending on the material and the system, impedance response is measured with a few hundred mV bias in the frequency range of

0.01 Hz to 10 MHz. Impedance is complex number with resistive and reactive

(capacitive/inductive) components. Some impedance related equations are given below:

Z = Z’ + iZ’’ = R + iX (2-9) |Z| = √(Z')2+(Z'')2 = √(R)2+(X)2 (2-10) Z'' X θ= tan-1 ( ) = tan-1 ( ) (2-11) Z' R Z’ or R = |Z| cosθ (2-12) Z’’ or X = |Z| sinθ = XL+XC (2-13) −1 −1 XC = −(ωC) = −(2πfC) (2-14) XL = ωL = 2πfL (2-15)

Where, Z is impedance, Z’ is the real part and Z’’ is the imaginary part of Z, |Z| is the magnitude and θ is the phase of impedance, R is resistance, X is total reactance, XC is capacitive reactance, XL is inductive reactance, C is capacitance, and L is inductance.

Usually, a frequency implicit Nyquist plot is used to depict complex impedance data. As an alternate, frequency explicit Bode plots can also be used. By fitting the impedance data, to RC circuits, resistance capacitances of various components of a resistive switch can be determined. Analysis of impedance spectroscopy data by Jiang

et al. [101] on their ITO/TiO2/ITO system revealed that in both LRS and HRS, the equivalent circuit consisted of three components: a series resistor and two parallel resistor and capacitor configurations as seen in Figure 2-16.

Figure 2-16. Schematic of various components of the ITO/TiO2/ITO system affecting impedance (Reprinted from Jiang et al. 2013 [101]).

They discovered that at the electrode oxide interface, equivalent capacitance (~107

F) and resistance (43.7 Ω and 47.9 Ω) was higher and lower, respectively than the other components. A larger capacitance in LRS was also observed for the second section, indicating that the conductive filaments in the oxide do not connect the electrodes all the way. Finally, they concluded that resistive switching is enabled by changing the oxide thickness between the filament and the top electrode.

Additionally, impedance spectroscopy performed by You et al. [102] on NiO resistive switches observed that due to the high work function of Pt electrode, only responses from the bulk were captured and not the NiO/Pt interface. They also observed gradual decrease in impedance with increasing frequency and bias independent capacitance at lower frequencies as shown in Figure 2-17.

Figure 2-17. Impedance spectroscopy of Pt/NiO/Pt thin-film resistive switches (Reprinted from You et al. 2006 [102]).

CHAPTER 3 EXPERIMENTAL PROCEDURES AND TECHNIQUES

In this chapter the tools and techniques used to fabricate and characterize core- shell nanowires are provided with brief descriptions.

3.1 Fabrication Techniques

Figure 3-1. Schematic for the fabrication of nanowires.

The schematic for the fabrication of core-shell nanowires in a class 1000 cleanroom at the Nanoscale Research Facility at University of Florida is described in

Figure 3-1. The steps are detailed in the following sections of this chapter.

3.1.1. Lithography

Lithography is the process by which desired patterns are created on wafers. Every step is critical in the fabrication of the final device and the steps are often complex and repetitive. In this process, circuit patterns are transferred onto the wafers using optical methods from master design images [103]. In this work, an electron beam (E-beam) is

used to transfer the desired pattern onto the surface of the wafer. The substrate used in this work is a p-type (boron doped) Si polished wafer with 100 nm of thermally grown

SiO2.

3.1.1.1. Resist coat (spinners)

Photoresists (PRs) are usually photo sensitive, organic polymers in solution of which a small quantity is dispensed onto the wafer/chip. The substrate is then spun at the desired rate which removes excess solution and as the solvent evaporates it leaves behind a thin layer of solid resist [103]. In this work, a positive PR 950 polymethyl methacrylate (PMMA) [104] A4 and A6 was used as PR when required. Spin curves for

A4 is shown in Figure 3-2 can be utilized in determining the speed of rotation to achieve the desired PR thickness.

Figure 3-2. Spin curves for 950 PMMA resist (A3, A4, and A7) (Reprinted from PMMA Data Sheet, https://kayakuam.com/wp- content/uploads/2019/09/PMMA_Data_Sheet.pdf (February 23, 2021) [105]).

For e-beam lithography among PRs, PMMA was one of the first polymers to be developed [106]. To deposit the PR of desired thickness on the substrate, a Laurell spinner as shown in Figure 3-3 was used.

Figure 3-3. Laurell spinner used to spin PMMA PR (Reprinted from Litho Process Laurell Spinner E-Beam Bay & Hot Plate/Oven - Research Service Centers, https://rsc.aux.eng.ufl.edu/ccb/resource.asp?id=68 (accessed Feb. 10, 2021) [107]).

3.1.1.2. Bake

Once the PR is applied, to support layer processing the density is usually not sufficient. As a result, a bake is necessary to densify the PR and evaporate the remaining solvent [103]. In this work once PMMA is spun on the substrate, it is then baked in an oven at 180°C for at least 2 hours. The bake can be shorter if a hot plate at the same temperature is used as contact heat transfer is faster [104].

3.1.1.3. Exposure by e-beam

Photoresists are subjected to photochemical reactions when exposed to light. In this work when a pattern (designed in RAITH 150 TWO software) is exposed on the substrate using an e-beam, PMMA breaks down into smaller fragments and are removed in the next step. Fine patterns essential to the present electronics industry can be created

using this technique. The desired patterns on PR are exposed as the tool scans an electron beam across the substrate. The primary traits that make this tool necessary in fabrication of core-shell nanowires are high resolution to produce small features and the technique is flexible and can be used to produce any pattern. However, this technique is more than order of magnitude slower optical lithography techniques, it is expensive and complicated to use. Additional details can be found in Chapter 2 of Handbook of

Microlithography. Micromachining, and Microfabrication Volume 1: Microlithography

[108].

The required circuit patterns are designed in the RAITH 150 software and RAITH

150 tool as shown in Figure 3-4 is used to transfer these patterns onto the substrate after alignment if necessary. Features of this tool include acceleration voltage: 200 eV – 30 keV; probe current: 4 pA – 10 nA; with beam size varying from 3 nm at 1 keV and 30 μm aperture to 1.5 nm at 20 keV and 30 μm aperture [109].

Figure 3-4. RAITH 150 (Reprinted from Raith 150, e-beam lithography - Research Service Centers, https://rsc.aux.eng.ufl.edu/ccb/resource.asp?id=101 (accessed Feb. 10, 2021) [110]).

3.1.1.4. Development

In this step, the regions on the PR that have been exposed to light or electron beam are removed. In this work, the substrate is immersed in a mixture of 1 part methyl isobutyl ketone (MIBK) and 3 parts of isopropyl alcohol (IPA) to dissolve the PMMA fragments that are present after exposure.

3.1.2. Deposition Techniques

3.1.2.1. Sputter deposition

This is a common technique used to deposit thin layers of materials on a substrate.

Categorized under physical vapor deposition, this technique makes use of positively charged ion bombardment of a target material resulting the formation of a vapor, which is then deposited on the substrate. Inert gases for bombardment can be ionized in two ways: either by applying a direct current (DC) voltage for conducting targets or radio frequency (RF) voltage for insulating materials [111]. In this work, the multi target sputter tool from Kurt J. Lesker Company as shown in Figure 3-5 was used.

Figure 3-5. Kurt J. Lesker multi target sputter tool used to deposit HfO2, Pt and Ti (Reprinted from Sputter Deposition, KJL CMS-18 Multi-Source - Research Service Centers, https://rsc.aux.eng.ufl.edu/ccb/resource.asp?id=117 (accessed Feb. 10, 2021) [112]).

This tool was utilized to deposit the active layer HfO2 and the electrodes Pt and Ti in an Ar atmosphere with a chamber pressure of 5 mTorr. When using HfO2 target, RF voltage was increased/decreased slowly during operation. This is due to the poor thermal conductivity of the target.

3.1.2.2. Atomic layer deposition (ALD)

This is a technique where the precursors are introduced sequentially and react on the surface of the substrate to deposit a thin film of the required material. As the name suggests, the deposition is atomic in nature and thickness can be precisely controlled.

This technique can be categorized under chemical vapor deposition (CVD). However,

ALD differs from CVD in the way precursors are introduced. The sequence of the deposition is as follows: a) first precursor is introduced, b) excess precursor is purged, c) second precursor is introduced, d) excess precursor is purged, and e) the previous steps are repeated until the desired thickness of film is obtained [113]. The deposition is performed in a heated chamber; therefore, PR cannot be used. As a result, to obtain necessary patterns on the substrate the oxide layer deposited must be etched down.

Figure 3-6. Fiji 200 ALD system (Reprinted from ALD - Cambridge Nano Fiji 200 - Research Service Centers, https://rsc.aux.eng.ufl.edu/ccb/resource.asp?id=9 (accessed Feb. 10, 2021) [114]).

In this work, the Fiji 200 ALD system (Figure 3-6) was used to deposit Al2O3. The deposition of Al2O3 on these prototypes is primarily done to isolate the nanowires from the vias that connect the nanowires and the electrode pads. For deposition of Al2O3 the precursors used are, water and trimethylaluminum (Al(CH3)3) in chamber at 200°C and at a pressure of 250 mTorr. The carrier gas used here is argon and the rate of deposition is 1 Å/cycle.

3.1.3. Other Techniques Used

3.1.3.1. Reactive ion etching (RIE)

In this technique, energetic ions charged by radiofrequency is bombarded against the substrate causing a synergistic reaction between the ions and the substrate. This anisotropic bombardment assists in unidirectional removal of the material on the substrate. Since lateral etch rate being low, this technique becomes extremely important when fabricating narrow channels [115]. In this work, to etch Al2O3 at specific locations, either BCl3 is used as an etchant in the Trion RIE/ICP or a combination of CH4. Ar, Cl2, and H2 in the Uniaxis RIE/ICP is used. Typical etch product will be AlCl3.

3.1.3.2. PR stripping and plasma ashing

After the deposition of the necessary materials on the substrate, to obtain the patterned device, the PR must be removed. To remove PMMA from the substrate, the chip is immersed in acetone and sonicated for a few minutes. The substrate is then doused with IPA, washed with de-ionized (DI) water, and is finally dried using compressed air. To prepare the substrate for subsequent PR coat and deposition, the chip is exposed to plasma in a plasma asher. Here, the plasma source is used to create a reactive monoatomic oxygen that reacts with residual PR on the surface and transforms it into either ash or gases of carbon. These are then removed by a vacuum pump [116]. In this

work, the barrel Anatech asher is used when needed. Additionally, to ensure desired features have been fabricated and to document the progress, the chip is inspected under a Nikon LV100 microscope after a macro step.

3.2. Electrical Characterization

3.2.1. Setup

The setup described is show in Figure 3-7. The nanowires fabricated on the

SiO2/Si chip in this work were electrically characterized at the benchtop probe station from

Micromanipulator. The chip was held on the stage by vacuum and the electrode pads were probed using Au probes. Current (I) – Voltage (V) measurements in DC sweep and pulse mode were performed using an Agilent 4156C Precision Semiconductor Parameter

Analyzer (PSPA). Programs from MATLAB were executed on the PSPA by interfacing it with a computer.

Figure 3-7. Probe station setup for electrical characterization of nanowires. (Photo courtesy author)

To perform AC impedance measurements, the probe station is connected to an

Agilent 4294A Precision Impedance Analyzer (PIA). A low resistance switch is employed

to switch back and forth between PSPA and PIA. The stage is replaced with a hot plate to measure I-V characteristics and AC impedance at higher temperatures.

3.2.2. DC I-V Measurement

3.2.2.1. I-V sweep mode

Initially during electroforming, voltage is applied by the PSPA along a single direction with peak voltage raised in steps until the node transitions into LRS from HRS.

The node is then RESET to return it back to HRS. These steps are important as they help in determining the threshold potentials of the node under investigation. With the threshold potentials, a DC triangular sweep wave will help us determine the existence of stable memristive I-V hysteresis (Figure 3-8). A hotplate is used to obtain I-V hysteresis at varying temperatures. An infrared laser thermometer was used to note the temperature on the surface of the chip.

150 100

A) 100

µ 50

0 50 LRS A)

-50 µ SET

0 Current ( -100 HRS

1 -50 Current (

0 -100 RESET -1 V V RESET SET

Voltage Voltage (V) -150 0 5 10 15 20 25 30 35 -2 -1 0 1 2 Time (s) Voltage (V) Figure 3-8. Example of I-V sweep on a single memristive node

3.2.2.2. I-V pulse mode and synaptic pulse modes

Voltage pulses with varying pulse schemes are applied to obtain different behavior from the node. This usually involves logical operations like write, read, and erase. In this mode, the pulse height, width, and interval between each pulse can be controlled. For

endurance as shown in Figure 3-9a, pulses of opposite polarities are applied to induce transition of state. The state of the system is read after each pulse at a desired read voltage. For retention as shown in Figure 3-9b, the device is either SET or RESET and the state of the system is read at intervals of 10x where x = 0, 1, 2, 3. etc. Constant pulse trains are used to induce synaptic potentiation or depression.

1 0.0 0.1 1 10 100 1000 10000 Time (s) -0.5

1 2 3 4 5 6 7 8

Pulse no. -1.0 Voltage (V) -1 Voltage (V) LRS Voltage -1.5

a) b) Figure 3-9. Examples of pulse schemes used: a) for endurance in a C8W switch and b) for retention in a C8W switch.

3.2.3. AC Impedance Measurement

The PIA is used to measure electrical parameters like impedance, phase, capacitance, resistance, and reactance of the core-shell nanowires in different resistance states. The node is either set in LRS or HRS by applying the necessary threshold voltage from the PSPA. The probes are then switched to PIA and the previously listed parameters are measured at 0.1 V DC bias between 800 Hz and 0.3 MHz.

3.2.4. Low-frequency Noise (LFN) Measurement

Trap assisted conduction can be characterized electrically by using LFN measurement. Figure 3-10 shows a schematic for the measurement setup used. Initially, the node under observation was placed in either low or high resistance state. The Agilent

4156 C PSPA was utilized to bias one of the top electrodes on the nanowire. The current coming out of the nanowire was fed into a low frequency noise amplifier (gain of 105 was used) to amplify the current prior to measuring the signal in the Diligent Analog Discovery

2 (DAD) board. Among the various features built into the DAD board, oscilloscope mode was used to export the noise current to perform fast fourier transform (FFT) to obtain PSD of the nanowires in different states.

Figure 3-10. LFN measurement setup.

3.3. Microstructural Characterization

The optical images in this work are obtained using a Nikon LV100 microscope located in the cleanroom at the Nanoscale Research Facility. The SEM images were captured in the FEI helios nanolab 600 dual beam FIB/SEM at NRF. High-resolution images were obtained at 2 kV with a working disance of 3.9 mm. FEI Themis Z S/TEM

was used to perform S/TEM EDS analysis. EDS was captured with a screencurrent of

10nA, Energy range 20keV, dwell time 50 μs. The SEM and TEM images used in this work are a courtesy of Eitan Herschkovitz from Dr. Honggyu Kim’s group.

CHAPTER 4 FABRICATION OF CORE-SHELL NANOWIRES

4.1. Prototypes Fabricated

Several prototypes were fabricated in the cleanroom at NRF, however, the electrical and material characterization discussed in this thesis are obtained from prototypes 4. Schematics of the desired core-shell nanowire and intersecting nanowires is shown in Figure 4-1a and Figure 4-1b.

a) b)

Figure 4-1. Schematics of fabricated core-shell nanowires: a) single wire, b) intersecting wires under a common node, and c) order and amount of deposition to fabricate a single nanowire.

A schematic with thickness of each layer present for prototype 4 is provided in

Figure 4-1c. The substrates used to fabricate these prototypes are parts of single side polished Si (p-type, (100)) wafer doped with boron. Additionally, 300 nm of SiO2 is thermally grown on them before processing. Patterns on all prototypes are exposed using the RAITH 150 e-beam tool and multiple devices were made of each prototype on the chip. The tools used and details on the nanowires fabricated are briefly listed below.

4.1.1. Prototype 1

The nanowires were patterned on PMMA with an electron beam on a SiO2/Si substrate. The HfO2 shell thickness was 15 nm around a 50 nm Ti core. The process of spinning PR, exposure via e-beam, deposition and lift-off are repeated as needed to obtain intersecting wires. A 40 nm film of aluminum oxide (Al2O3) was deposited using atomic layer deposition to isolate the wires from electrode connections. Top electrodes of 500 nm diameter were etched in the Al2O3 to probe the wires. Finally, 10 nm of Ti and

70 nm of Pt was deposited as top electrodes before lift-off to obtain the final device (Figure

4-2a). Details of steps involved is listed in Appendix C.

4.1.2. Prototype 2

To test the memristive behavior in more complex networks, a three-layer, random nanowire network (Pt/HfO2/Ti) was designed Figure 4-2b and fabricated via e-beam lithography. The network consisted of 94 wire, 64 electrodes in an 8×8 grid and contained

358 synaptic contacts Figure 4-2b. In these nanowires, the thickness of the hafnia shell was 7 nm and the Ti core was 40 nm thick. A 40 nm film of aluminum oxide (Al2O3) was deposited using atomic layer deposition to isolate the wires from electrode connections.

Top electrodes of 8 μm diameter were etched in the Al2O3 to probe the wires. Top electrodes were circular with a diameter of 8 μm were etched followed by the deposition

of 15 nm of Ti adhesion layer and 70 nm of Pt for top electrical contact. The completed final device is shown in Figure 4-2b. Details of steps involved is listed in Appendix C.

Figure 4-2. Preliminary prototypes. Final device images of a) prototype 1, b) prototype 2, and c) prototype 3.

4.1.3. Prototype 3

To test the effects of difference in core and top electrode materials, a new prototype was designed Figure 4-2c and fabricated with Pt core, HfO2 shell and TiN/Ti as top electrodes. The design is a combination of prototypes 1 and 2. Here, there are elements from prototype 1 to test the fundamental memristive behaviors of single wires, multiple electrodes on a single wire, etc. as described before. Also, a two-layer network with 31 wires and same top electrode dimensions were fabricated Figure 4-2c. Similar to devices before, the hafnia shell was 7 nm and the Pt core was 40 nm thick. Top electrodes were circular with 50 nm of TiN, 20 nm of Ti and 190 nm of Au. The completed final device is shown in Figure 4-2c. Details of steps involved is listed in Appendix C.

a) b)

Figure 4-3. Crossbar architectures with order and amount of deposition.

4.1.4. Crossbar Architectures

Crossbar architectures as seen in Figure 4-3, were fabricated to compare the resistive switching behavior with that of nanowires. This device was fabricated in three stages. Initially, bottom electrodes were patterned in the PR and 10 nm of Ti and 60 nm

of Pt was sputter deposited for the bottom electrode contact. Next, the PR was patterned to expose regions for the deposition of 7 nm of HfO2. Finally, the substrate was patterned, and 10 nm of Ti and 60 nm of Pt was sputter deposited for the top electrode contact.

Details of steps involved is listed in Appendix B.

4.1.5. Prototype 4

The designs for this prototype were made on the RAITH 150 TWO software with

200 μm write fields. Total device dimensions are 1400 μm × 1400 μm. Additionally, global marks and write field marks are placed in the corners of the device and each write field respectively for alignment. A detailed description of fabrication is provided below since the bulk of data presented and analyzed in this dissertation are from this prototype.

The steps involved in the fabrication are listed in Table 4-1.

4.1.5.1. Layer 1

On a clean SiO2/Si substrate, A4 PMMA was spun at 4000 rpm to get a 165 nm thick PR and was baked at 180°C. The sample was loaded in the RAITH 150 and layer

1 pattern was exposed at 20 keV accelerating voltage, 10 μm aperture, 5 nm step size, and an area dose of 400 μC/cm2. The substrate was then developed in a 1:3 mixture of

MIBK and IPA and was then cleaned with DI water and dried using compressed air. Next,

7 nm of HfO2 was deposited to form the base of the shell using the sputter tool in RF mode at a rate of 0.31 Å/s. Sputtering also coats the walls of channels in the PR, thus enabling us to build a core-shell nanowire. This is followed by the sputter deposition of 5 nm of Ti (1 Å/s) for adhesion and 35 nm of Pt (4.26 Å/s) in DC mode and together they form the core. Finally, 7 nm of HfO2 was RF sputtered at the same rate to complete the core-shell structure. The PR is then stripped off the substrate by sonicating in acetone.

Acetone is cleared by IPA and water to reveal the finished layer as seen in Figure 4-4.

Figure 4-4. Layer 1 of prototype 5 showing core-shell nanowires.

4.1.5.2. Layer 2

The substrates were descumed in an O2 plasma to remove residual PMMA and

A4 PMMA was spun at 4000 rpm to get a 165 nm thick PR and was baked at 180°C to pattern layer 2, where wires intersected with layer 1 were exposed.

The pattern was exposed at 20 keV accelerating voltage, 10 μm aperture, 5 nm step size with an area dose of 400 μC/cm2; and was then developed in the previously mentioned MIBK and IPA mixture. Next, 7 nm of HfO2 was deposited to form the base of the shell using the sputter tool in RF mode at a rate of 0.31 Å/s.

This is followed by the sputter deposition of 5 nm of Ti (1 Å/s) for adhesion and 35 nm of Pt (4.26 Å/s) in DC mode and together they form the core. Finally, 7 nm of HfO2 is

RF sputtered at the same rate to complete the core-shell structure. The PR is then stripped off the substrate by sonicating in acetone. Acetone is cleared by IPA and water to reveal the finished layer as seen in Figure 4-5.

Figure 4-5. Layer 2 of prototype 4 where wires intersecting with those of Layer 1 were exposed.

To isolate the core-shell nanowires from top electrode vias, 40 nm of Al2O3 is deposited in the ALD using a thermal recipe at 200°C at a rate of 1 Å/cycle.

4.1.5.3. Layer 3

A4 PMMA was spun at 2000 rpm to get a 300 nm thick PR and was baked at 180°C to pattern layer 3, where circles (8 μm diameter) are exposed on the nanowires to etch

Al2O3 for top electrical contact.

The pattern (Figure 4-6) was exposed at 20 keV accelerating voltage, 20 μm

2 aperture, 10 nm step size with an area dose of 300 μC/cm ; and was then developed in the previously mentioned MIBK and IPA mixture for 30 s. The substrate is placed on a clean Si test wafer to etch Al2O3 in a Trion RIE/ICP for 233 s using BCl3 as etchant.

The PR is then stripped off the substrate by sonicating in acetone. Acetone is cleared by IPA and water.

Figure 4-6. Layer 3 of prototype 4 with electrode circles (6 μm diameter) before etching 40 nm of Al2O3.

4.1.5.4. Layer 4

A6 PMMA was spun at 4000 rpm to get a 600 nm thick PR and was baked at 180°C to pattern layer 3, where circles, electrode vias and electrode pads are exposed for top electrical contact. The electrode vias were exposed at 30 keV accelerating voltage, 20

μm aperture, 20 nm step size with an area dose of 600 μC/cm2. The diameter of the electrode circles was reduced to 6 μm from 8 μm and similar conditions was used as the electrode vias but with a dose factor of 0.6 to reduce the area dose to 360 μC/cm2. Finally, the electrode pads were exposed at 30 keV accelerating voltage, 60 μm aperture, 80 nm step size with an area dose of 380 μC/cm2. The substrate was then developed in the previously mentioned MIBK and IPA mixture for 30 s before depositing 15 nm of Ti (1 Å/s) and 100 nm of Pt (4.26 Å/s). The PR is then stripped off the substrate by sonicating in

acetone. Acetone is cleared by IPA and water to reveal the finished layer as seen in

Figure 4-7.

Figure 4-7. Final device image of prototype 4.

Table 4-1. List of tools used to fabricate prototype 4.

Step Tool used Purpose/Details number

Spin 165 nm of A4 PMMA at 4000 rpm 1 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 2 lithography (Layer 1) aperture, 5 nm step size

3 MIBK:IPA = 1:3 solution Develop for 30 s

4 Nikon LV100 Inspection/optical microscopy

5 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

7 nm HfO2, 5 nm Ti, 35 nm Pt and 7 nm 6 KJL sputter tool HfO2

7 Acetone, IPA, DI water Liftoff

Table 4-2. Continued

Step Tool used Purpose/Details number

8 Nikon LV100 Inspection/optical microscopy

9 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

Spin 165 nm of A4 PMMA at 4000 rpm 10 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 11 lithography (Layer 2) aperture, 5 nm step size

12 MIBK:IPA = 1:3 solution Develop for 30 s

13 Nikon LV100 Inspection/optical microscopy

14 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

7 nm HfO2, 5 nm Ti, 35 nm Pt and 7 nm 15 KJL sputter tool HfO2

16 Acetone, IPA, DI water Liftoff

17 Nikon LV100 Inspection/optical microscopy

18 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

40 nm Al2O3, 1 Å/cycle thermal 19 Atomic layer deposition deposition rate

Spin 300 nm of A4 PMMA at 2000 rpm 20 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 21 lithography (Layer 3) aperture, 10 nm step size

22 MIBK:IPA = 1:3 solution Develop for 30 s

23 Nikon LV100 Inspection/optical microscopy

24 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

25 Trion RIE/ICP BCl3 etchant for 233 s

26 KJL sputter tool 4 nm HfO2

Table 4-3. Continued

Step Tool used Purpose/Details number

27 Acetone, IPA, DI water Liftoff

28 Nikon LV100 Inspection/optical microscopy

29 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

Spin 600 nm of A6 PMMA at 4000 rpm 30 Laurell spinner and bake at 180°C

Vias: 200 nm WF, 600 μC/cm2, 30 keV, RAITH e-beam 20 μm aperture, 20 nm step size, dose 31 lithography (Layer 3 and factor of 0.6 for layer 3 (reduced radius). 4) Pads: 380 μC/cm2, 30 keV, 60 μm aperture, 80 nm step size

32 MIBK:IPA = 1:3 solution Develop for 30 s

33 Nikon LV100 Inspection/optical microscopy

34 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

35 KJL sputter tool 15 nm Ti, 185 nm Pt

36 Acetone, IPA, DI water Liftoff

37 Nikon LV100 Inspection/optical microscopy

38 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

CHAPTER 5 COMPLEMENTARY RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES

In this chapter, to further investigate the effect of morphology on switching behavior, core-shell nanowires with Pt core and HfO2 shell were fabricated, as core-shell structure provides access to the oxide in the radial direction than in the axial direction and the conductive core assists in obtaining multibit memory capabilities [26], [27].

In this chapter, BRS and remarkably also CRS for the first time in core-shell nanowires is demonstrated. Here, both BRS and CRS can be operated by using certain threshold values. Additionally, several current conduction models by analyzing J – E curves for several resistance states will be discussed.

5.1. Electroforming

To induce BRS in metal oxide resistive switching devices, the process of electroforming must be performed. Here, the nanowire shown in Figure 5-1 are subjected to current stress or a high voltage to facilitate degradation of resistance of insulating materials. The dielectric breakdown is termed “soft”, since the high resistance state is recoverable [6]. In this work, the wires were probed electrically with a high voltage in sweep mode (170 mV/s) to induce electroforming. However, to prevent permanent dielectric breakdown, a compliance current of 10 μA/100 μA was used.

Figure 5-1. Fabricated core-shell nanowire: a) optical image of core-shell wires prior to the deposition of top electrodes (circular patterns), b) schematic of core (Pt)-shell (HfO2) wires indicating the probable evolution of oxygen vacancies between the core and the top electrodes (inset depicting formation of filament after electroforming), and c) SEM micrograph of a single wire with top electrode and vias (Image courtesy Eitan Hershkovitz from Dr. Honggyu Kim’s group).

5.2. Bipolar Resistive Switching (BRS)

The application of a triangular wave after electroforming results in eightwise BRS similar to some thin-film devices [43]–[45] and a core-shell nanowire system with HfO2 shell [26]. The device under bias undergoes a SET process where it transitions from a high resistance state (HRS) to a low resistance state (LRS) when the sweep voltage exceeds the threshold value. Due to the symmetric nature of this device, this transition can occur under positive or negative bias. For the memristor under consideration, SET transition occurred at a threshold value of ~+1 V. Subsequent negative bias sweep results in a RESET process where the device transitions from LRS to HRS as shown in

Figure 5-2. Cyclic voltammetry performed on the device displayed good reproducibility and stability of the devices as shown in Figure 5-3a. It has been established that resistive

switching in HfO2 is primarily due to the presence of oxygen vacancy filaments [43], [46]–

[48] and a similar behavior can be observed in this work. Work performed by Gonon et al. [49] on Au/HfO2/Pt thin-film system with 10 nm thick HfO2 revealed that due to a thin active layer, the filaments were eliminated during RESET causing fluctuations in RESET voltage. However, the device would SET at the same threshold voltage despite lack of filaments. Similarly, in this device it can be concluded, the RESET voltage is independent on the resistance of filaments.

150

100

100 SET A)

µ 50 LRS HRS 50

LRS 0 A)

µ SET -50 0 RESET HRS Current( -100

1 -50 Current( 0 RESET -100 V V -1 RESET SET

Voltage (V) -150 -2 -1 0 1 2 0 5 10 15 20 25 30 35 Time (s) Voltage (V) a) b) Figure 5-2. Electrical characterization in BRS mode: a) current and voltage change with time and b) I-V pinched hysteresis where SET occurs at 1.1 V and RESET occurs at -1.5 V with the compliance set at 100 μA.

Subsequently, to test the repeatability to store HRS and LRS in these devices, pulse measurements were performed. Figure 5-3b shows the endurance results for a pair of electrodes. For the memristor under test, SET and RESET voltage was kept constant at -1.5 V and 1.5 V for 0.5 ms while resistance was measured at 0.3 V after every SET and RESET pulse. The device was stable and displayed resistive switching even after switching on and off for 1000 cycles. This result, despite being much lower than the state-of-the art crossbar architecture (108 cycles) [8], is comparable to another

core-shell system (ITO/HfO2) [26]. Due to varying RESET current, the RESET resistance is unstable and noisy; however, the SET resistance does remain constant with an off-on resistance ratio ~ 13. This ratio is sufficient to have good learning accuracy during online training of these systems for neuromorphic computing. However, these systems will not be suitable as non-volatile memories as a higher resistance ratio (~100) is desired [1].

Thus, further confirming that RESET voltage is independent of the resistance of the filaments. To evaluate memory retention, a SET/RESET pulse was applied, and the state of the system was read at 10x intervals (where x=0, 1, 2, 3, etc.). The retention for this system was 104 s, as shown in Figure 5-3c.

200 1st Cycle 2nd Cycle 150 3rd Cycle 4th Cycle 100 5th Cycle 6th Cycle

A) 7th Cycle µ 50 8th Cycle 9th Cycle

10th Cycle 0

Current( -50

-100

-150 -2 -1 0 1 2 Voltage (V)

106 106 LRS LRS

HRS HRS

) )

 

5 5

10 10

Resistance ( Resistance (

4 10 4 10 0 250 500 750 1000 1 10 100 1000 10000 Cycle Time (s) b) c)

Figure 5-3. Electrical characterization in BRS mode (sweep and pulse schemes): a) subsequent 10 cycles displaying stable switching in the core-shell wires at a compliance of 100 μA; b) cyclic endurance obtained for 1000 cycles at pulse SET/RESET voltage of -1.5 and 1.5 V and a read pulse voltage of 0.3 V; and c) resistance retention obtained for 104 s for both LRS and HRS after reading the state of the system by applying a read pulse at 0.3 V after either a SET pulse of -1.5 V or a RESET pulse of 1.5 V.

Despite these results being nowhere near the performance of the best systems reported in literature, they are definitely a step in the right direction towards obtaining a retention of 10 years when the data is extrapolated as observed Lee et al. [50], [30], and

Jiang et al. [8]. This is particularly relevant considering that since the HfO2 is sputtered, a non-conformal amorphous layer may be present. Also, at low thickness like in this work, the thickness may also not be even across the length of the wire.

Although oxides are insulators, conduction of charge through them enables resistive switching to occur. To explain carrier transport in insulators, several mechanisms exist namely: space-charge-limited conduction, ionic conduction, ohmic conduction, Frenkel-Poole emission, thermionic emission, tunneling [51] and hopping conduction [42], [52]. Plotting current density to electric field (J – E) curves will enable us

to realize the carrier transport mechanism in this device. In the J – E curves for the HRS region of the first 10 cycles (not shown here) were observed, in the low-field region the current density is linearly proportional to the field. However, the device shows an exponential increase in current density in the high-field region. An exponential fit for the first cycle aligns this behavior with thermionic emission model. Also, the exponential increase in current density begins earlier as the cycles progress. This could be due to residual charges from previous cycles. However, overtime when the charges dissipate due to repeated cycling, the curve relaxes, and current density gradually increases.

Thermionic emission mechanism assumes that there is a thermal equilibrium at the plane of emission and postulates that the barrier profile shape is irrelevant, and the barrier height determines current flow.

Also, the metal-semiconductor (HfO2 in this case) barrier height is the same under bias for electrons. Therefore, the current flowing into the semiconductor is unaffected by voltage however, the current flowing out into the core electrode reaches an equilibrium.

This manifests physically in the formation of filaments in the oxide between the electrodes.

A linear behavior in a ln(J) vs E1/2 plot confirms that the conduction behavior is via thermionic emission and can be observed in Figure 5-4a. A linear fit for the first cycle is shown in the inset of Figure 5-4b.

A plot of ln(J) vs E1/2 for the HRS region is shown in Figure 5-4a. A linear fit for the first cycle as shown in Figure 5-4b is consistent with conduction behavior via thermionic emission. This is based on the thermionic emission equation provided in

Figure 5-4b.

15 15 1st Cycle Linear fit

10 10 1st Cycle 2nd Cycle 3rd Cycle

5 4th Cycle 5 ln(J) ln(J) -q(ϕ -√qE/4πε) 5th Cycle J = A**T2exp [ B ] 6th Cycle kT 7th Cycle 0 9th Cycle 0 10th Cycle 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 1/2 1/2 E E a) b)

Figure 5-4. Current conduction mechanism in HRS: a) ln(J) vs E1/2 plot of HRS for 10 BRS cycles and b) linear fit of data for the first cycle in a) and this corresponds to thermionic emission conduction mechanism in HRS.

4 4 1st Cycle Linear fit 2

) 2 2

0 )

A/cm 0 6 -2 1st Cycle 6th Cycle -∆Eac 2nd Cycle 7th Cycle J ∝ Eexp [ ] kT

J (A/cm -2 J(10 -4 3rd Cycle 8th Cycle 4th Cycle 9th Cycle 5th Cycle 10th Cycle -6 -4 -1500 -750 0 750 1500 3 -1500 -750 0 750 1500 E (10 V/cm) 3 E (10 V/cm) b) a)

Figure 5-5. Current conduction mechanism in LRS: a) J vs E plot of LRS for the 10 BRS cycles and b) linear fit of data for the first cycle in a) and this corresponds to Ohmic conduction mechanism in LRS.

J – E curves for the LRS region of the first 10 cycles is shown in Figure 5-5a. Here there exists a linear relationship between current density and applied field. Figure 5-5b shows the linear fit for the LRS region of the first cycle. This behavior aligns with ohmic conduction mechanism (equation in Figure 5-5b) of charge through the oxide. In this

mechanism, the electrons that are thermally excited, travel by hopping through subsequent isolated states.

This is confirmed in prior studies performed on HfO2 in thin-film memristors [43],

[53]. Here they concluded that when a continuous filament forms within the oxide, thermionic emission mechanism fades and Ohmic conduction becomes the dominant charge transport mechanism. In conclusion for BRS, the wires exhibit thermionic emission mechanism in HRS and Ohmic conduction mechanism in LRS.

5.2. Complementary Resistive Switching (CRS)

Based on the cross-section schematic of these devices as shown in Figure 5-6a, it can be implied that there exists two memristors (Figure 5-6b) between two top electrodes and the previously described BRS behavior only corresponds to the switching of one of them. Therefore, further investigation was done to observe CRS behavior.

a) b)

Figure 5-6. Core-shell nanowires structural schematic: a) the cross-section detailing the several layers present in the core-shell wire and b) an equivalent circuit diagram representing two memristors of similar polarity connected in an anti-serial manner.

Initially, a new core-shell wire was electroformed at a compliance current of 10 μA and subsequently eightwise I-V behavior was observed between 2 V and -2 V as shown in Figure 5-7a. Next, when the wire was biased starting on the negative direction, counter

eightwise behavior was observed between -3 V and 2 V as shown in Figure 5-7b.

Although, despite forming at 10 μA, the switching in some instances was unstable and the wires had to be electroformed again at 100 μA to have stable switching. This essentially results in a device that behaves as a voltage divider and when operated between determined voltage thresholds, a combined electrical response from both memristors is obtained.

20 10 LRS RESET

A) 10 µ SET A) 0 µ HRS HRS 0 SET -10 Current ( LRS Current ( -10 RESET V V RESET SET V V -20 SET RESET -2 -1 0 1 2 -20 Voltage (V) -3 -2 -1 0 1 2 Voltage (V) a) b)

Figure 5-7. Types of observed BRS curves: a) eightwise BRS for memristor B and b) counter eightwise BRS for memristor A.

It is imperative to determine all threshold values to operate the device. After testing the device at several threshold potentials, 2 V was determined to give the best result as shown in Figure 5-8a. Subsequent 10 stable cycles are shown in Figure 5-8b. After forming, memristor A is in LRS and when V>V1 is applied, memristor B switches on and a large spike in current is seen due to both memristors being in LRS. Next, after crossing

V2, memristor A switches off and effectively acts as a resistor leading to a reduction in the current flowing through the device. At V3, memristor A switches on resulting in increased current flow again. Finally, at V4, memristor B switches off and the current reduces again returning the device back to its original state. Unlike BRS, where information is stored in

either HRS or LRS, complementary resistive switches are programmed by accounting for the states of both memristors.

Information is stored in states 0 and 1, where in state 0 memristors A is in HRS and memristor B is in LRS respectively and vice-versa in state 1. The device is said to be ON when both memristors are in LRS.

200 200 1st cycle

100 100

A) µ µ V V

4 3

0 0 V V 1 2 -100 -100 10th cycle

Write Current ( Current ( Write Read "0" -200 "1" -200 5th cycle

-2 -1 0 1 2 -2 -1 0 1 2 Voltage (V) Voltage (V) a) b)

Figure 5-8. Electrical characterization in CRS mode: a) CRS behavior observed in core-shell Pt/HfO2 system with “0” and “1” as two defined states to store information b) next 10 cycles.

To understand the charge transport mechanism in states 0 and 1, J – E curves were plotted. Figure 5-9a shows a plot of ln(J) vs E for the 10 CRS cycles. A linear behavior observed in high electric field region in ln(J) vs E plot (Figure 5-9b) in state 0 corresponds to hopping conduction mechanism. This has been previously confirmed for

CRS state 0 in IrOx/GdOx/Al2O3/TiN crossbar system [42]. In this mechanism, electrons hop from one vacancy to another to enable conduction. Current density, J is defined as follows according to this mechanism,

qλE-E J=qnλfexp ( a) (5-1) kBT

where, q is electron charge, n is electron concentration in the conduction band, f is thermal vibration frequency of trapping sites, E is electric field, kB is Boltzmann constant, T is absolute temperature, λ is mean hopping distance, and Ea is activation energy. From Equation (5-1) the hopping distance is calculated to be approximately 0.39 nm which is in accordance with a study performed by Chen et al. [54]. In their system

(Pt/Zn:SiO2/TiN), hopping distance varied from 1.4 to 0.3 nm when current compliances was varied between 10 and 100 μA.

However, the conduction mechanism in state 1 is obtained by plotting J vs V2 for the 10 CRS cycles as shown in Figure 5-9c. A proportional change of current density to the square of electric field is observed and a linear fit to the first cycle can be seen in

Figure 5-9d. This behavior corresponds to space-charge-limited conduction mechanism

(equation is shown in Figure 5-9d). Although not observed in CRS systems, it has been observed in core-shell Au/Ga2O3 BRS system [25]. In this mechanism, mobility of electrons dominate as there is low carrier concentration due to low doping and traps.

Also, current conduction increases once the carriers fill the traps, and the excess carriers move into the conduction band. In conclusion for CRS, the wires exhibit hopping conduction mechanism in state 0 and space-charge-limited conduction mechanism in state 1.

As mentioned earlier, some wires despite forming at 10 μA did need to be electroformed again at 100 μA. This could be because of thinner filaments forming at lower compliances which can be unstable and dissipate under repeated cycling and thereby needing a higher compliance while forming. It is important to note that when the

wire is operated in CRS mode, it is self-complianced, i.e., a compliance current is not needed to limit current flow in the wire. This is because when the wires are biased, except during the ON states when both memristors are in LRS, at least one memristor is in HRS in states 0 and 1. As a result, the memristor that is in HRS acts as a resistor and limits the current flow in the wire.

1st Cycle 15 15 Linear fit

10 10

1st Cycle 6th Cycle qλE-Ea

2nd Cycle 7th Cycle J=qnλfexp [ ] ln(J) ln(J) 5 kBT 3rd Cycle 8th Cycle 4th Cycle 9th Cycle 5 5th Cycle 10th Cycle 0 0 0 750 1500 2250 3000 0 750 1500 2250 3000 3 3 E (10 V/cm) E (10 V/cm) a) b)

5 1st Cycle 1st Cycle 6th Cycle 3 Linear fit 4 2nd Cycle 7th Cycle 3rd Cycle 8th Cycle

4th Cycle 9th Cycle )

2 3

5th Cycle 10th Cycle ) 2 2

A/cm 2 6 9εμV2 1 J=

1 J(A/cm 8d3 J(10

0 0 0 1 2 3 4 0 1 2 3 4 V2 V2 c) d)

Figure 5-9. Current conduction mechanisms in CRS mode: a) ln(J) vs E plot of state 0 for the 10 CRS cycles, b) linear fit of data for the first cycle in a) and this corresponds to hopping conduction mechanism, c) J vs V2 plot of state 1 for the 10 CRS cycles and d) linear fit of data for the first cycle in c) and this corresponds to space-charge-limited conduction mechanism.

It is known that to transition into HRS state from LRS in a BRS device, appropriate threshold voltage and lack of compliance is required. This can be translated to CRS devices when memristor A which is already in LRS, transitions to HRS when the current is high at V4 of ~200 μA. Since operating energy consumption must be kept low wires showing stable BRS were made to exhibit CRS type behavior. From Figure 5-10 it can be clearly seen that the device formed at a lower compliance (Figure 5-10a) clearly has a lower peak current than the one formed at a higher compliance (Figure 5-10b). This knowledge can help us in building low energy consuming devices in the future.

40 200

A) 100

µ A) 0 µ

0 -20

Current ( -100 -40 Current ( -200 -60 -2 -1 0 1 2 -2 -1 0 1 2 Voltage (V) Voltage (V) a) b)

Figure 5-10. Effect of compliance current during initial BRS forming on peak current in CRS mode: a) CRS behavior when initial BRS was SET at a compliance of 10 μA and b) CRS behavior when initial BRS was SET at a compliance of 100 μA.

The formation of oxygen vacancy filaments and their effect on resistive switching in HfO2 devices has been discussed in prior studies [55], [56]. From the above results and literature, a soft breakdown of the oxide layer can be anticipated during the forming process leads to the formation of a filament between one of the top electrodes and the metallic core. This filament leads to conduction of charge between the nodes and subsequently, bipolar resistive switching. A similar formation of conductive filaments

under the other top electrode and the core is the likely cause for C8W and 8W BRS to exist.

Finally, when the nanowire is operated under the set thresholds, CRS can be achieved in these nanowires. A follow up transmission electron microscopy (TEM) study can help us analyze the conduction mechanism in this core-shell structure.

5.3. Conclusion

In summary, both BRS and CRS type of resisive switching was remarkably achieved in these systems. Either type of switching behavior can be employed based on the applied threshold voltages. Under BRS mode, pulse operations resulted in an endurance of 1000 cycles and memory retention of upto 104 s. Also by analyzing J vs E curves, the conduction mechanism in HRS was determined to be thermionic emission and the mechanism in LRS was determined to be ohmic. Under CRS mode, the conduction mechanism in state 0 is via hopping of electrons and the mechanism in state

1 was determined to be space-charge-limited. It was also observed that the operating current can be lowered by forming the wires at a lower compliance current thereby making them a potential candidate for low energy neuromorphic devices.

CHAPTER 6 IMPLICATIONS OF RESISTIVE SWITCHING MECHANISMS IN CORE-SHELL NANOWIRES

Resistive switching in HfO2 ReRAM devices has been attributed to the formation of conductive filaments due to the movement of oxygen vacancies under applied bias

[91]–[93]. This phenomenon is termed as valence change mechanism (VCM) and excellent reviews for ReRAM devices has been provided by Ielmini and Waser [9], Yang and Lu [26] and Sawa [25]. Detailed description of VCM is provided in chapter 2. In this chapter, energy dispersive spectroscopy (EDS) obtained from a scanning transmission electron microscope (STEM) will be analyzed to determine approximate stoichiometry at various interfaces. Utilizing this analysis, a schematic depiction of the mechanism involved in the different types of resistive switching will be discussed. The schematics shown here are exaggerated and are not to scale. Here, SET transitions are usually marked with accumulation of oxygen vacancies and the formation of the filament to place the node in LRS. RESET transitions are usually marked with the breaking of the filament to place the node in HRS.

6.1. TEM of Core-shell Nanowires

The electrodes chosen for the core and top electrical contact serve different roles when used adjacent to HfO2. Ti absorbed oxygen and enabled oxygen vacancy movement when used as a buffer layer by Lee et al. [20] Additionally, when Lee et al.

[24] analyzed the depth profile of Pt/HfO2/Au system using X-ray photoelectron spectroscopy, the spectrum revealed that oxygen (O 1s) peak intensity decreased rapidly as the depth profile deepened leading to nonstoichiometric film with oxygen deficiencies.

Ultimately, at the Pt/HfO2 interface the film was reduced to Hf and the oxygen peak disappeared. Therefore, from above results it can be inferred that Ti absorbs oxygen and

Pt repels oxygen which potentially leads to the formation of a conductive filament in the oxide layer [20], [24].

The STEM-EDS image of the region of interest shown in. Figure 6-1a confirms the presence Pt core, HfO2 shell, Ti/Pt top electrical contacts, and some residual Al2O3. The

HfO2 shell here was amorphous as no crystallographic orientation was discovered. From the line scan performed through the center as shown in Figure 6-1b, atomic fraction can be extracted at locations in a 45 nm × 9 nm area. As expected, oxygen is absorbed into the Ti top electrode and an oxygen gradient, increasing in atomic fraction from the Pt/Ti interface to the Ti/HfO2 interface is observed. This subsequently results in a decrease in oxygen concentration in the HfO2 layer. At the HfO2/Pt interface at the line scan distance of 31.87 nm, the hafnium oxide is sub-stoichiometric (HfO1.187) indicating a lack of oxygen and the presence of oxygen vacancies. The fraction of oxygen then steadily increases until the Ti/HfO2 interface. However, at the interface no clear distinction can be made between the electrode and the oxide. Therefore, at this interface, sub-stoichiometric oxides of Ti and Hf exist. Beyond this, oxygen diffusion slows down until the Pt/Ti interface is reached. The approximate atomic fractions extracted at interfaces is summarized in Table 6-1. Subsequently, using this analysis, schematics are presented to provide an atomistic view in comparison to the electrical data at different resistance states.

The conclusions obtained here are based on observing the interfaces after the nanowire was used for electrical characterization and not as deposited. The nodes under investigation had already undergone permanent breakdown post electrical characterization.

20 0.8

15 0.6

O Al 0.4 10 Ti Hf Pt 0.2

5 HAADF (kCounts)HAADF

0.0 (%) Atomic Fraction HAADF 0 0 10 20 30 40 50 60 Position (nm)

Figure 6-1.STEM analysis of core-shell nanowires: a) EDS map of the region of interest and b) atomic fraction from line scan. (Image courtesy Eitan Hershkovitz from Dr. Honggyu Kim’s group).

Table 6-1. Summary of stoichiometry at various interfaces Position on Atomic Interface Elements Stoichiometry the scan (nm) fraction (%)

Hf = 34.326 Pt/HfO2 Hf, O 31.87 HfOx O = 40.785

Hf = 26.39

HfO2/Ti Hf, O, Ti, 25.50 Ti = 17.47 TiOx, HfO2-x

O = 46.47

Ti = 57.49 Ti /Pt Ti, O 13.06 TiOx O = 24.44

The imaging via SEM and S/TEM was done at the once all nanowires had undergone permanent breakdown. This was done to preserve the pristine nature of the nanowire for electrical characterization as exposure to the electron beam in the microscopes could have induced breakdown.

From line scan plots in Figure 6-1b, the Ti/HfO2 is gradual and not abrupt. This could be a result of roughness of the deposited amorphous HfO2 surface. When HfO2 is sputtered from a HfO2 target and not via reactive sputtering, the substrate may contain

HfO2 and Hf metal in the deposited material. Additionally, Gruger et al. [128] estimated a root mean square roughness of 1.5 nm in as deposited 100 and 150 nm amorphous HfO2 films. Although, the deposition was considered even and the surface roughness is minimal when compared to the thickness of the film, if an equivalent roughness is present in this work it may have a significant impact on the Ti/HfO2 interface and subsequently, resistive switching. As the thickness of HfO2 in this work is 7 nm, a potential surface roughness of 1.5 nm can reduce endurance due to formation of shorter filaments that undergo permanent breakdown at high electric fields. The HfO2 shell has not been

annealed which could also be a factor, since Vargas et al. [129] observed that the root mean square roughness reduces by annealing and with increasing annealing temperatures.

Formation of vacancies by the applied field is highly unlikely in resistive switching devices as observed by Schie at al. [130] and Strand et al. [131]. Atomistic simulations performed by both concluded that the energy required for the formation of oxygen vacancies is ~6 eV [130]–[132]. The formation energy reduced only to ~ 5.9 eV by the application of 10 MV/cm bias which was still not enough to create vacancies [131] and only the application of 30 MV/cm resulted in sporadic defect formation [130]. This, however, is too high when compared to the fields applied in this work (see Chapter 5).

To achieve this field, a potential of at least 21 V must be applied to induce defect formation however, resistive switching occurs despite that at bias voltages < 2 V. Therefore, there must be other factors influencing defect formation. The Ti deposited on top of the HfO2 acts as an oxygen getting layer and as-deposited films have shown no significant oxygen concentration in previous works [133], [134]. Also, Panda et al. [135] observed no distinct separation between Ti and HfO2 layers after deposition. Usually in most works, the oxygen is absorbed into the Ti electrodes by annealing the samples at high temperatures thereby, creating vacancies [14], [16], [17]. Additionally, despite the stability of HfO2, Ti top electrode is capable of forming several sub-oxides due to comparable formation enthalpies. Therefore, in this work, Ti scavenges oxygen from HfO2 and results in the formation of oxygen vacancies [137]. Once the vacancies are formed, their movement can be controlled by the application of bias via redox reactions occurring at the Ti/HfO2 interface [135], [138].

Although it is known that clustering of oxygen vacancies result in resistive switching, ab initio modelling performed by Magyari-Kope et al. [139] has suggested the presence of nanofilaments in a larger filament. They suggested that during the SET transition, the filaments aggregate to conduct charge and during RESET transition the filaments dissipate. This contrasts with other filamentary models proposed where the filament breaks only at the electrode [93], [101], [140]. Additionally, some studies have also reported the presence of Hf nanoparticles [101] or Hf filaments [141] enabling resistive switching. Moreover, increased vacancy concentration like in this work at the

HfO2/Pt interface also results in increased Hf concentration. Therefore, from literature

[52], [137] it can be inferred that in this work that the filament of vacancies is wider at the

HfO2/Pt interface and narrower at the Ti/HfO2 interface. This, however, must be confirmed in the core-shell nanowires used in this work by performing EELS on a cross- section [141], [142]. Ultimately, this behavior is similar to valence change mechanism described earlier in chapter 2. Therefore, using this analysis, schematics are presented to provide an atomistic view in comparison to the electrical data at different resistance states.

6.2. Bipolar Resistive Switching

Bipolar resistive switching is observed in many HfO2 systems [42], [43], [55], [59],

[66], [84], [93], [140], [143]–[145] with resistive switching occurring at two different polarities and as mentioned earlier, it is of two types 8W and C8W. Beginning with the device in pristine condition as shown in Figure 6-2a, the state of the system for both the

Ti electrodes (nodes) is HRS. Bias is applied via Au probes onto electrode pads. Upon the application of positive bias in small increments with a compliance current, as indicated with an example in Figure 6-2b, it has been established from S/TEM analysis that oxygen

atoms diffuse into the Ti electrode resulting in the in the formation of vacancies. Since oxygen vacancies are positively charged, they are repelled away from the Ti electrode and begin to accumulate at the HfO2 shell/Pt core interface. Once formed, the device can undergo a SET transition with a positive sweep bias once a threshold voltage is crossed.

The current flowing through is controlled by setting a compliance current to limit the flow of current beyond the desired threshold. Here, the oxygen vacancy filament is complete and extends from the Pt core to the Ti top electrode as shown in Figure 6-2c. Finally,

RESET transition is induced by applying a negative sweep bias at a higher compliance current. This higher current causes the filament to break and the oxygen vacancies to either dissipate or recombine with the oxygen in Ti top electrode resulting in HRS as shown in Figure 6-2d. The type of BRS obtained from this operation is an 8W switch.

d) Figure 6-2. Schematics detailing switching mechanism in BRS mode under one node of a core-shell nanowire: a) pristine wire, b) forming, c) 8W SET, and d) 8W RESET.

Subsequently, when one node is formed, the other one undergoes SET transition sweep bias of the opposite polarity is applied as shown in Figure 6-3a. A point to note here is, the negative bias applied is negative relative to the probe that is in contact with the electrode on the right (in this example). As a result, when biased, oxygen drifts into

Ti and vacancies drift towards HfO2 shell/Pt core interface in a similar fashion as described before. To induce RESET transition in this node, a positive sweep bias is applied at a higher compliance as shown in Figure 6-3b. As before, this causes the oxygen vacancies to break away from the filament resulting in the HRS. The type of BRS obtained from this operation is a C8W switch.

b) Figure 6-3. Schematics detailing switching mechanism in BRS mode under the other node of a core-shell nanowire: a) C8W SET, and b) C8W RESET.

6.3. Complementary Resistive Switching

Complementary resistive switches have been obtained when two similar resistive switches are connected in an anti-serial manner, i.e. the device must contain an 8W and a C8W switches. An example of CRS curve discussed in chapter 5 is shown in Figure 6-

4. The different states in a complementary switch was adapted from Linn et al. [35] and is summarized in Table 6-2.

Utilizing the scheme provided in Table 6-2 an atomistic view can be extracted for the nanowire at different locations on the CRS curve shown in Figure 6-4. In this work,

CRS was always observed after electroforming and operating the nanowires in either of the BRS modes (8W or C8W).

200

100 A) µ V V

0 4 3

V V 1 2 -100 Current( Write Write Read "0" -200 "1"

-2 -1 0 1 2 Voltage (V)

Figure 6-4. CRS behavior observed in core-shell Pt/HfO2 system with “0” and “1” as two defined states to store information.

Table 6-2. Summary of CRS states based on the state of both memristors in a core- shell nanowire. (Adapted from Linn et al. [146]).

Voltage A B R of CRS CRS STATE

0 V OFF ON ≥ROFF “0” 0 V ON OFF ≥ROFF “1”

Read “0” V>V1 OFF ON ≥ROFF “0” Read “1” ON ON RON+RON “1”→”0” V>V1

Write “0” V>V2 OFF ON ≥ROFF “0” Write “1” ON OFF ≥ROFF “1” V

6-6a. This clearly implies that memristor B (8W switch) is in HRS and therefore the system as a whole is in a lower HRS. However, the resistance is high enough for current conduction to be limited. Once the first threshold is reached memristor B undergoes a

100

SET transition as shown in Figure 6-6b, since the voltage exceeds the threshold for this switch.

Figure 6-5. Schematics detailing switching mechanism in CRS mode utilizing both nodes of a core-shell nanowire: a) memristor A in LRS and memristor B in HRS, b) memristor A in LRS and memristor B in LRS.

This places the nanowire in position 2 and in a new state termed as ON where both the memristors A and B are in LRS where the current flow is high. Once the bias sweep crosses the second threshold as shown in Figure 6-6a, at position 3, memristor A has undergone a RESET transition since it is a C8W switch. This places the nanowire again in a lower HRS and limits the conduction of current. Next at position 4 as shown in

101

Figure 6-6b, the SET transition occurs in memristor A when the bias sweep crosses the third threshold voltage, the nanowire is returned to the ON state where both memristors are in LRS and conduction of current is high.

Finally, once the bias sweep crosses the fourth threshold voltage, into position 5 as shown in Figure 6-6c, a RESET transition occurs in memristor B and the nanowire is placed back in the state it began this operation with. It must be understood that current only flows when both the memristors are in LRS, otherwise the current conduction is low.

This is because the memristor that is in HRS acts as a resistor preventing the flow of charge.

102

c) Figure 6-6. Schematics detailing switching mechanism in CRS mode utilizing both nodes of a core-shell nanowire: a) memristor A in HRS and memristor B in HRS, b) memristor A in LRS and memristor B in LRS, and c) memristor A in LRS and memristor B in HRS.

6.4. Conclusion

In summary, STEM-EDS analysis revealed, upon resistive switching operation, Ti absorbed oxygen from the HfO2 leading to a sub-stoichiometric distribution of the HfO2 which results in the formation of oxygen vacancy filament. From STEM-EDS analysis, atomistic views of SET and RESET transitions in BRS mode and subsequently, the atomistic view of the nanowire in CRS mode is discussed. The schematics were drawn based on valence change mechanism leading to the formation of filaments for current conduction.

103

CHAPTER 7 ARTIFICIAL SYNAPTIC RESPONSE AND EFFECT OF TEMPERATURE ON BIPOLAR RESISTIVE SWITCHING IN CORE-SHELL NANOWIRES

As mentioned earlier in Chapter 2, neurons in the brain are connected through synapses to each other. Learning and memory retention in these synapses is controlled by the dynamic changes to their strength [72], [73]. This strength is varied by impulse spikes in the network [74]. Memristors as artificial synapses, as a minimum can be used to store one bit of memory by using it as a switch, where the state of the system is changed from LRS to HRS by the application of a voltage pulse [28]. Additionally, due to the analog nature of the synaptic states in artificial synapses, multilevel states can be extracted. Generally, the more states there are the better as it improves the robustness of the network. Previously, in chapter 5, pulsed voltage resulted in an ON-OFF endurance behavior of at least 1000 cycles thereby indicating the presence of a binary synapse. In this chapter, pulsed synaptic potentiation and depression in BRS mode and pulsed synaptic programming in CRS mode will be discussed. Subsequently, the effect of temperature on the conduction process and resistive switching will also be discussed.

7.1. Artificial Synaptic Response in BRS and CRS Mode

7.1.1. Potentiation and Depression in BRS Mode

To achieve practical implementation of artificial synapses in the nanowire, pulse voltage inputs must be used instead of a DC voltage sweep. It is imperative to identify the amplitude of the voltage pulse, as a higher amplitude pulse will result in sharper increase in resistance thereby reducing the number of states and a smaller amplitude pulse will result in no change to the resistance of the node [42], [147].

The node under investigation exhibits counter eight wise switching as show in

Figure 7-1 and the subsequent bias determination for synaptic weight update is shown in

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Figure 7-2. For potentiation, at a constant pulse width of 0.5 ms, voltage was varied between -0.1 V and -0.9 V in steps of 0.01 V. Although the change in resistance was gradual with the increase in bias, a large drop in resistance was observed at -0.64 V.

Since the bias should be just enough to cause a resistance change, -0.6 V was used as the biasing voltage for potentiation here. For depression, at the same constant pulse width of 0.5 ms, voltage is varied between 1 V and 0.2 V. Here, the increase in resistance was gradual and no clear change is observed. However, upon further investigation of depression attempted between 0.8 V and 1 V, 0.8 V was selected for operation as it provided gradual increase in resistance/decrease in current.

) 20

A µ

-20 Current( -40

V V -60 SET RESET

-1.0 -0.5 0.0 0.5 1.0 1.5 Voltage (V)

Figure 7-1. 8W BRS switch under investigation.

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1.0x105 5 Depression Potentiation 1.5x10

8.0x104

)

 ) 5  4 1.0x10

6.0x10

4.0x104

5.0x104 Resistance (

2.0x104 Resistance (

0.0 0.0 0.2 0.4 0.6 0.8 1.0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Voltage (V) Voltage (V)

a) b) Figure 7-2. Determination of bias for synapses: a) potentiation and b) depression.

With bias values known, a pulse train as shown in Figure 7-3a and b was applied to achieve potentiation (-0.6 V) and depression (0.8 V) at constant voltage pulse width of

0.5 ms duration while the state of the system is read at 0.15 V. Analog modulation of conductance due to the pulse train can be seen in Figure 7-3c. Two outcomes can be observed from Figure 7-3c: there is a quasi-continuous change in conductance and the dependance of conductance of the memristor on the applied bias history. For instance, here a train of -0.6 V pulses causes a gradual increase in conductance, which strengthens the synapse resulting in long-term potentiation.

Potentiation @ -0.6 V Depression @ 0.8 V 0.2 0.8

0.0 0.000 0.005 0.010 0.015 0.6

Time (s)

-0.2 0.4

-0.4 (V) Voltage Voltage Voltage (V) 0.2

-0.6 0.0 0.000 0.005 0.010 0.015 Time (s)

a) b)

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1.0

0.5

0.0 Potentiation @ -0.6 V

Normalized Conductance Depression @ 0.8 V 0 50 100 Pulse no.

c) Figure 7-3. Potentiation and depression in an 8W switch: a) pulse scheme for potentiation, b) pulse scheme for depression, and c) potentiation using - 0.6 V for 75 pulses and depression using 0.8 V for 25 pulses.

The conductance saturates at 75 pulses. Subsequently, a train of 0.8 V pulses caused a gradual decrease in conductance, which weakens the synapse resulting in long- term depression. The current saturates after 25 pulses. In total, at least 3 distinct conductance states can be achieved in both potentiation and depression.

Similarly, for another node exhibiting C8W resistive switching, constant voltage pulse for potentiation and depression was determined to be 0.9 V and -0.8 V, respectively.

The state of the system was read at 0.15 V. The train of constant pulses applied is shown in Figure 7-4 where potentiation was achieved after 50 pulses and depression was achieved after 25 pulses. In total, at least 3 distinct states can be achieved in both potentiation and depression.

The dynamic range or the ON-OFF ratio for the 8W switch and the C8W switch is calculated to be ~15 and ~11, respectively. This indicates that the nodes have a potential

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to possess 15 or 11 synaptic states with the minimum weight update for the 8W and C8W switch would then be 0.067 and 0.091.

1.0

0.5

0.0 Potentiation @ 0.9 V

Depression @ -0.8 V NormalizedConductance 0 25 50 75 Pulse no.

Figure 7-4. Potentiation using 0.9 V for 50 pulses and depression using -0.8 V for 40 pulses in a C8W switch.

However, based on application, total synaptic states >100 maybe desirable due to improved mapping capabilities [11]. Due to the testing equipment limitation, the lowest pulse width was 0.5 ms. Therefore, in the future a solution to improve the number of states in these nanowires should be to use shorter pulses in the 50 ns – 10 μs range.

Additionally, it is also observed that the weight update in both 8W and C8W switch is asymmetric and non-linear. The rapid change in conductance in the beginning and saturation at the end along with different trajectories for potentiation and depression are all characteristics of a realistic artificial synapse. This has previously been observed by

Chen et al. [148] in their TaOx/TiO2 crossbars devices and Woo et al. [84] in

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TiN/HfO2/Ti/TiN stack. This asymmetry, however, can be attributed to abrupt changes in conduction due to the movement of vacancies forming the filament. In prior works, a gradual SET process induced due to the addition of an AlOx layer adjacent to the HfO2 layer has helped in improving symmetry and linearity [84]. Despite the non-ideal nature of these synapses, these wires can still be used for training and implementation in neuromorphic architectures.

It must be noted that the mechanism for the synaptic potentiation and depression is the same for both 8W and C8W switch. Here, potentiation and depression of an 8W switch was chosen as an example as shown in Figure 7-5a. During potentiation the device was initially in HRS (Figure 7-5b) and since a filament already exists, the application of constant bias causes the oxygen vacancies to migrate towards the electrode to complete the filament as shown in Figure 7-5c. Once the filament is complete

(Figure 7-5d), potentiation reaches saturation. During depression, the reverse process occurs, where the application of constant bias causes oxygen vacancies to migrate away from the electrode (Figure 7-5c) until the original HRS is reached (Figure 7-5d).

3 1.0

2 4

0.5

5 1 0.0 Potentiation @ -0.6 V

Normalized Conductance Depression @ 0.8 V 0 50 100 Pulse no.

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b) c) d) Figure 7-5. Schematic for potentiation and depression in BRS mode: a) potentiation and depression of an 8W switch, b) schematic corresponding to positions 1 and 5 in a), c) schematic corresponding to positions 2 and 4 in a), and d) schematic corresponding to position 3 in a).

7.1.2. Synaptic Behavior in CRS Mode

As mentioned earlier in Chapter 5, unlike BRS mode where information is stored in either HRS or LRS, complementary resistive switches are programmed by accounting for the resistance states of both memristors.

Table 7-1 can be used to operate the complementary resistive switch to store information, using a pulse scheme proposed by Linn et al. [146]. Initially, a read pulse of

V>V1 but V

110

200

100 A) µ V V

0 4 3

V V 1 2 -100 Current( Write Write Read "0" -200 "1"

-2 -1 0 1 2 Voltage (V)

Figure 7-6. CRS behavior observed in core-shell Pt/HfO2 system with “0” and “1” as two defined states to store information.

Table 7-1. Summary of CRS states based on the state of both memristors in a core- shell nanowire. (Adapted from Linn et al. [146]).

Voltage A B R of CRS CRS STATE

0 V OFF ON ≥ROFF “0” 0 V ON OFF ≥ROFF “1”

Read “0” V>V1 OFF ON ≥ROFF “0” Read “1” ON ON RON+RON “1”→”0” V>V1

Write “0” V>V2 OFF ON ≥ROFF “0” Write “1” ON OFF ≥ROFF “1” VV2 writes the state 0 and a reduction in current is observed. The subsequent read pulse reads a low current in the system due to one of the memristors in HRS and the further application of write and read pulses do not result in any change and proves that the state 0 is written. When a pulse V

111

1 is written which can be proved by the high ON current when a subsequent positive read pulse is applied. The state 1 is however erased and a negative pulse must be applied again to transition the device to state 1. This implies that during the reading of state 1 the read-out is destructive.

The current spikes however are extremely important, as they are always present when the state of the system changes. As a result, if a program is designed to read the spikes then only 3 voltages are required to operate the device namely, V1 to read the state of the system, V2 to write state 0, and V4 to write state 1. The voltage and the current response profiles are shown in Figure 7-7.

0 10 20 30 40 Pulse no.

Voltage(V) -1

-2

112

25 A)

µ 0

10 20 30 40 Pulse no.

-25 Current(

-50

b) Figure 7-7. Synaptic response when operated in CRS mode: a) voltage pulse profile to program state 0 and state 1 and b) corresponding current response.

7.2. Effect of Temperature on Bipolar Resistive Switching

Once electroformed with a compliance current of 50 μA, an 8W BRS switch was studied to determine the impact of temperature on BRS. Bipolar I-V curves are obtained at five different temperatures ranging from 297K – 358K as seen in Figure 7-8a. From

Figure 7-8a, at room temperature, the SET and RESET process are abrupt and both these processes become more gradual as the temperature is increased. Additionally, a higher RESET current was also observed with increase in temperature.

Figure 7-8b displays resistance of the switch in ON and OFF state as a function of temperature. Surprisingly with increasing temperature the ON state resistance remains

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unchanged, however the OFF state resistance decreases showing a semiconducting behavior. Subsequently, ROFF/RON ratio reduced from 12.81 to 3.45 over the temperature range 297K – 358K. The increase RESET current and reduction in ROFF/RON is comparable to other prior works done by Walczyk et al. [18] and Fang et al. [66] on HfO2 thin-film devices. This behavior has been attributed to increased conduction as more vacancies are created at higher temperatures. However, the ON state resistance is not comparable to other prior works, where ON state resistance decreased when temperature was increased due to metallic nature of the filaments. A possible reason could be that the other memristor in series in the nanowire is in the OFF state and thus assists in the conduction of charge. Additionally, in contrast with prior works [18], [66], no significant temperature difference was observed in the SET or RESET voltages as seen in Figure 7-

8c.

150 297K 313K 100 323K 338K

358K A)

µ 50

0 Current(

-50

-1.0 -0.5 0.0 0.5 1.0 1.5 Voltage (V)

114

106

Ron 0.8 )

 Roff

105 0.4

Vset

Vreset 0.0

104 Voltage (V)

-0.4 Resistance( -0.25V at 103 -0.8 300 320 340 360 300 320 340 360 Temperature (K) Temperature (K) b) c) Figure 7-8. Impact of temperature ranging from 297K – 358K in an 8W BRS switch: a) I-V sweep response, b) Resistance at -0.25 V, and c) SET and RESET voltages.

-q(ϕ -√qE/4πε) J=A**T2exp [ B ] (7-1) kT

100 358K 10

) 297K A

µ 0.1

0.01 297K 313K

Current( 1E-3 323K 1E-4 338K 358K 1E-5 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 Voltage (V)

Figure 7-9. HRS segment of I-V from Figure 7-8a.

Figure 7-9 takes a closer look at HRS in the bias range of -0.55 V and 0.9 V from

Figure 7-8a. The plot is symmetric and from Chapter 5 it is already concluded that

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thermionic emission [64] is the dominant charge transport mechanism in HRS mode given by equation (7-1).

From the equation (7-1), a plot of ln(J/T2) vs 1/kT should help in determining the barrier height. The current density plot at different potentials ranging from 0.4 V – 0.9 V is shown in Figure 7-10. A temperature dependance has already been established however, a slight deviation from linearity at higher temperatures can be due to the presence of trapped charges [18]. From the slope of data at each bias, reduced barrier height ϕr can be determined. The barrier height values decrease as shown in Figure 7-

11 with increase electric field due to energy barrier lowering effect [149]. From Figure 7-

11, the trap energy level ϕ can be determined when E1/2 = 0, i.e., the y-intercept of the linear fit. The calculated trap level ϕ is 0.23 eV below the conduction band edge comparable to other HfO2 systems [18] of similar thickness (10 nm).

2.4

2.0

1.6

) 1/2

1.2 0.9 V 0.8

ln(J/T 0.8 V 0.7 V 0.4 0.6 V 0.5 V 0.0 0.4 V

32 34 36 38 40 1/kT (eV-1)

Figure 7-10. Current conduction plot based on thermionic emission equation (7-1).

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Linear fit of data 0.15

φr=φ-β

0.10 3 1⁄2

β=(q ⁄4π)

(eV)

r 

0.05

0.7 0.8 0.9 1.0 1.1 1.2 E1/2 (MV/cm)1/2

Figure 7-11. Reduced trap barrier height at different electric fields.

From Chapter 5 it is already concluded that ohmic conduction [64] is the dominant charge transport mechanism in LRS mode given by equation (7-2).

-∆Eac (7-2) J∝Eexp [ ] kT From the equation (7-2), a plot of lnJ vs 1/kT should help in determining the activation energy. The current density plot at different potentials ranging from -0.1 V – -

0.3 V is shown in Figure 7-12. From the slope of data at each bias, activation energy

ΔEac can be determined. From the slopes, the activation energies are obtained are: -0.1

V = 0.055 eV, -0.15 V = 0.057 eV, -0.2 V = 0.055 eV, -0.25 V = 0.052 eV, and -0.3 V =

0.054 eV. With a positive activation energy that is constant it can be inferred that after the SET process, the LRS is independent of temperature. Additionally, these values are extremely lower than the activation energy required for oxygen vacancy migration in HfO2 as observed by Li et al [150]. This can be attributed to the switch already placed in LRS implying no further movement of oxygen vacancies.

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-9.6 -0.1 V -9.8 -0.15 V -0.2 V -10.0 -0.25 V -10.2 -0.3 V

-10.4

-10.6 ln(J) -10.8 -11.0 -11.2

32 34 36 38 40 1/kT (eV-1)

Figure 7-12. Current conduction plot based on ohmic conduction equation (7-2).

7.3. Conclusion

In summary, in this chapter bias voltages for potentiation and depression was successfully determine in BRS switches exhibiting 8W and C8W switching. With these threshold voltages, asymmetric and non-linear synaptic potentiation and depression has been demonstrated. Additionally, at least 3 distinct synaptic states each in potentiation and depression was obtained for both types of switches. The dynamic range for the 8W switch and the C8W switch is determined to be ~15 and ~11, respectively. Subsequently, as temperature was increased from 297K – 358K, reset current increase, SET and

RESET voltages remained the same, and ROFF/RON ratio reduced from 12.81 to 3.45.

Moreover, the thermionic barrier height was determined to 0.23 eV when the node is HRS.

Finally, low positive activation energies were observed in LRS mode for oxygen vacancy movement indicating temperature independence of LRS and no vacancy movement after the SET process.

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CHAPTER 8 TYPES OF NOISE AND IMPEDANCE SPECTROSCOPY IN CORE-SHELL NANOWIRES

Earlier in Chapter 2, the types of noise in resistive switching devices was introduced namely, low-frequency, random telegraph, and stimulated telegraph noise and identifying them will provide an insight into defect characteristics and conduction mechanisms. Low-frequency noise (LFN) originates from the systems’ need for self- organization and a small fluctuation can result in global dynamic effects [88], [89].

Random telegraph noise (RTN) originates from charges moving between trapped defects at low voltages [91]–[96]. At higher voltage pulses, zero average stimulated telegraph noise (STN) is observed caused due to the trap movement in the oxide layer [91].

Additionally, the contributions from different regions in a resistive switching device is different and identifying them will assist in understanding the mechanism involved [101],

[102]. Therefore, in this chapter different types of noise are identified and discussed.

Also, impedance spectroscopy is performed to identify the electrical properties due to resistive switching.

8.1. Low-frequency and Telegraph Noise

Initially, to determine LFN in the nanowire, the measurement setup described in

Chapter 3 was utilized to measure the noise current in the time domain. The nanowire was operated in BRS mode and was held in LRS. Bias was varied between 0.05 V and

0.15 V to measure noise current and also to analyze the impact of bias. An example for the measured current is shown in Figure 8-1a where the inset shows a section of the noise current. An important aspect to note here is that the gain used on the noise amplifier was 10000, meaning the measured current is amplified by a factor of 10000 and therefore results in a higher measured current. By performing a fast Fourier transformation on the

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current-time series, power spectral density can be obtained. At different bias conditions, the calculated PSD can be seen in Figure 8-1b.

-200

-150 A)

µ -250

-300 Current( -350 0.00 0.02 0.04 0.06 0.08 0.10

-200 Time (s)

A) µ

-250 Current( -300

0.15 V -350 0.0 0.2 0.4 0.6 0.8 1.0 Time (s)

0.1

1.24 1E-3 1/f

1E-5

) -1

1E-7

(Hz 2 0.05 V

S/I 1E-9 0.1 V 0.15 V Linear fit of PSD @ 0.15 V 1E-11 95% Confidence lower limit 95% Confidence upper limit 1E-13 1 10 100 1000 Frequency (Hz)

b) Figure 8-1. Low-frequency noise: a) measured noise current in LRS at 0.15 V and b) normalized PSD in LRS at varying bias.

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Previously in chapter 2, the author mentioned that systems obeying power law given by equation (8-1) have long-range correlations, where a small change locally has global effects. Figure 8-1b shows the normalized PSD (normalized with average current) of nanowires in LRS obeying 1/fα power law (where f is frequency and 0<α<3) and the slope determined from a linear fit at all bias conditions provides an α ~ 1.24. Moreover, an interesting aspect to note is the independence of PSD with varying bias. In HfO2 resistive switching devices this behavior is regarded as an intrinsic characteristic of the system. Additionally, this behavior suggests that the conduction in the LRS is localized

[151] and is due to the presence of conduction filaments formed out of oxygen vacancies

[25], [152]. Therefore, the movement of electrons due to trapping and de-trapping in these vacancies result in LFN. This work is also in contrast with PSD obtained by Brivio et al. [93] when they compared doped vs undoped HfO2 ReRAMs. They observed α ~ 2 in undoped HfO2, which lies in contrast with this result. One reason for a more metallic nature of conduction in LRS of this work can be attributed a) the amorphous nature of the sputtered HfO2 and b) the ready absorption of oxygen by the top Ti electrode which facilitates the formation of a conductive filament.

1 PSD∝ (8-1) fα Since filamentary conduction model is proposed as the mechanism in HfO2 resistive switching devices, the vacancies and traps around the filament affect conduction by random trapping and de-trapping of charges [91]–[93]. This can become significant in

HRS due to an incomplete/narrow filament in the oxide [140] and can produce RTN. RTN is studied at voltages low enough to not cause switching or resistance states and to only cause movement of electrons through trap states. In this thesis, the nanowire was

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exposed to a constant pulse of 0.12 V with a pulse width of 0.5 ms to obtain a current in the time domain as shown in Figure 8-2a. From the figure it can be observed that after few pulses there is a spike in current of varying amplitude. This evidences the presence of conventional RTN at low voltages, where the current spike is detected when charges gain enough energy to move out of the trap sites. The spikes last <1 ms which further confirms charge movement without ionic rearrangement. Subsequently, at slightly higher bias of 0.25 V before each read voltage of 0.12 V, higher amplitude spikes were detected with every pulse and lasted < 1 ms. Therefore, from Figure 8-2b constant pulse trains diriving telegraphic noise current in HRS can be confirmed.

-1.2 -1.2 0.0 -0.4 -1.0 -0.6 -1.0

-0.5 -0.8 A)

-0.8 A) -0.8   -1.0 -1.0 -0.6 -1.2 -0.6 -1.4

-1.5 -0.4 -0.4

Voltage (V)

Voltage (V) Current ( Current ( -1.6 -0.2 -0.2 -2.0 -1.8 0.0 -2.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5 Time (s) Time (s) a) b) Figure 8-2. Random telegraph noise: a) pulse trains with constant bias and b) pulse with alternating transition bias and read voltages.

However, at a higher voltage with constant pulse trains a new type of noise known as STN appears. This behavior was introduced by Brivio et al. [91], where STN can have an impact on programming of the resistive switch if pulse trains are used. To confirm the presence of STN, constant pulse trains were applied at varying bias to the wire in LRS.

The evolution of resistance as a function of number of pulses is shown in Figure 8-3. The selected bias range is in such a way that a transition from LRS to HRS is induced. The bias is varied from 0.2 V to 0.8 V and the state of the system is read once after each pulse

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at 0.12 V. From Figure 8-3, with increasing bias gradual increase in resistance is demonstrated. The resistance reaches saturation after a certain number of pulses. Here, the noise is superimposed with non-volatile switching of states. Therefore, after a certain number of pulses due to the saturation, the state of the system is only disturbed by STN.

STN is therefore, a result of bias high enough to cause switching in the device. At higher bias voltages saturation resistance increases and a bias dependance is established.

10 0.2 V 0.4 V 0.6 V

0.8 V )

 1

0.1 Resistance (

0.01 1 10 100 Pulse no.

Figure 8-3. Stimulated telegraph noise driven by constant pulse trains with the state of the system read at 0.12 V after every pulse.

Additionally, for the last 50 pulses where there is minimal change in resistance, noise amplitude is calculated as the standard deviation to average resistance. The noise amplitude increased from 2.18 kΩ to 0.488 MΩ as bias was increased. This is in direct correlation with increase of resistance with bias. This behavior can be attributed to similar kinetics governing both noise and transition of state to HRS. Also, STN in LRS was not performed as Brivio et al. [91] observed no effect of bias on STN and that it is independent

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of prior programming of the device due to to lack of ionic effects in LRS. This also holds true in core-shell nanowires of this work, where once the filaments are formed in LRS, there is linear change in resistance. Resistance change due to train of pulses, has been studied before but studies have not considered the presence of noise and the phenomenon is usually attributed to synaptic, analog transition of the device [42], [143],

[144].

The noise described in this work is dependent on pulses and hence is telegraphic in nature. RTN has been ascribed to either the movement of charge between traps that are not oxygen vacancies and impact conduction in oxygen vacancies in their vicinity; or metastable vacancies that prevent charge movement through vacancies forming the conductive filament. Regardless, RTN is deemed to be temporary trapping and de- trapping of electrons [94]. STN however, is due to ionic effects, where diffusion and drift of oxygen vacancies near the conductive filament during the transition of state (e.g. HRS to LRS) [153]. Effects of conventional RTN and STN must be understood for future device integration, as RTN affects the read operation and STN affects the programming operation. Accommodating the effects of LFN, RTN and STN in future models should help in accounting for variability in the reading and programming of states in networks.

8.2. Impedance Spectroscopy

To determine the contributions of each component involved in resistive switching, impedance spectroscopy was performed in the frequency range of 800 Hz – 3 × 105 Hz with an oscillation voltage of 100 mV. Initially, when operating the nanowire in BRS mode, resistance was measured at varying bias in both LRS and HRS. As expected, the resistance reduced in HRS with increasing bias and remained the same in LRS.

However, two states were observed in LRS with the lowest resistance state dominating.

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The higher of the two LRS could only be obtained after transitioning to HRS but was only retained for a short period of time. This can be explained by alluding to the filamentary model of conduction [91]–[93], where LRS is obtained after the formation of filaments between the electrodes. When the node undergoes SET transition, the higher LRS is obtained due to the reorganization of the vacancies, however, due to the application of bias or the alternating frequency measuring the resistance causes other vacancies to drift towards the filament leading to a lower LRS and higher current.

Next, to study the impact of temperature on resistance in the frequency domain, temperature was varied from 297K – 358K. The measured resistance at varying temperatures in LRS and HRS is shown in Figure 8-4. The noise in the data can be ascribed to the higher oscillation voltage of 100 mV.

HRS 16 LRS

140 RT )

) RT 120 

 14 k k 313K

100 323K

12 80 313K 323K

60 Resistance( 10 Resistance ( 358K 40 358K

3 4 5 6 10 10 10 10 103 104 105 106 Frequency (Hz) Frequency (Hz) a) b) Figure 8-4. Resistance in BRS mode in the frequency domain at different temperatures: a) LRS and b) HRS.

Additionally, the capacitance was measured in the frequency domain when the nanowire was operated in the BRS mode. DC bias applied was varied between 0 V and

0.2 V in both LRS and HRS. The frequency dependance of the measured capacitance is shown in Figure 8-5a. From Figure 8-5a, despite the noise, there is no observed variation in capacitance in LRS at any bias, however, as the bias is increased in HRS, a negative

125

capacitance trend is observed as the bias is increased in lower frequencies. Additionally, reactance of the nanowires was measured in the frequency domain in BRS mode. The impact of temperature was also studied in the range of 297K – 358K. The applied DC bias was same as before for the nanowire in both LRS and HRS. Although, no appreciable trend was observed in LRS, at low bias and high frequencies, the reactance in HRS showed a negative trend. Moreover, observing reactance at different temperatures as shown in Figure 8-5b, the negative trend relaxes and drifts towards zero.

80 4 HRS 297K 40 3 HRS 313K HRS 323K ) 2 HRS 358K

0  k LRS 0 V 1

-40 LRS 0.1 V

LRS 0.15 V 0 -80 LRS 0.2 V HRS 0 V -1

-120 HRS 0.1 V Reactance ( HRS 0.15 V -2 -160 HRS 0.2 V

Capacitance (pF) (Parallel) -3 3 4 5 6 10 10 10 10 103 104 105 106 Frequency (Hz) Frequency (Hz) a) b) Figure 8-5. Impedance spectroscopy: a) capacitance in the frequency domain at varying bias and b) reactance in the frequency domain for HRS.

In previous chapters, the current conduction mechanisms in LRS was ascribed to ohmic conduction and in HRS thermionic emission dominated when the wire was operated in the BRS mode. A characteristic feature of thermionic emission is the increase in charge transport with increase in temperature due to its non-ohmic behavior [18], [154],

[155]. A similar behavior is observed here, where as temperature is increased from 297K

– 358K, HRS resistance decreases from ~146 kΩ to ~37 kΩ, respectively. Almost an order of magnitude decrease in resistance is due to the accelerated movement of charge through the trap sites. The rise in temperature provides the charges enough energy to overcome the barrier height to move out of the trap sites and into the conduction band.

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This phenomenon accelerates with increase in temperature, eventually leading to the reduction in resistance.

Next, if ohmic conduction is the dominant mechanism to transport charge in LRS, increasing temperature results in the increase of resistance [18], [154], [155]. This is attributed to hindrance to the flow of electrons due to the vibration of atoms. However, in this work a contrasting behavior is observed, where the resistance decreases with increasing temperature. Despite adhering to ohmic conduction models, at higher temperatures the behavior in LRS appears to be non-metallic. This behavior has been observed before in ZrO2 [154] and TaOy/Ta2O5-x [155] resistive switching crossbar systems, where with increasing temperature, the LRS resistance displayed a negative temperature coefficient. This behavior was deemed non-metallic by Karkkanen et al.

[154], however, resistance determination at temperatures ranging from 5K – 250K by

Zhang et al. [155] evidenced a transition in conduction from ohmic to hopping in LRS with increasing temperature. A similar approach can be adopted for the behavior observed in this work. The oxygen vacancy filaments formed in the oxide layer between the core and the top electrode adhere to ohmic conduction. However, the traps and vacancies present in the node of interest and the adjacent node the nanowire is connected are potentially having an impact on current conduction. Although the mechanism may not be thermionic or hopping, the behavior appears to be similar and therefore results in the decrease of resistance with rise in temperature due to electrons moving out of traps into the conduction band.

Capacitance in resistive switching devices is generally low remains constant in

LRS and HRS over the frequency domain. Jiang et al. [101] even observed a slight

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increase in capacitance in LRS due to the reduction in the oxide layer between the filament and the electrode when compared to that in HRS. However, in this work, despite the low capacitance, in HRS at lower frequencies a negative capacitance is observed.

This behavior although not observed previously in resistive switching devices, it has been observed by Kytin et al. [156] in porous TiO2. In their work, capacitance was negative at lower frequencies due to the presence of inductive behavior. This was due to slow polarization affecting the injection currents entering the oxide. Therefore, an inductive behavior maybe dominating in the core-shell nanowires of this work.

Subsequently, with the wire in HRS reactance measured at room temperature showed negative trend in the high frequency range. When temperature was increased the negative trend relaxed the reactance. The appearance of negative reactance usually indicates a positive capacitance in the device [157]. However, it has been previously established that capacitance in HRS has a negative trend due to inductive effects. This combined behavior can be attributed to the presence of traps and oxygen vacancies in

HRS in the nanowire and has been presented by Mitra et al. [158] in polycrystalline TiO2.

They observed an apparent negative capacitance when a RLC circuit was used, due to the accumulation of space charge and their movement between non-linear sites leading to an inductive dispersion.

In the core-shell nanowires discussed here, the active layer in HRS contains traps and vacancies. However, at low temperatures with the application of bias, the delocalized charge carriers are causing inductive dispersion. Therefore, at higher frequencies the despite the appearance of a capacitive effect, the inductive reactance dominates in these nanowires over the capacitive reactance.

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8.3. Conclusion

In summary, in this chapter, when the wire is operated in the BRS mode, in LRS,

LFN obeys 1/fα with α~1.24 indicating a metallic behavior. In HRS, at low voltages, short lived current spikes indicate the presence of RTN. Additionally, with pulse stimulation at a higher bias, STN can be observed. RTN has been ascribed to the movement of charge between trap sites and STN is a result of ionic effects like vacancy movement that exist during transition of states. Moreover, bias dependance of noise amplitude was also observed. Impedance spectroscopy revealed a potential hopping mechanism with ohmic conduction in LRS due to the decrease in resistance with increase in temperature. Finally, the observance of negative capacitance despite negative reactance alludes to the presence of inductive dispersion due to charge movement between trap states.

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CHAPTER 9 SUMMARY AND FUTURE WORK

9.1. Summary

9.1.1. Complementary Resistive Switching in Core-shell Nanowires

In chapter 5, the substrate patterned using e-beam lithography, utilized techniques like sputtering and liftoff to successfully fabricate Pt/HfO2 core (40 nm)-shell (7 nm) naowires with Ti top electrodes. Remarkably when characterized electrically, 8W and

C8W BRS was observed. Additonally, when combined a new form of switching known as CRS was observed in these systems. Either type of switching behavior can be employed based on the type of applied threshold voltages. Under BRS mode, pulse operations resulted in an endurance of 1000 cycles and memory retention of upto 104 s.

Also by analyzing J vs E curves, the conduction mechanism in HRS was determined to be thermionic emission and the mechanism in LRS was determined to be ohmic. Under

CRS mode, the conduction mechanism in state 0 is via hopping of electrons and the mechanism in state 1 was determined to be space-charge-limited. It was also observed that the operating current can be lowered by forming the wires at a lower compliance current thereby making them a potential candidate for low energy neuromorphic devices.

9.1.2. Implications of Resistive Switching Mechanisms in Core-shell Nanowires

STEM-EDS analysis revealed, upon resistive switching operation, Ti absorbed oxygen from the HfO2 leading to a sub-stoichiometric distribution of the HfO2 which results in the formation of oxygen vacancy filament. From STEM-EDS analysis, atomistic views of SET and RESET transitions in BRS mode and subsequently, the atomistic view of the nanowire in CRS mode is discussed. The schematics were drawn based on valence change mechanism leading to the formation of filaments for current conduction.

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9.1.3. Artificial Synaptic Response and Effect of Temperature on Bipolar Resistive Switching in Core-shell Nanowires

In chapter 7, bias voltages for potentiation and depression were successfully determined in BRS switches exhibiting 8W and C8W switching. With these threshold voltages, asymmetric and non-linear synaptic potentiation and depression has been demonstrated. Additionally, at least 3 distinct synaptic states each in potentiation and depression was obtained for both types of switches. The dynamic range for the 8W switch and the C8W switch is determined to be ~15 and ~11, respectively. Subsequently, as temperature was increased from 297K – 358K, reset current increase, SET and RESET voltages remained the same, and ROFF/RON ratio reduced from 12.81 to 3.45. Moreover, the thermionic barrier height was determined to 0.23 eV when the node is HRS. Finally, low positive activation energies were observed in LRS mode for oxygen vacancy movement indicating temperature independence of LRS and no vacancy movement after the SET process.

9.1.4. Types of Noise and Impedance Spectroscopy in Core-shell Nanowires

In chapter 8 various types of noise in LRS and HRS are discussed along with impedance spectroscopy. Here, when the wire is operated in the BRS mode, in LRS,

LFN obeys 1/fα with α~1.24 indicating a metallic behavior. In HRS, at low voltages, short lived current spikes indicate the presence of RTN. Additionally, with pulse stimulation at a higher bias, STN can be observed. RTN has been ascribed to the movement of charge between trap sites and STN is a result of ionic effects like vacancy movement that exist during transition of states. Impedance spectroscopy revealed a potential hopping mechanism with ohmic conduction in LRS due to the decrease in resistance with increase in temperature. Finally, the observance of negative capacitance despite negative

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reactance alludes to the presence of inductive dispersion due to charge movement between trap states.

9.2. Future Work

The core-shell nanowires fabricated here have two memristors that are connected in an anti-serial manner and are probed electrically only via the top electrodes. Therefore, any I-V response obtained is a result of current conduction through both the memristors.

The SET/RESET transitions in one memristor will be influenced by the other memristor and the true response of the individual memristor is never known and must be assessed.

Therefore, by tweaking the design and the order of lithography and deposition, new core- shell nanowires with the core extending out of the wire into an electrode can be fabricated.

This will aid in isolating each memristor in the core-shell nanowire and will also help in determining the resistive switching dynamics accurately.

Current conduction is attributed to the formation of a filament due to the movement of oxygen vacancies. However contrasting results have been observed for similar electrode-insulator combinations. Therefore, fabricating structures emulating core-shell nanowires for in-situ TEM/STEM analysis combined with electron energy loss spectroscopy (EELS) will help in confirming the nature of conductive filaments.

Synaptic potentiation and depression observed in this work was asymmetric and non-ideal. Part of the reason can be the testing equipment’s lower limit on pulse width of

0.5 ms. Pulse widths in the ns or μs range with a higher bias have previously shown steady and linear symmetric weight updates. Additionally, applying spike time dependent plasticity pulse schemes will help in assessing the adaptive learning capabilities of these core-shell nanowires. Moreover, as mentioned earlier, any potentiation and depression in a 8W or a C8W switch is influenced by the presence of the other memristor and the

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fabrication of core-shell nanowires with an extended core will help in observing the true synaptic potentiation and depression.

Both BRS and CRS are abrupt due to the rapid movement of oxygen vacancies to form the filament. This could be an artifact oxygen diffusion into the top Ti electrode. By the addition of Al instead of Ti, Woo et al. [84] have managed to obtain gradual SET and

RESET along with linear synaptic potentiation and depression. Similar solutions will be explored to improve reliability of these core-shell nanowires.

Finally, despite understanding the switching dynamics of a single core-shell nanowire, network integration and performance against machine learning benchmark tasks will require a substantial amount of work. From determining methods to control of resistive switching in the desired wire in a network to study the effect of the state of one node on the current required to change the state in another node. Additionally, performance of the network must be compared in BRS and CRS mode against standard machine learning tasks to determine which mode of operation is better.

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APPENDIX A LESSONS LEARNED

Figure A-1 shows the S/TEM image for a cross-section of the nanowire. The wires were expected to be non-cylindrical but however on the edges, pillars can be seen. This is due to the use of sputter deposition during fabrication, as the sputtered molecules deposit along the PR channel walls. This ultimately is undesirable as it may provide additional locations for the formation of the conductive filament where the HfO2 thickness is low. This can be eliminated by using ALD for HfO2 deposition and e-beam PVD for the deposition of metal for the core. However, photoresists cannot be used with ALD.

Therefore, a negative PR should be used after deposition to etch down the HfO2 to obtain core-shell nanowires.

Figure A-1. S/TEM image of a core-shell nanowire. (Image courtesy Eitan Hershkovitz from Dr. Honggyu Kim’s group).

Another disadvantage of this route is that the diameters of the wires will be more as the smallest feature can only be 200 nm wide. Additionally, negative PR can

134

polymerize and become hard when exposed to the plasma during etching. Thorough inspection must be done to ensure no PR is left. Finally, residual Al2O3 can also be observed in Figure A-1. Since this Al2O3 has been grown using ALD, it is crystalline and can be a source of unwanted capacitance during switching. The etch rates in the tools keep changing, therefore it is prudent to test etch rates before etching the actual prototype. Auger electron spectroscopy can be used to check if any Al2O3 is left behind.

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APPENDIX B LOW-FREQUENCY NOISE AMPLIFIER ASSEMBLY

Low-Frequency Noise Amplifiers (LFNA) are single port active linear devices which amplify a noise signal while limiting the attenuation of the noise figure. In other words, the theoretical application of the LFNA is to increase both the signal and noise present at the input, while adding a minimal amount of noise from its own system. Setting an appropriate gain to maintain the same signal-to-noise ratio from input, minimizing attenuation of the noise figure, and using circuit elements which will preserve the linearity of the signal are all attributes that are considered when designing a LFNA. The amplifier for this work was assembled by Marc Martorell at the Nino Research Group. The amplifier shown in Figure

B-1 is a replica of the ANF124 [159], a LFNA with four circuit stages.

Figure B-1. Low-frequency noise amplifier assembled by Marc Martorell of the Nino Research Group (Photo courtesy author).

In Figure B-2, a flow chart of the LFNA stages is provided. First, from the input port the low-frequency noise source DC component is filtered. Next, the signal is input to

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a parallel network of frequency amplifiers whose gain is determined by frequency. The parallel network of amplifiers are configured to output an average between the four individual configurations. Then, a series of two integrating operational amplifiers are introduced, this takes the voltage at the output of the averaging frequency amplifiers and produces an output voltage which is proportional to the integral of the input voltage. Last, the integrated signal is filtered once more to produce the final amplified noise figure at the output port.

Figure B-2. Flowchart of the stages within the LFNA ANF124 replica.

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APPENDIX C FABRICATION DETAILS OF PRELIMINARY PROTOTYPES

C.1. Prototype 1

Table C-1. List of tools used to fabricate prototype 1

Step Tool used Purpose/Details number

Spin 165 nm of A4 PMMA at 4000 rpm 1 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 2 lithography (Layer 1) μm aperture, 5 nm step size

3 MIBK:IPA = 1:3 solution Develop for 30 s

4 Nikon LV100 Inspection/optical microscopy

5 Asher Anatech Descumming at 200 W, 300 sccm, 60 s

6 KJL sputter tool 16 nm HfO2

E-beam physical vapor 7 50 nm Ti deposition

8 KJL sputter tool 16 nm HfO2

9 Acetone, IPA, DI water Liftoff

10 Nikon LV100 Inspection/optical microscopy

11 Asher Anatech Descumming at 200 W, 300 sccm, 60 s

Spin 165 nm of A4 PMMA at 3700 rpm 12 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 13 lithography (Layer 2) μm aperture, 5 nm step size

14 MIBK:IPA = 1:3 solution Develop for 30 s

15 Nikon LV100 Inspection/optical microscopy

16 Asher Anatech Descumming at 200 W, 300 sccm, 60 s

17 KJL sputter tool 16 nm HfO2

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Table C-2. Continued

Step Tool used Purpose/Details number

E-beam physical vapor 18 50 nm Ti deposition

19 KJL sputter tool 16 nm HfO2

20 Acetone, IPA, DI water Liftoff

21 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 60 s 22 Asher Anatech s

40 nm Al2O3, 1 Å/cycle thermal 23 Atomic layer deposition deposition rate

Spin 300 nm of A4 PMMA at 2000 rpm 24 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 25 lithography (Layer 3) μm aperture, 10 nm step size

26 MIBK:IPA = 1:3 solution Develop for 30 s

27 Nikon LV100 Inspection/optical microscopy

28 Asher Anatech Descumming at 200 W, 300 sccm, 60 s

BCl3 etchant for 233 s (etched after 29 Trion RIE/ICP testing etch rate)

30 Acetone, IPA, DI water Liftoff

31 Nikon LV100 Inspection/optical microscopy

32 Asher Anatech Descumming at 200 W, 300 sccm, 60 s

33 Laurell spinner Spin 300 nm of A4 PMMA at 4000 rpm

After 180°C bake Vias: 200 nm WF, 600 RAITH e-beam μC/cm2, 30 keV, 20 μm aperture, 20 nm 34 lithography (Layer 3 and step size, dose factor of 0.6 for layer 3 4) (reduced radius). Pads: 380 μC/cm2, 30 keV, 60 μm aperture, 80 nm step size

139

Table C-3. Continued

Step Tool used Purpose/Details number

35 MIBK:IPA = 1:3 solution Develop for 30 s

36 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 60 s 37 Asher Anatech s

38 KJL sputter tool 10 nm Ti, 70nm Pt

39 Acetone, IPA, DI water Liftoff

40 Nikon LV100 Inspection/optical microscopy

41 Asher Anatech Descumming at 200 W, 300 sccm, 60 s C.2. Prototype 2

Table C-4. List of tools used to fabricate prototype 1

Step number Tool used Purpose/Details

Spin 165 nm of A4 PMMA at 4000 rpm 1 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 2 lithography (Layer 1) μm aperture, 5 nm step size

3 MIBK:IPA = 1:3 solution Develop for 30 s

4 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 5 Asher Anatech s

6 KJL sputter tool 7 nm HfO2

8 KJL sputter tool 5 nm HfO2

9 Acetone, IPA, DI water Liftoff

10 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 11 Asher Anatech s

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Table C-5. Continued

Step number Tool used Purpose/Details

Spin 165 nm of A4 PMMA at 3700 rpm 12 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 13 lithography (Layer 2) μm aperture, 5 nm step size

14 MIBK:IPA = 1:3 solution Develop for 30 s

15 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 16 Asher Anatech s

17 KJL sputter tool 7 nm HfO2

E-beam physical vapor 18 40 nm Ti deposition

19 KJL sputter tool 5 nm HfO2

20 Acetone, IPA, DI water Liftoff

21 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 22 Asher Anatech s

Spin 165 nm of A4 PMMA at 3700 rpm 23 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 24 lithography (Layer 3) μm aperture, 5 nm step size

25 MIBK:IPA = 1:3 solution Develop for 30 s

Descumming at 200 W, 300 sccm, 120 27 Asher Anatech s

28 KJL sputter tool 7 nm HfO2

E-beam physical vapor 29 40 nm Ti deposition

30 KJL sputter tool 5 nm HfO2

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Table C-6. Continued

Step number Tool used Purpose/Details

31 Acetone, IPA, DI water Liftoff

32 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 33 Asher Anatech s

40 nm Al2O3, 1 Å/cycle thermal 34 Atomic layer deposition deposition rate

Spin 300 nm of A4 PMMA at 2000 rpm 35 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 36 lithography (Layer 3) μm aperture, 10 nm step size

37 MIBK:IPA = 1:3 solution Develop for 30 s

38 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 39 Asher Anatech s

BCl3 etchant for 233 s. (etched after 40 Trion RIE/ICP testing)

41 KJL sputter tool 5 nm HfO2,

42 Acetone, IPA, DI water Liftoff

43 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 44 Asher Anatech s

RAITH e-beam Vias: 200 nm WF, 600 μC/cm2, 30 keV, 46 lithography (Layer 4 and 20 μm aperture, 20 nm step size, dose 5) factor of 0.6 for layer 3 (reduced radius).

47 MIBK:IPA = 1:3 solution Develop for 30 s

48 Nikon LV100 Inspection/optical microscopy

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Table C-7. Continued

Step number Tool used Purpose/Details

Descumming at 200 W, 300 sccm, 120 49 Asher Anatech s

50 KJL sputter tool 10 nm Ti, 70 nm Pt

51 Acetone, IPA, DI water Liftoff

52 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 53 Asher Anatech s

Spin 600 nm of A6 PMMA at 4000 rpm 54 Laurell spinner and bake at 180°C

RAITH e-beam Pads: 380 μC/cm2, 30 keV, 60 μm 55 lithography (Layer 6) aperture, 80 nm step size

56 MIBK:IPA = 1:3 solution Develop for 30 s

57 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 58 Asher Anatech s

59 KJL sputter tool 15 nm Ti, 200 nm Au

60 Acetone, IPA, DI water Liftoff

61 Nikon LV100 Inspection/optical microscopy

Descumming at 200 W, 300 sccm, 120 62 Asher Anatech s C.3. Prototype 3

Table C-8. List of tools used to fabricate prototype 4

Step number Tool used Purpose/Details

Spin 165 nm of A4 PMMA at 4000 rpm 1 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 2 lithography (Layer 1) aperture, 5 nm step size

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Table C-9. Continued

Step number Tool used Purpose/Details

3 MIBK:IPA = 1:3 solution Develop for 30 s

4 Nikon LV100 Inspection/optical microscopy

5 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

6 KJL sputter tool 7 nm HfO2, 40 nm Pt and 7 nm HfO2

7 Acetone, IPA, DI water Liftoff

8 Nikon LV100 Inspection/optical microscopy

9 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

Spin 165 nm of A4 PMMA at 3700 rpm 10 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 11 lithography (Layer 2) aperture, 5 nm step size

12 MIBK:IPA = 1:3 solution Develop for 30 s

13 Nikon LV100 Inspection/optical microscopy

14 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

15 KJL sputter tool 7 nm HfO2, 40 nm Pt and 7 nm HfO2

16 Acetone, IPA, DI water Liftoff

17 Nikon LV100 Inspection/optical microscopy

18 Asher Anatech Descumming at 300 W, 300 sccm, 120 s

40 nm Al2O3, 1 Å/cycle thermal 19 Atomic layer deposition deposition rate

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 21 lithography (Layer 3) aperture, 10 nm step size

22 MIBK:IPA = 1:3 solution Develop for 30 s

23 Nikon LV100 Inspection/optical microscopy

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Table C-10. Continued

Step number Tool used Purpose/Details

24 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

PMMA ~ 35 nm/min, Al2O3 ~ 15 nm/min for 3 min, pressure = 5 mTorr, RF1 = 175 25 Uniaxis SLR RIE/ICP W, RF2 = 0 W, 17 sccm CH4, 8 sccm H2, 5 sccm Ar, 5 Cl2. (etch rate was tested and PR coated wafer was used)

26 KJL sputter tool 5 nm HfO2

27 Acetone, IPA, DI water Liftoff

28 Nikon LV100 Inspection/optical microscopy

29 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

Spin 300 nm of A4 PMMA at 2000 rpm 30 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 μm 31 lithography (Layer 3) aperture, 10 nm step size

32 MIBK:IPA = 1:3 solution Develop for 30 s

33 Nikon LV100 Inspection/optical microscopy

34 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

35 KJL sputter tool 50 nm TiN, 20 nm Ti

36 Acetone, IPA, DI water Liftoff

37 Nikon LV100 Inspection/optical microscopy

38 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

Vias: 200 nm WF, 600 μC/cm2, 30 keV, RAITH e-beam 20 μm aperture, 20 nm step size, dose 40 lithography (Layer 3 factor of 0.6 for layer 3 (reduced radius). and 4) Pads: 380 μC/cm2, 30 keV, 60 μm aperture, 80 nm step size

41 MIBK:IPA = 1:3 solution Develop for 30 s

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Table C-11. Continued

Step number Tool used Purpose/Details

42 Nikon LV100 Inspection/optical microscopy

43 Asher Anatech Descumming at 200 W, 300 sccm, 120 s

44 KJL sputter tool 10 nm Ti, 190 nm Au

45 Acetone, IPA, DI water Liftoff

46 Nikon LV100 Inspection/optical microscopy

47 Asher Anatech Descumming at 200 W, 300 sccm, 120 s C.4. Crossbar Architectures

Table C-12. List of tools used to crossbar architectures.

Step number Tool used Purpose/Details

Spin 165 nm of A4 PMMA at 4000 rpm 1 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 400 μC/cm2, 20 keV, 10 2 lithography (Layer 1) μm aperture, 5 nm step size

3 MIBK:IPA = 1:3 solution Develop for 30 s

4 Nikon LV100 Inspection/optical microscopy

Descumming at 300 W, 300 sccm, 120 5 Asher Anatech s

6 KJL sputter tool 10 nm Ti, 60 nm Pt

7 Acetone, IPA, DI water Liftoff

8 Nikon LV100 Inspection/optical microscopy

Spin 165 nm of A4 PMMA at 3700 rpm 10 Laurell spinner and bake at 180°C

RAITH e-beam 200 nm WF, 380 μC/cm2, 20 keV, 10 11 lithography (Layer 2) μm aperture, 10 nm step size

12 MIBK:IPA = 1:3 solution Develop for 30 s

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Table C-13. Continued

Step number Tool used Purpose/Details

13 Nikon LV100 Inspection/optical microscopy

Descumming at 300 W, 300 sccm, 120 14 Asher Anatech s

15 KJL sputter tool 7 nm HfO2,

16 Acetone, IPA, DI water Liftoff

17 Nikon LV100 Inspection/optical microscopy

Descumming at 300 W, 300 sccm, 120 18 Asher Anatech s

Spin 165 nm of A4 PMMA at 4000 rpm 19 Laurell spinner and bake at 180°C

200 nm WF, 400 μC/cm2, 20 keV, 10 RAITH e-beam 20 μm aperture, 10 nm step size for lines lithography (Layer 3) and 80 nm step size for pads

21 MIBK:IPA = 1:3 solution Develop for 30 s

22 Nikon LV100 Inspection/optical microscopy

Descumming at 300 W, 300 sccm, 120 23 Asher Anatech s

24 KJL sputter tool 10 nm Ti, 60 nm Pt

25 Acetone, IPA, DI water Liftoff

26 Nikon LV100 Inspection/optical microscopy

Descumming at 300 W, 300 sccm, 120 27 Asher Anatech s

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BIOGRAPHICAL SKETCH

Shangradhanva Eswara Vasisth (Shangri) was born in 1994 in Bengaluru, India and was raised in the same city. After his schooling, he took the Karnataka state common entrance test and was accepted to B.M.S. College of Engineering, an autonomous college under Visvesvaraya Institute of Technology. Here, he studied chemical engineering to earn a bachelor’s degree in 2016. During this period, he was inspired by role of materials in everyday life and decided to pursue graduate degree in materials science and engineering in the United States of America. He joined the Department of Materials

Science and Engineering at the University of Florida as a master’s student in the fall of

2016 and began working with Professor Nino’s research group from the spring of 2017.

Given the multidisciplinary and diverse nature of the group, he was involved in multiple research projects involving water treatment, casting of gels for muscle and neuron co- culture, neutron activation analysis, and fabrication and characterization of nanowires.

However, the bulk of his work is concentrated on studying resistive switching in core-shell nanowires, which also forms the basis of his Ph.D. from the University of Florida.

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