RISC-V and CHIPS Alliance Address New Compute Requirements

Zvonimir Z. Bandic, Chairman, CHIPS Alliance Sr. Director, Western Digital Corporation AGENDA

Who are we? Today’s compute CHIPS Alliance requirements/challenges projects

2 Who Are We? What is CHIPS Alliance?

• Open organization which develops and hosts: › Open source hardware code (IP cores) and open source software design tools › Interconnect IP (phy and logical protocols) • A barrier free environment for collaboration: › Standards organization framework for collaboration and development › Legal framework – Apache v2 license • Shared resources ($ and time) which lower the cost of hardware development: › For IP and tools

44 CHIPS Alliance – who are we? Welcome our newest members!

Wilson Snyder Olof Kindgren

5 CHIPS Alliance – organizational structure

Elected CHIPS Alliance Board of Directors Zvonimir Bandic (Chairman) Staff Richard Ho (Vice-chairman) Xiaoning Qi Dave Ditzel Yunsup Lee

Henry Cook Ted Marena Michael Gielda Technical Committee Interim Director Outreach Committee

Brian Warner Workgroup Chairs Marketing Chairs Community Manager

Project Maintainers Finance Outreach

Verif. Engineers Operations Events

SW/HW Engineers Legal Advocacy

Technology Development Membership + Operations Visibility + Growth

6 Events

• Upcoming CHIPS Alliance events: › CHIPS Alliance & CHISEL workshop (Milpitas, January 29–30, 2020) › China workshop (Shanghai, April 2020)

• Past events: › Held in Mountain View, June 19 2019 › Design verification workshop (Munich, Nov 14-15, 2019)

77 Today’s Compute Requirements/challenges Todays Compute Requirements

Cloud and data center application Mobile and wireless

Automotive Consumer and IoT devices

Industrial IoT Memory

More processing, wider variety of workloads, increased development costs

9 Compute and Design Challenges

Costs of hardware Innovation often stalled Need more increasing in corporate structures purpose-built significantly architectures

1010 CHIPS Alliance Goals and Deliverables

• Lower the Cost of Development › Build common IP – RISC-V cores, Neural network accelerator, Uncore components (PCIe, DDR…), Interconnects › Open source software design tools • Open Source Collaboration for Breakthrough Innovation › Leverage broad expertise and diverse experience • Design open source RTL › Enables purpose-built solutions

1111 CHIPS Alliance Projects Workgroups

Interconnect: › TileLink 2.0 Chisel-WG › OmniXtendTM

› Cores-WG: › SweRV CoreTM Tools-WG: › FuseSOC › Cocotb-verilator

13 SweRV Core Roadmap

https://github.com/chipsalliance/Cores-SweRV

14 Design Verification using Co-Sim with reference model

RTL Simulation Metrics.log Open Source RISC-V RTL SystemVerilog & Memory UVM GCC/ RISC-V Compare LLVM Instruction Stream Imperas ISS (CPU+Memory) Generator RISCV. RISCV.elf Imperas.log

Open source Stressful Transaction & Instruction Generator (STIG): SystemVerilog design + UVM simulator for RTL Model and simulation golden reference of RISC-V CPU

15 Direct to Caches over Commodity Fabric - OmniXtend

L1 $ L1 $ L1 $ L1 $ L1 $ L1 $ L1 $ L1 $

Internal Cache Coherence Switch Internal Cache Coherence Switch

L2 cache Cache Coherence Serializer Ethernet Cache Coherence Serializer L2 cache with Cache Coherency Coherence Manager 802.3 PHY 802.3 PHY Coherence Manager

DRAM DRAM TofinoTM

802.3 Phy 802.3 Phy NVM Programmable ML NVM (P4) Switch Accelerator NVM – Main Memory

Ethernet based, open cache coherency fabric OmniXtend Architecture Overview

RISC-V node

17 OmniXtend Reference Design

Join us and further develop OmniXtend

18 FuseSOC (and SweRV support!)

Core Storage Core Libraries FuseSoC Edalize

Core Library ABCD.vc B

Core Manager EDAM A API C A ABCD.xpr A C Edalizer ABCD B C B ABCD.qsf

Ok FuseSoC! D Run a simulation D of core A using D Verilator Core Library ABCD.scr

User Fusesoc run –target=sim –tool=verilator A

FuseSoC is a package manager… ...and a build tool for HDL

19 Verilator

• Super Fast Simulation • License Free Executable • Runs Anywhere • Builds Into Apps • 100% C++ Code

System CLANG RTL Design Lint

XML User’s Tools

2020 Verilator roadmap

Full System Verilog Support

21 Dromajo, a new RISC-V RV64GC Emulator for RTL co-simulation • Esperanto Technologies emulator for co-simulation › Emulator based on F. Bellard’s RISCVEMU, bug fixed and enhanced with ISA 2.3/priv 1.11 › Single core co-simulation with support for exceptions and MMIO › Reasonably fast: ~17 MIPS on a 3GHz Xeon Platinum 8124M › Apache license › https://github.com/chipsalliance/dromajo • Capacity to create and resume checkpoints reusable across different cores • Work-in-Progress › Integrate with external cores: BOOM, Ariane, black-parrot, … › Efficient SPEC2017 checkpoints

2222 BAG: Berkeley Analog Generator

Draw(Re-)Size Draw(Re-)Size Schematic Schematic (Virtuoso) (Virtuoso)

Verify specs Verify specs (simulate (simulate

(Re-) Draw (Re-) Draw Layout Layout (Virtuoso) (Virtuoso)

Generator Script

• Core design loop has not changed in 30+ years • Captures design knowledge in an executable generator

2323 Join CHIPS Alliance

• Contribute to the development of open source design tool software • Share resources to lower the cost of hardware development • Receive high quality, open source CPU/SoC designs and complex IP blocks • Have your brand associated with a forward-thinking organization

See more: https://chipsalliance.org/join/

24 backup

25