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The PoC-Library Documentation Release 1.2.0 Patrick Lehmann, Thomas B. Preusser, Martin Zabel Sep 11, 2018 Introduction I Introduction1 1 What is PoC? 5 1.1 What is the History of PoC?.....................................6 1.2 Which Tool Chains are supported?..................................6 1.3 Why should I use PoC?.......................................7 1.4 Who uses PoC?............................................7 2 Quick Start Guide 9 2.1 Requirements and Dependencies...................................9 2.2 Download............................................... 10 2.3 Configuring PoC on a Local System................................. 10 2.4 Integration.............................................. 10 2.5 Run a Simulation........................................... 12 2.6 Run a Synthesis........................................... 13 2.7 Updating............................................... 13 3 Get Involved 15 3.1 Report a Bug............................................. 15 3.2 Feature Request........................................... 15 3.3 Talk to us on Gitter.......................................... 15 3.4 Contributers License Agreement................................... 16 3.5 Contribute to PoC.......................................... 16 3.6 Give us Feedback........................................... 18 3.7 List of Contributers.......................................... 18 4 Apache License 2.0 19 4.1 1. Definitions............................................. 19 4.2 2. Grant of Copyright License..................................... 20 4.3 3. Grant of Patent License....................................... 20 4.4 4. Redistribution............................................ 20 4.5 5. Submission of Contributions.................................... 21 4.6 6. Trademarks............................................. 21 4.7 7. Disclaimer of Warranty....................................... 21 4.8 8. Limitation of Liability....................................... 21 4.9 9. Accepting Warranty or Additional Liability............................ 21 II Main Documentation 23 5 Using PoC 25 5.1 Requirements............................................. 26 i 5.2 Downloading PoC.......................................... 28 5.3 Integrating PoC into Projects..................................... 31 5.4 Configuring PoC’s Infrastructure.................................. 32 5.5 Creating my_config/my_project.vhdl................................ 36 5.6 Adding IP Cores to a Project..................................... 37 5.7 Simulation.............................................. 38 5.8 Synthesis............................................... 45 5.9 Project Management......................................... 49 5.10 Pre-Compiling Vendor Libraries................................... 49 5.11 Miscellaneous............................................ 56 6 IP Core Interfaces 57 6.1 Command-Status-Error (PoC.CSE) Interface............................ 57 6.2 PoC.FIFO Interface......................................... 57 6.3 PoC.Mem Interface.......................................... 57 6.4 PoC.Stream Interface......................................... 59 7 IP Core Documentations 61 7.1 Common Packages.......................................... 61 7.2 Simulation Packages......................................... 62 7.3 PoC.alt................................................ 64 7.4 PoC.arith............................................... 64 7.5 PoC.bus................................................ 74 7.6 PoC.cache.............................................. 80 7.7 PoC.comm.............................................. 91 7.8 PoC.dstruct.............................................. 92 7.9 PoC.fifo................................................ 94 7.10 PoC.io................................................ 101 7.11 PoC.mem............................................... 118 7.12 PoC.misc............................................... 137 7.13 PoC.net................................................ 152 7.14 PoC.sort............................................... 188 7.15 PoC.xil................................................ 196 8 Third Party Libraries 203 8.1 Cocotb................................................ 203 8.2 OSVVM............................................... 203 8.3 UVVM................................................ 204 8.4 VUnit................................................. 204 8.5 Updating Linked Git Submodules.................................. 204 9 Constraint Files 207 9.1 IP Core Constraint Files....................................... 207 9.2 Board Constraint Files........................................ 208 10 Tool Chain Specifics 213 10.1 Aldec Active-HDL.......................................... 213 10.2 Mentor QuestaSim.......................................... 213 10.3 Xilinx ISE.............................................. 213 10.4 Xilinx Vivado............................................. 213 11 Examples 215 III References 217 12 Command Reference 219 12.1 PoC Wrapper Scripts......................................... 219 12.2 Main Program (PoC.py)...................................... 220 ii 12.3 Pre-compile Scripts......................................... 220 13 IP Core Database 231 13.1 Overview............................................... 231 13.2 Database Structure.......................................... 232 13.3 Supported Options.......................................... 234 13.4 Files in detail............................................. 235 13.5 User Defined Variables........................................ 235 14 More References 237 14.1 List of Supported FPGA Devices.................................. 237 14.2 List of Supported Boards....................................... 238 14.3 Wrapper Script Hook Files...................................... 238 14.4 File Formats............................................. 239 14.5 Naming Conventions......................................... 243 14.6 Known Issues............................................. 245 14.7 Local License Copies........................................ 246 IV Appendix 261 15 Change Log 263 16 Index 265 iii iv Part I Introduction 1 The PoC-Library Documentation, Release 1.2.0 This library is published and maintained by Chair for VLSI Design, Diagnostics and Architecture - Faculty of Computer Science, Technische Universität Dresden, Germany https://tu-dresden.de/ing/informatik/ti/vlsi PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and con- stants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy. Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend. News See Change Log for latest updates. Cite the PoC-Library The PoC-Library hosted at GitHub.com. Please use the following biblatex entry to cite us: # BibLaTex example entry @online{poc, title={{PoC - Pile of Cores}}, author={{Chair of VLSI Design, Diagnostics and Architecture}}, organization={{Technische Universität Dresden}}, year={2016}, url={https://github.com/VLSI-EDA/PoC}, urldate={2016-10-28}, } 3 The PoC-Library Documentation, Release 1.2.0 4 CHAPTER 1 What is PoC? PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs. All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and con- stants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy. Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based Infrastruture to offer a command line based frontend. The PoC-Library pursues the following five goals: • independence in the platform, target, vendor and tool chain • generic, efficient, resource sparing and fast implementations of IP cores • optimized for several device architectures, if suitable • supportive scripts to ease the IP core handling with all supported vendor tools on all listed operating systems • ship all IP cores with testbenches for local and online verification In detail the PoC-Library is: • synthesizable for ASIC and FPGA devices, e.g. from Altera, Lattice, Xilinx, . , • supports a wide range of simulation and synthesis tool chains, and is • executable on several host platforms: Darwin, Linux or Windows. This is achieved by using generic HDL descriptions, which work with most synthesis and simulation tools men- tioned above. If this is not the case, then PoC uses vendor or tool dependent work-arounds.