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Design Principles for Packet Deparsers on Fpgas

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Design Principles for Packet Deparsers on Fpgas Design Principles for Packet Deparsers on FPGAs Thomas Luinaud Jeferson Santiago da Silva [email protected] [email protected] Polytechnique Montréal Kaloom Inc. Montréal, Canada Montréal, Canada J.M. Pierre Langlois Yvon Savaria [email protected] [email protected] Polytechnique Montréal Polytechnique Montréal Montréal, Canada Montréal, Canada ABSTRACT KEYWORDS The P4 language has drastically changed the networking field as it Packet deparsers; Graph optimization; P4 language allows to quickly describe and implement new networking appli- ACM Reference Format: cations. Although a large variety of applications can be described Thomas Luinaud, Jeferson Santiago da Silva, J.M. Pierre Langlois, and Yvon with the P4 language, current programmable switch architectures Savaria. 2021. Design Principles for Packet Deparsers on FPGAs. In Proceed- impose significant constraints on P4 programs. To address this ings of the 2021 ACM/SIGDA International Symposium on Field Programmable shortcoming, FPGAs have been explored as potential targets for P4 Gate Arrays (FPGA ’21), February 28-March 2, 2021, Virtual Event, USA. ACM, applications. P4 applications are described using three abstractions: New York, NY, USA, 7 pages. https://doi.org/10.1145/3431920.3439303 a packet parser, match-action tables, and a packet deparser, which reassembles the output packet with the result of the match-action tables. While implementations of packet parsers and match-action 1 INTRODUCTION tables on FPGAs have been widely covered in the literature, no gen- The P4 Domain Specific Language (DSL) [6] has reshaped the net- eral design principles have been presented for the packet deparser. working domain as it allows describing custom packet forwarding Indeed, implementing a high-speed and efficient deparser on FPGAs applications with much flexibility. There has been a growing in- remains an open issue because it requires a large amount of inter- terest in using FPGAs to offload networking tasks. For instance, connections and the architecture must be tailored to a P4 program. Microsoft already deploy FPGAs in their data centers to implement As a result, in several works where a P4 application is implemented the data plane of Azure servers [8]. In-network computing is an- on FPGAs, the deparser consumes a significant proportion of chip other avenue where FPGAs have recently been considered [20]. resources. Hence, in this paper, we address this issue by presenting In addition, several recent works exploit FPGA reconfigurability design principles for efficient and high-speed deparsers on FPGAs. to create programmable data planes and implement P4 applica- As an artifact, we introduce a tool that generates an efficient vendor- tions [5, 13, 21]. agnostic deparser architecture from a P4 program. Our design has As presented in Figure 1, a P4 application comprises three ab- been validated and simulated with a cocotb-based framework. The stractions: the packet parser, the processing stage (match-action resulting architecture is implemented on Xilinx Ultrascale+ FPGAs tables), and the packet deparser (§2.2). While designs of efficient and supports a throughput of more than 200 Gbps while reducing packet parsers on FPGA have been widely explored [3, 5, 19], little resource usage by almost 10× compared to other solutions. effort has been dedicated to the implementation of efficient packet deparsers. First, to the best of our knowledge, only a single paper CCS CONCEPTS covers this topic [7]. However, Cabal et al. [7] report only the FPGA resource consumption for a 100 Gbps packet deparser, while the • Hardware ! Reconfigurable logic applications; • Computer design principles and microarchitectural details are not covered. arXiv:2103.07750v1 [cs.AR] 13 Mar 2021 systems organization ! Reconfigurable computing; High- Second, as Luinaud et al. [16] have observed, a packet deparser can level language architectures; • Networks ! Programming in- consume more than 80% of the resources needed to implement a terfaces. complete pipeline, which can jeopardize the ability of FPGAs to implement more complex P4 applications. This paper introduces an open-source solution to generate effi- cient and high-speed packet deparsers on FPGAs. It lays the foun- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed dations for the design principles of packet deparsers on FPGAs. It for profit or commercial advantage and that copies bear this notice and the full citation comprises an architecture and a compiler to generate a deparser on the first page. Copyrights for components of this work owned by others than ACM from a P4 program. must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a The deparser compiler (§4) is described in Python and generates fee. Request permissions from [email protected]. synthesizable VHDL code for the proposed deparser architecture. FPGA ’21, February 28-March 2, 2021, Virtual Event, USA The generated architecture leverages the inherent configurability © 2021 Association for Computing Machinery. ACM ISBN 978-1-4503-8218-2/21/02...$15.00 of FPGAs to avoid hardware constructs that cannot be efficiently https://doi.org/10.1145/3431920.3439303 implemented on FPGAs, such as crossbars or barrel shifters [1, 25]. PHV_data PHV PHV_valid Pkt_in Pkt_out shifters Pkt_out PHV PHV Selector Payload Payload Parser shifters Deparser Processing Figure 2: Deparser architecture overview Packet Payload Because the sequence of emit statements determines the header Figure 1: Considered switch architecture emission order, and because the validity bit can be altered by previ- ous control blocks, the deparser must be able to insert or remove headers at runtime. The simulation environment is based on cocotb [11], which al- lows using several off-the-shelf Python packages, such as Scapy, 2.2 P4 Program Components to generate test cases. In addition, it is possible to connect the This paper considers the switch structure proposed by Benáček design under test with virtual network interfaces [12]. As a re- et al. [5], composed of three parts: a parser, a processing part and a sult, behavioural validation can be done using the P4 behavioural deparser, as presented in Figure 1. reference model [17]. The generated architecture has been evaluated for a variety of Parser. The parser takes as input a packet and generates a Packet packet headers. The evaluations show that the generated deparser Header Vector (PHV) and a packet payload. In our design, we as- supports more than 200 Gbps packet throughput while reducing sume that the PHV is composed of two parts : the PHV_data bus the resource usage by more than 10× compared to state-of-the-art containing header data and a bitmap vector, the PHV_valid bus, in- solutions (§5). dicating the validity bit of each header component. We also assume The contributions of this paper are as follows: that the packet payload is sent through a streaming bus with the • A deparser architecture that leverages FPGA configurabil- first byte at position 0. ity (§3); Processing. The processing part takes as input the PHV from • An open-source P4-to-VHDL packet deparser compiler (§4); the parser and outputs a modified PHV, which is forwarded tothe and, deparser. The operations on the PHV can either be header data • A simulation environment based on cocotb to simplify de- modifications or header validity bit alteration. parser verification (§5). Deparser. The deparser block takes as input the PHV from the processing part and the payload from the parser. It outputs the 2 PACKET PROCESSING packet to be sent on a streaming bus. This section introduces the P4 language and how P4 program com- ponents are organized to describe packet processing. 3 DEPARSER ARCHITECTURE PRINCIPLES In this section we cover the deparser architecture principles. First, 2.1 P4 language we introduce a deparser abstract machine. Second, we cover the P4 [6] is an imperative DSL used to describe custom packet pro- deparser I/O signals. Third, we present the microarchitecture of cessing on programmable data planes. the proposed deparser. All our design choices use the inherent configurability of the FPGAs and provide configurable blocks for 2.1.1 Overview of P4 programs. There are four components that the deparser compiler. structure a P4 program: header, parser, control, and switch.A header is a structure composed of fields of specific width anda 3.1 Deparser Abstract Machine validity bit. A struct of headers is used to define the set of headers that can be processed by a P4 program. The parser block expresses The deparser abstract machine is described in Figure 2. In this in which order and how to extract packet headers. The Control architecture, we assume that the PHV is buffered and arrives at the block describes the operations to perform on headers. deparser together with a PHV valid vector. Algorithm 1 presents the pseudo-code for the PHV shifters mod- 2.1.2 Control Operations. In a control block, multiple operation ule while Algorithm 2 illustrates the payload shifter. types can be performed to modify headers. Two specific opera- The main limiting factors to implement a deparser on FPGAs are tions are of interest for the deparser, setValid and setInvalid, the high number of interconnections and barrel shifters required which can be used to set a header validity bit to valid or invalid, for header insertion. To limit the use of these blocks, we construct respectively. a new packet based on the header and the payload. Thus, as the P4 In P4, control blocks also implement the deparsing logic. These deparsing logic can entirely be inferred at compile time and since blocks are composed of a series of emit statements. First, the order FPGAs are reconfigurable, we tailor the deparser architecture toa of these statements determines in which order headers are emitted.
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