VIA C3 Nehemiah Processor Datasheet
Revision 1.13
September 29, 2004
VIA TECHNOLOGIES, INC.
VIA C3 Nehemiah Processor Datasheet September 29, 2004
This is Version 1.13 of the VIA C3 Nehemiah Processor Datasheet.
© 2003-2004 VIA Technologies, Inc All Rights Reserved.
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LIFE SUPPORT POLICY
VIA processor products are not authorized for use as components in life support or other medical devices or systems (hereinafter life support devices) unless a specific written agreement pertaining to such intended use is executed be- tween the manufacturer and an officer of VIA. 1. Life support devices are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. This policy covers any component of a life support device or system whose failure to perform can cause the failure of the life support device or system, or to affect its safety or effectiveness.
September 29, 2004 VIA C3 Nehemiah Processor Datasheet
Revision History
Document Release Date Revision Initials 1.0 11/26/03 Initial external release EY 1.10 3/11/04 Updated table 5-3 JW Updated POWERGOOD information in figures 4-5, 4-6 and 1.11 07/30/04 table 3-3 JW 1.12 9/1/04 Updated table 4-13 JW 1.13 9/29/04 Updated table A-3 JW
Revision History i VIA C3 Nehemiah Processor Datasheet September 29, 2004
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ii Revision History September 29, 2004 VIA C3 Nehemiah Processor Datasheet
Table of Contents INTRODUCTION ...... 1-1 1.1 DATASHEET OUTLINE ...... 1-1 1.2 BASIC FEATURES ...... 1-2 1.3 PROCESSOR VERSIONS ...... 1-3 1.4 COMPATIBILITY ...... 1-4 PROGRAMMING INTERFACE...... 2-1 2.1 GENERAL ...... 2-1 2.2 ADDITIONAL FUNCTIONS ...... 2-3 2.3 ACHINE-SPECIFIC FUNCTIONS...... 2-4 2.3.1 general...... 2-4 2.3.2 standard cpuid instruction functions...... 2-4 2.3.3 extended cpuid instruction functions...... 2-6 2.3.4 centaur extended cpuid instruction functions...... 2-9 2.3.5 processor identification...... 2-10 2.3.6 edx value after reset ...... 2-10 2.3.7 control register 4 (cr4)...... 2-11 2.3.8 Machine-Specific Registers...... 2-11 2.4 OMITTED FUNCTIONS...... 2-12 HARDWARE INTERFACE ...... 3-1 3.1 BUS INTERFACE ...... 3-1 3.1.1 differences ...... 3-2 3.1.2 clarifications ...... 3-3 3.1.3 omissions...... 3-6 3.2 PIN DESCRIPTION ...... 3-7 3.3 POWER MANAGEMENT...... 3-10 3.4 TEST & DEBUG ...... 3-12 3.4.1 bist...... 3-12 3.4.2 jtag ...... 3-12 3.4.3 debug port ...... 3-12 ELECTRICAL SPECIFICATIONS ...... 4-1 4.1 AC TIMING TABLES ...... 4-1 4.2 DC SPECIFICATIONS ...... 4-12 4.2.1 recommended operating conditions ...... 4-12 4.2.2 maximum ratings...... 4-14 4.2.3 dc characteristics ...... 4-15 4.2.4 power dissipation ...... 4-16 MECHANICAL SPECIFICATIONS...... 5-1 5.1 CPGA PACKAGE ...... 5-1 5.2 EBGA PACKAGE ...... 5-7 THERMAL SPECIFICATIONS ...... 6-1 6.1 INTRODUCTION...... 6-1 6.2 TYPICAL ENVIRONMENTS ...... 6-1 6.3 MEASURING TC ...... 6-2
Table of Contents i VIA C3 Nehemiah Processor Datasheet September 29, 2004
6.4 MEASURING TJ ...... 6-2 6.5 ESTIMATING TC ...... 6-3 MACHINE SPECIFIC REGISTERS...... A-1 A.1 GENERAL ...... A-1 A.2 CATEGORY 1 MSRS ...... A-4 A.3 CATEGORY 2 MSRS ...... A-8
ii Table of Contents September 29, 2004 VIA C3 Nehemiah Processor Datasheet
List of Figures
Figure 4-1. BCLK Generic Clock Timing Waveform...... 4-5 Figure 4-2. Valid Delay Timings...... 4-5 Figure 4-3. Setup and Hold Timings ...... 4-6 Figure 4-4. Cold/Warm Reset and Configuration Timings ...... 4-6 Figure 4-5. Power-on Sequence and Reset Timings...... 4-7 Figure 4-6. Power Down Sequencing and Timings (VCC Leading)...... 4-8 Figure 4-7. Power Down Sequencing and Timings (VTT Leading) ...... 4-9 Figure 4-8. Stop Grant/Sleep Timing (SLP# assertion method)...... 4-10 Figure 4-9. Stop Grant/Deep Sleep Timing (BCLK Stopping method) ...... 4-11 Figure 5-1. CPGA Pinout (Pinside View) ...... 5-2 Figure 5-2. CPGA with Heat Slug Dimensions...... 5-5 Figure 5-3. CPGA Top Marking Design ...... 5-6 Figure 5-4. EBGA Ball Diagram (Bottom View)...... 5-8 Figure 5-5. EBGA Mechanical Specification...... 5-13 Figure 5-6. EBGA Top Marking Design...... 5-14
List of Figures i VIA C3 Nehemiah Processor Datasheet September 29, 2004
List of Tables
Table 3-1. BSEL Frequency Mapping...... 3-2 Table 3-2. Core Voltage Settings ...... 3-4 Table 3-3. Pin Descriptions ...... 3-7 Table 3-4. BGA only Pin Descriptions...... 3-8 Table 3-5. Clock Ratio ...... 3-9 Table 4-1: System Bus Clock AC Specifications (133 MHz)1 ...... 4-1 Table 4-2. System Bus Clock AC Specifications (100 MHz)1 ...... 4-2 Table 4-3. Bus Signal Groups AC Specifications1,8 ...... 4-2 Table 4-4. CMOS and Open-drain Signal GROUPS AC Specifications1,2 ...... 4-3 Table 4-5. Reset Configuration AC Specifications and Power On/Power Down Timings ...... 4-3 Table 4-6. APIC Bus Signal AC Specifications1...... 4-4 Table 4-7. StopGrant / Sleep / Deep Sleep AC Specifications1, 3, 4 ...... 4-4 Table 4-8. Recommended Operating Conditions ...... 4-12
Table 4-9. VCC Static and Transient Tolerance...... 4-13 Table 4-10. Maximum Ratings...... 4-14 Table 4-11. DC Characteristics ...... 4-15 Table 4-12. CMOS DC Characteristics ...... 4-15 Table 4-13. Thermal Design Power Information...... 4-16
Table 4-14. VTT-I/O Power Consumption...... 4-16 Table 5-1. CPGA Pin Cross Reference ...... 5-3 Table 5-2. CPGA Package Dimensions...... 5-5 Table 5-3. EBGA Ball Cross Reference...... 5-9 Table A-1. Category 1 MSRs ...... A-2 Table A-2. Category 2 MSRs ...... A-3 Table A-3. FCR Bit Assignments...... A-8
ii List of Tables September 29, 2004 VIA C3 Nehemiah Processor Datasheet
SECTION
INTRODUCTION
The VIA C3 Nehemiah processor is based on a unique internal architecture and is manufactured using an advanced 0.13µ CMOS technology. This architecture and process technology provides a highly compati- ble, high-performance, low-cost and low-power solution for the desktop PC, notebook and Internet Appliance markets. The VIA Nehemiah family also provides Padlock, a suite a security technologies. The VIA C3 Nehemiah processor is available in several GHz versions. When considered individually, the compatibility, function, performance, cost and power dissipation of the VIA C3 Nehemiah processor family are all very competitive. When considered as a whole, the VIA C3 Nehemiah processor family offers a breakthrough level of value.
1.1 DATASHEET OUTLINE The intent of this datasheet is to make it easy for a direct user—a board designer, a system designer, or a BIOS developer—to use the VIA C3 Nehemiah processor. In the datasheet, Section 1 summarizes the key features of the VIA C3 Nehemiah processor. Section 2 specifies the primary programming interface and Section 3 does the same for the bus interface. Sections 4, 5, and 6 specify the classical datasheet topics of AC timings, pinouts and mechanical specifications. Appendix A documents the VIA C3 Nehemiah processor machine specific registers (MSRs).
Section 1 Architecture 1-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004
1.2 BASIC FEATURES The VIA C3 Nehemiah processor family currently consists of two basic models with several different GHz versions. Due to its low power dissipation, the two models are ideally suited for both desktop and mobile applications. All versions share the following common features (except as noted):