. Inc s e gi l o ia d VIA Eden-Nnt re hnol i c de Embeddede Systemi quPlatform T nf e Processoro R IA C A V D DatasheetN
Revision 0.92 October 22, 2004
VIA TECHNOLOGIES, INC.
VIA Eden-N Processor Datasheet October 22, 2004
This is Version 0.92 of the VIA Eden-N Processor Datasheet.
© 2003-2004 VIA Technologies, Inc All Rights Reserved.
VIA reserves the right to make changes in its products without notice in order to improve design or performance characteristics. This publication neither states nor implies any representations or warranties of any kind, including but not limited to any implied warranty of merchantability or fitness for a particular purpose. No license, express or implied, to any intellectual property rights is granted by this document. VIA makes no representations or warranties with respect to the accuracy or completeness of the con- tents of this publication or the information contained herein, and reserves the right to make. changes at any time, without notice. VIA disclaims responsibility for any consequences resulting from the use of the information included herein. Inc Cyrix and VIA C3 are trademarks of VIA Technologies, Inc. s CentaurHauls is a trademark of Centaur Technology Corporation. e AMD, AMD K6, and Athlon are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoftgi Corporation. l o a Intel, Pentium, Celeron, and MMX are registered trademarks of Intel Corporation.i d Other product names used in this publication are for identification purposes only and maye be trade- marks of their respective companies. nt r hnol i c ide qu e e LIFE SUPPORT POLICY T nf VIA processor products are not authorized for use as componentso in life Rsupport or other medical devices or systems (hereinafter life support devices)A unless a specificC written agreement pertaining to such intended use is executed be- tween the manufacturer and anI officer of VIA. A 1. Life support devices are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to Vperform, when properly used in accordanceD with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. This policy covers any component of a life support deviceN or system whose failure to perform can cause the failure of the life support device or system, or to affect its safety or effectiveness. October 22, 2004 VIA Eden-N Processor Datasheet
Revision History
Document Release Date Revision Initials 0.7 11/12/03 For internal use only CJH 0.8 11/28/03 Release Candidate CJH Modified Table 3-2 BR[1:0] renamed to BREQ[1:0] Added IERR# Added Vcc_Sense Added Vss_Sense . Added Vref_cmos Modified Figure 5-1 and Table 5-1 and 5-2 nc Renamed ball A-18 as Vref_cmos I Renamed ball G-17 as RSVD (was sPREQ) Renamed ball N-17 as IERR (wase RSVD) Renamed ball K-5 as Vss_sensegi (was Vss)l Renamed ball P-7 as Vcc_senseo (was Vcc)a Renamed ball U-12 as RSVD (was BSEL1)i d e Renamed ball U-13 as RSVD (wasnt BSEL0) r Fixed Table linkhnol in notes of Table 4-4 i Adjusted formattingc in Sectionde 4 0.9 6/1/04 Updated tables 4-8, 4-12 i qu JW e e 0.91 7/30/04 UpdatedT POWERGOODnf information in figures 4-5, 4-6 and table JW 3-2 o R 0.92 10/22/04A Updated tableC 4-12 JW I A V D N
Revision History i VIA Eden-N Processor Datasheet October 22, 2004
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ii Revision History October 22, 2004 VIA Eden-N Processor Datasheet
Table of Contents
INTRODUCTION...... 1-1
1.1 DATASHEET OUTLINE ...... 1-1 1.2 BASIC FEATURES ...... 1-2 1.3 PROCESSOR VERSIONS...... 1-2 1.4 COMPATIBILITY...... 1-3 PROGRAMMING INTERFACE ...... 2-1
2.1 GENERAL ...... 2-1 2.2 ADDITIONAL FUNCTIONS...... 2-3 2.3 MACHINE-SPECIFIC FUNCTIONS...... 2-4. 2.3.1 General ...... nc ...... 2-4 2.3.2 Standard CPUID Instruction Functions...... I ...... 2-4 2.3.3 Extended CPUID Instruction Functions...... 2-6 2.3.4 Centaur Extended CPUID Instruction Functions...... s .2-8 2.3.5 Processor Identification...... e ...... 2-9 2.3.6 EDX Value after Reset...... gi l ...... 2-9 2.3.7 Control Register 4 (CR4)...... o a ...... 2-10 2.3.8 Machine-Specific Registers...... i d...... 2-10 2.4 OMITTED FUNCTIONS ...... nt re ...2-11 HARDWARE INTERFACE ...... hnol i 3-1 3.1 BUS INTERFACE...... c de ...... 3-1 3.1.1 Clarifications ...... e i qu ...... 3-2 3.1.2 Omissions...... nf e ...... 3-2 BALL DESCRIPTION ...... T ...... 3-3 3.2 o R 3.3 POWER MANAGEMENTA...... 3-6 3.4 TEST & DEBUG...... C A ...... 3-8 3.4.1 BIST ...... I ...... 3-8 3.4.2 JTAG...... V D ...... 3-8 3.4.3 Debug Port ...... N ...... 3-8 ELECTRICAL SPECIFICATIONS ...... 4-1
4.1 AC TIMING TABLES...... 4-1 4.2 DC SPECIFICATIONS...... 4-11 4.2.1 Recommended Operating Conditions ...... 4-11 4.2.2 Maximum Ratings ...... 4-12 4.2.3 DC Characteristics ...... 4-13 4.2.4 Power Dissipation ...... 4-14
Table of Contents i VIA Eden-N Processor Datasheet October 22, 2004
MECHANICAL SPECIFICATIONS...... 5-1
5.1 NANOBGA PACKAGE...... 5-1 THERMAL SPECIFICATIONS ...... 6-1
6.1 INTRODUCTION ...... 6-1 6.2 TYPICAL ENVIRONMENTS ...... 6-1
6.3 MEASURING TC ...... 6-2
6.4 MEASURING TJ...... 6-2
6.5 ESTIMATING TC ...... 6-3 MACHINE SPECIFIC REGISTERS ...... 7-1
7.1 GENERAL ...... 7-1 7.2 CATEGORY 1 MSRS ...... nc ...... 7-4 7.3 CATEGORY 2 MSRS ...... I ...... 7-8 s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
ii Revision History October 22, 2004 VIA Eden-N Processor Datasheet
List of Figures FIGURE 3-1: POWER MANAGEMENT STATE DIAGRAM...... 3-7 FIGURE 4-1. BCLK GENERIC CLOCK TIMING WAVEFORM ...... 4-5 FIGURE 4-2. VALID DELAY TIMINGS ...... 4-5 FIGURE 4-3. SETUP AND HOLD TIMINGS...... 4-6 FIGURE 4-4. COLD/WARM RESET AND CONFIGURATION TIMINGS ...... 4-6 FIGURE 4-5. POWER-ON SEQUENCE AND RESET TIMINGS ...... 4-7 FIGURE 4-6. POWER DOWN SEQUENCING AND TIMINGS (VCC LEADING)...... 4-8 FIGURE 4-7. POWER DOWN SEQUENCING AND TIMINGS (VTT LEADING)...... 4-9 FIGURE 4-8. STOP GRANT /SLEEP TIMING (BCLK STOPPING METHOD)...... 4-10 FIGURE 4-9. STOP GRANT/SLEEP TIMING (SLP# ASSERTION METHOD)...... 4-10 FIGURE 5-1 NANOBGA BALLOUT (TOP VIEW)...... 5-2 FIGURE 5-2. NANOBGA DIMENSIONS...... 5-13.
Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
List of Figures i VIA Eden-N Processor Datasheet October 22, 2004
List of Tables TABLE 2-1. CPUID RETURN VALUES (EAX = 0)...... 2-4 TABLE 2-2. CPUID FEATURE FLAG VALUES (EAX = 1)...... 2-5 TABLE 2-3. EXTENDED CPUID FUNCTIONS ...... 2-6 TABLE 2-4. L1 CACHE & TLB CONFIGURATION ENCODING ...... 2-7 TABLE 2-5. L2 CACHE CONFIGURATION ENCODING ...... 2-7 TABLE 2-6. CENTAUR EXTENDED CPUID INSTRUCTION FUNCTIONS...... 2-8 TABLE 2-7. CENTAUR EXTENDED CPUID FEATURE FLAG VALUES ...... 2-8 TABLE 2-8. CR4 BITS ...... 2-10 TABLE 3-1. CORE VOLTAGE SETTINGS...... 3-2 TABLE 3-2. BALL DESCRIPTIONS ...... 3-3 TABLE 3-3. CLOCK RATIO...... 3-5 TABLE 4-1. SYSTEM BUS CLOCK AC SPECIFICATIONS (133 MHZ)1...... 4-1. TABLE 4-2. SYSTEM BUS CLOCK AC SPECIFICATIONS (100 MHZ)1...... 4-2 TABLE 4-3. BUS SIGNAL GROUPS AC SPECIFICATIONS1,8...... 4-2nc TABLE 4-4. CMOS AND OPEN-DRAIN SIGNAL GROUPS AC SPECIFICATIONS1,I 2...... 4-3 TABLE 4-5. RESET CONFIGURATION AC SPECIFICATIONS AND POWER ON/POWER DOWN TIMINGS ...... 4-3 TABLE 4-6. APIC BUS SIGNAL AC SPECIFICATIONS1...... 4-4s TABLE 4-7. STOPGRANT/DEEP SLEEP AC SPECIFICATIONS1, 3, 4...... 4-4e TABLE 4-8. RECOMMENDED OPERATING CONDITIONS ...... 4-11 TABLE 4-9. MAXIMUM RATINGS ...... 4-12gi l TABLE 4-10. DC CHARACTERISTICS...... 4-13o a TABLE 4-11. CMOS DC CHARACTERISTICS ...... 4-13i d TABLE 4-12. THERMAL DESIGN POWER INFORMATION ...... 4-14e TABLE 4-13. VTT-I/O POWER CONSUMPTION ...... 4-15nt r TABLE 5-1. SIGNAL LISTING (ALPHABETICAL ORDER)...... 5-3i TABLE 5-2. SIGNAL LISTING IN NUMERICAL ORDERhnol...... 5-8de TABLE 7-1. CATEGORY 1 MSRS ...... 7-2c i qu TABLE 7-2. CATEGORY 2 MSRS ...... 7-3e e TABLE 7-3. BUS CLOCK FREQUENCY TRATIO ...... 7-5nf TABLE 7-4. FCR BIT ASSIGNMENTS ...... 7-8R o IA C A V D N
ii List of Tables October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. INTRODUCTION Inc s The VIA Eden-N processor is based on a unique internal architecture and is manufactured using an ad- vanced 0.13µ CMOS technology. This architecture and the processe technology provide a highly compatible, high-performance, low-cost and low-power consumptiongi solutionl for fanless, embedded markets. The VIA Eden-N processor is available at numerouso operating frequencies.a When considered individually, the compatibility, function, performance, icost and power dissipationd of the VIA Eden-N processor family are all very competitive. When considered as a whole,e the VIA Eden-N processor family offers a breakthrough level of value. nt r hnol i c ide qu 1.1 DATASHEET OUTLINE e e The intent of this datasheet is to makeT it easy for a nfdirect user—a board designer, a system designer, or a BIOS developer—to use the VIA Eden-N processor.o R In the datasheet, Section 1 summarizesA the Ckey features of the VIA Eden-N processor. Section 2 specifies the primary programmingI interface and Section 3 does theA same for the bus interface. Sections 4, 5 and 6 specify the classicalV datasheet topics of AC timings, balloutsD and mechanical specifications. Section 7 documents the VIA Eden-N processorN machine specific registers (MSRs).
Section 1 Introduction 1-1 VIA Eden-N Processor Datasheet October 22, 2004
1.2 BASIC FEATURES With the low power dissipation, the VIA Eden-N processor is ideally suited for fanless embedded applica- tions. All versions share the following common features (except as noted):
World’s smallest x86 processor with package size of 15mm x 15 mm
World’s fasted AES encryption using the Advanced Cryptography Engine (ACE)
Software-compatible with thousands of x86 software applications available
MMX-compatible instructions
SSE-compatible instructions
Two large (64-KB each, 2-way) on-chip caches . 64-KB Level 2 victim cache (16-way) nc Two large TLBs (128 entries each, 8-way) I Branch Target Address Cache with 1k entries each identifying 2 sbranches Unique and sophisticated branch prediction mechanisms e Bus speeds up to 133 MHz gi l Extremely low power dissipation o a 2 i d Very small die-47 mm in TSMC 0.13µ technology e nt ir 1.3 PROCESSOR VERSIONS hnol c ide Typically, there are five specification parameterse that characterize differentqu versions of a processor family: package, voltage, maximum case temperature,T externalnf bus speed, and einternal MHz. The VIA Eden-N processor family is delivered ino a nanoBGA package.R The processor core voltage is de- fined by motherboard strappingA options. The internal operating frequency (MHz) ofC a particular VIAA Eden-N processor is defined by two parame- ters: the specified externalI bus speed and the internal bus-clock multiplier. VIA Eden-N processors operate the bus at 133V MHz bus. D The bus-clock multiplier is also configured by motherboard strapping options. Several different clock- multiplier versions are currently offered. N
The VIA Eden-N processor is available at these speed grades: • 533 MHz (4.0 x 133-MHz bus) • 800 MHz (6.0 x 133-MHz bus) • 1.0 GHz (7.5 x 133-MHz bus)
Future versions of the VIA Eden-N processor may provide other speed grades, bus speed combina- tions and different core voltages. More information on these topics is included in Sections 4, 5 and 6 of this datasheet.
1-2 Introduction Section 1 October 22, 2004 VIA Eden-N Processor Datasheet
1.4 COMPATIBILITY The VIA Eden-N processor has a unique footprint. Experienced system designers will find the bus proto- col and electrical characteristics familiar to prior Eden processors. Currently, BIOS support for the VIA Eden-N processor is available from Award, AMI, Phoenix, and Insyde. The VIA Eden-N processor integrates termination of bus signals. Physical and bus compatibility is cov- ered in more detail in Section 4 of this datasheet. The VIA Eden-N processor supports SSE instructions for better video, audio and faster 3D graphics. Other software functions are provided and are identified to software with the CPUID instruction. The VIA Eden-N processor carefully follows the protocol for defining the availability of these optional features. Both the additional and omitted optional features are covered in more detail in Section 2 of this datasheet. To verify compatibility of the VIA Eden-N processor with real PC applications and. hardware, VIA has performed extensive testing of boards and peripherals, thousands of software applications, and over forty operating systems. Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 1 Introduction 1-3 VIA Eden-N Processor Datasheet October 22, 2004
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1-4 Introduction Section 1 October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. PROGRAMMING INTERFACE Inc s e 2.1 GENERAL gi l o a The VIA Eden-N processor’s functions include: i d All basic x86 instructions, registers, and functions nt re All floating-point (numeric processor) hnolinstructions, registers and functions i All basic operating modes: real mode,c protect mode,i virtual-8086de modequ System Management Interrupt (SMI)e and the associated Systeme Management Mode (SMM) All interrupt and exception Tfunctions nf All debug functions (including the new I/Oo breakpoint function)R A All input/output functionsI C A All tasking functionsV (TSS, task switch, etc.) D Processor initialization behavior
Page Global Enable feature N
MMX instructions
SSE instructions
PAT (Page Attribute Table)
VME (Virtual Mode Enhancements)
SYSENTER/SYSEXIT functions
Section 2 Architecture 2-1 VIA Eden-N Processor Datasheet October 22, 2004
However, there are some software differences between the VIA Eden-N processor and the Intel Celeron processor. These differences fall into three groups:
Implementation-specific differences. Examples are cache and TLB testing features, and perform- ance monitoring features that expose the internal implementation features. These types of functions are incompatible among all different x86 implementations.
Omitted functions. Some Intel Celeron processor functions are not provided on the VIA Eden-N processor because they are not used or are not needed in the targeted PC systems. Examples are some specific bus functions such as functional redundancy checking and performance monitoring. Other examples are architectural extensions such as support for Physical Address Extensions, and JTAG boundary scan. These types of differences are similar to those among various versions of the processors. The CPUID instruction is used by system software to determine whether these features. are supported. Low-level behavioral differences. A few low-level VIA Eden-N processor functions are different from Intel Celeron because the results are (1) documented in the documentationnc as undefined, and (2) known to be different for different x86 implementations. That is,I compatibility with the Intel Celeron processor for these functions is clearly not needed for software compatibility (or they would not be different across different implementations). s This chapter summarizes the first three types of differences: additionale functions, implementation-specific functions and omitted functions. Section 7 contains more detailsgi on machine-specificl functions. o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
2-2 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
2.2 ADDITIONAL FUNCTIONS The VIA Eden-N processor includes a suite of security technologies called Padlock. One Padlock feature is called the Advanced Cryptography Engine (ACE) and provides a high performance implementation of the Advanced Encryption Standard (AES), as specified by the US Government. VIA Eden-N processors also extend Padlock by including two separate Random Number Generators.
Advanced Cryptography Engine: ACE Padlock's Advanced Cryptography Engine provides the world’s fastest AES encryption implementation. Wherever AES software encryption implementations are used today, it can be optimized for ACE with minimal effort. World class AES performance is a user-level instruction away as only one opcode handles encrypt and decrypt functions. See the Padlock ACE programming guide for further details.. Random Number Generator: RNG nc VIA Eden-N processors incorporate two random number generators on the processorsI die for a fast source of entropy. See the Padlock RNG programming guide for further details.s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 2 Architecture 2-3 VIA Eden-N Processor Datasheet October 22, 2004
2.3 MACHINE-SPECIFIC FUNCTIONS
2.3.1 GENERAL All x86 processor implementations provide a variety of machine-specific functions. Examples are cache and TLB testing features and performance monitoring features that expose the internal implementation features. This section describes the VIA Eden-N processor machine-specific functions that are most likely used by software, and compares them to related processors where applicable. Section 7 describes the machine- specific registers (MSRs). This section covers those features of Intel Pentium-compatible processors that are. used to commonly identify and control processor features. All Pentium-compatible processors have the same mechanisms, but the bit-specific data values often differ. nc I 2.3.2 STANDARD CPUID INSTRUCTION FUNCTIONS s The CPUID instruction is available on all contemporary x86 processors.e The CPUID instruction has two standard functions requested via the EAX register. The first function returns a vendor identification string in registers EBX, ECX, and EDX. The second CPUID functiongi returns an assortmentl of bits in EAX and EDX that identify the chip version and describe the specifico features available.ia See the followingd table. Table 2-1. CPUID Return Values (EAX = 0) e EAX TITLE OUTPUT nt ir 0 Largest Function Input Value hnol EAX=1 c EBX,ECX,EDX=”CentaurHauls”ide qu 1 Processor Signature and Featuree Flags EAX[3:0]=Steppinge ID T nfEAX[7:4]=Model ID o EAX[11:8]=Model R ID A C EAX[13:12]=Type ID I EBX,ECX=ReservedA V DEDX=Feature Flags (see Table 2-2)
N
2-4 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
The specific feature flag details in EDX when EAX == 1 are listed in Table 2-2.
Table 2-2. CPUID Feature Flag Values (EAX = 1) EDX BITS – MEANING VIA EDEN-N NOTES 0 – FPU present 1 1 - Virtual Mode Extension 1 2 - Debugging Extensions 1 3 - Page Size Extensions (4MB) 1 4 – Time Stamp Counter (TSC) supported 1 5 - Model Specific Registers present 1 6 - Physical Address Extension 0 7 - Machine Check Exception 0 . 8 - CMPXCHG8B instruction 1 nc 1 9 – APIC supported 1 I 10- Reserved s 11- Fast System Call e 1 12- Memory Range Registers 1 13 - PTE Global Bit supported gi 1/0 l 2 o 14- Machine Check Architecture supported 0 ia d 15- Conditional Move supported 1 e 16- Page Attribute Table nt 1 i r 17- 36-bit Page Size Extensionhnol de 0 18- Processor serial numberc i 0 qu 22:19 - Reserved e e 23- MMX supported nf 1 T o R 24- FXSR A 1 25- StreamingI SIMD ExtensionC supported A 1 31:26V - Reserved D Notes On CPUID Feature Flags: General: an “x/y” entry means that the defaultN setting of this bit is x; however the bit (and the underly- ing function) can be set to y using the FCR MSR. 1. The CMPXCHG8B instruction is provided and always enabled. However, to avoid a bug in an early version of Windows NT, it can be disabled in the corresponding CPUID function bit 8. This default can be changed via bit 1 in the FCR MSR. 2. The VIA Eden-N processor’s support for Page Global Enable can be enabled or disabled by a bit in the FCR. The CPUID bit reports the current setting of this enable control.
Section 2 Architecture 2-5 VIA Eden-N Processor Datasheet October 22, 2004
2.3.3 EXTENDED CPUID INSTRUCTION FUNCTIONS The VIA Eden-N processor supports extended CPUID functions that provide additional information on the VIA Eden-N processor. Extended CPUID functions are requested by executing CPUID with EAX set to any value in the range 0x80000000 through 0x80000006.
The following table summarizes the extended CPUID functions.
Table 2-3. Extended CPUID Functions EAX TITLE OUTPUT 80000000 Largest Extended Function EAX=80000006 Input Value EBX,ECX,EDX=Reserved 80000001 Processor Signature and Fea- EAX=Processor Signature ture Flags EBX,ECX=Reserved . EDX=Extended Feature Flagsnc 80000002 Processor Name String EAX,EBX,ECX,EDX I 80000003 Processor Name String EAX,EBX,ECX,EDXs 80000004 Processor Name String EAX,EBX,ECX,EDXe 80000005 TLB and L1 Cache Information EAX = Reserved EBX = TLBgi Information l ECXo = L1 Data Cachei aInformation d EDX = L1 Instruction Cache Informatione 80000006 L2 Cache Information EAX, EBX, EDXnt = Reserved ir hnolECX = L2 Cache Information c ide Largest Extended Function Inpute Value (EAX==0x80000000) qu Returns 0x80000006 in EAX, the largest extended function input value.e T nf Processor Signature and Feature Flags (EAX==0x80000001)o R Returns processor version informationA in EAX.C A Processor Name StringI (EAX==0x80000002–0x80000004) Returns the name ofV the processor, suitable for BIOSD to display on the screen (ASCII). The string can be up to 48 characters in length. If the string is shorter, the rightmost characters are padded with zero. The leftmost characters go in EAX, then EBX, ECX,N and EDX. The leftmost character goes in least signifi- cant byte (little endian). For example, the string “VIA Nehemiah” would be returned by extended function EAX=0x80000002 as follows: EAX = 0x20414956 EBX = 0x6568654E ECX = 0x6861696D EDX = 0x00000000 Since the string is less than 17 bytes, the extended functions EAX=0x80000003 and EAX=0x80000004 return zero in EAX, EBX, ECX and EDX.
2-6 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
L1 Cache Information (EAX == 0x80000005) Returns information about the implementation of the TLBs and caches:
Table 2-4. L1 Cache & TLB Configuration Encoding
REGISTER DESCRIPTION VALUE
EAX Reserved
EBX TLB Information EBX[31:24] D-TLB associativity 8 EBX[23:16] D-TLB # entries 128 EBX[15: 8] I-TLB associativity 8 EBX[ 7: 0] I-TLB # entries 128 ECX L1 Data Cache Information . ECX[31:24] Size (Kbytes) 64 ECX[23:16] Associativity nc 2 ECX[15: 8] Lines per Tag I 1 ECX[ 7: 0] Line Size (bytes) s 32 EDX L1 Instruction Cache Informatione EDX[31:24] Size (Kbytes) gi l 64 EDX[23:16] Associativityo a 2 EDX[15: 8] Lines per Tag i 1 d e EDX[ 7: 0] Line Size (bytes) nt ir32 Notes On CPUID L1 Cache Associativity: hnol Stepping 8 has an erratum that will inadvertentlyc report 4-wayde L1 caches instead of the proper 2-way L1 caches. The erratum is fixed in future steppings. i qu e e L2 Cache Information (EAX ==T 0x80000006) nf Returns information about the implementation ofo the L2 cache: R A ITable 2-5. L2 CacheC ConfigurationA Encoding REGISTERV DESCRIPTIOND VALUE EAX, EBX, EDX Reserved
ECX L2 DataN Cache Information ECX[31:16] Size (Kbytes) 64 ECX[15:12] Associativity 16 ECX[11: 8] Lines per Tag 1 ECX[ 7: 0] Line Size (bytes) 32
Section 2 Architecture 2-7 VIA Eden-N Processor Datasheet October 22, 2004
2.3.4 CENTAUR EXTENDED CPUID INSTRUCTION FUNCTIONS The VIA Eden-N processor supports special CPUID functions that provide additional information on the VIA Eden-N processor. Centaur CPUID functions are requested by executing CPUID with EAX set to 0xC0000000 or 0xC0000001.
Table 2-6. Centaur Extended CPUID Instruction Functions
EAX INPUT TITLE OUTPUT
Largest Centaur Extended Function Input 0xC0000000 EAX=0xC0000001 Value
EDX=Centaur Extended Feature Flags 0xC0000001 Centaur Extended Feature Flags EAX, EBX, ECX=Reserved. Table 2-7. Centaur Extended CPUID Feature Flag Values EDX BIT VALUE Inc EDX[0]=0 Alternate Instruction Set (AIS) not supported 0 s EDX[0]=1 Alternate Instruction Set (AIS)e supported EDX[1]=0 AIS Disabled 1 EDX[1]=1 AIS Enabled gi l EDX[2]=0 Random Number Generatoro (RNG) Presenta 2 i d EDX[2]=1 Random Number Generator (RNG) Not Present e EDX[3]=0 RNG Disabled 3 nt r EDX[3]=1 RNGhnol Enabled i EDX[4]=0 Longhaul MSR 0x110Ade not available 4 c EDX[4]=1 Longhaul MSR 0x110Ai available qu e e 5 ReservedT nf EDX[6]=0 Advancedo Cryptography EngineR (ACE) Present 6 A EDX[6]=1 AdvancedC CryptographyA Engine (ACE) Not Present I EDX[6]=0 ACE Disabled 7 V EDX[6]=1 ACE EnabledD 31:8 Reserved N
2-8 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
2.3.5 PROCESSOR IDENTIFICATION The VIA Eden-N processor provides a number of machine-specific features. These features are identified by the standard CPUID function EAX=1. Other machine-specific features are controlled by MSRs. Some of these features are not backward compatible with the predecessors in the VIA processor family. System software must not assume that all future processors in the VIA processor family will implement all of the same machine-specific features, or even that these features will be implemented in a backward- compatible manner. In order to determine if the processor supports particular machine-specific features, system software should follow the following procedure.
Identify the processor as a member of the VIA processor family by checking for a Vendor Identification String of “CentaurHauls” using CPUID with EAX=0. Once this has been verified, system software must determine the processor version in order to properly configure the machine-specific registers. In general, system software can determine the processor version by comparing the. Family and Model Identification fields returned by the CPUID standard, extended, or Centaur extendednc functions. If the processor version is not recognized, system software will be unable toI activate any machine-specific feature. s 2.3.6 EDX VALUE AFTER RESET e After reset the EDX register holds a component identification ginumber as follows:l 31:14 13:12 11:8 7:4o 3:0i a d EDX Reserved Type ID Family ID Model ID Stepping ID e 18 2 4 4 nt 4 ir The specific values for the VIA Eden-N processorhnol are listed here: c de PROCESSOR TYPE ID FAMILYe ID MODELi ID STEPPINGqu ID VIA Eden-N 0 T 6 nf 9 Beginse at 8 o R IA C A V D N
Section 2 Architecture 2-9 VIA Eden-N Processor Datasheet October 22, 2004
2.3.7 CONTROL REGISTER 4 (CR4) Control register 4 (CR4) controls some of the advanced features of the Celeron processor. The VIA Eden-N processor provides a CR4 with the following specifics:
Table 2-8. CR4 Bits CELERON CELERON CR4 BITS - MEANING VIA EDEN-N NOTES MODEL 6 MODEL 8 0: VME: Enables VME feature 0/1 0/1 0/1 1: PVI: Enables PVI feature 0/1 0/1 0/1 2: TSD: Makes RDTSC inst privileged 0/1 0/1 0/1 3: DE: Enables I/O breakpoints 0/1 0/1 0/1 4: PSE: Enables 4-MB pages 0/1 0/1 . 0/1 5: PAE: Enables address extensions r r r 6: MCE: Enables machine check exception 0/1 0/1I nc 0/1 1 7: PGE: Enables global page feature 0/1 0/1 0/1 8: PCE: Enables RDPMC for all levels 0/1 s 0/1 0/1 9: OSFXSR: Enables FXSAVE//FXRSTOR Support 0/1 e r 0/1 10: OSXMMEXCPT: O/S Unmasked Exception Support 0/1gi r l 0/1 31:11 – reserved o r ia r r d Notes On CR4 e General: a “0/1” means that the default setting of this bit is 0 but ntthe bit can be setr to (1). A “0” means that the bit is always 0; it cannot be set. An “r” means that this bit is reserved. It appearsi as a 0 when read, and a GP exception is signaled if an attempt ishnol made to writede a 1 to this bit. 1. The VIA Eden-N processor Machine Checkc has different ispecifics than thequ Machine Check function of com- patible processors. e T nf e 2.3.8 MACHINE-SPECIFIC R EGISTERS o R The VIA Eden-N processorA implements theC concept of Machine Specific Registers (MSRs). RDMSR and WRMSR instructions areI provided and the CPUID instructionA identifies that the processor does support MSRs. D In general, the MSRsV are not advantageous to application or operating system software and even they are not used. (This is to be expected since the MSRsN vary from different processors) Section 7 contains a de- tailed description of the VIA Eden-N processor’s MSRs.
2-10 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
2.4 OMITTED FUNCTIONS This section summarizes the functions that are not in the VIA Eden-N processor. A bit in the CPUID fea- ture flags indicates whether these feature are present or not.
Physical Address Extensions: PAE It is absent from the VIA Eden-N processor since our target market are for fanless embedded systems. These systems do not use 2 MB paging; they have greater than 4 GB of system memory.
Page Size Extensions: PSE-36 It is absent since the target operating systems for the VIA Eden-N do not require greater than 4 GB of system memory. . Other Functions Model specific registers pertaining to Machine Check, and Debug, Performancenc Monitoring, and Trace features are not supported. I s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 2 Architecture 2-11 VIA Eden-N Processor Datasheet October 22, 2004
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. Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
2-12 Architecture Section 2 October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. HARDWARE INTERFACE Inc s e 3.1 BUS INTERFACE gi l o a The VIA Eden-N processor bus interface is electrically similar to other VIAi Eden processors.d The majority of the pins within the bus interface are involved with ntthe physical memorye and I/O interface. The remaining pins are power and ground pins, test and debug support pins, and ivarrious ancillary control functions. The pin information and associatedhnol functions are listed and described in this section. c de Bus-to-Core Frequency Ratio Controle i qu The VIA Eden-N processor supports both fixed andnf software controle of the bus-to-core frequency ratio. At reset, the fixed ratio is used fromT motherboard strapping options (BR[4:0] signals). Although unsup- ported on non-PowerSaver processors, this ratioo may be adjusted R via software using the PowerSaver extensions (documented Iseparately).A This adjustmentC lasts Auntil the next reset. Bus Frequency Selection The VIA Eden-N processorV bus frequency is providedD by the motherboard through motherboard strapping options. The VIA Eden-N processor is designed to operate at bus frequencies of 66, 100, 133, or 200 MHz. N
Section 3 Hardware Interface 3-1 VIA Eden-N Processor Datasheet October 22, 2004
3.1.1 CLARIFICATIONS
Power Supply Voltage The voltage provided to the processor core is accomplished through motherboard strapping options. The VIA Eden-N processor expects a voltage mapping corresponding to a mobile VRM like the Maxim 1718. Table 3-1 indicates the voltage range.
Table 3-1. Core Voltage Settings
VID[4:0] VCC VID[4:0] VCC VID[4:0] VCC VID[4:0] VCC 00000 1.750 01000 1.350 10000 0.975 11000 0.775 00001 1.700 01001 1.300 10001 0.950 11001 0.750 00010 1.650 01010 1.250 10010 0.925 11010 0.725. 00011 1.600 01011 1.200 10011 0.900 11011nc 0.700 00100 1.550 01100 1.150 10100 0.875 11100I 0.675 00101 1.500 01101 1.100 10101 0.850 11101 0.650 00110 1.450 01110 1.050 10110 0.825 s11110 0.625 00111 1.400 01111 1.000 10111 0.800e 11111 0.600
RESET# gi l The VIA Eden-N processor is reset by the assertion of the oRESET# pin. ia d Thermal Monitoring e An on-die thermal diode supports thermal monitoring via the THERMDNnt and THERMDPir pins. Advanced Peripheral Interrupt Controllerhnol (APIC) de The VIA Eden-N processor supports thec APIC. Even iif the APIC functionalityqu is not desired, the PICCLK, PICD0, and PICD1 balls muste be connected. T nf e 3.1.2 OMISSIONS o R A C Breakpoint and PerformanceI Monitoring Signals A The VIA Eden-N processor internally supports instruction and data breakpoints. However, the processor does not support theV external indication of breakpointD matches. Similarly, the VIA Eden-N processor con- tains performance monitoring hooks internally, but it does not support the indication of performance monitoring events. N
Error Checking Because of no support for error checking, the VIA Eden-N processor does not equip with BERR#, BINIT#, AERR#, AP#[1:0], DEP#[7:0], IERR#, RP# and RSP# balls.
3-2 Hardware Interface Section 3 October 22, 2004 VIA Eden-N Processor Datasheet
3.2 BALL DESCRIPTION
Table 3-2. Ball Descriptions
Pin Name Description I/O Clock A[31:3]# The address Bus provides addresses for physical memory and external I/O devices. I/O BCLK During cache inquiry cycles, A31#-A3# are used as inputs to perform snoop cycles. A20M# A20 Mask causes the CPU to make (force to 0) the A20 address bit when driving the I(1.5V) ASYNC external address bus or performing an internal cache access. A20M# is provided to emulate the 1 MByte address wrap-around that occurs on the 8086. Snoop addressing is not affected. ADS# Address Strobe begins a memory/I/O cycle and indicates the address bus (A31#-A3#) I/O BCLK and transaction request signals (REQ#) are valid. . APICEN APICEN is a hardware strapping option that enables the APIC functionality when con- I None nected to ground. Otherwise the APIC is disabled. BCLK Bus Clock provides the fundamental timing for the VIA Eden-N CPU. The frequencync of I(2.5V) -- the VIA Eden-N CPU input clock determines the operating frequency of the CPU’s bus. BCLKB I For single ended clocking, external timing is referenced to the rising edges of BCLK.. For differential clocking, external timing is referenced to the crossing point of the rising edge of BCLK and the falling edge of BCLKB e BNR# Block Next Request signals a bus stall by a bus agent unable to accept new transac- I/O BCLK tions. gi l BPRI# Priority Agent Bus Request arbitrates for ownership of othe system bus. ia Id BCLK BR[4:0] Hardware strapping options for setting the processors internal clock multiplier. VIA I Eden-N processors do not have their clock multiplier set to a factory default value. Use e jumpers or populate 0Ω resistors to select the rated multiplier. Thent BR[4:0] balls shouldr be wired to VSS for a value of “0” or wired to OPEN for setting of “1.” See Table 3-3i for ratio values. hnol BREQ[1:0]# BREQ[1:0]# signals request accessc to the system bus.i de qu I/O None CFUSE1 Board strapping option to indicatee the processor bus speed to software.e I None D[63:0]# Data Bus signals are bi-directional signals whichnf provide the data path between the VIA I/O BCLK Eden-N CPU and external T memory and I/O devices. The data bus must assert DRDY# to indicate valid data transfer. o R DBSY# Data Bus Busy Ais asserted by the dataC bus driver to indicate data bus is in use. I/O BCLK DEFER# Defer is assertedI by target agent (e.g., north bridge) andA indicates the transaction can- I BCLK not be guaranteed as an in-order completion. DRDY# Data ReadyV is asserted by data driver to indicateD that a valid signal is on the data bus. I/O BCLK FERR# FPU Error Status indicates an unmasked floating-point error has occurred. FERR# is O(1.5V) ASYNC asserted during execution of the FPU instructionN that caused the error. FLUSH# Flush Internal Caches writing back all data in the modified state. I(1.5V) ASYNC HIT# Snoop Hit indicates that the current cache inquiry address has been found in the cache I/O BCLK (exclusive or shared states). HITM# Snoop Hit Modified indicates that the current cache inquiry address has been found in I/O BCLK the cache and dirty data exists in the cache line (modified state). IGNNE# Ignore Numeric Error forces the VIA Eden-N CPU to ignore any pending unmasked I(1.5V) ASYNC FPU errors and allows continued execution of floating point instructions. IERR# This signal is used for debugging purposes. It should be routed to a test point on the O(1.5V) ASYNC system board.
Section 3 Hardware Interface 3-3 VIA Eden-N Processor Datasheet October 22, 2004
Pin Name Description I/O Clock INIT# Initialization resets integer registers and does not affect internal cache or floating point I(1.5V) ASYNC registers. INTR Indicates external interrupt. Becomes LINT0 when using the APIC. I(1.5V) ASYNC LOCK# Lock Status is used by the CPU to signal to the target that the operation is atomic. I/O BCLK
NCHCTRL Control integrated I/O pull-ups. Connect this signal to VTT with a 14Ω resistor. I ASYNC NMI Indicates Non-Maskable Interrupt. Becomes LINT1 when using the APIC I(1.5V) ASYNC PICCLK APIC clock for operation with the system I/O APIC I APIC PICD[1:0] Bi-directional serial pins for communicating APIC messages to the system I/0 APIC PLL[2:1] Decoupled inputs for the processor’s internal PLL. I (Vcc) ASYNC PWRGD Indicates that the processor’s VCC is stable. I (1.5V) ASYNC REQ[4:0]# Request Command is asserted by bus driver to define current transaction type. . I/O BCLK RESET# Resets the processor and invalidates internal cache without writing back. I BCLK RS[2:0]# Response Status signals the completion status of the current transaction when thenc I BCLK CPU is the response agent. I RTTCTRL Control the output impedance on the on-die termination resistance. Connect this signal I ASYNC to VSS with a 56Ω resistor if relying upon on-die termination. Connect sthis signal to VSS with a 110Ω resistor if relying upon board termination. e SLP# Sleep, when asserted in the stop grant state, causes the CPU to enter the sleep state. I(1.5V) ASYNC SMI# System Management (SMM) Interrupt forces the processor gito save the CPU statel to I(1.5V) ASYNC the top of SMM memory and to begin execution of the SMIo services routine aat the be- ginning of the defined SMM memory space. An SMI is a high-priority interrupti than NMI. d STPCLK# Stop Clock causes the CPU to enter the stop grant state. e I(1.5V) ASYNC THERMDN The anode/cathode pair of an on-chip thermal diode for measuringnt the processor corer O None temperature. i THERMDP hnol TRDY# Target Ready indicates that the targetc is ready to receivede a write or write-back transfer I BCLK from the CPU. e i qu VCC Core voltage power supply. nf e - VCC_SENSE Isolated low impedance Ttrace to processor core power for use in power measurement - or VRM feedback. o R VID[4:0] The Voltage IdentificationA signals indicate the core voltage required from system board O(1.5V) ASYNC VRM. I C A VREF Reference voltage for the processor bus. -
VREF_CMOS ReferenceV voltage for the CMOS signals. D - VSS Ground power supply. N - VSS_SENSE Isolated low impedance ground trace to processor core for use in power measurement - or VRM feedback.
VTT Processor bus termination voltage power supply. -
3-4 Hardware Interface Section 3 October 22, 2004 VIA Eden-N Processor Datasheet
Table 3-3. Clock Ratio
BR[4] BR[3] BR[2] BR[1] BR[0] Bus Ratio 0 0 0 0 0 9.0X 0 0 0 0 1 3.0X 0 0 0 1 0 4.0X 0 0 0 1 1 10.0X 0 0 1 0 0 5.5X 0 0 1 0 1 3.5X 0 0 1 1 0 4.5X 0 0 1 1 1 9.5X 0 1 0 0 0 5.0X 0 1 0 0 1 7.0X . 0 1 0 1 0 8.0X 0 1 0 1 1 6.0X nc 0 1 1 0 0 12.0X I 0 1 1 0 1 7.5X s 0 1 1 1 0 8.5Xe 0 1 1 1 1 6.5X 1 0 0 0 0 giReserved l 1 0 0 0 1o 11.0X ia d 1 0 0 1 0 12.0X e 1 0 0 1 1 Reservednt r 1 0 1 hnol0 0 13.5X i 1 0 c1 0 1 de11.5X 1 0 e 1 1 i0 12.5X qu 1 0 1 1nf 1 10.5X e 1 T1 0 0 0 R13.0X 1 1 0 o0 1 15.0X A1 1 C0 1 0A 16.0X I 1 1 0 1 1 14.0X V 1 1 1 0 D 0 Reserved 1 1 1 0 1 15.5X 1 1 1 N1 0 Reserved 1 1 1 1 1 14.5X
Section 3 Hardware Interface 3-5 VIA Eden-N Processor Datasheet October 22, 2004
3.3 POWER MANAGEMENT The VIA Eden-N processor provides both static and dynamic power management. The VIA Eden-N processor supports five power management states: NORMAL, QUICKSTART, SLEEP, DEEP SLEEP and DEEPER SLEEP. Using dynamic power management techniques, the VIA Eden-N processor reduces power consumption in the NORMAL state. In NORMAL state, the on-chip arrays, selected datapaths, and the associated control logic are powered down when not in use. Also, units that are in use attempt to minimize switching of in- active nodes. NORMAL state is the normal operating state for the processor. . QUICKSTART state is the low power state where most of the processor clocks do not toggle. It is entered when the STPCLK# signal is asserted or when the processor execunctes the HALT instruc- tion. Snoop cycles are supported in this state. I SLEEP state is the low power state where only the processor's PLL (phase lock loop) toggles. It is entered from STOP GRANT state when the processor samples thes SLP# signal asserted. Snoop cy- cles that occur while in SLEEP state or during a transition intoe or out of SLEEP state will cause unpredictable behavior. gi l DEEP SLEEP state is a very low power state. It is enteredo when thea BCLK signal is stopped while the processor is in the SLEEP state. Snoop cycles are completely ignoredi in this state.d DEEPER SLEEP state is the lowest power state. It is enterednt when the processore core voltage is lowered while the processor is in the DEEP SLEEP state. Snoop cycles areir completely ignored in this state. hnol c de e i qu T nf e o R IA C A V D N
3-6 Hardware Interface Section 3 October 22, 2004 VIA Eden-N Processor Datasheet
BCLK stopped STPCLK# or BCLK on HLT instruction and !SLP# Normal Quick Start
halt break or
!STPCLK# SLP#
BCLK stopped snoop snoop serviced occurs !SLP# Sleep Deep Sleep
BCLK on and SLP#
. Core Voltage Snoop Lowered
Core Voltage IncRaised s e Deeper Sleep
gi l o a Figure 3-1: Power Management State Diagrami d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 3 Hardware Interface 3-7 VIA Eden-N Processor Datasheet October 22, 2004
3.4 TEST & DEBUG
3.4.1 BIST A Built-in Self-Test (BIST) can be requested as part of the VIA Eden-N processor reset sequence by holding INIT# asserted as RESET# is de-asserted. The VIA Eden-N processor BIST performs the following general functions:
A hardware-implemented exhaustive test of (1) all internal microcode ROM, and (2) the X86 in- struction decode, instruction generation, and entry point generation logic. An extensive microcode test of all internal registers and datapaths. . An extensive microcode test of data and instruction caches, their tags, andnc associated TLBs. BIST requires about four million internal clocks. I EAX Value After Reset s The result of a BIST is indicated by a code in EAX. EAX is normallye zero after reset. If a BIST is re- quested as part of the Reset sequence, EAX will contain the BIST results. A 0 in EAX after BIST Reset means that no failure was detected. Any value other than zero giindicates an errorl has occurred during BIST. o a 3.4.2 JTAG i d The VIA Eden-N processor owns a JTAG scan interface that is usednt for test functionse and the proprietary Debug Port. However, the VIA Eden-N processor does not offer a fully compatibleir IEEE 1149.1 JTAG function. hnol de From a practical user viewpoint, JTAG cdoes not exist iand the associated pins (TCLK, and so forth) should not be used. e qu T nf e 3.4.3 DEBUG PORT o R Certain processors have a proprietaryA DebugC Port that uses the JTAG scan mechanism to control internal debug features (“probe mode”).I A The VIA Eden-N processorV does not have a debug interface.D N
3-8 Hardware Interface Section 3 October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. ELECTRICAL SPECIFICATIONS Inc s e 4.1 AC TIMING TABLES gi l o ia d Table 4-1. System Bus Clock AC Specifications (133 MHz)e1 SYMBOL PARAMETER MIN MAX ntUNIT FIGUREi r NOTES System Bus Frequency hnol 133 MHz T1S BCLK Period c 7.5 ide 7.65 ns qu Figure 4-1 (2) T1Sabs BCLK Period – Instantaneouse Minimum 7.25 e (2) T2S BCLK Period StabilityT nf +250 ps (2),(3),(4) T3S BCLK High Time o 1.4 R ns Figure 4-1 at>2.0V T4S BCLK Low TimeA C 1.4 ns Figure 4-1 at<0.5V T5S BCLK RiseI Time 0.4 A 1.6 ns Figure 4-1 (5) T6S BCLKV Fall Time D 0.4 1.6 ns Figure 4-1 (5) Notes: 1. All AC timings for bus and CMOS signalsN are referenced to the rising edge of BCLK at 1.25V. 2. Period, jitter, skew and offset are all measured at 1.25V. 3. Not 100% tested. Specified by design/characterization 4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a component of BCLK skew between devices. 5. Measured between 0.5V and 2.0V.
Section 4 Electrical Specifications 4-1
VIA Eden-N Processor Datasheet October 22, 2004
Table 4-2. System Bus Clock AC Specifications (100 MHz)1 SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES System Bus Frequency 100 MHz
T1S1 BCLK Period 10 ns Figure 4-1 (2)
T1S1abs BCLK Period – Instantaneous Minimum 9.75 ns (2)
T2S1 BCLK Period Stability +250 ps (2), (3), (4)
T3S1 BCLK High Time 2.70 ns Figure 4-1 At>2.0V
T4S1 BCLK Fall Time 2.45 ns Figure 4-1 At<0.5V
T5S1 BCLK Rise Time 0.4 1.6 ns Figure 4-1 (5)
T6S1 BCLK Fall Time 0.4 1.6 ns Figure 4-1 (5)
Notes: . 1. All AC timings for bus and CMOS signals are referenced to the risingnc edge of BCLK at 1.25V. 2. Period, jitter, skew and offset are all measured at 1.25V. I 3. Not 100% tested. Specified by design/characterization 4. Measured on the rising edge of adjacent BCLKs at 1.25V. Thes jitter present must be accounted for as a component of BCLK skew between devices. e 5. Measured between 0.5V and 2.0V. gi l o a 1,8 Table 4-3. Bus Signal Groups AC Specificationsi d SYMBOL PARAMETER MIN MAX UNIT FIGURE eNOTES T7 Bus Output Valid Delay 0.40 3.25 nt ns Figurei 4-2r T8 Bus Input Setup Time hnol 0.95 ns (2), (3), (6) c 1.30 ide quFigure 4-4 (7) T9 Bus Input Hold Time e 1 nse (4) T nf Figure 4-4 T10 RESET# Pulse Width o 1 R ms Figure 4-4 (5) Notes: A C 1. All AC timingsI for Bus and CMOS signals areA referenced to the rising edge of BCLK at 1.25V. All bus signals are referenced at VREF. Unless specified, all timings apply to both 100 MHz and 133V MHz bus frequencies. D 2. RESET# can be asserted (active) asynchN ronously, but must be deasserted synchronously. 3. Specification is for a minimum 0.4V swing from VREF-200 mV to VREF+200 mV. 4. Specification is for a maximum 0.8V swing from VTT-0.8V to VTT. 5. After VCC, VTT and BCLK all become stable and then PWRGOOD is asserted. 6. Applies to processors supporting 133 MHz bus clock frequency. 7. Applies to processors supporting 100 MHz bus clock frequency. 8. Rtt=56Ω internally or terminated to VTT externally; VREF=2/3 VTT; Load = 50Ω
4-2 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
Table 4-4. CMOS and Open-drain Signal GROUPS AC Specifications1, 2 SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES
T14 1.5V Input Pulse Width, except PWRGOOD and 2 BCLKs Figure 4-2 Active and inactive LINT[1:0] states
T14B LINT[1:0] Input Pulse Width 6 BCLKs Figure 4-2 (3)
T15 PWRGOOD Inactive Pulse Width 2 µs Figure 4-5 (4)
Notes: 1. All AC timings for CMOS and Open-drain signals are referenced to the rising edge of BCLK at 1.25V. All CMOS and Open-drain signals are referenced at 1.0V. 2. Minimum output pulse width on CMOS outputs is 2 BCLKs. 3. This specification only applies when the APIC is enabled and the LINT[1:0] signals are configured as edge triggered interrupts with fixed delivery, otherwise specification T14 applies.. 4. When driven inactive, or after VCC, VTT and BCLK become stable. PWRGOOD must remain be- low VIL18MAX until all the voltage planes meet the voltage tolerancenc specifications in Table 4-8 and BCLK meet the BCLK AC specifications in Table 4-1 and Table I 4-2 for a least 2 µs. Table 4-5. Reset Configuration AC Specifications and Powers On/Power Down Timings SYMBOL PARAMETER MIN TYP MAXe UNIT FIGURE NOTES
T16 Reset Configuration Signals (A[15:5]#, 4 BCLKs Figure 4-4 Before deas- BREQ0#, FLUSH#, INIT#, PICD0) Setup Time gi l sertion of o a RESET# T17 Reset Configuration Signals (A[15:5]#, 2 20 BCLKsi Figure 4-4 After clock BREQ0#, FLUSH#, INIT#, PICD0) Hold Time dthat deasserts nt e RESET# T18 RESET#/PWRGOOD Setup Time 1 ms Figurer 4-5 Before deas- i sertion of hnol de RESET#1 T18B VCC to PWRGOOD Setup Time c 10 ms Figure 4-5 e i qu T18D RESET# inactive to Valid Outputs 1 nf e BCLK Figure 4-4 T18E RESET# inactive to Drive Signals T o 4 R BCLKs Figure 4-4 T19A Time from VCC(nominal)-12% to PWRGOOD 0 ns VCC(nominal) low A is the VID I C A voltage setting T19B All outputs valid after PWRGOOD low 0 ns
T19C All inputs requiredV valid after PWRGOOD low 0 D ns T20B All outputs valid after VTT-12% N 0 ns Figure 4-7 T20C All inputs required valid after VTT-12% 0 ns Figure 4-7
T20D VID, BSEL signals valid after VTT-12% 0 ns Figure 4-7
Notes: 1. At least 1 ms must pass after PWRGOOD rises above VIH18min and BCLK meet their AC timing specification until RESET# may be de-asserted.
Section 4 Electrical Specifications 4-3
VIA Eden-N Processor Datasheet October 22, 2004
Table 4-6. APIC Bus Signal AC Specifications1 SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES
T21 PICCLK Frequency 2 33.3 MHz (2)
T22 PICCLK Period 30 500 ns Figure 4-1
T23 PICCLK High Time 10.5 ns Figure 4-1 at>1.6V
T24 PICCLK Low Time 10.5 ns Figure 4-1 at<0.4V
T25 PICCLK Rise Time 0.25 3.0 ns Figure 4-1 (0.4V-1.6V)
T26 PICCLK Fall Time 0.25 3.0 ns Figure 4-1 (1.6V-0.4V)
T27 PICD[1:0] Setup Time 8.0 ns (3)
T28 PICD[1:0] Hold Time 2.5 ns (3) T29 PICD[1:0] Valid Delay (Rising Edge) 1.5 8.7 ns . (3),(4) PICD[1:0] Valid Delay (Falling Edge) 1.5 12.0 ns
Notes: nc 1. All AC timing for APIC signals referenced to the rising edge PICCLK I at 1.0V. All CMOS signals are referenced at 1.0V. s 2. The minimum frequency is 2MHz when PICD0 is at 1.5V at ereset referenced to PICCLK Rising Edge. 3. For open-drain signals, Valid Delay is synonymous withgi Float Delay. l 4. Valid delay timings for these signals are specifiedo into 150Ω to 1.5Va and 0pF of external load. For real system timings these specifications must be derated for externali capacitance dat 105ps/pF. 1, 3, 4 e Table 4-7. StopGrant/Deep Sleep AC Specificationsnt r SYMBOL PARAMETER hnol MIN MAX UNIT FIGUREi NOTES T45 Stop Grant Cycle Completion to SLP# assertion or 100 BCLKs Figure 4-8, BCLK stopped c de e i quFigure 4-9 T46 Stop Grant Cycle Completion to Input Signals Stablenf 0 e µs Figure 4-8, T o R Figure 4-9 T47 Sleep PLL Lock Latency 0 30 µs Figure 4-8, (2) IA C A Figure 4-9 T48 STPCLK# Hold Time from PLL Lock 0 µs Figure 4-8, V D Figure 4-9 T49 Input Signal Hold Time from STPCLK# DeassertionN 8 BCLKs Figure 4-8, Figure 4-9
T60 BCLK Settling Time 150 ns
Notes: 1. Input Signals other than RESET# and BPRI# must be held constant in the Stop Grant state. 2. The BCLK Settling Time specification (T60) applies to all sleep state exits under all conditions. 3. In Figure 4-8 after SLP# is asserted, BCLK can be stopped and the processor will enter the Deep Sleep state. To exit the Deep Sleep state, all timings shown in Figure 4-9 must be observed. 4. Vcore must be at nominal stable voltage before Deep Sleep exit after a Deeper Sleep transition.
4-4 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
Th Tr
VH VTRIP CLK VL
Tf Tl
Tp
NOTES:
Tr=T5S, T5S1, T25 (Rise Time) Tf=T6S, T6S1, T26 (Fall Time) Th=T3S, T3S1, T23 (High Time) Tl=T4S, T4S1, T24 (Low Time) T =T1S, T1S1, T22 (Period) p . VTRIP=1.25v for BCLK; 1.0V for PICCLK VL=0.5v for BCLK; 0.4V for PICCLK V =2.0v for BCLK; 1.6V for PICCLK H nc I Figure 4-1. BCLK Generic Clock Timing Waveforms e gi l V V CLK C o ia C d T T X nt X re hnolV Valid Valid i c ide TPW qu e e NOTES: T nf T =T7, T29 (Valid Delay) X T =T14, T14B (Pulse Width) o R PW V=V for bus signal group; 1.0v for CMOS, Open-drain, and APIC signal groups REF A V = 1.25v C C I A
V D Figure 4-2.N Valid Delay Timings
Section 4 Electrical Specifications 4-5
VIA Eden-N Processor Datasheet October 22, 2004
V CLK C
TS Th
Signal V Valid
NOTES:
TS=T8 (Setup Time)
Th=T9 (Hold Time)
V=VREF for bus signals; 1.0v for CMOS V = 1.25v C . nc Figure 4-3. Setup and Hold Timings I s e
V BCLK giC l o a T u i d T t e RESET# ntV ir Tv hnol T T w x Configuration c de (A[15:5], BREQ0#, iValid qu FLUSH#, INIT# e e nf T T y o R Valid Bus outputs A C A T I z Non-configuration Active inputsV D N NOTES:
Tt=T9 (Bus Input Hold Time) Tu=T8 (Bus Input Setup Time) Tv=T10 (RESET# Pulse Width) Tw=T16 (Reset Configuration Signals (A[15:5#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time) Tx=T17 (Reset Configuration Signals (A[15:5#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time) Ty=T18D (RESET# inactive to Valid Outputs) Tz=T18E (RESET# inactive to Drive Signals) VC=1.25v
Figure 4-4. Cold/Warm Reset and Configuration Timings
4-6 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
BCLK
VTT
VID[4:0]/ Valid BSEL[1:0]
VREF
VCC T a .
Tc V PWRGOOD IH15,min VIL15,max nc I T b RESET# s e
NOTES: gi l Ta=T15 (PWRGOOD Inactive Pulse Width) T =T18 (RESET#/PWRGOOD Setup Time) o a b T =T18B (Setup time from VCC valid until PWRGOOD assertion) i d c e nt ir Figure 4-5. Power-onhnol Sequence and Reset Timings c de e i qu T nf e o R IA C A V D N
Section 4 Electrical Specifications 4-7
VIA Eden-N Processor Datasheet October 22, 2004
VTT, VREF
VID[4:0] BSEL[1:0]
V -12% VCC CC
BCLK Valid . nc T a I PWRGOOD V IL15 s e RESET# gi l Bus Outputs Valid Other CMOS Outputs o ia d T b e nt ir hnol de All Inputs c Valid e i qu T T nf ec NOTES: T =T19A (Time from VCC(nominal)-12% to PWRGOODo low) R a T =T19B (All outputs valid after PWRGOOD low) b A T =T19C (All inputs required valid after PWRGOODC low) c I A V D Figure 4-6. Power Down SequencingN and Timings (VCC Leading)
4-8 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
VCC-12% VTT, VREF
VID[4:0] Valid BSEL[1:0]
VCC
Ta, Tb, Tc
BCLK Valid . Inc PWRGOOD s e RESET# gi l o ia d e Bus Outputs Valid nt r Other CMOS Outputs i hnol de All Inputs cValid e i qu T nf e NOTES: T =T20B (All outputs valid after VTT - 12%) o R a Tb=T20C (All inputs required valid after VTT - 12%) T =T20D (VID, BSELA signals valid afterC VTT - 12%) c I A V D Figure 4-7. Power Down SequencingN and Timings (VTT Leading)
Section 4 Electrical Specifications 4-9
VIA Eden-N Processor Datasheet October 22, 2004
Normal Stop Grant Sleep Stop Grant Normal
BCLK Stopped
Tv STPCLK#
Tx Ty CPU bus stpgnt
SLP#
Tw Tz Compatibility . Changing Frozen Signals Inc NOTES: Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay) T =T46 (Setup Time to Input Signal Hold Requirement) s w T =T47 (Sleep PLL Lock Latency) x e Ty=T48 (PLL lock to STPCLK# Hold Time) T =T49 (Input Signal Hold Time) z gi l o a Figure 4-8. Stop Grant /Sleep Timing (BCLK Stoppingi Method)d nt e Normal Stop Grant Sleep Stop Grantr Normal hnol i BCLK c ide qu T e v e STPCLK# T nf T T o x R y CPU bus IA stpgnt C A SLP#V D Tw Tz Compatibility Changing N Frozen Signals
NOTES:
Tv=T45 (Stop Grant Acknowledge Bus Cycle Completion to DPSLP# assertion)
Tw=T46 (Setup Time to Input Signal Hold Requirement)
Tx=T47 (Sleep PLL Lock Latency)
Ty=T48 (PLL lock to STPCLK# Hold Time)
Tz=T49 (Input Signal Hold Time)
Figure 4-9. Stop Grant/Sleep Timing (SLP# Assertion Method)
4-10 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
4.2 DC SPECIFICATIONS
4.2.1 RECOMMENDED OPERATING CONDITIONS
Functional operation of the VIA Eden-N processor is guaranteed if the conditions in Table 4-8 are met. Sustained operation outside of the recommended operating conditions may damage the device.
Table 4-8. Recommended Operating Conditions PARAMETER MIN NOM MAX UNITS NOTES
Operating Case Temperature 0 85 °C 0.90 V . VCORE Voltage 0.95 V 1.00 V nc VCORE Static Tolerance -2% +2% I V (1) VCORE Dynamic Tolerance -5% +5% s V (2) VTT Voltage 1.25 e V 1.25V±3% (3) IVTT Termination Supply Current 800 mA (4)
VREF -2% 2/3 VTT gi+2% V l RTT 50 56 o 115 iaΩ (5)d V1.5 – 1.5V Supply Voltage 1.365 1.635 V e Notes: nt ir 1. DC measurement. Regulator Circuit should supporthnol current drawde up to 15A. 2. AC noise measured with bandwidth limitedc to 20MHz i qu 3. Boards must hold VTT to 1.25V ±9% ewhile the bus is active and 1.25V ±3% when bus is idle. nf e 4. DC measurement. Measured with T 250 µs samplingo rate. R 5. RTT is controlled by RTTCTRL pin. RTTCTRL should be 56Ω when relying upon on-die bus termination. RTTCTRL should beI 110AΩ when relying Cupon board termination.A V D N
Section 4 Electrical Specifications 4-11
VIA Eden-N Processor Datasheet October 22, 2004
4.2.2 MAXIMUM RATINGS
While functional operation is not guaranteed beyond the operating ranges listed in Table 4-8, the device may be subjected to the limits specified in Table 4-9 without causing long-term damage. These conditions must not be imposed on the device for a sustained period—any such sustained imposi- tion may damage the device. Likewise exposure to conditions in excess of the maximum ratings may damage the device.
Table 4-9. Maximum Ratings PARAMETER MIN MAX UNITS NOTES
Storage Temperature -65 150 °C Supply Voltage (VCC) -0.5 1.6 V . CMOS I/O Voltage -0.5 VCMOS +0.5 V I/O Voltage -0.5 VTT +0.5 V Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
4-12 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
4.2.3 DC CHARACTERISTICS
Table 4-10. DC Characteristics PARAMETER MIN MAX UNITS NOTES
IOL – Low level output current -9.0 mA @ V = VOL(max)
VOH – High Level Output Voltage VTT V
VOL – Low Level Output Voltage 0 0.4 V @ Iol = -8mA
IL – Input Leakage Current ± 15 µA
ILU – Input Leakage Current for inputs with pull-ups 200 µA
ILD – Input Leakage Current for inputs with pull-downs -400 µA Table 4-11. CMOS DC Characteristics . PARAMETER MIN MAX UNITS NOTES VIL -- Input Low Voltage -0.58 0.700 V nc VIH1.5 – Input High Voltage VREF + 0.2 VTT IV (2) VIH2.5 – Input High Voltage 2.0 3.18 s V (3) VOL – Low Level Output Voltage 0.40e V @ IOL VOH – High Level Output Voltage VCMOS V (1)
IOL – Low Level Output Current 9 gi mAl @ VOL ILI – Input Leakage Current o ±100 iaµA (4) d ILO – Output Leakage Current ±nt100 µA (4)e Notes: ir 1. All CMOS signals are open drain. hnol de 2. Applies to all CMOS signals except BCLKc. e i qu 3. Applies only to BCLK. nf e 4. Leakage current is specified for T the range between VSS and VCC. I/O’s are diode clamped to the VCC and VSS rails. BCLK has three series diodes betweeno the input and R VCC and a single diode between the input and VSS. All other signalsA have a single Cdiode between the signal and VCC and another single diode between the signal and VSS. I A V D N
Section 4 Electrical Specifications 4-13
VIA Eden-N Processor Datasheet October 22, 2004
4.2.4 POWER DISSIPATION Table 4-12 gives the core power consumption information for the VIA Eden-N processor at various oper- ating frequencies and voltages. Note that this does not include the power consumed by the I/O pads.
Table 4-12. Thermal Design Power Information PARAMETER TDP MAX1,2 UNITS NOTES Normal Mode
Eden-N 533 MHz 900mV 2.5 W Eden-N 533 MHz 900mV 3.0 W 85°C, 2, 4 Eden-N 800 MHz 950mV 50 W Eden-N 1.0 GHz 1.0V 7.0 W StopGrant / AutoHalt Mode .
Eden-N 900mV 1.00 W Eden-N 900mV 1.09 W nc I 50°C, 2 Eden-N 950mV 1.21 W Eden-N 1.0V 1.81 sW Sleep Mode e Eden-N 900mV 1.02 gi W l Eden-N 900mV 1.23 W o a 50°C, 2 Eden-N 950mV 1.23 Wi d Eden-N 1.0V 1.81 W e Deep Sleep Mode nt ir Eden-N 900mV hnol0.81 W Eden-N 900mV c 0.90de W i qu 35°C, 2 Eden-N 950mV e 0.99 eW Eden-N 1.0V T nf1.31 W Deeper Sleep Mode o R Eden-N 900mV A C 0.25 W Eden-N 900mV I 0.25A W 35°C, 2 Eden-N 950mVV D 0.25 W Eden-N 1.0V 0.25 W
Notes: N 1. 100% tested. Consider these numbers as the factory maximum. The factory will reject processors that exceed these values. 2. The above power consumption is preliminary and based on case temperature as noted. 3. All normal mode frequencies use 133MHz as the CPU clock frequency. 4. Conservative thermal solutions must be designed to account for worst-case core and I/O power consumption.
4-14 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
Table 4-13. VTT-I/O Power Consumption
PARAMETER TYPICAL MAX UNITS NOTES
PTT-I/O – I/O Operating 0.3 1.2 W Power Consumption
. Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 4 Electrical Specifications 4-15
VIA Eden-N Processor Datasheet October 22, 2004
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. Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
4-16 Electrical Specifications Section 4
October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. MECHANICAL SPECIFICATIONS Inc s e 5.1 NANOBGA PACKAGE gi l o a The VIA Eden-N processor is available in a unique ball grid array, nanoBGA.i It is designedd for small form factor motherboards and facilitates compact and economical surface mounting.e The VIA Eden-N bus is functionally similar to prior Eden CPU’s but is obviously notnt mechanically compatible.r hnol i c de e i qu T nf e o R IA C A V D N
Section 5 Mechanical Specifications 5-1 VIA Eden-N Processor Datasheet October 22, 2004
1 2 3 4 5 6 7 8 9 101112131415161718
A A VSS D23# D26# D33# D29# D34# D38# D39# D42# D41# D47# D59# D57# D58# D50# D60# D61# VREF CMOS B B D19#VSS D16# D21# D31# D28# D22# D37# D44# D49# D51# D63# D48# D54# D53# D56# BR4 VREF C C D7# D30#VSS D25# D32# D35# D43# D36# D45# D27# D40# D52# D55# D46# D62# CFUSE1APICEN VTT D D D13# D24# D20# VCC VSSVCC VTT VCCVSS VCC VSS VTTVSSVCC VSS VTT VTT VTT E E D11# D2# D3# VCCVSSVCC VSS VCC VSS VCC VSS VCC VSSVCC VSS RSVD VTT VTT F F D10# D9# D14# VSSVCC VSS VCC VSS VCC VSS VCC VSS VCCVSS VCC DVIDENPICD0 PICCLK G G D12# D17# D18# VTT VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS RSVD RSVD VSS H H D8# D1# D5# VSSVCC VSS VCC VSSVCC VSS VCC VSS VCC VSS VCC PICD1 NMI BCLK J J D15# D6# D4# VCC VSSVCC VSSVCC VSS VCC VSS VCC VSS VCC VSS INTR BR3 BCLKB. K K D0# RESET# BREQ1#VSS VCCVSS VCC VSSVCC VSSVCC VSS VCC VSS VCC NCHCTRL BR2 VSS SENSE L nc L A26# A29# A18# VCC VSSVCC VSSVCC VSS VCC VSS VCCVSS VCC VSS RTTCTRL BR1 PLL2 M I M A27# A30# A23# VTT VCCVSS VCC VSSVCC VSSVCC VSS VCC VSS VCC FLUSH# BR0 PLL1 N s N VSS A24# A20# VCC VSSVCC VSSVCC VSSVCC VSS VCC VSSeVCC VSSSTPCLK# IERR# VSS P P A17# A31# A25# VSSVCC VSSVCC VSSVCC VSSVCC VSS VCC VSS VCC INIT# VID3 FERR# SENSE R gi R A19# A22# A21# VSSVCC VSSVTT VSSVCC VSS VCC VTT VCC VSS VCC RSVDl VID4 A20M# T o a T A28# RSVD VSS A3# A6# A4# A14# REQ1# BPRI# REQ3# HIT# DBSY# BREQ0# SLP#RSVDi RSVD SMI# IGNNE# d U U A10#VSS A12# A16# A9# A11# A7# REQ4# REQ0# RS1# TRDY# RSVD RSVD RS2# ADS# THRMDP RSVD THRMDN e V nt V VSS A15# A5# A13# A8# VSS BNR# REQ2#DEFER# LOCK# HITM# DRDY# RS0# PWRGD VID0 VID2 VID1irRSVD 1 2 3 4 5 6 7 8hnol 9 101112131415161718 c ide qu VSS VCC VTTe Other T nf e Figure 5-1 nanoBGAo Ballout (TopR View) IA C A V D N
5-2 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
Table 5-1. Signal Listing (Alphabetical Order) Ball Name Ball No. Type Ball Name Ball No. Type A3# T-4 AGTL I/O BR2 K-17 Power/Other A4# T-6 AGTL I/O BR3 J-17 Power/Other A5# V-3 AGTL I/O BR4 B-17 Power/Other A6# T-5 AGTL I/O BREQ0# T-13 AGTL I/O A7# U-7 AGTL I/O BREQ1# K-3 AGTL I/O A8# V-5 AGTL I/O CFUSE1 C-16 Power/Other A9# U-5 AGTL I/O D0# K-1 AGTL I/O A10# U-1 AGTL I/O D1# H-2 AGTL I/O A11# U-6 AGTL I/O D2# E-2 AGTL I/O A12# U-3 AGTL I/O D3# E-3 AGTL I/O . A13# V-4 AGTL I/O D4# J-3 AGTL I/O A14# T-7 AGTL I/O D5# H-3 AGTL I/Onc A15# V-2 AGTL I/O D6# J-2 AGTL I I/O A16# U-4 AGTL I/O D7# C-1 sAGTL I/O A17# P-1 AGTL I/O D8# H-1 e AGTL I/O A18# L-3 AGTL I/O D9# F-2 AGTL I/O A19# R-1 AGTL I/O D10# F-1gi AGTL I/Ol o A20# N-3 AGTL I/O D11# E-1 AGTLia I/O d A20M# R-18 CMOS Input D12# G-1 AGTL I/O e A21# R-3 AGTL I/O D13# D-1 ntAGTL I/O ir A22# R-2 AGTL I/O hnolD14# F-3 AGTL I/O A23# M-3 AGTL I/O c D15# ideJ-1 AGTL I/O A24# N-2 AGTL I/O e D16# B-3 AGTLqu I/O A25# P-3 AGTL I/O T D17#nf G-2 eAGTL I/O A26# L-1 AGTL I/O oD18# G-3 R AGTL I/O A27# M-1 AGTL I/O A C D19# B-1 AGTL I/O A28# T-1 AGTL I/OI D20# AD-3 AGTL I/O A29# L-2 AGTL I/O D21# B-4 AGTL I/O A30# M-2 AGTLV I/O D22#D B-7 AGTL I/O A31# P-2 AGTL I/O ND23# A-2 AGTL I/O ADS# U-15 AGTL I/O D24# D-2 AGTL I/O APIC_EN C-17 Power/Other D25# C-4 AGTL I/O BCLK H-18 System Bus Clock D26# A-3 AGTL I/O BCLKB J-18 System Bus Clock D27# C-10 AGTL I/O BNR# V-7 AGTL I/O D28# B-6 AGTL I/O BPRI# T-9 AGTL Input D29# A-5 AGTL I/O BR0 M-17 Power/Other D30# C-2 AGTL I/O BR1 L-17 Power/Other D31# B-5 AGTL I/O
Section 5 Mechanical Specifications 5-3 VIA Eden-N Processor Datasheet October 22, 2004
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type D32# C-5 AGTL I/O HIT# T-11 AGTL I/O D33# A-4 AGTL I/O HITM# V-11 AGTL I/O D34# A-6 AGTL I/O IGNNE# T-18 CMOS Input D35# C-6 AGTL I/O INIT# P-16 CMOS Input D36# C-8 AGTL I/O INTR J-16 CMOS Input D37# B-8 AGTL I/O LOCK# V-10 AGTL I/O D38# A-7 AGTL I/O NCHCTRL K-16 Power/Other D39# A-8 AGTL I/O NMI H-17 CMOS Input D40# C-11 AGTL I/O PICCLK F-18 APIC Clock Input . D41# A-10 AGTL I/O PICD0 F-17 APIC I/O D42# A-9 AGTL I/O PICD1 H-16 APIC I/O nc D43# C-7 AGTL I/O PLL1 M-18 Power/OtherI D44# B-9 AGTL I/O PLL2 L-18 sPower/Other D45# C-9 AGTL I/O PWRGD V-14 e CMOS Input D46# C-14 AGTL I/O REQ0# U-9 AGTL I/O D47# A-11 AGTL I/O REQ1# T-8gi AGTL I/Ol D48# B-13 AGTL I/O REQ2# oV-8 AGTLa I/O D49# B-10 AGTL I/O REQ3# T-10 AGTLi I/O d D50# A-15 AGTL I/O REQ4# U-8 nt AGTL I/O re D51# B-11 AGTL I/O Reserved E-16 Reserved fori future use D52# C-12 AGTL I/O hnolReserved de G-16 Reserved for future use D53# B-15 AGTL I/O c Reserved G-17 Reserved for future use e i qu D54# B-14 AGTL I/O IERR# N-17 eCMOS Output D55# C-13 AGTL I/O Reservednf R-16 Reserved for future use T R D56# B-16 AGTL I/O oReserved T-2 Reserved for future use D57# A-13 AGTL I/O A C Reserved A T-15 Reserved for future use D58# A-14 AGTL I/OI Reserved T-16 Reserved for future use D59# A-12 AGTLV I/O ReservedD U-12 Reserved for future use D60# A-16 AGTL I/O Reserved U-13 Reserved for future use D61# A-17 AGTL I/O NReserved U-18 Reserved for future use D62# C-15 AGTL I/O Reserved V-18 Reserved for future use D63# B-12 AGTL I/O RESET# K-2 AGTL Input DBSY# T-12 AGTL I/O RS0# V-13 AGTL Input DEFER# V-9 AGTL Input RS1# U-10 AGTL Input DRDY# V-12 AGTL I/O RS2# U-14 AGTL Input DVIDEN F-16 Power/Other RTTCTRL L-16 Power/Other FERR# P-18 CMOS Output SLP# T-14 CMOS Input FLUSH# M-16 CMOS Input SMI# T-17 CMOS Input
5-4 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type
STPCLK# N-16 CMOS Input VCC K-5 Power/Other
THERMDN U-17 Power/Other VCC K-7 Power/Other
THERMDP U-16 Power/Other VCC K-9 Power/Other
TRDY# U-11 AGTL Input VCC K-11 Power/Other
VCC D-4 Power/Other VCC K-13 Power/Other
VCC D-6 Power/Other VCC K-15 Power/Other
VCC D-8 Power/Other VCC L-4 Power/Other
VCC D-10 Power/Other VCC L-6 Power/Other
VCC D-14 Power/Other VCC L-8 Power/Other VCC E-4 Power/Other VCC L-10 Power/Other . VCC E-6 Power/Other VCC L-12 Power/Other VCC E-8 Power/Other VCC L-14 Power/Othernc VCC E-10 Power/Other VCC M-5 Power/Other I VCC E-12 Power/Other VCC M-7 sPower/Other VCC E-14 Power/Other VCC M-9 e Power/Other VCC F-5 Power/Other VCC M-11 Power/Other
VCC F-7 Power/Other VCC M-13gi Power/Otherl VCC F-9 Power/Other VCC oM-15 Power/Otheria d VCC F-11 Power/Other VCC N-4 Power/Other e VCC F-13 Power/Other VCC N-6 ntPower/Other r VCC F-15 Power/Other hnolVCC N-8 Power/Otheri VCC G-6 Power/Other c VCC deN-10 Power/Other VCC G-8 Power/Other e VCC i N-12 Power/Otherqu VCC G-10 Power/Other VCCnf N-14 ePower/Other V G-12 Power/Other T VCC P-5 Power/Other CC o R VCC G-14 Power/OtherA VCC P-9 Power/Other VCC H-5 Power/OtherI C VCC AP-11 Power/Other VCC H-7 Power/Other VCC P-13 Power/Other
VCC H-9 Power/OtherV VCC D P-15 Power/Other VCC H-11 Power/Other NVCC R-5 Power/Other VCC H-13 Power/Other VCC R-9 Power/Other
VCC H-15 Power/Other VCC R-11 Power/Other
VCC J-4 Power/Other VCC R-13 Power/Other
VCC J-6 Power/Other VCC R-15 Power/Other
VCC J-8 Power/Other VCC_SENSE P-7 Power/Other
VCC J-10 Power/Other VID0 V-15 Power/Other
VCC J-12 Power/Other VID1 V-17 Power/Other
VCC J-14 Power/Other VID2 V-16 Power/Other
Section 5 Mechanical Specifications 5-5 VIA Eden-N Processor Datasheet October 22, 2004
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type
VID3 P-17 Power/Other VSS J-7 Power/Other
VID4 R-17 Power/Other VSS J-9 Power/Other
VREF B-18 Power/Other VSS J-11 Power/Other
VREF_CMOS A-18 Power/Other VSS J-13 Power/Other
VSS A-1 Power/Other VSS J-15 Power/Other
VSS B-2 Power/Other VSS K-6 Power/Other
VSS C-3 Power/Other VSS K-8 Power/Other
VSS D-5 Power/Other VSS K-10 Power/Other VSS D-9 Power/Other VSS K-12 Power/Other . VSS D-11 Power/Other VSS K-14 Power/Other VSS D-13 Power/Other VSS K-18 Power/Othernc VSS D-15 Power/Other VSS L-5 Power/OtherI VSS E-5 Power/Other VSS L-7 sPower/Other VSS E-7 Power/Other VSS L-9 e Power/Other VSS E-9 Power/Other VSS L-11 Power/Other VSS E-11 Power/Other VSS L-13gi Power/Otherl VSS E-13 Power/Other VSS oL-15 Power/Othera V E-15 Power/Other V M-6 Power/Otheri SS SS d V F-4 Power/Other V M-8 Power/Other e SS SS nt r VSS F-6 Power/Other VSS M-10 Power/Otheri VSS F-8 Power/Other hnolVSS deM-12 Power/Other VSS F-10 Power/Other c VSS M-14 Power/Other e i qu VSS F-12 Power/Other VSS N-1 ePower/Other V F-14 Power/Other V nf N-5 Power/Other SS T SS R VSS G-5 Power/Other oVSS N-7 Power/Other VSS G-7 Power/OtherIA C VSS AN-9 Power/Other VSS G-9 Power/Other VSS N-11 Power/Other VSS G-11 Power/OtherV VSS D N-13 Power/Other VSS G-13 Power/Other NVSS N-15 Power/Other VSS G-15 Power/Other VSS N-18 Power/Other
VSS G-18 Power/Other VSS P-4 Power/Other
VSS H-4 Power/Other VSS P-6 Power/Other
VSS H-6 Power/Other VSS P-8 Power/Other
VSS H-8 Power/Other VSS P-10 Power/Other
VSS H-10 Power/Other VSS P-12 Power/Other
VSS H-12 Power/Other VSS P-14 Power/Other
VSS H-14 Power/Other VSS R-4 Power/Other
VSS J-5 Power/Other VSS R-6 Power/Other
5-6 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
(Continued) Ball Name Ball No. Type
VSS R-8 Power/Other VSS R-10 Power/Other V R-14 Power/Other SS VSS T-3 Power/Other
VSS U-2 Power/Other
VSS V-1 Power/Other
VSS V-6 Power/Other
VSS_SENSE K-4 Power/Other
VTT C-18 Power/Other VTT D-7 Power/Other V D-12 Power/Other . TT VTT D-16 Power/Other nc VTT D-17 Power/Other I VTT D-18 Power/Other s VTT E-17 Power/Other e VTT E-18 Power/Other VTT G-4 Power/Other gi l VTT M-4 Power/Other o a VTT R-7 Power/Other i d VTT R-12 Power/Other e nt ir hnol c de e i qu T nf e o R IA C A V D N
Section 5 Mechanical Specifications 5-7 VIA Eden-N Processor Datasheet October 22, 2004
Table 5-2. Signal Listing in Numerical Order Ball Name Ball No. Type Ball Name Ball No. Type
VSS A-1 Power/Other VSS C-3 Power/Other D23# A-2 AGTL I/O D25# C-4 AGTL I/O D26# A-3 AGTL I/O D32# C-5 AGTL I/O D33# A-4 AGTL I/O D35# C-6 AGTL I/O D29# A-5 AGTL I/O D43# C-7 AGTL I/O D34# A-6 AGTL I/O D36# C-8 AGTL I/O D38# A-7 AGTL I/O D45# C-9 AGTL I/O D39# A-8 AGTL I/O D27# C-10 AGTL I/O D42# A-9 AGTL I/O D40# C-11 AGTL I/O . D41# A-10 AGTL I/O D52# C-12 AGTL I/O D47# A-11 AGTL I/O D55# C-13 AGTL I/Onc D59# A-12 AGTL I/O D46# C-14 AGTL I I/O D57# A-13 AGTL I/O D62# C-15 sAGTL I/O D58# A-14 AGTL I/O CFUSE1 C-16 e Power/Other D50# A-15 AGTL I/O APICEN C-17 Power/Other
D60# A-16 AGTL I/O VTT C-18gi Power/Otherl D61# A-17 AGTL I/O D13# oD-1 AGTLia I/O d VREF_CMOS A-18 Power/Other D24# D-2 AGTL I/O e D19# B-1 AGTL I/O D20# D-3 ntAGTL I/O r VSS B-2 Power/Other hnolVCC D-4 Power/Otheri D16# B-3 AGTL I/O c VSS deD-5 Power/Other D21# B-4 AGTL I/O e VCC i D-6 Power/Otherqu D31# B-5 AGTL I/O VTTnf D-7 ePower/Other D28# B-6 AGTL I/O T oVCC D-8 R Power/Other D22# B-7 AGTL I/O A VSS D-9 Power/Other D37# B-8 AGTL I/OI C VCC AD-10 Power/Other D44# B-9 AGTL I/O VSS D-11 Power/Other
D49# B-10 AGTLV I/O VTT D D-12 Power/Other D51# B-11 AGTL I/O NVSS D-13 Power/Other D63# B-12 AGTL I/O VCC D-14 Power/Other
D48# B-13 AGTL I/O VSS D-15 Power/Other
D54# B-14 AGTL I/O VTT D-16 Power/Other
D53# B-15 AGTL I/O VTT D-17 Power/Other
D56# B-16 AGTL I/O VTT D-18 Power/Other BR4 B-17 Power/Other D11# E-1 AGTL I/O VREF B-18 Power/Other D2# E-2 AGTL I/O D7# C-1 AGTL I/O D3# E-3 AGTL I/O
D30# C-2 AGTL I/O VCC E-4 Power/Other
5-8 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type
VSS E-5 Power/Other VSS G-7 Power/Other
VCC E-6 Power/Other VCC G-8 Power/Other
VSS E-7 Power/Other VSS G-9 Power/Other
VCC E-8 Power/Other VCC G-10 Power/Other
VSS E-9 Power/Other VSS G-11 Power/Other
VCC E-10 Power/Other VCC G-12 Power/Other
VSS E-11 Power/Other VSS G-13 Power/Other
VCC E-12 Power/Other VCC G-14 Power/Other
VSS E-13 Power/Other VSS G-15 Power/Other VCC E-14 Power/Other Reserved G-16 Reserved for future. use VSS E-15 Power/Other Reserved G-17 Reserved for future use Reserved E-16 Reserved for future use VSS G-18 Power/Othernc VTT E-17 Power/Other D8# H-1 AGTL I I/O VTT E-18 Power/Other D1# H-2 sAGTL I/O D10# F-1 AGTL I/O D5# H-3 e AGTL I/O D9# F-2 AGTL I/O VSS H-4 Power/Other
D14# F-3 AGTL I/O VCC H-5gi Power/Otherl VSS F-4 Power/Other VSS oH-6 Power/Otheria d VCC F-5 Power/Other VCC H-7 Power/Other e VSS F-6 Power/Other VSS H-8 ntPower/Other r VCC F-7 Power/Other hnolVCC H-9 Power/Otheri VSS F-8 Power/Other c VSS deH-10 Power/Other VCC F-9 Power/Other e VCC i H-11 Power/Otherqu VSS F-10 Power/Other VSSnf H-12 ePower/Other V F-11 Power/Other T VCC H-13 Power/Other CC o R VSS F-12 Power/OtherA VSS H-14 Power/Other VCC F-13 Power/OtherI C VCC AH-15 Power/Other VSS F-14 Power/Other PICD1 H-16 APIC I/O
VCC F-15 Power/OtherV NMID H-17 CMOS Input DVIDEN F-16 Power/Other NBCLK H-18 System Bus Clock PICD0 F-17 APIC I/O D15# J-1 AGTL I/O PICCLK F-18 APIC Clock Input D6# J-2 AGTL I/O D12# G-1 AGTL I/O D4# J-3 AGTL I/O
D17# G-2 AGTL I/O VCC J-4 Power/Other
D18# G-3 AGTL I/O VSS J-5 Power/Other
VTT G-4 Power/Other VCC J-6 Power/Other
VSS G-5 Power/Other VSS J-7 Power/Other
VCC G-6 Power/Other VCC J-8 Power/Other
Section 5 Mechanical Specifications 5-9 VIA Eden-N Processor Datasheet October 22, 2004
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type
VSS J-9 Power/Other VSS L-11 Power/Other
VCC J-10 Power/Other VCC L-12 Power/Other
VSS J-11 Power/Other VSS L-13 Power/Other
VCC J-12 Power/Other VCC L-14 Power/Other
VSS J-13 Power/Other VSS L-15 Power/Other
VCC J-14 Power/Other RTTCTRL L-16 Power/Other
VSS J-15 Power/Other BR1 L-17 Power/Other INTR J-16 CMOS Input PLL2 L-18 Power/Other BR3 J-17 Power/Other A27# M-1 AGTL I/O . BCLKB J-18 System Bus Clock A30# M-2 AGTL I/O D0# K-1 AGTL I/O A23# M-3 AGTL I/Onc RESET# K-2 AGTL Input VTT M-4 Power/OtherI BREQ1# K-3 AGTL I/O VCC M-5 sPower/Other VSS_SENSE K-4 Power/Other VSS M-6 e Power/Other VCC K-5 Power/Other VCC M-7 Power/Other VSS K-6 Power/Other VSS M-8gi Power/Otherl VCC K-7 Power/Other VCC oM-9 Power/Othera V K-8 Power/Other V M-10 Power/Otheri SS SS d V K-9 Power/Other V M-11 Power/Other e CC CC nt r VSS K-10 Power/Other VSS M-12 Power/Otheri VCC K-11 Power/Other hnolVCC deM-13 Power/Other VSS K-12 Power/Other c VSS M-14 Power/Other e i qu VCC K-13 Power/Other VCC M-15 ePower/Other V K-14 Power/Other FLUSH#nf M-16 CMOS Input SS T R VCC K-15 Power/Other oBR0 M-17 Power/Other NCHCTRL K-16 Power/OtherIA C PLL1 AM-18 Power/Other BR2 K-17 Power/Other VSS N-1 Power/Other VSS K-18 Power/OtherV A24#D N-2 AGTL I/O A26# L-1 AGTL I/O NA20# N-3 AGTL I/O A29# L-2 AGTL I/O VCC N-4 Power/Other
A18# L-3 AGTL I/O VSS N-5 Power/Other
VCC L-4 Power/Other VCC N-6 Power/Other
VSS L-5 Power/Other VSS N-7 Power/Other
VCC L-6 Power/Other VCC N-8 Power/Other
VSS L-7 Power/Other VSS N-9 Power/Other
VCC L-8 Power/Other VCC N-10 Power/Other
VSS L-9 Power/Other VSS N-11 Power/Other
VCC L-10 Power/Other VCC N-12 Power/Other
5-10 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
(Continued) Ball Name Ball No. Type Ball Name Ball No. Type
VSS N-13 Power/Other VCC R-15 Power/Other
VCC N-14 Power/Other Reserved R-16 Reserved for future use
VSS N-15 Power/Other VID4 R-17 Power/Other STPCLK# N-16 CMOS Input A20M# R-18 CMOS Input IERR# N-17 CMOS Output A28# T-1 AGTL I/O
VSS N-18 Power/Other Reserved T-2 Reserved for future use
A17# P-1 AGTL I/O VSS T-3 Power/Other A31# P-2 AGTL I/O A3# T-4 AGTL I/O A25# P-3 AGTL I/O A6# T-5 AGTL I/O VSS P-4 Power/Other A4# T-6 AGTL I/O . VCC P-5 Power/Other A14# T-7 AGTL I/O VSS P-6 Power/Other REQ1# T-8 AGTL I/Onc VCC_SENSE P-7 Power/Other BPRI# T-9 AGTL I Input VSS P-8 Power/Other REQ3# T-10 s AGTL I/O VCC P-9 Power/Other HIT# T-11 e AGTL I/O VSS P-10 Power/Other DBSY# T-12 AGTL I/O
VCC P-11 Power/Other BREQ0# T-13gi AGTL I/Ol VSS P-12 Power/Other SLP# oT-14 CMOSia Input d VCC P-13 Power/Other Reserved T-15 Reserved for futuree use VSS P-14 Power/Other Reserved T-16 nt Reserved for futurer use VCC P-15 Power/Other hnolSMI# T-17 CMOS Inputi INIT# P-16 CMOS Input c IGNNE# deT-18 CMOS Input VID3 P-17 Power/Other e A10# i U-1 AGTLqu I/O FERR# P-18 CMOS Output VSSnf U-2 ePower/Other A19# R-1 AGTL I/O T oA12# U-3 R AGTL I/O A22# R-2 AGTL I/O A A16# U-4 AGTL I/O A21# R-3 AGTL I/OI C A9# AU-5 AGTL I/O VSS R-4 Power/Other A11# U-6 AGTL I/O
VCC R-5 Power/OtherV A7#D U-7 AGTL I/O VSS R-6 Power/Other NREQ4# U-8 AGTL I/O VTT R-7 Power/Other REQ0# U-9 AGTL I/O
VSS R-8 Power/Other RS1# U-10 AGTL Input
VCC R-9 Power/Other TRDY# U-11 AGTL Input
VSS R-10 Power/Other Reserved U-12 Reserved for future use
VCC R-11 Power/Other Reserved U-13 Reserved for future use
VTT R-12 Power/Other RS2# U-14 AGTL Input
VCC R-13 Power/Other ADS# U-15 AGTL I/O
VSS R-14 Power/Other THERMDP U-16 Power/Other
Section 5 Mechanical Specifications 5-11 VIA Eden-N Processor Datasheet October 22, 2004
(Continued) Ball Name Ball No. Type THERMDN U-17 Power/Other Reserved U-18 Reserved for future use
VSS V-1 Power/Other A15# V-2 AGTL I/O A5# V-3 AGTL I/O A13# V-4 AGTL I/O A8# V-5 AGTL I/O
VSS V-6 Power/Other BNR# V-7 AGTL I/O REQ2# V-8 AGTL I/O . DEFER# V-9 AGTL Input LOCK# V-10 AGTL I/O Inc HITM# V-11 AGTL I/O DRDY# V-12 AGTL I/O s RS0# V-13 AGTL Input e PWRGD V-14 CMOS Input gi l VID0 V-15 Power/Other o a VID2 V-16 Power/Other i d VID1 V-17 Power/Other e Reserved V-18 Reserved for future use nt r hnol i c de e i qu T nf e o R IA C A V D N
5-12 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
. Inc s e gi l 0.80 0.57 o ia 0.50 d N/A e nt ir hnol Figure 5-2.c nanoBGA Dimensionsde e i qu T nf e o R IA C A V D N
Section 5 Mechanical Specifications 5-13 VIA Eden-N Processor Datasheet October 22, 2004
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5-14 Mechanical Specifications Section 5
October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. THERMAL SPECIFICATIONS Inc s e 6.1 INTRODUCTION gi l o a The VIA Eden-N processor is specified for operation with device case temperaturesi in thed range of 0°C to 85°C. Operation outside of this range will result in functional failures and may potentiallye damage the device. nt ir Care must be taken to ensure that the case temperaturhnole remains within the specified range at all times dur- ing operation. An effective heat sink with cadequate airflow isde therefore a requirement during operation. e i qu T nf e 6.2 TYPICAL ENVIRONMENTS o R Typical thermal solutions involveA three components:C a heat sink, an interface material between the heat sink and the package, andI a source of airflow. The best thermalA solutions rely on the use of all three com- ponents. To the extent that any of these components are not used, the other components must be improved to compensateV for such omission. In particDular, the use of interface material such as thermal grease, silicone paste, or graphite paper can make a 40°C difference in the case temperature. Likewise, the imposition of airflow is realistically a requirement.N
Section 6 Thermal Specifications 6-1 VIA Eden-N Processor Datasheet October 22, 2004
6.3 MEASURING TC
The case temperature (TC) should be measured by attaching a thermocouple to the center of the VIA Eden-N package. The heat produced by the processor is very localized so measuring the case temperature anywhere else will underestimate the case temperature. The presence of a thermocouple is inherently invasive; effort must be taken to minimize the effect of the measurement. The thermocouple should be attached to the processor through a small hole drilled in the heat sink. Thermal grease should be used to ensure that the thermocouple makes good contact with the package, but the thermocouple should not come in direct contact with the heat sink.
Physical Test Conditions Case temperature measurements should be made in the worst case operating environments.. Ideally, sys- tems should be maximally configured and tested at the worst-case ambient temperature.nc Test Patterns I During normal operation, the processor attempts to minimize power consumption. Consequently, normal power consumption is much lower than the maximum power consumption.s Thermal testing should be done while running software, which causes the processor to operate eat its thermal limits. gi l o a 6.4 MEASURING TJ i d e The junction temperature of the die can be measured by using the processor’snt on-chipr diode. hnol i c de e i qu T nf e o R IA C A V D N
6-2 Thermal Specifications Section 6
October 22, 2004 VIA Eden-N Processor Datasheet
6.5 ESTIMATING TC The VIA Eden-N processor’s case temperature can be estimated based on the general characteristics of the thermal environment. This estimate is not intended as a replacement for actual measurement. Case temperature can be estimated where,
TA ≡ Ambient Temperature
TC ≡ Case Temperature
θCA ≡ case-to-ambient thermal resistance
θJA ≡ junction-to-ambient thermal resistance . θ ≡ junction-to-case thermal resistance () JC Inc P ≡ power consumption (Watts) s and, e The nanoBGA with heat spreader has θJC =0.9ºC/W. gi l T = T + (P * θ ) o a J C JC i d e TA = TJ – (P * θJA) nt ir TA = TC – (P * θCA) hnol c de θCA = θJA – θJC e i qu T nf e o R IA C A V D N
Section 6 Thermal Specifications 6-3 VIA Eden-N Processor Datasheet October 22, 2004
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6-4 Thermal Specifications Section 6
October 22, 2004 VIA Eden-N Processor Datasheet
SECTION
. MACHINE SPECIFIC REGISTERS Inc s e 7.1 GENERAL gi l o a Table 7-1 and Table 7-2 summarize the VIA Eden-N processor machine-specifici registersd (MSRs). Fur- ther description of each MSR follows the table. MSRs are read usingnt the RDMSR instructione and written using the WRMSR instruction. ir There are four basic groups of MSRs (not necessarilyhnol with contiguous addresses). Other than as defined below, a reference to an undefined MSR causesc a General Protectionde exception. e i qu 1. Generally these registers canT have some utilitynf to low-level programse (like BIOS). Note that some of the MSRs (address 0 to 0x4FF) have noR function in the VIA Eden-N processor. These MSRs do not cause a GP when usedo on the VIA Eden-N processor; instead, reads to these MSRs return zero, andA writes are ignored.C Some of these undocumented MSRs may have ill side ef- fects when written Ito indiscriminately. Do not write Ato undocumented MSRs. 2. There are someV undocumented internal-use MSRsD used for low-level hardware testing purposes. At- tempts to read or write these undocumented MSRs cause unpredictable and disastrous results; so don’t use MSRs that are not documented inN this datasheet! 3. MSRs used for cache and TLB testing. These use MSR addresses that are not used on compatible processor. These test functions are very low-level and complicated to use. They are not documented in this datasheet but the information will be provided to customers given an appropriate justification MSRs are not reinitialized by the bus INIT interrupt; the setting of MSRs is preserved across INIT.
Section 7 Machine Specific Registers 7-1 VIA Eden-N Processor Datasheet October 22, 2004
Table 7-1. Category 1 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES TSC Time Stamp Counter 10h TSC[63:32] TSC[31:0] RW
EBL_CR_POWERON EBL_CR_POWERON 2Ah n/a Control bits RW PERFCTR0 Performance counter 0 C1h TSC[39:32] TSC[31:0] RW 1 PERFCTR1 Performance counter 1 C2h 0 Count[31:0] RW BBL_CR_CTL3 L2 Hardware Disabled 11Eh n/a 00800000h RO EVNTSEL0 Event counter 0 select 186h n/a 00470079h RO 1 EVNTSEL1 Event counter 1 select 187h n/a Control bits RW
MTRR MTRRphysBase0 200h Control bits Control bits RW MTRR MTRRphysMask0 201h Control bits Control bits RW. MTRR MTRRphysBase1 202h Control bits Control bits RW MTRR MTRRphysMask1 203h Control bits Control bitsnc RW MTRR MTRRphysBase2 204h Control bits Control I bits RW MTRR MTRRphysMask2 205h Control bits Controls bits RW MTRR MTRRphysBase3 206h Control bits e Control bits RW MTRR MTRRphysMask3 207h Control bits Control bits RW MTRR MTRRphysBase4 208h Controlgi bits Control bitsl RW MTRR MTRRphysMask4 209h Controlo bits Controlia bits RW d MTRR MTRRphysBase5 20Ah Control bits Control bits RWe MTRR MTRRphysMask5 20Bh Control bits nt Control bits ir RW MTRR MTRRphysBase6 hnol 20Ch Control bits Control bits RW MTRR MTRRphysMask6c 20Dh Controlide bits Control bits RW MTRR MTRRphysBase7 20Eh Control bits Controlqu bits RW e e MTRR MTRRphysMask7T 20Fhnf Control bits Control bits RW MTRR MTRRfix64K_00000 o 250h Control bitsR Control bits RW MTRR A MTRRfix16K_80000C 258h Control bits Control bits RW MTRR I MTRRfix16K_A0000 259h ControlA bits Control bits RW MTRR V MTRRfix4K_C0000 268h D Control bits Control bits RW MTRR MTRRfix4K_C8000 269h Control bits Control bits RW MTRR MTRRfix4K_D0000 N 26Ah Control bits Control bits RW MTRR MTRRfix4K_D8000 26Bh Control bits Control bits RW MTRR MTRRfix4K_E0000 26Ch Control bits Control bits RW
MTRR MTRRfix4K_E8000 26Dh Control bits Control bits RW MTRR MTRRfix4K_F0000 26Eh Control bits Control bits RW
MTRR MTRRfix4K_F8000 26Fh Control bits Control bits RW MTRR MTRRdefType 2FFh Control bits Control bits RW
7-2 Machine Specific Registers Section 7
October 22, 2004 VIA Eden-N Processor Datasheet
Notes: 1. PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR that reflects this limitation.
Table 7-2. Category 2 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES FCR Feature Control Reg 1107h n/a FCR value RW FCR2 Feature Control Reg 2 1108h FCR2_Hi FCR2 value RW 1 FCR3 Feature Control Reg 3 1109h FCR3_Hi FCR3 value WO 1
Notes: 1. FCR2 and FCR3 provide system software with the ability to specify the Vendor ID string returned by the CPUID instruction. . Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
Section 7 Machine Specific Registers 7-3 VIA Eden-N Processor Datasheet October 22, 2004
7.2 CATEGORY 1 MSRS
10H: TSC (TIME STAMP COUNTER)
VIA Eden-N processor has a 64-bit MSR that materializes the Time Stamp Counter (TSC). System in- crements the TSC once per processor clock. The TSC is incremented even during AutoHalt or StopClock. A WRMSR to the TSC will clear the upper 32 bits of the TSC.
2AH: EBL_CR_POWERON 31:27 27 26 25:22 21:20 19:18 17:15 14 13 . 12:0 Res BF4 Low- BF[3:0] Res BSEL Res 1MPOV IOQDepth Reserved '11000 PowerEn nc(Ignored on write; ' returns 0 on '1' I s read) 5 1 1 4 2 2 3 1 e 1 13 gi l IOQDepth: 0 = In Order Queue Depth with up to 8o transactions a 1 = 1 transaction i d 1MPOV: 0 = Power on Reset Vector at 0xFFFFFFF0 (4Gbytes)nt re 1 = Power on Reset Vectorhnol at 0x000FFFF0 (1 Mbyte) i BSEL: 01 = 133 MHz Bus c de 10 = 100 MHz Buse i qu T nf e o R IA C A V D N
7-4 Machine Specific Registers Section 7
October 22, 2004 VIA Eden-N Processor Datasheet
BF[4:0]: Bus Clock Frequency Ratio
Table 7-3. Bus Clock Frequency Ratio Clock Multiplier MSR 0x2A [27] MSR 0x2A [25:22] 5.0 0 0000b 16.0 0 0001b Reserved 0 0010b 10.0 0 0011b 5.5 0 0100b Reserved 0 0101b Reserved 0 0110b 9.5 0 0111b 9.0 0 1000b . 7.0 0 1001b 8.0 0 1010b Inc 6.0 0 1011b 12.0 0 1100b s 7.5 0 1101b e 8.5 0 1110bgi l 6.5 0 o 1111b a 9.0 1 0000b i d 11.0 1 0001b e 12.0 1 0010b nt ir 10.0 1 hnol 0011b 13.5 c1 i 0100bde qu 11.5 e 1 0101b e 12.5 T 1 nf 0110b 10.5 1 o 0111b R A13.0 C1 1000b I 15.0 1 A 1001b V 16.0 1 D 1010b 14.0 1 1011b 12.0 1 N 1100b 15.5 1 1101b Reserved 1 1110b 14.5 1 1111b LowPowerEn: This bit always set to '1'
Section 7 Machine Specific Registers 7-5 VIA Eden-N Processor Datasheet October 22, 2004
0C1H-C2H: PERFCTR0 & PERFCTR1 These are events counters 0 and 1. VIA Eden-N processor’s PERFCTR0 is an alias for the lower 40 bits of the TSC.
11EH: BBL_CR_CTL3
31:24 23 22:0 Reserved L2_Hdw_Disable Reserved (Ignored on write; ‘1’ returns 0 on read) 8 1 23 . The VIA Eden-N processor does contain an L2 cache. For compatibility, this read-only MSR indicates to the BIOS or system software that the L2 is disabled even if the L2 is enabled. nc L2_Hdw_Disable: This bit always set to '1' I s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
7-6 Machine Specific Registers Section 7
October 22, 2004 VIA Eden-N Processor Datasheet
186H: EVNTSEL0 (EVENT COUNTER 0 SELECT)
31:24 23:16 15:9 8:0 Reserved Reserved Reserved CTR0 Event Select = 79h 8 8 7 9 PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR which reflects this limitation. The CTR0_Event Select field always returns 0x0079, which corresponds to counting of processor clocks.
187H: EVNTSEL1 (EVENT COUNTER 1 SELECT)
31:24 23:16 15:9 8:0 . Reserved Reserved Reserved CTR1 Event nc Select I 8 8 7 9s VIA Eden-N processor have two MSRs that contain bits defining thee behavior of the two hardware event counters: PERFCTR0 and PERFCTR1. The CTR1_Event_Select control field defines which of severalgi possible eventsl is counted. The possible Event Select values for PERFCTR1 are listed in the table below.o Note thatia CTR1_Event_Selectd is a 9-bit field. e The EVNTSEL1 register should be written before PERFCTR1 isnt written to initializer the counter. The counts are not necessarily perfectly exact; the counters are intended for use over ia large number of events and may differ by one or two counts from whathnol might be expected. c de Most counter events are internal implementation-e dependenti debug functions,qu having no meaning to soft- ware. The counters that can have end-userT utility are:nf e EVENT DESCRIPTIONo R C0h A InstructionsC executed 1C0h I Instructions executed and string iterationsA 79h V Internal clocks (default eventD for CTR0) N
Section 7 Machine Specific Registers 7-7 VIA Eden-N Processor Datasheet October 22, 2004
7.3 CATEGORY 2 MSRs
1107H: FCR (FEATURE CONTROL REGISTER) The FCR controls the major optional feature capabilities of the VIA Eden-N processor. Table 7-4 con- tains the bit values for the FCR. The default settings shown for the FCR bits are not necessarily exact. The actual settings can be changed as part of the manufacturing process and thus a particular VIA Eden-N processor version can have slightly different default settings than shown here. All reserved bit values of the FCR must be preserved by using a read-modify-write sequence to update the FCR.
Table 7-4. FCR Bit Assignments BIT NAME DESCRIPTION DEFAULT. 0 ALTINST Reserved for test & special uses nc0 1 ECX8 Enables CPUID reporting CMPXCHG8B I 1 2 Reserved s 0 3 Reserved e 0 4 Reserved 0 5 DSTPCLK Disables supporting STPCLKgi l 0 6 Reservedo ia 0 d 7 EPGE Enables CR4.PGE and CPUID.PGE (Page Global Enable) 1e 8 DL2 Disables L2 Cache nt r0 9 hnolReserved i 1 10 c Reservedide 0 11 e Reserved qu 0 12 EBRPRED T Enablesnf Branch Prediction e 1 13 DIC o Disables I-Cache R 0 14 DDCA C Disables D-Cache 0 31:15 I ReservedA 0/1 V D ALTINST: 0 = Normal x86 instruction execution. 1 = Alternate instruction set executionN is enabled (see details below) ECX8: 0 = The CPUID instruction does not report the presence of the CMPXCHG8B instruction (CX8 = 0). The instruction actually exists and operates correctly, however. 1 = The CPUID instruction reports that the CMPXCHG8B instruction is supported (CX8 = 1). DSTPCLK: 0 = STPCLK interrupt properly supported. 1 = Ignores SPCLK interrupt. EPGE: 0 = The processor does not support Page Global Enable and therefore CPUID Feature Flags reports EDX[13]=0; attempts to set CR4.PGE are ignored.
7-8 Machine Specific Registers Section 7
October 22, 2004 VIA Eden-N Processor Datasheet
1 = The processor supports Page Global Enable and therefore CPUID Feature Flags re- ports EDX[13]=1; CR4.PGE can be set to 1. DL2: 0 = L2 Cache enabled. 1 = L2 Cache disabled. EBRPRED: 0 = Disables branch prediction function. 1 = Enables branch prediction function. DIC: 0 = Enables use of I-Cache. 1 = Disables use of I-Cache: cache misses are performed as single transfer bus cycles, PCD is de-asserted. This overrides any setting of CR0.CD and CR0.NW.
DDC: 0 = Enables use of D-Cache. 1 = Disables use of D-Cache: same semantics as for DIC except for D-Cache.. 1108H: FCR2 (FEATURE CONTROL REGISTER 2) nc This MSR contains more feature control bits — many of which are undefined. I It is important that all re- served bits are preserved by using a read-modify-write sequence to updates the MSR. 63:32 e Last 4 characters of Alternate Vendor ID stringgi l o ia d 31:15 14 13:12 11:8 7:4 3:0 e Reserved AVS Res Family ID Modelnt ID Res ir 17 1 2 hnol4 de4 4 AVS: 0 = The CPUID instructionc vendor ID is “CentaurHauls”i qu 1 = The CPUID instructione returns the alternate Vendore ID. The first 8 characters of the alternate Vendor IDT are stored in FCR3nf and the last 4 characters in FCR2[63:32]. These 12 characters are undefined aftero RESET and mayR be loaded by system software using WRMSR. A C Family ID: This fieldI will be returned as the family AID field by subsequent uses of the CPUID in- struction D Model ID: ThisV field will be returned as the model ID field by subsequent uses of the CPUID in- struction N
Section 7 Machine Specific Registers 7-9 VIA Eden-N Processor Datasheet October 22, 2004
1109H: FCR (FEATURE CONTROL REGISTER 3) This MSR contains the first 8 characters of the alternate Vendor ID. The alternate Vendor ID is returned by the CPUID instruction when FCR2[AVS] is set to ‘1’. FCR3 is a write-only MSR. 63:32 First 4 characters of Alternate Vendor ID string
31:0 Middle 4 characters of Alternate Vendor ID string
. Inc s e gi l o ia d nt re hnol i c de e i qu T nf e o R IA C A V D N
7-10 Machine Specific Registers Section 7