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Single-Chip North Bridge for Pentium 4 Cpus with 800 Mhz FSB

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Single-Chip North Bridge for Pentium 4 Cpus with 800 Mhz FSB Single-Chip North Bridge for Pentium 4 CPUs with 800 MHz FSB and8x/4x/2xAGPBus plus Advanced ECC Memory Controller supporting DDR400, 333, 266, and 200 (PC3200 / 2700 / 2100 / 1600) DDR DRAM for Desktop PC Systems Revision 0.4 April 14, 2003 VIA TECHNOLOGIES, INC. Copyright Notice: Copyright © 2001, 2002, 2003, VIA Technologies Incorporated. All Rights Reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of VIA Technologies Incorporated. The material in this document is for information only and is subject to change without notice. VIA Technologies Incorporated reserves the right to make changes in the product design without reservation and without notice to its users. Trademark Notices: VT8235, VT8236, VT8237 and PT800 may only be used to identify products of VIA Technologies. Intel™, Pentium™ and MMX™ are registered trademarks of Intel Corp. VIA C3™ is a registered trademark of VIA Technologies Athlon™ and AMD-K7™ are registered trademarks of Advanced Micro Devices Corp. Windows XP™. Windows 2000™. Windows ME™, Windows 98™, and Plug and Play™ are registered trademarks of Microsoft Corp. PCI™ is a registered trademark of the PCI Special Interest Group. PS/2™ is a registered trademark of International Business Machines Corp. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of VIA Technologies, Inc. VIA Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable as of the publication date of this document. However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: VIA Technologies Incorporated VIA Technologies Incorporated USA Office: Taiwan Office: 940 Mission Court 8th Floor, No. 533 Fremont, CA 94539 Chung-Cheng Road, Hsin-Tien USA Taipei, Taiwan ROC Tel: (510) 683-3300 Tel: (886-2) 2218-5452 Fax: (510) 683-3301 or (510) 687-4654 Fax: (886-2) 2218-5453 Web: http://www.viatech.com Web: http://www.via.com.tw PT800 Pentium 4 DDR V-Link North Bridge REVISION HISTORY Document Release Date Revision Initials 0.1 1/14/03 Initial internal release based on P4X400 data sheet rev 0.92 published 1/14/03 DH Added “Review Only” watermark and “Preliminary” to document revision Changed chipset name to PT400 and part # to VT8754A Added FSB800 and DDR400 support Updated Rx54[7-6], 55[0], 64[7-6,2], 69[7-6] 0.2 2/18/03 Fixed VAD0-1 CPU Freq strap defs (swapped 166 & 200) & Dev0 Rx54[7-6] DH Added Device 0 Rx67[7] and updated table under Rx69[6] 0.3 3/19/03 Removed "Preliminary" from document revision; Fixed misc typographical errors DH Updated document watermark to "VIA Confidential, NDA Required" Changed South Bridge to VT8237; Changed AGP pin names to AGP 8x default 0.4 4/14/03 Changed chip name to PT800 and removed VT# DH Fixed incorrect JEDEC-spec reference in mechanical diagram Revision 0.4, April 14, 2003 -i- Revision History PT800 Pentium 4 DDR V-Link North Bridge TABLE OF CONTENTS REVISION HISTORY .......................................................................................................................................................................I TABLE OFCONTENTS................................................................................................................ .................................................. II LIST OFFIGURES .................................................................................................................. .......................................................IV LIST OFTABLES ................................................................................................................... ........................................................IV PRODUCT FEATURES.................................................................................................................................................................... 1 OVERVIEW....................................................................................................................................................................................... 3 NORTH BRIDGE.............................................................................................................................................................................. 3 SOUTH BRIDGE .............................................................................................................................................................................. 4 POWER MANAGEMENT.................................................................................................................................................................. 4 PINOUTS............................................................................................................................................................................................ 5 PIN DESCRIPTIONS ........................................................................................................................................................................ 8 REGISTERS..................................................................................................................................................................................... 17 REGISTER OVERVIEW ................................................................................................................................................................. 17 MISCELLANEOUS I/O .................................................................................................................................................................. 21 CONFIGURATION SPACE I/O ....................................................................................................................................................... 21 DEVICE 0REGISTER DESCRIPTIONS........................................................................................................................................... 22 Device 0 Host Bridge Header Registers .............................................................................................................................. 22 Device 0 Host Bridge Device-Specific Registers................................................................................................................. 24 V-Link Control...................................................................................................................................................................................... 24 Host CPU Control................................................................................................................................................................................. 27 DRAM Control ..................................................................................................................................................................................... 29 PCIBus Control.................................................................................................................. .................................................................. 35 GART / Graphics Aperture ................................................................................................................................................................... 37 AGP 2.0 Registers................................................................................................................................................................................. 38 CPU-to-Memory Access Control.......................................................................................................................................................... 38 AGP 3.0 Registers................................................................................................................................................................................. 40 AGP 2.0 / 3.0 Registers......................................................................................................................................................................... 42 V-Link Compensation / Drive Control.................................................................................................................................................. 44 Power Management Control ................................................................................................................................................................. 45 Extended Power Management Control.................................................................................................................................................. 46 Error Control......................................................................................................................................................................................... 46 Host CPU AGTL+ I/O Control ............................................................................................................................................................
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