DOCSLIB.ORG

Quick Modeling, Simulation, and Synthesis

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Quick Modeling, Simulation, and Synthesis Fakultät II – Informatik, Wirtschafts- und Rechtswissenschaften Department für Informatik Dynamic Partial Self-Reconfiguration: Quick Modeling, Simulation, and Synthesis Von der Carl von Ossietzky Universität Oldenburg - Fakultät II (Department Wirtschafts- und Rechtswissenschaften) - zur Erlangung des Grades eines Doktors der Ingenieurwissenschaften (Dr.-Ing.) genehmigte Dissertation von Herrn Dipl.-Inform. Andreas Schallenberg geboren am 21. August 1974 in Osnabrück. Tag der Disputation: 12. Mai 2010 Erstgutachter: Prof. Dr.-Ing. Wolfgang Nebel Carl von Ossietzky University Oldenburg Zweitgutachter: Prof. Dr. Marco Platzner University of Paderborn Drittgutachter: Prof. Dr. rer. nat. Achim Rettberg Carl von Ossietzky University Oldenburg 2 Contents 1 Introduction 9 1.1 Motivation . .9 1.2 State of the Art in Dynamic Partial Reconfiguration . 10 1.3 Goals of this Work . 11 1.4 Outline of this Work . 17 2 State of the Art 19 2.1 System Design . 19 2.2 C++ . 21 2.2.1 Pointers and Instances . 21 2.2.2 Polymorphism in C++ . 23 2.3 Hardware Description using C++ and SystemC . 25 2.4 SystemC . 27 2.5 OSSS . 32 2.5.1 Synthesizable Subset . 32 2.5.2 Hardware Implementation of Object Oriented Descriptions . 32 2.5.3 Polymorphic Objects . 33 2.5.4 Shared Objects . 34 2.6 Dynamic Partially Reconfigurable Hardware . 35 2.6.1 Classification of DPR FPGAs . 38 2.6.2 FPGA Architectures in the Market . 40 2.6.3 Industrial Tool Flow . 41 2.7 Chapter Summary . 42 3 Related Work 43 3.1 Categorization . 43 3.2 Related Approaches . 46 3.2.1 SystemC Based Approaches . 46 3.2.2 Other C Language Style Approaches . 52 3.2.3 VHDL Based Approaches . 55 3.2.4 Other Approaches . 57 3.3 Classification of OSSS+R . 58 3.4 Overview of the Approaches . 59 3.5 Chapter Summary . 60 4 OSSS+R Modeling 61 4.1 Design Flow . 61 4.2 Objects and Modules . 64 4.3 Polymorphism and Runtime Reconfiguration . 65 4.3.1 Reconfigurable Objects . 65 4.3.2 Contexts . 69 4.3.3 Access Scheduler . 73 4.3.4 Reconfiguration Times . 76 3 4.3.5 Reconfiguration Scheduling . 77 4.4 Optimization Techniques . 79 4.4.1 Functional Density . 79 4.4.2 Trashing . 80 4.4.3 Locks . 82 4.4.4 Transient Attributes . 85 4.4.5 Slots Inside Reconfigurable Areas . 86 4.4.6 Refined Context Management . 90 4.4.7 Roundup: Elements of the Reconfigurable System . 91 4.5 Chapter Summary . 92 5 Simulation Semantics of OSSS+R Models 93 5.1 Mandatory Structural Modeling Elements . 93 5.2 Optional Structural Modeling Elements . 99 5.2.1 Multiple Reconfigurable Areas . 99 5.2.2 Scheduling Algorithms . 100 5.2.3 User-Defined Timing Datatype . 102 5.2.4 User-Defined Placement Algorithms . 103 5.3 Object Manipulation Modeling Elements . 104 5.3.1 Operations on Reconfigurable Objects . 104 5.3.2 Operations on Persistent Contexts . 107 5.3.3 Locking Mechanisms . 109 5.3.4 Transient Attributes . 112 5.4 Possible Extensions . 113 5.5 Chapter Summary . 113 6 Synthesis of OSSS+R Models 115 6.1 Synthesis Process . 115 6.1.1 SystemC and OSSS Synthesis . 115 6.1.2 Design Decisions . 117 6.1.3 OSSS+R Synthesis . 118 6.2 Synthesis Results . 120 6.2.1 Access Controller . 121 6.2.2 Crossbar . 125 6.2.3 Slot . 125 6.2.4 Context Attribute Storage . 127 6.2.5 User-Defined Process . 128 6.2.6 Reconfiguration Controller . 129 6.3 Board Support Package . 130 6.4 Chapter summary . 131 7 Experiments and Evaluation 133 7.1 Implementation Using Xilinx EAPR Tool Flow . 134 7.2 Benchmark: Waveform Generator . 135 7.3 Benchmark: Cyclic Redundancy Check . 141 7.4 Evaluation . 149 7.5 Chapter Summary . 153 8 Conclusion 155 A Simulation Timing Testcase 157 B RTL Simulation Testcase 163 4 List of Figures 1.1 Trade off between flexibility and efficiency . .9 1.2 Simplified tool flow for OSSS+R . 16 2.1 Memory layout in a Von Neumann architecture . 22 2.2 Simple class diagram . 24 2.3 Polymorphism and resource allocation . 27 2.4 Different configuration granularities . 36 4.1 Detailed tool flow for OSSS+R . 62 4.2 Analogy: Polymorphism and dynamic partial reconfiguration . 65 4.3 Artificial interface class . 70 4.4 State diagram for reconfigurable objects . 72 4.5 State diagram for user processes . 74 4.6 Execution with trashing effects . 81 4.7 Execution without trashing . 81 4.8 Simplified block diagram for cryptography example . 82 4.9 Class diagram for cryptography classes . 82 4.10 Resource groups . 87 4.11 Abstract crosslink block diagram . 87 4.12 Reconfigurable objects and their content . 92 5.1 Artificial initial model . 93 5.2 Model with reconfigurable objects . 94 5.3 Model with usage statements . 95 5.4 Model with permanent contexts . 96 5.5 Model with reconfiguration control . 98 5.6 Model with control interfaces . 98 6.1 Components currently generated by synthesis tool . 118 6.2 Synthesis sequence . 119 6.3 Block diagram: Access controller . 121 6.4 Timing diagram: Request and create . 121 6.5 DFA: Protocol for access controller and user-defined process . 122 6.6 Timing diagram: Lock and simultaneous unlock and permission release 123 6.7 Timing diagram: Crossbar . 124 6.8 Block diagram: Crossbar . 125 6.9 Block diagram: Slot . 126 6.10 Timing diagram: Method invocation . 126 6.11 DFA: Protocol for user-defined process and slot . 126 6.12 Block diagram: Context attribute storage . 127 6.13 DFA: Protocol for context attribute storage and slot . 128 6.14 Block diagram: User-defined process . 129 6.15 Block diagram: Reconfiguration controller . 129 6.16 Block diagram for ML401/ML501 board support package . 130 5 7.1 Xilinx EAPR flow (simplified) . 135 7.2 Class diagram: Waveform generators . 135 7.3 Block diagram: Waveform generator synthesis model . 139 7.4 Block diagram: Waveform generator simulation model . 140 7.5 Block diagram: CRC benchmark with two processes . 143 7.6 CRC: 3 implementations, slice count . 144 7.7 CRC: Adding processes . 146 7.8 Area trend when adding further polynomials . 148 6 List of Tables 1.1 Platform and tool-chain requirements . 13 2.1 Value and entity types . 26 2.2 FPGA classification by configuration storage . 37 2.3 Comparison of mainstream FPGA families . 41 3.1 Properties of related approaches . 59 3.2 Properties of related approaches, symbol legend . 60 4.1 Request information table available to the access scheduler . 73 4.2 Dynamic state changes upon various requests . 75 4.3 Elements of timing annotations . 77 4.4 Request information table available to the reconfiguration scheduler . 78 4.5 Summands for time in functional density . ..
Load more

Recommended publications
  • Prostep Ivip CPO Statement Template
    CPO Statement of Mentor Graphics For Questa SIM Date: 17 June, 2015 CPO Statement of Mentor Graphics Following the prerequisites of ProSTEP iViP’s Code of PLM Openness (CPO) IT vendors shall determine and provide a list of their relevant products and the degree of fulfillment as a “CPO Statement” (cf. CPO Chapter 2.8). This CPO Statement refers to: Product Name Questa SIM Product Version Version 10 Contact Ellie Burns [email protected] This CPO Statement was created and published by Mentor Graphics in form of a self-assessment with regard to the CPO. Publication Date of this CPO Statement: 17 June 2015 Content 1 Executive Summary ______________________________________________________________________________ 2 2 Details of Self-Assessment ________________________________________________________________________ 3 2.1 CPO Chapter 2.1: Interoperability ________________________________________________________________ 3 2.2 CPO Chapter 2.2: Infrastructure _________________________________________________________________ 4 2.3 CPO Chapter 2.5: Standards ____________________________________________________________________ 4 2.4 CPO Chapter 2.6: Architecture __________________________________________________________________ 5 2.5 CPO Chapter 2.7: Partnership ___________________________________________________________________ 6 2.5.1 Data Generated by Users ___________________________________________________________________ 6 2.5.2 Partnership Models _______________________________________________________________________ 6 2.5.3 Support of
    [Show full text]
  • Powerpoint Template
    Accellera Overview February 27, 2017 Lu Dai | Accellera Chairman Welcome Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 2 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera Systems Initiative Our Mission To provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. 3 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Corporate Members 4 © 2017 Accellera Systems Initiative, Inc. February 2017 Broad Industry Support Associate Members 5 © 2017 Accellera Systems Initiative, Inc. February 2017 Global Presence SystemC Evolution Day DVCon Europe DVCon U.S. SystemC Japan Design Automation Conference DVCon China Verification & ESL Forum DVCon India 6 © 2017 Accellera Systems Initiative, Inc. February 2017 Agenda . About Accellera . Current news . Technical activities . IEEE collaboration 7 © 2017 Accellera Systems Initiative, Inc. February 2017 Accellera News . Standards - IEEE Approves UVM 1.2 as IEEE 1800.2-2017 - Accellera relicenses SystemC reference implementation under Apache 2.0 . Outreach - First DVCon China to be held April 19, 2017 - Get IEEE free standards program extended 10 years/10 standards . Awards - Thomas Alsop receives 2017 Technical Excellence Award for his leadership of the UVM Working Group - Shrenik Mehta receives 2016 Accellera Leadership Award for his role as Accellera chair from 2005-2010 8 © 2017 Accellera Systems Initiative, Inc. February 2017 DVCon – Global Presence 29th Annual DVCon U.S. 4th Annual DVCon Europe www.dvcon-us.org 4th Annual DVCon India www.dvcon-europe.org 1st DVCon China www.dvcon-india.org www.dvcon-china.org 9 © 2017 Accellera Systems Initiative, Inc.
    [Show full text]
  • Co-Simulation Between Cλash and Traditional Hdls
    MASTER THESIS CO-SIMULATION BETWEEN CλASH AND TRADITIONAL HDLS Author: John Verheij Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) Computer Architecture for Embedded Systems (CAES) Exam committee: Dr. Ir. C.P.R. Baaij Dr. Ir. J. Kuper Dr. Ir. J.F. Broenink Ir. E. Molenkamp August 19, 2016 Abstract CλaSH is a functional hardware description language (HDL) developed at the CAES group of the University of Twente. CλaSH borrows both the syntax and semantics from the general-purpose functional programming language Haskell, meaning that circuit de- signers can define their circuits with regular Haskell syntax. CλaSH contains a compiler for compiling circuits to traditional hardware description languages, like VHDL, Verilog, and SystemVerilog. Currently, compiling to traditional HDLs is one-way, meaning that CλaSH has no simulation options with the traditional HDLs. Co-simulation could be used to simulate designs which are defined in multiple lan- guages. With co-simulation it should be possible to use CλaSH as a verification language (test-bench) for traditional HDLs. Furthermore, circuits defined in traditional HDLs, can be used and simulated within CλaSH. In this thesis, research is done on the co-simulation of CλaSH and traditional HDLs. Traditional hardware description languages are standardized and include an interface to communicate with foreign languages. This interface can be used to include foreign func- tions, or to make verification and co-simulation possible. Because CλaSH also has possibilities to communicate with foreign languages, through Haskell foreign function interface (FFI), it is possible to set up co-simulation. The Verilog Procedural Interface (VPI), as defined in the IEEE 1364 standard, is used to set-up the communication and to control a Verilog simulator.
    [Show full text]
  • Development of Systemc Modules from HDL for System-On-Chip Applications
    University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications".
    [Show full text]
  • Download the Compiled Program File Onto the Chip
    International Journal of Computer Science & Information Technology (IJCSIT) Vol 4, No 2, April 2012 MPP SOCGEN: A FRAMEWORK FOR AUTOMATIC GENERATION OF MPP SOC ARCHITECTURE Emna Kallel, Yassine Aoudni, Mouna Baklouti and Mohamed Abid Electrical department, Computer Embedded System Laboratory, ENIS School, Sfax, Tunisia ABSTRACT Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Software Tool named MppSoCGEN was developed in order to accelerate the design process of complex mppSoC. Starting from an architecture parameters design, VHDL code will be automatically generated using parsing method. Configuration rules are proposed to have a correct and valid VHDL syntax configuration. Finally, an automatic generation of Processor Elements and network topologies models of mppSoC architecture will be done for Stratix II device family. Our framework improves its flexibility on Netbeans 5.5 version and centrino duo Core 2GHz with 22 Kbytes and 3 seconds average runtime. Experimental results for reduction algorithm validate our MppSoCGEN design flow and demonstrate the efficiency of generated architectures. KEYWORD MppSoC, Automatic code generation; mppSoC configuration;parsing ; MppSoCGEN; 1. INTRODUCTION Parallel machines are most often used in many modern applications that need regular parallel algorithms and high computing resources, such as image processing and signal processing. Massively parallel architectures, in particular Single Instruction Multiple Data (SIMD) systems, have shown to be powerful executers for data-intensive applications [1].
    [Show full text]
  • UNIVERSITY of CALIFORNIA RIVERSIDE Emulation of Systemc
    UNIVERSITY OF CALIFORNIA RIVERSIDE Emulation of SystemC Applications for Portable FPGA Binaries A Dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by Scott Spencer Sirowy June 2010 Dissertation Committee: Dr. Frank Vahid, Chairperson Dr. Tony Givargis Dr. Sheldon X.-D. Tan Copyright by Scott Spencer Sirowy 2010 The Dissertation of Scott Spencer Sirowy is approved: Committee Chairperson University of California, Riverside ABSTRACT OF THE DISSERTATION Emulation of SystemC Applications for Portable FPGA Binaries by Scott Spencer Sirowy Doctor of Philosophy, Graduate Program in Computer Science University of California, Riverside, June 2010 Dr. Frank Vahid, Chairperson As FPGAs become more common in mainstream general-purpose computing platforms, capturing and distributing high-performance implementations of applications on FPGAs will become increasingly important. Even in the presence of C-based synthesis tools for FPGAs, designers continue to implement applications as circuits, due in large part to allow for capture of clever spatial, circuit-level implementation features leading to superior performance and efficiency. We demonstrate the feasibility of a spatial form of FPGA application capture that offers portability advantages for FPGA applications unseen with current FPGA binary formats. We demonstrate the portability of such a distribution by developing a fast on-chip emulation framework that performs transparent optimizations, allowing spatially-captured FPGA applications to immediately run on FPGA platforms without costly and hard-to-use synthesis/mapping tool flows, and sometimes faster than PC-based execution. We develop several dynamic and transparent optimization techniques, including just-in-time compilation , bytecode acceleration , and just-in-time synthesis that take advantage of a platform’s available resources, resulting in iv orders of magnitude performance improvement over normal emulation techniques and PC-based execution.
    [Show full text]
  • White Paper - Investigate the High-Level HDL Chisel
    White Paper - Investigate the high-level HDL Chisel Florian Heilmann, Christian Brugger, Norbert Wehn Microelectronics Research Group, University Kaiserslautern Kaiserslautern, Germany [email protected], [email protected], [email protected] Abstract— Chisel (Constructing Hardware in a Scala designer can simply not use it. Another approach involves embedded language) is a new programming language, which using a language suited for the domain of the target application. embedded in Scala, used for hardware synthesis. It aims to Examples include Esterel [4], which has been modeled for increase productivity when creating hardware by enabling reactive programs and DIL[5], which is an intermediate designers to use features present in higher level programming programming language used to target pipelined reconfigurable languages to build complex hardware blocks. In this paper, the architectures like PipeRench. Moreover, there are languages most advertised features of Chisel are investigated and compared like BlueSpec[6] which is essentially a subset of to their VHDL counterparts, if present. Afterwards, the authors’ SystemVerilog putting emphasis on avoiding race conditions opinion if a switch to Chisel is worth considering is presented. by automatically generating scheduling and arbitration logic Additionally, results from a related case study on Chisel are from a set of “rules” which express synthesizable behavior. briefly summarized. The author concludes that, while Chisel has promising features, it is not yet ready for use in the industry. These languages are usually designed to support a specific design domain. This, however, leads to these approaches performing poorly when used outside the domain they were intended for. Keywords—Hardware design; Chisel; VHDL; HDL III.
    [Show full text]
  • The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014
    The Hardware Design Toolchain Approaches and State of the Art Fredo Erxleben August 27, 2014 We will hate the tools (FCCM 1996 prediction for 2001) We will still hate the tools (FCCM 1998 prediction for 2003) We will merely dislike the tools (FCCM 2000 prediction for 2005) We [will] hate the tools more (FCCM 2007 prediction for 2012) 1 Motivation used for hardware design will be presented in an attempt to outline where weaknesses in the currently available tool-chains for hardware de- Since the introduction of integrated circuits, sign are found. Due to the sheer amount of hardware complexity has increased rapidly and different approaches made over the years and constantly. This complexity naturally is a hard tools that were developed with the intention of thing for humans to handle once it reaches a helping to improve the design process, it is not certain threshold. As a consequence, the need possible to look at them all or in more detail. for tools arises to enable the people involved in Instead, in the following, an overview over ap- the hardware design process to continue work- proaches made to create tool-chains for hard- ing on, advancing and improving the matter. ware design or single tools to be used in them, While this is a fact for any evolving branch of shall be given. It will also be outlined, what science and production, the speed, by which the their current state in productive use is. tools adapt varies greatly. Taking software de- velopment as a comparison, we find that there are often a lot of tools available for one task, 2 Criteria each one of them filling a niche or being tai- lored with a special use-case in mind.
    [Show full text]
  • Hardware Description Languages Compared: Verilog and Systemc
    Hardware Description Languages Compared: Verilog and SystemC Gianfranco Bonanome Columbia University Department of Computer Science New York, NY Abstract This library encompasses all of the necessary components required to transform C++ into a As the complexity of modern digital systems hardware description language. Such additions increases, engineers are now more than ever include constructs for concurrency, time notion, integrating component modeling by means of communication, reactivity and hardware data hardware description languages (HDLs) in the types. design process. The recent addition of SystemC to As described by Edwards [1], VLSI an already competitive arena of HDLs dominated verification involves an initial simulation done in by Verilog and VHDL, calls for a direct C or C++, usually for proof of concept purposes, comparison to expose potential advantages and followed by translation into an HDL, simulation of flaws of this newcomer. This paper presents such the model, applying appropriate corrections, differences and similarities, specifically between hardware synthesization and further iterative Verilog and SystemC, in effort to better categorize refinement. SystemC is able to shorten this the scopes of the two languages. Results are based process by combining the first two steps. on simulation conducted in both languages, for a Consequently, this also decreases time to market model with equal specifications. for a manufacturer. Generally a comparison between two computer languages is based on the number of Introduction lines of code and execution time required to achieve a specific task, using the two languages. A Continuous advances in circuit fabrication number of additional parameters can be observed, technology have augmented chip density, such as features, existence or absence of constructs consequently increasing device complexity.
    [Show full text]
  • Real-Time Operating System Modelling and Simulation Using Systemc
    Real-Time Operating System Modelling and Simulation Using SystemC Ke Yu Submitted for the degree of Doctor of Philosophy Department of Computer Science June 2010 Abstract Increasing system complexity and stringent time-to-market pressure bring chal- lenges to the design productivity of real-time embedded systems. Various System- Level Design (SLD), System-Level Design Languages (SLDL) and Transaction- Level Modelling (TLM) approaches have been proposed as enabling tools for real-time embedded system specification, simulation, implementation and verifi- cation. SLDL-based Real-Time Operating System (RTOS) modelling and simula- tion are key methods to understand dynamic scheduling and timing issues in real- time software behavioural simulation during SLD. However, current SLDL-based RTOS simulation approaches do not support real-time software simulation ade- quately in terms of both functionality and accuracy, e.g., simplistic RTOS func- tionality or annotation-dependent software time advance. This thesis is concerned with SystemC-based behavioural modelling and simu- lation of real-time embedded software, focusing upon RTOSs. The RTOS-centric simulation approach can support flexible, fast and accurate real-time software tim- ing and functional simulation. They can help software designers to undertake real- time software prototyping at early design phases. The contributions in this thesis are fourfold. Firstly, we propose a mixed timing real-time software modelling and simula- tion approach with various timing related techniques, which are suitable for early software modelling and simulation. We show that this approach not only avoids the accuracy drawback in some existing methods but also maintains a high simu- lation performance. Secondly, we propose a Live CPU Model to assist software behavioural timing modelling and simulation.
    [Show full text]
  • Concepmon ( G ~ E Janvier
    CONCEPMONET MISE EN CE= D'UN SYST~MEDE RECONFIOURATION DYNAMIQUE PRESENTE EN VUE DE L'OBTENTION DU DIP~MEDE WSERs SCIENCES APPLIQUEES (G~EÉLE~QUE) JANVIER2000 OCynthia Cousineau, 2000. National Library Bibliothèque nationale I*I of Canada du Canada Acquisitions and Acquisitions et Bibliographie Services services bibliographiques 395 Wellington Street 395, rue Wellington OttawaON K1AON4 Ottawa ON K1A ON4 Canada Canada The author has granted a non- L'auteur a accordé une licence non exclusive licence allowing the exclusive permettant à la National Library of Canada to Bibliothèque nationale du Canada de reproduce, loan, distribute or sel1 reproduire, prêter, distribuer ou copies of this thesis in microform, vendre des copies de cette thèse sous paper or electronic formats. la forme de microfiche/film, de reproduction sur papier ou sur format électronique. The author retains ownership of the L'auteur conserve la propriété du copyright in this thesis. Neither the droit d'auteur qui protège cette thèse. thesis nor substantial extracts f?om it Ni la thèse ni des extraits substantiels may be printed or otherwise de celle-ci ne doivent être imprimés reproduced without the author's ou autrement reproduits sans son permission. autorisation. Ce mémoire intitulé: CONCEFMONET MISE EN OEWRE D'UN SYST&MEDE RECONFIGURATION DYNAMIQUE présenté par : COUSINEAU Cvnthia en vue de l'obtention du diplôme de : Maîtrise ès sciences amliauees a été dûment accepté par le jury d'examen constitué de: M. BOIS GUY, Ph.D., président M. SAVARIA Yvon, Ph.D., membre et directeur de recherche M. SAWAN Mohamad , Ph.D., membre et codirecteur de recherche M.
    [Show full text]
  • Review of FPD's Languages, Compilers, Interpreters and Tools
    ISSN 2394-7314 International Journal of Novel Research in Computer Science and Software Engineering Vol. 3, Issue 1, pp: (140-158), Month: January-April 2016, Available at: www.noveltyjournals.com Review of FPD'S Languages, Compilers, Interpreters and Tools 1Amr Rashed, 2Bedir Yousif, 3Ahmed Shaban Samra 1Higher studies Deanship, Taif university, Taif, Saudi Arabia 2Communication and Electronics Department, Faculty of engineering, Kafrelsheikh University, Egypt 3Communication and Electronics Department, Faculty of engineering, Mansoura University, Egypt Abstract: FPGAs have achieved quick acceptance, spread and growth over the past years because they can be applied to a variety of applications. Some of these applications includes: random logic, bioinformatics, video and image processing, device controllers, communication encoding, modulation, and filtering, limited size systems with RAM blocks, and many more. For example, for video and image processing application it is very difficult and time consuming to use traditional HDL languages, so it’s obligatory to search for other efficient, synthesis tools to implement your design. The question is what is the best comparable language or tool to implement desired application. Also this research is very helpful for language developers to know strength points, weakness points, ease of use and efficiency of each tool or language. This research faced many challenges one of them is that there is no complete reference of all FPGA languages and tools, also available references and guides are few and almost not good. Searching for a simple example to learn some of these tools or languages would be a time consuming. This paper represents a review study or guide of almost all PLD's languages, interpreters and tools that can be used for programming, simulating and synthesizing PLD's for analog, digital & mixed signals and systems supported with simple examples.
    [Show full text]