Fakultät II – Informatik, Wirtschafts- und Rechtswissenschaften Department für Informatik Dynamic Partial Self-Reconfiguration: Quick Modeling, Simulation, and Synthesis Von der Carl von Ossietzky Universität Oldenburg - Fakultät II (Department Wirtschafts- und Rechtswissenschaften) - zur Erlangung des Grades eines Doktors der Ingenieurwissenschaften (Dr.-Ing.) genehmigte Dissertation von Herrn Dipl.-Inform. Andreas Schallenberg geboren am 21. August 1974 in Osnabrück. Tag der Disputation: 12. Mai 2010 Erstgutachter: Prof. Dr.-Ing. Wolfgang Nebel Carl von Ossietzky University Oldenburg Zweitgutachter: Prof. Dr. Marco Platzner University of Paderborn Drittgutachter: Prof. Dr. rer. nat. Achim Rettberg Carl von Ossietzky University Oldenburg 2 Contents 1 Introduction 9 1.1 Motivation . .9 1.2 State of the Art in Dynamic Partial Reconfiguration . 10 1.3 Goals of this Work . 11 1.4 Outline of this Work . 17 2 State of the Art 19 2.1 System Design . 19 2.2 C++ . 21 2.2.1 Pointers and Instances . 21 2.2.2 Polymorphism in C++ . 23 2.3 Hardware Description using C++ and SystemC . 25 2.4 SystemC . 27 2.5 OSSS . 32 2.5.1 Synthesizable Subset . 32 2.5.2 Hardware Implementation of Object Oriented Descriptions . 32 2.5.3 Polymorphic Objects . 33 2.5.4 Shared Objects . 34 2.6 Dynamic Partially Reconfigurable Hardware . 35 2.6.1 Classification of DPR FPGAs . 38 2.6.2 FPGA Architectures in the Market . 40 2.6.3 Industrial Tool Flow . 41 2.7 Chapter Summary . 42 3 Related Work 43 3.1 Categorization . 43 3.2 Related Approaches . 46 3.2.1 SystemC Based Approaches . 46 3.2.2 Other C Language Style Approaches . 52 3.2.3 VHDL Based Approaches . 55 3.2.4 Other Approaches . 57 3.3 Classification of OSSS+R . 58 3.4 Overview of the Approaches . 59 3.5 Chapter Summary . 60 4 OSSS+R Modeling 61 4.1 Design Flow . 61 4.2 Objects and Modules . 64 4.3 Polymorphism and Runtime Reconfiguration . 65 4.3.1 Reconfigurable Objects . 65 4.3.2 Contexts . 69 4.3.3 Access Scheduler . 73 4.3.4 Reconfiguration Times . 76 3 4.3.5 Reconfiguration Scheduling . 77 4.4 Optimization Techniques . 79 4.4.1 Functional Density . 79 4.4.2 Trashing . 80 4.4.3 Locks . 82 4.4.4 Transient Attributes . 85 4.4.5 Slots Inside Reconfigurable Areas . 86 4.4.6 Refined Context Management . 90 4.4.7 Roundup: Elements of the Reconfigurable System . 91 4.5 Chapter Summary . 92 5 Simulation Semantics of OSSS+R Models 93 5.1 Mandatory Structural Modeling Elements . 93 5.2 Optional Structural Modeling Elements . 99 5.2.1 Multiple Reconfigurable Areas . 99 5.2.2 Scheduling Algorithms . 100 5.2.3 User-Defined Timing Datatype . 102 5.2.4 User-Defined Placement Algorithms . 103 5.3 Object Manipulation Modeling Elements . 104 5.3.1 Operations on Reconfigurable Objects . 104 5.3.2 Operations on Persistent Contexts . 107 5.3.3 Locking Mechanisms . 109 5.3.4 Transient Attributes . 112 5.4 Possible Extensions . 113 5.5 Chapter Summary . 113 6 Synthesis of OSSS+R Models 115 6.1 Synthesis Process . 115 6.1.1 SystemC and OSSS Synthesis . 115 6.1.2 Design Decisions . 117 6.1.3 OSSS+R Synthesis . 118 6.2 Synthesis Results . 120 6.2.1 Access Controller . 121 6.2.2 Crossbar . 125 6.2.3 Slot . 125 6.2.4 Context Attribute Storage . 127 6.2.5 User-Defined Process . 128 6.2.6 Reconfiguration Controller . 129 6.3 Board Support Package . 130 6.4 Chapter summary . 131 7 Experiments and Evaluation 133 7.1 Implementation Using Xilinx EAPR Tool Flow . 134 7.2 Benchmark: Waveform Generator . 135 7.3 Benchmark: Cyclic Redundancy Check . 141 7.4 Evaluation . 149 7.5 Chapter Summary . 153 8 Conclusion 155 A Simulation Timing Testcase 157 B RTL Simulation Testcase 163 4 List of Figures 1.1 Trade off between flexibility and efficiency . .9 1.2 Simplified tool flow for OSSS+R . 16 2.1 Memory layout in a Von Neumann architecture . 22 2.2 Simple class diagram . 24 2.3 Polymorphism and resource allocation . 27 2.4 Different configuration granularities . 36 4.1 Detailed tool flow for OSSS+R . 62 4.2 Analogy: Polymorphism and dynamic partial reconfiguration . 65 4.3 Artificial interface class . 70 4.4 State diagram for reconfigurable objects . 72 4.5 State diagram for user processes . 74 4.6 Execution with trashing effects . 81 4.7 Execution without trashing . 81 4.8 Simplified block diagram for cryptography example . 82 4.9 Class diagram for cryptography classes . 82 4.10 Resource groups . 87 4.11 Abstract crosslink block diagram . 87 4.12 Reconfigurable objects and their content . 92 5.1 Artificial initial model . 93 5.2 Model with reconfigurable objects . 94 5.3 Model with usage statements . 95 5.4 Model with permanent contexts . 96 5.5 Model with reconfiguration control . 98 5.6 Model with control interfaces . 98 6.1 Components currently generated by synthesis tool . 118 6.2 Synthesis sequence . 119 6.3 Block diagram: Access controller . 121 6.4 Timing diagram: Request and create . 121 6.5 DFA: Protocol for access controller and user-defined process . 122 6.6 Timing diagram: Lock and simultaneous unlock and permission release 123 6.7 Timing diagram: Crossbar . 124 6.8 Block diagram: Crossbar . 125 6.9 Block diagram: Slot . 126 6.10 Timing diagram: Method invocation . 126 6.11 DFA: Protocol for user-defined process and slot . 126 6.12 Block diagram: Context attribute storage . 127 6.13 DFA: Protocol for context attribute storage and slot . 128 6.14 Block diagram: User-defined process . 129 6.15 Block diagram: Reconfiguration controller . 129 6.16 Block diagram for ML401/ML501 board support package . 130 5 7.1 Xilinx EAPR flow (simplified) . 135 7.2 Class diagram: Waveform generators . 135 7.3 Block diagram: Waveform generator synthesis model . 139 7.4 Block diagram: Waveform generator simulation model . 140 7.5 Block diagram: CRC benchmark with two processes . 143 7.6 CRC: 3 implementations, slice count . 144 7.7 CRC: Adding processes . 146 7.8 Area trend when adding further polynomials . 148 6 List of Tables 1.1 Platform and tool-chain requirements . 13 2.1 Value and entity types . 26 2.2 FPGA classification by configuration storage . 37 2.3 Comparison of mainstream FPGA families . 41 3.1 Properties of related approaches . 59 3.2 Properties of related approaches, symbol legend . 60 4.1 Request information table available to the access scheduler . 73 4.2 Dynamic state changes upon various requests . 75 4.3 Elements of timing annotations . 77 4.4 Request information table available to the reconfiguration scheduler . 78 4.5 Summands for time in functional density . ..