MachXO2-1200HC Control Development Kit User Guide
March 2015 EB60_1.6 MachXO2-1200HC Control Development Kit User Guide
Introduction Thank you for choosing the Lattice Semiconductor MachXO2™-1200HC Control Development Kit!
This guide describes how to start using the MachXO2-1200HC Control Development Kit, an easy-to-use platform for rapidly prototyping system control designs using MachXO2 PLDs. Along with the evaluation board and accesso- ries, this kit includes a pre-loaded control system-on-chip (Control SoC) design that demonstrates board diagnostic functions including I/O control, voltage monitoring, time-stamps and data logging to non-volatile memory. The Power Manager II ispPAC®-POWR1014A and 8-bit LatticeMico8™ microcontroller are featured in the board and demonstration design.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and bill of materials for the MachXO2-1200HC Control Evaluation Board.
Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO2-1200HC Control Development Kit QuickSTART Guide for handling and storage tips. Features The MachXO2-1200HC Control Development Kit includes:
• MachXO2-1200HC Control Evaluation Board – The MachXO2-1200HC Control Evaluation Board features the following on-board components and circuits: – MachXO2 LCMXO2-1200HC-csBGA132 PLD. The board is designed for density migration, allowing a higher-density MachXO2 device (up to 4000 LUTs) to be assembled on the board. - Part number LCMXO2-1200HC-C-EVN is populated with the R1 silicon. For more information on the R1 to Standard migration refer to the AN8086, Designing for Migration from MachXO2-1200-R1 to Stan- dard (Non-R1) Devices. – Power Manager II POWR1014A mixed-signal PLD – 4 Mbit SPI Flash memory – microSD (micro Secure Digital) memory socket – 60-ball VFBGA footprint for LPDDR memory. When populated, 128-Mbit LPDDR memory will be added to the board. – Current and voltage sensor circuits – Voltage ramp circuits – Electret microphone – Audio amplifier and Delta-Sigma ADC – PWM analog output circuit – Audio output channel – Up to two DVI sources and one DVI output – Up to two 7:1 LVDS sources and one 7:1:VDS output – Expansion header for JTAG, SPI, I2C and PLD I/Os – LEDs and switches – Standard USB cable for device programming – RS-232/USB and JTAG/USB interface – RoHS-compliant packaging and process – AC adapter (international plugs)
• Pre-loaded Reference Designs and Demo – The kit includes the pre-loaded Control SoC demo design that integrates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus controller, soft Delta-Sigma ADC, SPI master controller, UART peripheral, Embedded Block RAM and additional control functions. • USB connector Cable – A mini B USB port provides a communication and debug port via a USB-to-RS-232 physical channel and programming interface to the MachXO2 JTAG port.
2 MachXO2-1200HC Control Development Kit User Guide
• AC Adapter (international plugs) with 5 V DC output, center positive. • QuickSTART Guide – Provides information on connecting the MachXO2-1200HC Control Evaluation Board, installing Windows hardware drivers, and running the Control SoC demo.
Figure 1 shows the top side of the MachXO2-1200HC Control Evaluation Board with comments on the specific fea- tures that are designed in the board.
Figure 1. MachXO2-1200HC Control Evaluation Board, Top Side
DVI 7:1 LVDS Video Output Video Output
GSR Push-button 5V Power Indicator MachXO2 DIP Switches Electret Microphone
2x20 GPIO Header Speaker/Headphone Jack MachXO2-1200/4000
AC-DC Adapter Jack microSD Socket ADC Input (J9: Pin 2) POWR1014A
JTAG Device Select (J6), MachXO2 Position Shown 7:1 LVDS Video Source MachXO2 LED Field (Channel Link)
DVI Video Source USB 2.0 Interface Socket
Note: The bill of materials of this board has the following limitations:
• Video Source 1 is available in both DVI and 7:1 LVDS interfaces. Video Source 2 is not populated. • LPDDR memory component is not populated. This feature will be populated with greater MachXO2 device den- sity on the board. • The initial MachXO2 device that is assembled on the board is LCMXO2-1200HC. The footprint is compatible with greater device densities and an LCMXO2-4000HC device is planned to be populated in future versions of the board. Lattice Semiconductor Devices MachXO2 This board features a 3.3 V MachXO2 PLD packaged in a 132-ball csBGA package. This package allows density migration to devices as large as 4340 LUTs. A complete description of this device can be found in DS1035, MachXO2 Family Data Sheet. Power Manager II This board also features a Power Manager II mixed-signal PLD. The POWR1014A device serves as a general-purpose power supply monitor, reset generator, sequence controller, and high-voltage FET drivers. More information about Power Manager II devices can be found on the Lattice web site at www.latticesemi.com/products/powermanager.
3 MachXO2-1200HC Control Development Kit User Guide
Software Requirements You should install the following software before you begin developing designs for the evaluation board:
• Lattice Diamond™ 1.2 or higher • ispVM™ System 17.9.1 or higher Control SoC Demonstration Design The Control System-on-Chip (SoC) demonstration illustrates the use of the LatticeMico8 microcontroller, peripher- als, and firmware integrated to provide system control features such as power supply sequencing, voltage monitor- ing, data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication and PLL status monitoring.
• The Power Manager II device sequences the power-up of voltage rails on the board and performs reset distribu- tion. • LatticeMico8 executable program initializes the peripherals that are embedded in the SoC design. During initial- ization, LatticeMico8 uploads the user menu on the HyperTerminal of a PC. • Users interact with LatticeMico8 and the board through the HyperTerminal of a PC.
Figure 2. Control SoC Demo Block Diagram
MachXO2 Control Evaluation Board
MachXO2-1200
Timer/ LatticeMico8 LEDs/ PC UART USB/ Counter Microcontroller DIP Switches RS232
WISHBONE Bus
Soft Master Embedded ADC SPI Block RAM
Analog SPI Signal Flash
Power management is handled in two phases by the MachXO2-1200HC Control Evaluation Board system:
1. Power On – After power is supplied to the board and the 3.3 V rail is stable, the POWR1014A sequences four supply rails. Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETs using the high-voltage (HVOUT) outputs and two demonstrate power rail enable of VCC_CORE and VCCP of the MachXO2 using digital outputs. Next, the POWR1014A asserts the MachXO2 reset. Finally, the POWR1014A enters a supply monitoring state.
Note: SW2 should be set to the off position or the cycle will be repeated.
2. Post Power On – During the second phase of power management, the board’s “condition” is monitored. Power supply rail voltage, and current is monitored by the POWR1014A. If any supply rail fails, the POWR1014A asserts a reset for the MachXO2.
MachXO2 Function – After the reset is de-asserted, LatticeMico8 initializes the peripherals embedded in the MachXO2 device and uploads the user menu onto the HyperTerminal window of a PC.
4 MachXO2-1200HC Control Development Kit User Guide
Figure 3. HyperTerminal User Menu
Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the HyperTermi- nal menu. The available options are:
•‘m’ – This option will re-display the main menu anytime during the demonstration. •‘a’ – This option will sample the voltage in the pin #2 of header J9. By default, the node is biased at 1.65 V, which is half of the VCCIO = 3.30 V. The voltage will be displayed in the HyperTerminal window. The ADC input voltage should be limited to the range 0 to 3.0 V to avoid device damage. •‘s’ – This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal. The resulting ID is hexadecimal 0x44, which corresponds to AT25DF041A device. •‘t’ – This option samples and displays the elapsed time since the reset was de-asserted. •‘r’ - This option samples the DIP switches (reference designator SW1) on the board and displays the data in the HyperTerminal. Users can change the DIP switches on the board and press ‘r’ to display the new value. •“0-9” – These are BCD numerical values that can be typed on the keyboard. The value will be received by LatticeMico8, which will update the LEDs (D0-D3) on the board. •‘l’ – This is a lower case ‘L’ character. Pressing ‘l’ will sample the voltage in pin #2 of header J9 and log the data in the SPI Flash device on the board. The WRITE page pointer will increment when ‘l’ is pressed. The initial value of the page pointer after power-up or after a reset is 0. •‘d’ – This option will read the data from SPI Flash device and display it on the HyperTerminal window. The READ page pointer will increment when ‘d’ is pressed. The initial value of the page pointer after power-up or after a reset is 0. •‘c’ – This option will clear (reset) the WRITE and READ page pointers. •‘e’ – This selection will perform a bulk-erase of the Flash memory in the SPI Flash device. Setting up the Board Drivers and Firmware Before you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site.
1. Browse to the www.latticesemi.com/MachXO2-control-kit and locate the hardware device drivers for the USB interface.
5 MachXO2-1200HC Control Development Kit User Guide
2. Download the ZIP file to your system and unzip it to a location on your PC.
Linux Support:
The USB interface drivers for the evaluation board are included in Linux kernel 2.4.20 or greater including distribu- tions compatible with Lattice Diamond design software (Red Hat Enterprise v.3, v.4 or Novell SUSE Enterprise v.10).
The Control SoC Demo is preprogrammed into the MachXO2-1200HC Control Evaluation Board, however over time it is likely that your board will be modified.
To download the demo source files and reprogram the MachXO2-1200HC Control Evaluation Board:
1. Download demo application source code from www.latticesemi.com/mxo2-control-kit.
2. Use .\Demo_MachXO2_Control_SoC\project\control_soc_demo.jed to restore the MachXO2280 Control SoC demo design.
3. Use .\Demo_PM_Control_BM\project\bm_demo.jed to restore the POWR1014A Board Management demo design. Connecting to the MachXO2-1200HC Control Evaluation Board 1. Plug the AC-DC adopter to an outlet.
2. Power the board by inserting the AC-DC adopter into the power jack with reference designator J11. Once the connection is made, a red LED with reference designator D12 will illuminate.
3. Connect the evaluation board to your PC using the USB cable provided. The USB connector in the board has reference designator J5.
4. If you are prompted, “Windows may connect to Windows Update”, select No, not this time from available options and click Next to proceed with the installation.
5. Choose the Install from specific location (Advanced) option and click Next.
6. Select Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created earlier. Select the CDM 2.04.06 WHQL Certified folder and click OK.
7. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful. Programming the PLDs The three-pin header with reference designator J6 is used to select between the JTAG port of the MachXO2 or POWR1014A device. Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device. Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device.
Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4. This exam- ple shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been selected.
6 MachXO2-1200HC Control Development Kit User Guide
Figure 4. J6 Header Used for Selecting the JTAG Port of the PLDs
Using ispVM System software, users can scan and perform JTAG operations, including programming, with the MachXO2 and POWR1014A devices. Setting Up Windows HyperTerminal You will use a terminal program to communicate with the evaluation board. The following instructions describe the Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program if desired although setup will be different. Windows 7 does not include HyperTerminal. Tera Term has been verified to work with Windows 7. For Linux, Minicom is a good alternative.
Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows ver- sion.
1. From the Start menu, select Control Panel > System. The “System Properties” dialog appears.
2. Select the Hardware tab and click Device Manager. The “Device Manager” dialog appears.
Figure 5. Device Manager – COM Port
3. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port.
4. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTer- minal application and a “Connection Description” dialog appear.
7 MachXO2-1200HC Control Development Kit User Guide
Figure 6. New Connection – COM Port
5. Specify a Name and Icon for the new connection. Click OK. The “Connect To” dialog appears.
6. Select the COM port identified in Step 3 from the Connect using: list. Click OK.
Figure 7. Selecting the COM Port
7. The “COMn Properties” dialog appears where n is the COM port selected from the list.
8. Select the following Port Settings and click OK. Bits per second: 115200 Data bits: 8 Parity: None Stop bits: 1 Flow control: None
Figure 8. COM Port Properties
8 MachXO2-1200HC Control Development Kit User Guide
9. The HyperTerminal window appears.
10. From the MachXO2-1200HC Control Evaluation Board, press the reset push-button with reference designator S1. The Control SoC demo main menu appears. Setting Up Linux Minicom Minicom is a terminal program found with most Linux distributions. It can be used to communicate with the MachXO2-1200HC Control Evaluation Board.
To setup Minicom:
1. Check active serial ports:
#dmesg | grep tty
Note the tty label assigned to the USB port
2. From a command prompt, start Minicom:
#minicom –s
The configuration menu appears.
3. Highlight Serial port setup and press Enter. Serial port settings appear.
4. Press A (Serial Device). Specify the active serial device noted in Step 1 and press Enter.
5. Press E (Bps/Par/Bits). Specify 115200, None, 8 and press Enter.
6. Press F (Hardware Flow Control). Specify None and press Enter.
7. Press Esc. The configuration menu appears.
8. Select Save setup as dfl. Minicom saves the port setup as the new default.
9. Select Exit. The Minicom interface appears.
10. From the evaluation board, press the S1 push-button (GSR).The Control SoC demo main menu appears. Ordering Information
China RoHS Environment-Friendly Description Ordering Part Number Use Period (EFUP)
MachXO2-1200HC Control Development Kit LCMXO2-1200HC-C-EVN
9 MachXO2-1200HC Control Development Kit User Guide
Technical Support Assistance e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary March 2015 1.6 Updated Features section. Added “center positive” to AC Adapter description. Updated Technical Support Assistance information. March 2013 01.5 Document title changed from MachXO2 Control Development Kit User’s Guide to MachXO2-1200HC Control Development Kit User’s Guide. Updated power management handling information in the Control SoC Demonstration Design section. Added reference to Appendix A on how to use the Crystal OSC (X2). June 2012 01.4 Added Appendix C, Limitations. February 2012 01.3 Updated document with new corporate logo. December 2011 01.2 Updated Bill of Materials list. July 2011 01.1 Updated Features list with information on migration from MachXO2- 1200-R1 to Standard (non-R1) devices. April 2011 01.0 Initial release.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 MachXO2-1200HC Control Development Kit User Guide
Appendix A. Schematic Figure 9. Architecture B D A C of 214 1 1 Tuesday, February 15, 2011 15, February Tuesday, Architecture MachXO2 Control Board A SD Flash LPDDR 128Mb SW & LEDs Audio IN Audio OUT Crystal B Title Size Document NumberDate: Sheet Rev Title Size Document NumberDate: Sheet Rev Page 8 Page 7 2 2 Page 8 Page 7 Page 12 Page 12 7:1LVDS Conn Page 10 DAC: Page 12 DVI Conn 7:1LVDS Conn ADC: Page 14 ADC-DAC DVI to 7:1LVDS Conversion Page 13,14 3 3 Page 11 7:1LVDS RX MachXO2 DVI Conn 7:1LVDS TX 7:1LVDS to DVI Conversion DVI Conn DVI to 7:1LVDS Conversion GPIO Page 9 RESET Page 7 7:1LVDS Conn UART Page 4 4 4 SW & LEDs Page 4 GPIO I2C Bus SPI Bus Power Manager II ispPAC POWR1014A Page 6 Page 3,5 UART & USB PORT JTAG Chain Board Power Managment Voltage Monitor Page 8
High Voltage Drivers 5 Header 2x20 5 SPI 4Mbit Page 7 MachXO2 Control Board Architecture C B D A
11 MachXO2-1200HC Control Development Kit User Guide
Figure 10. VCC33, VCC18, VCC12 B D A C A 1 of 1 314 VCC33 VCC18 Sheet C53 22uF C65 22uF DI DI 4 2 4 2 DI NCP1117ST18 DI NCP1117ST33 TAB TAB OUT OUT 1 1 GND GND U12 U11 IN IN 3 3 Tuesday, February 15, 2011 15, February Tuesday, DI Power VCC33, VCC18, VCC12 VCC18, VCC33, Power Board Control MachXO2 C54 10uF DI C66 10uF B Title Size Document NumberDate: Sheet Rev Title Size Document NumberDate: Rev 2 2 R122 470
DI
D12 LED LED DI D12 VCC5 VCC33 Linear VREG Step Down 5V to 3.3V Rail Linear VREG Step Down Linear VREG Step Down 3.3V to 1.8V Rail Linear VREG Step Down 3 3 PM_OUT8 [4,5] R81 10K VCC33 DI Q6 BSS138LT1 VCC_CORE DI C106 10uF 4 VCC12 4 R200 10K VCC33 DI 9 8 7 6 5 9 ~SD NC_1 IO19 IO20 SENSE OUTPUT VCC5 U17 LP3879MR_1_2 DI 1 2 3 INPUT BYPASS NC GND 4 1 2 3 DI C33 10uF J11DI PWR_JACK VCC33 5 5 5V Input C108 0_01uF DI AC-DC Jack - 5V Linear VREG Step Down 3.3V to 1.2V Rail Linear VREG Step Down C B D A
12 MachXO2-1200HC Control Development Kit User Guide
Figure 11. ispPAC-POWR1014A B D A C of 414 1 1 Tuesday, February 15, 2011 15, February Tuesday, Power ispPAC-POWR1014APower MachXO2 Control Board A B Title Size Document NumberDate: Sheet Rev Title Size Document NumberDate: Sheet Rev 2 2 SW2 SW DIP_2 DI
PM DIP Switch
R163 R163 10K 10K DI DI
R164 10K 10K DI DI VCC33 R164 PM_IN3 PM_IN4 3 3 HVOUT1HVOUT2 [7] PM_SMBA_OUT3 [7] [14] PM_OUT8PM_OUT9 [3,5] XO2_RESETn [7,14] [5] PM_OUT11PM_OUT12 [14] PM_OUT13 [14] PM_OUT14 [14] PM_PLDCLK [7,14] PM_MCLK [7,14] DI C107 0_1uF RN4 RN2_4_470 DI DI
DI C99 0_1uF
DI
5 4
DI
HVOUT1 HVOUT2 PM_SMBA_OUT3 PM_LED0 PM_LED1 PM_OUT8 PM_OUT9 PM_OUT10 PM_OUT11 PM_OUT13 PM_OUT14 PM_PLDCLK PM_MCLK PM_LED2 PM_LED3 PM_OUT12 6 3
DI
7 2
8 1 VCC33 43 7 31 12 11 10 9 8 6 13 15 14 3 2 40 30 5 4 1 42 LED D7 PM LEDs PM DIP SWITCH DI C89 0_1uF D8 LED OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 MCLK GNDA GNDD GNDD OUT12 OUT13 OUT10 OUT11 OUT14 LED D9 PLDCLK RESETB HVOUT1 HVOUT2 PM_LED0 PM_LED2 PM_LED1 PM_LED3
D10 LED SMBA_OUT3
VCCJ
20
VCCPROG
VCC33 24
VCCINP
45
VCCA
29
VCCD
IO18 41
VCCD 23 4 4 VMON4 VMON2 VMON7 VMON10 IN1 IN2 IN4 ATDI TDI TCK TDO SDA VMON1 VMON3 VMON5 VMON6 VMON8 VMON9 IN3 TDISEL TMS SCL VMON7 VMON8 ispPAC-POWR1014A DI U7 28 26 34 37 44 46 48 17 18 22 21 38 25 27 32 33 35 36 47 19 16 39 R179 200 R198
200
Q2 2N7002E DI DI Q5 2N7002E DI DI
3 2 3 2 VCC33 VCC33 VMON1 VMON4 VMON5 VMON6 VMON8 PM_IN1 VMON3 VMON7 VMON9 VMON10 PM_IN2 PM_IN3 PM_IN4 1 1 SDA SCL DI DI C83 1uF C35 1uF DI DI R195 1K R196 1K POWER MANAGER II SCL SDA Voltage Ramp Circuit PM_TDI ICC_Sense ICCIO33_Sense ICCIO18_Sense VMON9 VMON10 PM_IN1 PM_IN2 PM_TMS PM_TCK PM_TDO [6] [7,14] [5] [5] [5] [7] [7] [7,14] [6] [6] [6] [14] [14] HVOUT2 HVOUT1 5 5 VCCIO33 VCC_CORE C B D A
13 MachXO2-1200HC Control Development Kit User Guide
Figure 12. Power Current Sense B D A C ICCIO18_Sense [4] 1 1 of 514 R189 3_92K DI C91 0_01uF DI AD8604ARZ U16A AD8604ARZ U16D 14 1
C105 0_1uF DI
4 11 4 11 VCC33 VCC33 + - + - 3 2 13 12 DI 3_92K R193 Tuesday, February 22, 2011 22, February Tuesday, Power Current Sense Current Power MachXO2 Control Board A R194 100 DI DI 100 R184 B Title Size Number Document Date: Sheet Rev Title Size Number Document Date: Sheet Rev 2 2 ICCIO18_P ICCIO18_N Current Sense ICC_Sense [4] ICCIO33_Sense [4] R204 2K DI C38 0_01uF DI C41 0_01uF DI R190 3_92K DI U16B AD8604ARZ U16C AD8604ARZ 8 7
DI C44 0_1uF DI C46 0_1uF
4 11 4 11 VCC33 VCC33 + - + - 6 5 9 10 3 3 DI DI 2K 3_92K R197 R192 R201 100 DI DI 100 R206 R191 100 DI DI 100 R185 ICC_N ICCIO33_P ICCIO33_N ICC_P 4 4 ICC_N VCC_CORE IO11 R59 1 DI R58 0 DNI ICCIO33_N IO7 VCCIO33 VCC12
DI ZDT758 Q7A R235 2 DI 5
6 3 ZDT758 Q7B DI
7
ICCIO18_N 8 VCC33 IO9 1 IO8 VCC33 VCCIO18 IO15 4 R232 DI R67 1K DI 1K 2 ICC_P ICCIO33_P R148 2 DI IO14 VCC18 DI DI 10uF MachXO2 Power Rails Power MachXO2 10uF C143 C142 ICCIO18_P 5 MachXO2 - Core Current R60 220 DI 5 R219 220 MachXO2 - ICCIO33 Current MachXO2 - ICCIO18 Current DI PM_OUT9 PM_OUT8 C142, C143 to limit Vcc, Vccio ramp rates to data sheet spec. [4] [3,4] C B D A
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Figure 13. Configuration USB Port B D C A A Rev Rev of R66 614 4_7K DI R55 4_7K DI Sheet 1 1 R54 4_7K DI PM_TDO [4] XO2_TDO [13] XO2_TMS [7,13,14] R65 PM_TCK [4] XO2_TCK [7,13,14] PM_TDI [4] PM_TMS [4] XO2_TDI [13,14] 4_7K DI R88 4_7K DI VCC33 R89 4_7K DI R85 4_7K DI PM_TMS PM_TCK XO2_TDI PM_TDO XO2_TMS XO2_TCK XO2_TDO PM_TDI Tuesday, February 15,Tuesday, 2011 R84 4_7K DI USB_UART_TX [14] Configuration Port USB ControlMachXO2 Board USB_UART_RX [14] DI DI DI DI DI DI 0 0 0 0 0 0 DI C DI DI Title Size Document Number Date: Sheet Title Size Document Number Date: R62 R70 R71 R76 R87 R61 0 R80 68 R86 68 PM_TMS XO2_TMS XO2_TDI PM_TDO PM_TCK XO2_TCK PM_TDI XO2_TDO DI R83 0 15 4 12 9 14 1 6 7 R82 1S1 2S1 3S1 4S1 3S2 4S2 1S2 2S2 STG3693QTR U5 D1 123SEL 4SEL GND VCC D2 D3 D4 DI 8 3 2 5 C109 13 16 10 11 0_1uF VCC33 DI DI DI DI DI DI 0 0 0 0 2 2 R36 R37 R38 R78R75 0 0 R39 VCC33 2 1 3 VBUS J6 Jumper_2way DI
R205 R249 10k 4_7K DI
1 2
C30 0.1uF cc0402
1 2
17 46 27 57 59 60 21 23 26 29 30 32 38 40 44 48 36 16 19 28 33 39 43 54 58 45 41 18 22 24 34 52 53 55
VCCIO
56
VCCIO
VCC33 42 C85 0.1uF cc0402
VCCIO GND
51
31 BDBUS6 ADBUS2 ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS3 ACBUS4 ACBUS5 ACBUS7 BDBUS0 BDBUS2 BDBUS5 BCBUS0 BCBUS1 BCBUS2 BCBUS4 ADBUS0 ADBUS1 ADBUS3 ACBUS2 ACBUS6 BDBUS1 BDBUS4 BDBUS7 BCBUS3 BCBUS6 ACBUS1 BDBUS3 BCBUS5 BCBUS7
GND VCCIO PWREN#
20 47 1 2
SUSPEND# GND
35
GND
25
VCORE GND
64 15
VCORE GND
37 11
VCORE GND
5 12 C82 0.1uF cc0402
GND
1
VPLL
9 2 1 3 3
VPHY AGND
4 10 C48 0.1uF cc0402
C104 0.1uF FTDI High-Speed USB High-Speed FTDI FT2232H
DM EECS VREGIN VREGOUT REF EEDATA OSCI TEST DP RESET# EECLK OSCO
1 2 1 2 3 7 6 8 2 50 14 62 63 49 61 13 U20 FT2232HL
C144 4u7
2 1 C145 0.1uF C31 0.1uF cc0402
1 2
1 2 1% VCC33 2 2
C28 10u R56
1 C23 18pF
1 2
FT_EECLK FT_EECS FT_EEDATA 2 1 2k2 L3 R199 12k 1 1 600ohm 500mA 2 3 4 VCC33 3 G2 VCC33 1 G1 X3 12MHZ
1 2
2 1 VCC18FT 18pF C29 4 4 FT_EECS FT_EECLK FT_EEDATA
R241 10k
1 2 Dp tion 1
R240 R202 10k
1 2 Dm 2k2 2
R203 10k
1 2 R68 0 DI 2 4 1 3 DI R63 0 DI U21 CS DO CLK 93LC56-SO8 VCC NU ORG VSS C32 DI 8 7 5 6 0_01uF R79 100K DI VBUS The USB interface draws no power from VCC33 5 5 the USB bus. It is self-powered.
SHLD_Debug 1 2 C27
DI
9 3 4 7 8 1 2 6 10 11 5 0.1uF
1 2 D- D+ NC VCC MH1 MH2 GND CASE CASE CASE CASE C126
0.1uF
1 2 C119 J5 USB_MINI_B 0.1uF USB Port: CPLD Configuration & USB<->UART Communica D C B A
15 MachXO2-1200HC Control Development Kit User Guide
Figure 14. Software, LED, Crystal, Header B D A C Rev Rev of 714 1 1
Note: For more information on how to use the Crystal OSC (X2), refer to. AN8080, Using a Discrete Crystal as a CT1934MS-ND 8 7 6 5 PLD Clock Source. Tuesday, February 15, 2011 15, February Tuesday, DI SW, LED, Crystal, Header Crystal, SW, LED, MachXO2 Control Board A SW1 SWDIP_4 1 3 4 2 B R124 10K DI Title Size Document Number Date: Sheet Title Size Document Number Date: Sheet R125 10K DI 2 2 R126 10K DI VCC33 R127 10K DI X_1 [14] X_2 [14] 3W WS S3 SW0 SW1 SW2 C8 0_1uF X_2 X_1 DI IO3 IO2 VCC33 SW0 SW1 SW2 SW3 R3 0 DNI 4-DIP Switch R2 1M DI 4 3 [14] [14] [14] [14] DI R4 1K DI C11 12pF VCC OUTPUT X1 DI 2 3 3 CTS-CB3LV-3C-25MHz X2 DI GND EOH R1 10K 1 2 1 DI HCM49 24.000MABJ-UT HCM49 C4 12pF R128 10K C63 0_1uF 24 MHz Crystal 24 MHz OSC 25 MHz DI DI VCC33 4 3 S1 DI 1 2 XO2 Global Reset XO2 [4,14] [4,14] XO2_ADC_IN [14] HVOUT1HVOUT2 [4] PM_PLDCLK [4] [4,14] PM_MCLK [4,14] PM_OUT14 XO2_GPIO_11 [14] XO2_GPIO_10 [14] XO2_GPIO_9XO2_GPIO_8 [14] XO2_SPI_CLK [14] [8,14] XO2_SPI_OUT [8,14] XO2_SPI_IN [8,14] SCL SDA XO2_RESETn 4 4 Reset Push-Button Switch [4,14] VCC18 SCL XO2_SPI_CLK HVOUT2 PM_MCLK SDA PM_OUT14 PM_PLDCLK XO2_SPI_IN XO2_SPI_OUT HVOUT1 XO2_GPIO_11 XO2_GPIO_10 XO2_GPIO_9 XO2_ADC_IN XO2_GPIO_8 2 6 8 12 14 22 24 28 30 32 34 36 38 40 4 10 18 20 26 16 J4 CON40A DNI 2x20x100mil 3 9 1 5 7 RN1 RN2_4_470 DI DI 11 35 13 17 21 23 27 29 33 37 39 15 19 25 31
DI
5 4
DI
6 3
DI
7 2
8 1 VCC33 VMON10 XO2_GPIO_0 VMON9 XO2_GPIO_6 XO2_GPIO_1 XO2_GPIO_2 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_3 XO2_GPIO_7 LED D1 VCC33 5 5 XO2_LED2 XO2_LED1 XO2_LED0 XO2_LED3 LED D2 VCC12 LED D3 TCK_HDR TDI_HDR TMS_HDR TDO_HDR D4 LED XO2_GPIO_1 XO2_GPIO_0 XO2_GPIO_2 XO2_GPIO_3 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_6 XO2_GPIO_7 XO2_LED1 XO2_LED2 XO2_LED3 VMON9 XO2_LED0 VMON10 XO2 LEDs [14] [14] [14] [14] [14] [14] [14] [4] [14] [13] [13] 2x20 Header [4] [6,13,14] [6,13,14] [14] [14] [14] [14] C B D A
16 MachXO2-1200HC Control Development Kit User Guide
Figure 15. Memory LPDDR, SD, SPI B D A C Rev Rev of 814 VCC18 1 1 DI DI DI 7 6 8 5 4 3 2 1 LPDDR_LDM [14] LPDDR_DQ0 [14] LPDDR_DQ1 [14] LPDDR_DQ2 [14] LPDDR_DQ3 [14] LPDDR_DQ4 [14] LPDDR_DQ5 [14] LPDDR_DQ6 [14] LPDDR_DQ7 [14] LPDDR_LDQS [14] 9 13 10 11 12 14 15 16 R158 10K R159 10K RN3 RN1_8_10K resistors are used for bias. LPDDR_DQ1 LPDDR_DQ3 LPDDR_DQ5 LPDDR_DQ7 LPDDR_LDM LPDDR_DQ0 LPDDR_DQ2 LPDDR_DQ4 LPDDR_DQ6 LPDDR_LDQS U6 Lower Byte Mask & Strobe Mask Byte Lower MT46H16M16LFBF VCC18 D3 C3 B7 B8 C8 D8 E7 E3 D2 B3 F8 A8 E8 A2 F2 E2 C7 D7 C2 B2
Tuesday, February 15, 2011 15, February Tuesday,
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ0 VSSQ VDDQ LDM
UDM
E1
E9 DQ10 DQ12 DQ11 DQ13 DQ14 DQ15 Memory LPDDR, SD, SPI SD, LPDDR, Memory MachXO2 Control Board A LDQS
UDQS
VDDQ VSSQ
C1 VCC18 D1
VDDQ VSSQ
B9 C9 DNI
VDDQ VSSQ
A3
B1 B
7 6 5 4 3 2 1 8
VDDQ VSS
K1 A7 Title Size Document Number Date: Sheet Title Size Document Number Date: Sheet
VDD VSS
K9 F1
VDD VSS
F9 A1
VDD A9 A12 CK CKE CS# RAS# BA1 WE# NC NC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 CK# CAS# BA0 NC 9 10 13 16 11 12 14 15 DI stors. The internal XO2 stors. The J8 J9 J1 J2 J3 J7 F3 F7 K7 K8 K2 K3 H3 H7 H9 D9 H1 H2 H8 G3 G2 G1 G9 G7 G8 2 2 C79 0_1uF RN2 RN1_8_10K DI C75 0_1uF R186 0 DI LPDDR_DQ2 LPDDR_DQ3 LPDDR_DQ5 LPDDR_DQ6 LPDDR_DQ0 LPDDR_DQ1 LPDDR_DQ4 LPDDR_DQ7 LPDDR_WEn LPDDR_A1 LPDDR_A2 LPDDR_A3 LPDDR_A4 LPDDR_A5 LPDDR_A6 LPDDR_A7 LPDDR_A9 LPDDR_A10 LPDDR_A11 LPDDR_A12 LPDDR_CKn LPDDR_CKE LPDDR_RASn LPDDR_CASn LPDDR_BA0 LPDDR_BA1 LPDDR_A0 LPDDR_A8 LPDDR_CK LPDDR_CSn DI C72 0_01uF DI LPDDR_A0 LPDDR_A4 LPDDR_A10 LPDDR_CK LPDDR_CSn LPDDR_RASn LPDDR_CASn LPDDR_BA0 LPDDR_BA1 LPDDR_A1 LPDDR_A2 LPDDR_A3 LPDDR_A5 LPDDR_A6 LPDDR_A7 LPDDR_A8 LPDDR_A9 LPDDR_A11 LPDDR_A12 LPDDR_CKn LPDDR_CKE LPDDR_WEn C71 0_001uF [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] Empty External Pull-UP resi Pull-UP External Empty LPDDR - 128Mb (4 Meg x 4 banks 8 data) (4 Meg LPDDR - 128Mb 3 3 DI C81 0_1uF VCC33 XO2_SPI_CS0 [14] XO2_SPI_CLK [7,14] XO2_SPI_IN [7,14] XO2_SPI_OUT [7,14] 6 4 4 4 VSS VDD XO2_SPI_CS0 XO2_SPI_CS0 XO2_SPI_CLK XO2_SPI_CLK XO2_SPI_IN XO2_SPI_OUT XO2_SPI_IN XO2_SPI_OUT U1 DAT1 DAT2 CD/DAT3 CMD CLK DAT0 microSD Socket 2 7 8 1 3 5 2 2 6 5 1 1 6 5 S S C D C D Q Q Package: UDFN AT25DF041A-SH-B AT25DF041A-MH-B U14 U15 Reset W Vcc W Vss Vcc Vss Reset Package: SOIC8 (WIDE) 3 8 4 7 7 3 8 4 uSD_DAT3 uSD_DAT1 uSD_CMD uSD_DAT0 uSD_DAT2 uSD_CLK VCC33 VCC33 5 uSD_DAT2 uSD_DAT3 uSD_DAT0 uSD_DAT1 5 uSD_CLK C74 DI Micro SD Card Socket SD Card Micro uSD_CMD 0_1uF 4MBit SPI 4MBit (Refer to Appendix C. Limitations) [14] [14] [14] [14] [14] [14] C B D A
17 MachXO2-1200HC Control Development Kit User Guide
Figure 16. Video Input 1 B D C A A Rev Rev of 914 Sheet Sheet XO2_IN3_1_N [14] XO2_IN0_1_N [14] XO2_IN1_1_N [14] XO2_IN2_1_N [14] XO2_CLKIN_1_P [14] XO2_IN2_1_P [14] XO2_IN3_1_P [14] XO2_IN0_1_P [14] XO2_IN1_1_P [14] XO2_CLKIN_1_N [14] 1 1 Video Input 1 Tuesday, February 15,Tuesday, 2011 MachXO2 ControlMachXO2 Board C135 0_001uF DI C17 0_001uF DI C14 0_001uF DI C Title Size Number Document Date: Title Size Number Document Date: NS_LVCC_1 NS_PVCC_1 TI_PVDD_1 0_01uF DI C18 0_01uF DI C15 0_01uF DI C136 DI DNI DNI DI DNI DI DI DI DNI DNI DNI DI DI DI DI DI DNI DNI DNI DNI C19 0_1uF DI C141 0_1uF DI C112 0_1uF DI R231 0 R226 0 R222 0 R224 0 R218 0 R216 0 R214 0 R230 0 R229 0 R228 0 R227 0 R223 0 R225 0 R217 0 R215 0 R213 0 R209 0 R212 0 R211 0 R210 0 10uF DI C20 10uF DI C22 10uF DI C140 TX_OUT2_P_1 TX_OUT3_P_1 TX_OUT0_P_1 TX_OUT1_P_1 TX_OUT0_N_1 TX_OUT1_N_1 TX_OUT2_N_1 TX_OUT3_N_1 TX_CLKOUT_P_1 TX_CLKOUT_N_1 MDR_TX_OUT2_N_1 MDR_TX_OUT3_P_1 MDR_TX_OUT0_P_1 MDR_TX_OUT1_P_1 MDR_TX_OUT2_P_1 MDR_TX_OUT3_N_1 MDR_TX_OUT0_N_1 MDR_TX_OUT1_N_1 MDR_TX_CLKOUT_N_1 MDR_TX_CLKOUT_P_1 Resistor MUX MUX Resistor VCC33 2 2 NS_STB_1 C125 0_001uF C113 0_001uF DI C137 0_001uF DI DI DVDD_1 NS_PVCC_1 NS_LVCC_1 DVDD_1 TI_AVDD_1 TI_OVDD_1 C124 0_01uF DI C6 0_01uF DI C5 0_01uF DI TX_OUT0_P_1 TX_OUT2_P_1 TX_OUT3_P_1 TX_OUT1_P_1 TX_OUT3_N_1 TX_OUT0_N_1 TX_OUT1_N_1 TX_OUT2_N_1 TX_CLKOUT_P_1 TX_CLKOUT_N_1 C123 0_1uF C16 0_1uF DI C115 0_1uF DI DI 5 13 37 44 36 43 26 21 53 9 49 48 46 42 34 35 1 39 29 40 38 33 47 45 41 17 VCC VCC VCC VCC GND GND GND GND GND 10uF C21 10uF DI C122 DI C121 10uF DI PLLVCC PLLGND PLLGND TxOUT0P TxOUT1P TxOUT2P TxOUT3P TxOUT0N TxOUT1N TxOUT2N TxOUT3N LVDSVCC LVDSGND LVDSGND LVDSGND TxCLKOUTP TxCLKOUTN TxIN26 TxIN23 TxIN21 TxIN20 TxIN17 TxIN15 TxIN12 TxIN10 TxIN7 TxIN4 TxIN1 TxIN27 TxIN24 TxIN19 TxIN18 TxIN16 TxIN14 TxIN13 TxIN8 TxIN5 TxIN3 TxIN2 TxIN0 TxIN25 TxIN22 TxIN11 TxIN9 TxIN6 TxCLKIN PWRDWN DS90CR287 U19 3 8 4 6 2 7 20 28 24 31 32 30 25 22 18 11 56 52 50 27 19 16 14 12 54 51 10 23 15 55 VCC33 TXIN27_1 TXIN24_1 TXIN21_1 TXIN16_1 TXIN14_1 TXIN10_1 TXIN8_1 TXIN7_1 TXIN5_1 TXIN2_1 TXIN0_1 TXIN26_1 TXIN25_1 TXIN22_1 TXIN20_1 TXIN19_1 TXIN18_1 TXIN17_1 TXIN15_1 TXIN12_1 TXIN11_1 TXIN9_1 TXIN6_1 TXIN4_1 TXIN3_1 TXIN1_1 TXCLKIN_1 PWRDWN_1 TXIN23_1 TXIN13_1 3 3 D5 LED_Green 3 Q1 BSS138LT1 2 SOT-23 (3) Drain DI 470 1 TOP View Package (1) Gate (2) Source IO5 IO4 R27 LED will be ON when link is active. (SCDT high) R G B DVDD_1 SCDT_1 TXIN17_1 TXIN19_1 TXIN9_1 TXIN8_1 TXIN11_1 TXIN27_1 TXIN3_1 TXIN22_1 TXIN20_1 TXIN6_1 TXIN26_1 TXIN25_1 TXIN1_1 TXIN0_1 TXIN16_1 TXIN10_1 TXIN5_1 TXIN2_1 TXIN24_1 TXIN21_1 TXIN23_1 TXIN13_1 TXIN12_1 TXIN4_1 TXCLKIN_1 CTL3_1 CTL2_1 TXIN18_1 TXIN15_1 TXIN14_1 SCDT_1 CTL1_1 74 46 17 52 41 36 34 33 30 27 25 22 8 73 72 70 64 62 61 47 55 10 77 71 42 40 37 35 32 31 26 23 63 20 16 14 11 44 60 59 56 54 53 51 50 49 48 24 75 69 66 21 15 12 65 13 DE
QE8 QE6 QE4 QE1 QE9 QE7 QE5 QE2 QE3 QE0 QO6 QO9 QO8 QO7 QO5 QO4 QO2 QO1 QO0 QO3
CTL2 CTL3 CTL1 QE12 QE22 QE20 QE19 QE16 QE15 QE13 QE10 QE23 QE21 QE18 QE17 QE14 QE11 QO23 QO18 QO22 QO21 QO16 QO15 QO20 QO19 QO17 QO14 QO13 QO11 QO10 QO12 SCDT
ODCK R-even R-odd R-odd G-even G-even G-odd G-odd B-even B-even B-odd B-odd R-even VSYNC HSYNC NS_STB_1 CTL1_1 CTL2_1 OCK_INV_1 PDN_1 NS_STB_1 DFO_1 STAGN_1 OCK_INV_1 CTL3_1 PDON_1 PWRDWN_1 PIXS_1 ST_1 DNI DNI DI DI DI DNI DI DI DNI DI DI DI DI DI R237 10K R-in G-in B-in Clk-in R236 10K R5 0 R18 10K R233 10K R239 10K R242 10K R8 0 R6 0 R21 10K R244 10K R19 10K R22 10K R20 10K 4 4 Rx2P Rx1N AVDD RxCP AVDD STAGN DVDD OVDD PGND AGND AVDD Rx1P AGND high) (Tie RSVD OCK_INV DFO PIXS DVDD DVDD DGND DGND OVDD OVDD OVDD OGND OGND OGND AGND Rx2N AVDD AGND Rx0P Rx0N AGND RxCN ST PDON DGND OGND OGND PVDD EXT_RES PDN OVDD TFP401A U2 9 7 6 2 1 4 5 3 79 81 82 89 90 91 92 94 39 28 58 97 80 86 88 93 95 78 98 96 29 83 84 85 87 99 38 67 68 18 43 57 19 45 76 DVDD_1 TXIN7_1 100 ODCK opposite edge from Video Source 2 OCK_INV_1 DFO_1 PIXS_1 ST_1 PDON_1 DVDD_1 TI_PVDD_1 STAGN_1 PDN_1 TI_OVDD_1 DVDD_1 TMDS_1_DATA1_P TMDS_1_DATA0_N TMDS_1_DATA2_N TI_AVDD_1 TMDS_1_CLK_P TMDS_1_CLK_N TMDS_1_DATA2_P TMDS_1_DATA1_N TMDS_1_DATA0_P Supporting Circuits DVI - TMDSDVI Decoder Translator LVDS DS DDC_CLK DDC_DATA [10,11] [10,11] [14] DI Hot_Plug_Video Hot_Plug_Video TMDS_1_CLK_P TMDS_1_CLK_N TMDS_1_DATA0_P TMDS_1_DATA2_P DDC_DATA TMDS_1_DATA0_N TMDS_1_DATA2_N DDC_CLK TMDS_1_DATA1_N TMDS_1_DATA1_P MDR_TX_OUT3_N_1 MDR_TX_OUT0_P_1 MDR_TX_OUT2_N_1 MDR_TX_CLKOUT_P_1 MDR_TX_OUT3_P_1 MDR_TX_OUT1_P_1 MDR_TX_OUT0_N_1 MDR_TX_OUT1_N_1 MDR_TX_OUT2_P_1 MDR_TX_CLKOUT_N_1 R248 0 Channel Link - RX 15 C1 21 22 3 11 C4 9 13 24 C2 16 7 2 5 10 C5 17 8 14 C6 19 20 18 23 6 C3 1 4 12 5 5 26 23 1 12 22 14 19 6 17 16 9 3 11 4 21 15 7 18 25 8 27 24 28 20 5 13 10 2 DDC_Data +5V_Power DDC_Clock Analog_Red Analog_Blue GND(for +5V) TMDS_Clock- TMDS_Data5- TMDS_Data2- TMDS_Data4- TMDS_Data1- TMDS_Data3- TMDS_Data0- TMDS_Clock+ Analog_Green TMDS_Data2+ TMDS_Data4+ TMDS_Data1+ TMDS_Data0+ TMDS_Data5+ TMDS_Data3+ USB- USB+ J2 Sense RxIn2- RxIn3- RxIn0- RxIn1- RxIn2+ RxIn0+ RxIn1+ RxIn3+ Hot_Plug_Detect Analog_Ground_2 Analog_Ground_1 RxClkIn- RxClkIn+ DDC/SCL RxIn1Gnd DDC/SDA RxIn0Gnd RxIn2Gnd RxIn3Gnd TMDS_Clock_Shield Mounting_L RxClkInGnd USB_Shield Mounting_R Analog_Vertical_Sync DDC_Gnd_1 USB_+5VDC TMDS_Data0/5_Shield TMDS_Data2/4_Shield TMDS_Data1/3_Shield DDC_+5VDC DDC_Gnd_26 Analog_Horizontal_Sync USB/DDC_Gnd DVI_I J1 10226-1A10PE-ND DVI-Integrated DVI Connector MDR Connector Video Input Source 1 : DVI or MDR for direct 7:1LV D C B A
18 MachXO2-1200HC Control Development Kit User Guide
Figure 17. Video Input 2 B D C A Rev Rev of 10 14 XO2_IN0_2_N [14] XO2_IN3_2_P [14] XO2_CLKIN_2_P [14] XO2_IN0_2_P [14] XO2_IN1_2_P [14] XO2_IN2_2_P [14] XO2_IN2_2_N [14] XO2_IN3_2_N [14] XO2_CLKIN_2_N [14] XO2_IN1_2_N [14] Sheet 1 1 C39 0_001uF DI C37 0_001uF DI C131 0_001uF DI Tuesday, February 15,Tuesday, 2011 Video InputVideo 2 ControlMachXO2 Board A NS_PVCC_2 TI_PVDD_2 NS_LVCC_2 DI DNI DNI DNI DI DI DI DI DI DNI C138 0_01uF DI C36 0_01uF DI DI DI DI DI DNI DNI DNI DNI DNI DNI C40 0_01uF DI C Title Size Document Number Title Size Document Number Date: Sheet Date: 0_1uF DI C110 0_1uF DI C42 0_1uF DI C133 R111 0 R220 0 R107 0 R99 0 R95 0 R92 0 R112 0 R221 0 R108 0 R102 0 R110 0 R207 0 R106 0 R104 0 R98 0 R96 0 R93 0 R113 0 R208 0 R109 0 C43 10uF DI C129 10uF DI C111 10uF DI TX_OUT3_P_2 TX_OUT0_P_2 TX_OUT1_P_2 TX_OUT2_P_2 TX_OUT0_N_2 TX_OUT1_N_2 TX_OUT2_N_2 TX_OUT3_N_2 TX_CLKOUT_N_2 TX_CLKOUT_P_2 MDR_TX_OUT2_P_2 MDR_TX_OUT3_P_2 MDR_TX_OUT0_P_2 MDR_TX_OUT1_N_2 MDR_TX_OUT1_P_2 MDR_TX_OUT2_N_2 MDR_TX_OUT3_N_2 MDR_TX_OUT0_N_2 MDR_TX_CLKOUT_N_2 MDR_TX_CLKOUT_P_2 Resistor MUX MUX Resistor VCC33 2 2 C132 0_001uF DI C139 0_001uF DI C114 0_001uF DI NS_STB_2 DVDD_2 NS_PVCC_2 NS_LVCC_2 DVDD_2 TI_AVDD_2 TI_OVDD_2 0_01uF DI C34 0_01uF DI C117 0_01uF C130 DI TX_OUT1_P_2 TX_OUT2_P_2 TX_OUT0_P_2 TX_OUT3_P_2 TX_OUT2_N_2 TX_OUT3_N_2 TX_OUT0_N_2 TX_OUT1_N_2 TX_CLKOUT_N_2 TX_CLKOUT_P_2 0_1uF DI C128 0_1uF DI C116 0_1uF DI C45 33 13 21 38 1 36 43 49 40 5 29 45 41 37 44 17 42 34 47 9 53 48 46 35 39 26 VCC VCC VCC VCC GND GND GND GND GND DI C118 10uF DI C127 10uF C120 10uF DI PLLVCC PLLGND PLLGND TxOUT0P TxOUT1P TxOUT2P TxOUT3P TxOUT2N TxOUT0N TxOUT1N TxOUT3N LVDSVCC LVDSGND LVDSGND LVDSGND TxCLKOUTP TxCLKOUTN TxIN27 TxIN25 TxIN22 TxIN20 TxIN19 TxIN16 TxIN14 TxIN11 TxIN9 TxIN6 TxIN3 TxIN0 TxCLKIN TxIN26 TxIN23 TxIN18 TxIN17 TxIN15 TxIN13 TxIN12 TxIN7 TxIN4 TxIN2 TxIN1 PWRDWN TxIN24 TxIN21 TxIN10 TxIN8 TxIN5 DS90CR287 U18 8 2 7 3 4 6 19 27 23 50 28 24 20 16 10 55 51 31 30 25 18 15 12 11 56 52 32 22 14 54 VCC33 TXIN26_2 TXIN23_2 TXIN20_2 TXIN15_2 TXIN13_2 TXIN9_2 TXIN7_2 TXIN6_2 TXIN4_2 TXIN1_2 PWRDWN_2 TXIN27_2 TXIN25_2 TXIN24_2 TXIN21_2 TXIN19_2 TXIN18_2 TXIN17_2 TXIN16_2 TXIN14_2 TXIN11_2 TXIN10_2 TXIN8_2 TXIN5_2 TXIN3_2 TXIN2_2 TXIN0_2 TXIN22_2 TXIN12_2 TXCLKIN_2 LVDS Translator 3 3 D11 LED_Green 3 2 Q8 BSS138LT1 SOT-23 (3) Drain DI 470 1 R114 IO17 IO16 (1) Gate (2) Source TOP Package View SCDT_2 (SCDT high) LED will be ON when link is active. B R G DVDD_2 TXIN1_2 TXIN16_2 TXIN23_2 TXIN8_2 TXIN26_2 TXIN10_2 TXIN2_2 TXIN21_2 TXIN19_2 TXIN4_2 TXIN25_2 TXIN0_2 TXIN17_2 TXIN11_2 TXIN5_2 TXIN27_2 TXIN3_2 TXIN24_2 TXIN22_2 TXIN20_2 TXIN6_2 TXIN12_2 TXIN9_2 TXIN13_2 TXCLKIN_2 CTL3_2 TXIN15_2 SCDT_2 CTL2_2 CTL1_2 TXIN18_2 TXIN14_2 37 73 16 56 51 40 35 33 32 27 26 24 72 71 69 63 61 46 47 54 75 70 42 41 36 34 31 30 25 22 8 62 21 15 13 10 60 59 55 53 52 50 49 23 77 74 65 20 17 14 11 44 48 66 64 12 DE
QE9 QE5 QE3 QE0 QE8 QE7 QE6 QE4 QE1 QE2 QO5 QO9 QO8 QO6 QO4 QO3 QO1 QO0 QO7 QO2
CTL1 CTL3 CTL2 QE23 QE11 QE21 QE19 QE18 QE15 QE14 QE12 QE22 QE20 QE17 QE16 QE13 QE10 QO22 QO17 QO23 QO21 QO20 QO14 QO19 QO18 QO16 QO15 QO13 QO12 QO10 QO11 SCDT
ODCK R-even R-odd R-odd G-even G-even G-odd G-odd B-even B-even B-odd B-odd R-even VSYNC HSYNC NS_STB_2 CTL2_2 CTL3_2 CTL1_2 PDON_2 PWRDWN_2 DFO_2 STAGN_2 OCK_INV_2 PDN_2 NS_STB_2 PIXS_2 ST_2 OCK_INV_2 DNI DNI DI DNI DI DI DI DI DI DI DI DI DNI DI G-in B-in Clk-in R101 10K R-in R120 10K R117 10K R105 0 R103 0 R121 10K R119 10K R97 10K R116 10K R243 10K R100 0 R115 10K R118 10K R94 10K 4 4 AGND Rx2N AGND RxCN ST DVDD DVDD PVDD Rx2P AVDD AVDD Rx1N AVDD Rx0P AGND RxCP AVDD DFO PIXS STAGN PDN DVDD DGND DGND OVDD OVDD OVDD OGND OGND PGND AGND Rx1P AGND Rx0N EXT_RES high) (Tie RSVD OCK_INV DGND OVDD OGND OGND OGND PDON OVDD TFP401A U9 3 6 9 1 4 7 2 5 83 85 87 91 96 99 68 18 19 45 76 79 81 89 94 43 80 82 84 86 88 90 92 93 95 67 39 29 57 78 28 58 98 38 97 TXIN7_2 DVDD_2 100 PDN_2 DVDD_2 OCK_INV_2 DFO_2 PIXS_2 STAGN_2 DVDD_2 TI_OVDD_2 TI_PVDD_2 ST_2 PDON_2 TI_AVDD_2 TMDS_2_DATA1_N TMDS_2_DATA0_P TMDS_2_CLK_P TMDS_2_DATA1_P TMDS_2_CLK_N TMDS_2_DATA2_P TMDS_2_DATA2_N TMDS_2_DATA0_N Supporting Circuits DVI - TMDS Decoder - DVI [9,11] [9,11] [14] DDC_CLK DDC_DATA DI Hot_Plug_Video Hot_Plug_Video TMDS_2_CLK_P TMDS_2_CLK_N TMDS_2_DATA0_P TMDS_2_DATA2_P DDC_DATA TMDS_2_DATA1_P TMDS_2_DATA0_N TMDS_2_DATA2_N DDC_CLK TMDS_2_DATA1_N R247 0 MDR_TX_OUT1_P_2 MDR_TX_OUT0_N_2 MDR_TX_OUT0_P_2 MDR_TX_OUT1_N_2 MDR_TX_OUT2_P_2 MDR_TX_CLKOUT_N_2 MDR_TX_OUT2_N_2 MDR_TX_CLKOUT_P_2 MDR_TX_OUT3_N_2 MDR_TX_OUT3_P_2 Channel Link - RX 23 3 10 18 C2 6 C3 C5 C1 15 C6 22 C4 1 4 12 16 21 8 24 2 5 13 14 7 11 19 9 17 20 5 5 6 5 23 15 20 18 9 24 4 28 21 12 22 26 1 25 10 2 3 27 13 14 19 16 11 7 8 17 DDC_Data +5V_Power DDC_Clock Analog_Red Analog_Blue GND(for +5V) TMDS_Clock- TMDS_Data1- TMDS_Data0- TMDS_Data5- TMDS_Data2- TMDS_Data4- TMDS_Data3- TMDS_Clock+ Analog_Green TMDS_Data2+ TMDS_Data4+ TMDS_Data3+ TMDS_Data1+ TMDS_Data0+ TMDS_Data5+ USB- USB+ J10 Sense RxIn2- RxIn0- RxIn1- RxIn3- RxIn0+ RxIn1+ RxIn3+ RxIn2+ Hot_Plug_Detect Analog_Ground_1 Analog_Ground_2 RxClkIn- RxClkIn+ DDC/SCL DDC/SDA RxIn2Gnd RxIn0Gnd RxIn1Gnd RxIn3Gnd TMDS_Clock_Shield Mounting_L RxClkInGnd USB_Shield Mounting_R Analog_Vertical_Sync DDC_Gnd_1 USB_+5VDC TMDS_Data2/4_Shield TMDS_Data1/3_Shield TMDS_Data0/5_Shield DDC_+5VDC DDC_Gnd_26 Analog_Horizontal_Sync USB/DDC_Gnd J13 10226-1A10PE-ND DVI_I DVI-Integrated DVI Connector MDR Connector Video Input Source 2 : DVI or MDR for direct 7:1LVDS D C B A
19 MachXO2-1200HC Control Development Kit User Guide
Figure 18. Video Output B D C A Rev of 11 14 J3 DVI-Integrated DVI_I DDC_Data TMDS_Clock+ TMDS_Data2- TMDS_Data2/4_Shield TMDS_Data4+ DDC_Clock Analog_Vertical_Sync TMDS_Data1- TMDS_Data3- Analog_Green Analog_Horizontal_Sync Analog_Ground_1 TMDS_Data4- TMDS_Data0+ Analog_Red TMDS_Data1+ GND(for +5V) TMDS_Data0- TMDS_Data0/5_Shield TMDS_Data5+ TMDS_Clock- Analog_Blue TMDS_Data2+ TMDS_Data1/3_Shield TMDS_Data3+ Hot_Plug_Detect TMDS_Data5- TMDS_Clock_Shield Analog_Ground_2 +5V_Power 1 1 1 3 6 8 4 2 7 5 9 15 11 16 20 22 14 23 12 18 10 17 19 21 24 13 C4 C2 C5 C1 C3 C6 Sheet C7 0_001uF DI C1 0_001uF C55 0_001uF DI DI NS_PVCC NS_LVCC TI_PVDD C56 0_01uF DI DNI DNI C52 0_01uF DI C2 0_01uF DI DDC_CLK DDC_DATA [14] TMDS_DATA1_P TMDS_DATA0_N TMDS_CLK_N TMDS_DATA2_P TMDS_DATA1_N TMDS_CLK_P TMDS_DATA2_N TMDS_DATA0_P 0_1uF C10 0_1uF DI C61 0_1uF DI C64 DI Hot_Plug_Video R246 10K TMDS - DVI Connector R245 10K [9,10] [9,10] DDC_CLK 10uF DI C134 0_1uF DI C9 10uF DI C3 10uF DI C13 DDC_DATA Tuesday, February 15,Tuesday, 2011 VCC5 MachXO2 ControlMachXO2 Board A Video OutputVideo C Title Size Document NumberDate: Rev Title Size Number Document Date: Sheet DVDD TI_TVDD TI_PVDD SM_R_0603 MSEN TMDS_DATA2_P TMDS_DATA2_N TI_TVDD TMDS_DATA1_P TMDS_DATA1_N TMDS_DATA0_N TMDS_CLK_N TMDS_DATA0_P TMDS_CLK_P VCC33 R31 510, 1% 31 23 49 18 1 12 20 24 28 25 48 11 29 34 33 21 17 30 16 64 32 26 27 22 19 0_001uF C50 0_001uF DI C26 DI C12 0_001uF DI N/C TX1P TX0P TX2P TX1N TX0N TX2N TXCP TXCN TVDD TVDD PVDD TGND TGND TGND DVDD DVDD DVDD PGND DGND DGND DGND TFADJ MSEN/PO1 DVDD TI_TVDD NS_DVDD C51 0_01uF DI C25 0_01uF DI C24 0_01uF DI 2 2 G/CTL1 Clk Out 0_1uF C59 0_1uF DI R/HVSync B/CTL3:2 C57 0_1uF DI C58 DI RESERVED (Tie to GND) RESERVED (Tie C49 10uF DI C60 10uF DI C62 10uF DI DATA21 DATA20 DATA18 DATA15 DATA13 DATA11 DATA8 DATA5 DATA0 IDCKN DKEN ISEL/RSTN BSEL/SCL DATA22 DATA19 DATA16 DATA14 DATA9 DATA6 DATA4 DATA3 DATA2 DATA1 IDCKP DE VSYNC HSYNC VREF EDGE/HTPLG CTL3/A3/DK3 CTL2/A2/DK2 DSEL/SDA DATA23 DATA17 DATA12 DATA10 DATA7 CTL1/A1/DK1 PDN U3 TFP410 4 7 8 2 5 3 9 6 37 36 47 51 10 38 39 41 44 50 53 58 63 56 35 15 40 43 45 52 55 59 60 61 62 57 14 42 54 46 13 31R 1R 01 04 VCC33 RXOUT18 EDGE DKEN CTL2 BSEL DSEL PDN RXOUT15 RXOUT14 VREF ISEL CTL3 CTL1 RXOUT9 RXOUT0 RXOUT27 RXOUT6 RXOUT26 RXOUT1 RXOUT16 RXOUT10 RXOUT5 RXOUT3 RXOUT2 RXOUT24 RXOUT22 RXOUT20 RXOUT13 RXOUT12 RXOUT8 RXOUT25 RXOUT17 RXOUT11 RXOUT21 RXOUT19 RXOUT23 RXOUT4 DI DI IO10 IO13 RXCLKOUT TMDS - DVI Decoder DVI - TMDS RXOUT27 RXOUT25 RXOUT24 RXOUT22 RXOUT21 RXOUT19 RXOUT17 RXOUT16 RXOUT13 RXOUT10 RXOUT8 RXOUT6 RXOUT5 RXOUT3 RXOUT0 RXCLKOUT RXOUT26 RXOUT23 RXOUT20 RXOUT18 RXOUT15 RXOUT14 RXOUT12 RXOUT11 RXOUT9 RXOUT7 RXOUT4 RXOUT1 RXOUT2 3 3 D6 LED_Green LED will be OFF when a powered receiver is attached to DVI. Q3 BSS138LT1 (MSEN low) 3 2 SOT-23 (3) Drain 38 34 27 54 35 26 32 3 55 49 45 41 39 37 33 30 29 7 5 1 53 50 46 42 6 2 51 47 43 TOP View Package (1) Gate (2) Source 1 DI RxOUT6 RxOUT9 RxOUT7 RxOUT4 RxOUT2 RxOUT1 RxOUT8 RxOUT5 RxOUT0 RxOUT3 RxOUT27 RxOUT25 RxOUT22 RxOUT19 RxOUT17 RxOUT14 RxOUT11 RxOUT26 RxOUT23 RxOUT20 RxOUT18 RxOUT15 RxOUT12 RxOUT24 RxOUT21 RxOUT16 RxOUT13 RxOUT10 RxCLKOUT R123 10K DI R64 470 MSEN GND RxIN0P RxIN1N RxIN2N RxIN3N RxCLKINN LVDSGND PLLVCC PLLGND PLLGND VCC VCC GND GND RxIN0N RxIN3P RxCLKINP LVDSVCC LVDSGND VCC GND GND RxIN1P RxIN2P PWRDWN LVDSGND VCC DS90CR288A U10 9 8 4 20 28 12 16 25 21 40 10 11 15 19 17 14 23 22 24 31 56 52 18 13 48 36 44 DVDD RX_IN0_N RX_IN1_N RX_IN2_N RX_IN3_P NS_LVCC RX_IN0_P RX_IN1_P RX_IN2_P RX_IN3_N PWRDWN NS_PVCC NS_DVDD RX_CLKIN_P RX_CLKIN_N CTL2 PWRDWN DSEL VREF EDGE CTL1 CTL3 EDGE BSEL PDN DKEN ISEL DI DI DI DI DI DI DI DI DI DI DI DNI LVDS Translator 4 4 R43 10K R47 10K R50 0 R46 10K R132 10K R7 10K R45 10K R44 10K R51 0 R48 10K R32 10K R49 0 RXOUT7 DVDD RX_IN0_P RX_IN1_N RX_IN1_P RX_IN2_N RX_IN3_P RX_CLKIN_P RX_IN0_N RX_IN2_P RX_IN3_N RX_CLKIN_N R130 100 SM_R_0603 R134 100 SM_R_0603 R129 100 SM_R_0603 R135 100 R133 100 SM_R_0603 SM_R_0603 MDR_RX_IN0_P MDR_RX_IN2_P MDR_RX_IN3_P MDR_RX_IN0_N MDR_RX_IN1_N MDR_RX_IN2_N MDR_RX_IN3_N MDR_RX_IN1_P MDR_RX_CLKOUT_P MDR_RX_CLKOUT_N 961R 8 471R 7 61R 71R 5 0 71R 6 92R 61 2 7 3 2 1R 1R 1R 1 1 1 9R 1 3R 2R 1 1R R R R R R R R 07 0 01 0 00 0 07 04 0 0 03 05 0 03 01 0 02 0 0 0 DNI DNI DNI DI DI DI DNI DNI DI DNI DI DNI DNI DI DI DNI DI DI DI DNI DDC/SDA TxOut2+ TxClkOutGnd Mounting_R DDC_Gnd_1 TxOut0- TxOut0+ TxOut1- TxOut1+ TxOut2- TxOut2Gnd USB_Shield TxClkOut- USB_+5VDC TxOut0Gnd USB/DDC_Gnd USB+ DDC/SCL TxClkOut+ DDC_+5VDC TxOut3- TxOut3+ Mounting_L Sense TxOut1Gnd USB- TxOut3Gnd DDC_Gnd_26 J8 10226-1A10PE-ND 3 1 4 8 2 9 7 5 6 16 20 23 24 13 28 18 17 21 25 26 14 15 19 22 11 12 10 27 5 5 XO2_OUT0_P XO2_OUT2_P XO2_OUT3_P XO2_OUT1_P XO2_OUT1_N XO2_OUT3_N XO2_OUT0_N XO2_OUT2_N XO2_CLKOUT_P XO2_CLKOUT_N [14] [14] [14] [14] [14] [14] [14] [14] MDR_RX_IN3_N MDR_RX_IN0_P MDR_RX_IN2_N MDR_RX_CLKOUT_P MDR_RX_IN3_P MDR_RX_IN0_N MDR_RX_IN2_P MDR_RX_IN1_N MDR_RX_IN1_P MDR_RX_CLKOUT_N Resistor De-MUX De-MUX Resistor [14] [14] MDR Connector Supporting Circuits Channel Link - TX Video Output : DVI or MDR for direct 7:1LVDS D C B A
20 MachXO2-1200HC Control Development Kit User Guide
Figure 19. Audio In/Audio Out B D A C Rev of 1 1 12 14 DI C67 10uF DNI C68 0_1uF D2A_OUT Tuesday, February 15, 2011 15, February Tuesday, AUDIO / AUDIO IN OUT MachXO2 Control Board A DI 100 R136 R146 100 DI 2 3 1 R145 330
Q4 2N2369A DI B
1 3 Title Size Document NumberDate: Sheet Rev Title Size Document Number Date: Sheet DI VCC5 2 2 2 J12 PHONEJACK STEREO R151 10K DI AUDIO_OUT AUDIO_OUT [14] PWM Analog Signal Output 3 3 AUDIO_IN AUDIO_IN [14] R161 0 DNI 4 4 U13 AUDIO_SIG Optional Bypass MCP6L71R
1
AUDIO_SIG
2 DI 5 - + 4 3 DI R154 0 R160 680K VCC33 C47 0_1uF DI C70 10uF DI DI R147 2_2K DI VCC33 R150 10K AUDIO_SIG 1 2 DI DI C69 0_1uF 5 C73 10uF 5 TERM1 TERM2 U8 CMA-4544PF-W R162 1000K DI R149 1000K DI VCC33 Microphone Audio Amplifier C B D A
21 MachXO2-1200HC Control Development Kit User Guide
Figure 20. MachXO2 Supplies, JTAG B D A C of TDI_HDR [7] TDO_HDR [7] 13 14 R156 0 DNI 1 1 XO2_TDIXO2_TMSXO2_TCK [6,14] [6,7,14] XO2_TDO [6,7,14] XO2_TDO_PIN [6] [14] TMS_HDRTCK_HDR [6,7,14] [6,7,14] XO2_TDO DI DNI XO2_TMS XO2_TDO XO2_TDI XO2_TCK R157 0 XO2_TDO_PIN XO2_TMS XO2_TCK R155 0 MachXO2 Tuesday, February 15, 2011 15, February Tuesday, XO2_TDO_PIN XO2 Supplies, JTAG MachXO2 Control Board A Expand JTAG Chain to Prototype Header: B
TDO Title Size Document NumberDate: Sheet Rev Title Size Document NumberDate: Sheet Rev R201 2 2 XO2_TDO XO2_TDI XO2_TMS XO2_TCK R203 TDI VCC33
To Prototype Header R202 5 4 1 2 6 3 7 8 NC TDI TCK TDO TMS GND TRST POWER TDO TDI J7 XO2 JTAG HD NOT Populated JTAG Header J12 Expand JTAG Chain to Prototype Header: MachXO2 JTAG Port C98 0_1uF DI 3 3 VCC_CORE C76 0_1uF DI C97 0_1uF DI P5 B11 A1 N1 P14 A14 L2 L13 A5 D13 H13 G2 D2 P10 VCC VCC VCC VCC GND GND GND GND GND GND GND GND GND GND U4E VCCIO33 DI C100 0_1uF DI C103 0_1uF 4 4 DNI C102 0_1uF LCMXO2-1200-CSBGA132 VCCIO0 VCCIO0 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 NC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO3 MH1 M_HOLE1 DI IW_MNT0 1 DNI L1 A8 P1 C5 C7 D3 G1 M6 C101 L12 B10 H14 D14 N11 0_1uF MH2 M_HOLE1 DI IW_MNT0 1 C93 0_1uF DNI MH16 M_HOLE1 DI IW_MNT0 1 C94 0_1uF DNI MH13 M_HOLE1 DI IW_MNT0 1 C80 0_1uF DI C77 0_1uF DI VCCIO33 Socket (080SQ 132U6618A) Mounting Holes Socket (080SQ 132U6618A) C87 0_1uF DNI C88 0_1uF DNI 5 5 C95 0_1uF DNI 0_1uF C86 DNI C90 0_1uF DI C92 0_1uF DI C84 0_1uF DI C96 0_1uF DI VCCIO18 VCCIO33 MachXO2 Power C B D A
22 MachXO2-1200HC Control Development Kit User Guide
Figure 21. MachXO2 Top, Bottom B D C A Rev Rev of [7] 14 14 uSD_DAT3 [8] AUDIO_OUT [12] PM_PLDCLK [4,7] XO2_LED2 [7] XO2_LED3 [7] XO2_LED1 [7] XO2_LED0 [7] X_1 [7] uSD_DAT2 [8] X_2 [7] SW3 1 1 LPDDR_A1 [8] LPDDR_A0 [8] LPDDR_DQ6 [8] LPDDR_DQ4 [8] LPDDR_DQ3 [8] LPDDR_DQ2 [8] LPDDR_LDQS [8] LPDDR_DQ7 [8] LPDDR_DQ5 [8] LPDDR_DQ0 [8] LPDDR_DQ1 [8] XO2_GPIO_10 [7] VCC18 uSD_DAT3 AUDIO_OUT XO2_LED3 XO2_LED1 XO2_LED2 XO2_LED0 XOUT SW3 XIN DI LVDS_COMP_N uSD_DAT2 LVDS_COMP_P_VREF PM_PLDCLK 3 7R PWM_FB_Delta_Sigma K01 LPDDR_DQ4 LPDDR_DQ1 LPDDR_A0 LPDDR_DQ7 LPDDR_DQ6 LPDDR_DQ5 LPDDR_DQ3 LPDDR_DQ2 LPDDR_DQ0 LPDDR_A1 E1 F3 G3 B1 F2 E2 F1 C2 D1 H2 C1 E3 C3 B2 LPDDR_LDQS Tuesday, February 15,Tuesday, 2011 XO2_GPIO_10 XO2 TOP, BOTTOM ControlMachXO2 Board A PL4B PL4A PL4D PL3D PL4C PL3C J13 M13 K13 M14 L14 J12 N14 M12 K14 N13 K12 J14 C Title Size Document Number Date: Sheet Title Size Document Number Date: Sheet PR9B PR8B PR9A PR8A PR8C PR8D PR9D PR9C PR10B PR10A PR10C PL5A/PCLKT3_1 PL3A/PCLKT3_2 PR10D PL3B/PCLKC3_2 PL5B/PCLKC3_1 PL2C/L_GPLLT_IN PL2D/L_GPLLC_IN PL2A/L_GPLLT_FB PL2B/L_GPLLC_FB Bank3
Bank1
R91 R91 DI DI
U4D 4_7K 4_7K PL9B/PCLKC3_0 PL5D PL8A PL8B PL8C PL8D PL9A/PCLKT3_0 PL10C PL5C PL10B PL10D LCMXO2-1200-CSBGA132 VCC33
J1 J2 J3
L3 K1 K3 K2 H3 H1 M2 M1 R90 R90 DI DI
U4B 4_7K 4_7K PR3B PR4B PR5B PR5C/PCLKT1_0 PR2B PR2C PR2D PR3A PR4A PR4C PR5A PR2A PR4D PR5D/PCLKC1_0 LCMXO2-1200-CSBGA132 SCL SDA F12 F13 F14 E14 E12 E13 B14 H12 C13 C14 D12 G14 G13 G12 2 2 I2C Bus Pull-up Resistors PM_MCLK PM_OUT11 PM_OUT12 PM_OUT13 XO2_RESETn USB_UART_TX USB_UART_RX uSD_CLK uSD_DAT1 uSD_CMD uSD_DAT0 LPDDR_A9 LPDDR_A7 LPDDR_A5 LPDDR_A12 LPDDR_A2 LPDDR_CKn LPDDR_LDM LPDDR_A11 LPDDR_A8 LPDDR_A6 LPDDR_A4 LPDDR_A3 LPDDR_A10 LPDDR_CK PM_MCLK PM_OUT11 PM_OUT13 PM_OUT12 XO2_RESETn USB_UART_TX USB_UART_RX [4,7] uSD_CLK uSD_DAT1 [4] [4] uSD_DAT0 [4] [6] [6] LPDDR_A2 LPDDR_A11 LPDDR_A8 LPDDR_A6 LPDDR_A4 LPDDR_A3 LPDDR_CK LPDDR_A10 [4,7] LPDDR_A12 LPDDR_A9 LPDDR_A7 LPDDR_A5 MachXO2 Bank 3 uSD_CMD LPDDR_CKn LPDDR_LDM [8] MachXO2 Bank 1 [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [8] [7] [7] LPDDR_CKE
LPDDR_CKE_1p8 R69 R69 DI DI R74 R74 DI DI
820 820 1K 1K LPDDR_CKE_3p3 XO2_OUT0_N [11] SW0 [7] XO2_OUT0_P [11] LPDDR_CSn [8] LPDDR_WEn [8] LPDDR_RASn [8] LPDDR_CASn [8] SW2 XO2_GPIO_11 [7] SW1 XO2_SPI_IN [7,8] XO2_IN0_1_N [9] XO2_IN2_1_P [9] XO2_IN0_1_P [9] XO2_IN2_1_N [9] [8] LPDDR_BA0
LPDDR_BA0_1p8 R187 R187 DI DI R183 R183 DI DI
SW0 SW1 MOSI SW2 820 820 1K 1K LPDDR_BA1_3p3 LPDDR_CSn XO2_IO_3 XO2_IO_4 LPDDR_CKE_3p3 XO2_IO_2 XO2_GPIO_11 LPDDR_BA0_3p3 XO2_IO_5 XO2_IO_6 XO2_IO_7 XO2_IO_8 XO2_IO_9 LPDDR_WEn 3 3 XO2_OUT0_P XO2_OUT0_N LPDDR_RASn LPDDR_CASn XO2_IN0_1_P XO2_IN2_1_P XO2_IN2_1_N XO2_IN0_1_N LPDDR_BA0_3p3 [8] P8 C11 A13 P13 N12 A9 A10 P11 M8 M9 N10 M11 B9 A11 C9 A12 M7 N8 N9 M10 P12 C10 C12 P9 B13 B12 LPDDR_BA1
PT15B PT16A PT15A PT17B PT16B PT17A PT15C PT16C PT16D PB15B PB18A PB18B PB20A PB15A PB20B PB18D PB15D PB18C PB15C
LPDDR_BA1_1p8 R188 R188 DI DI R182 R182 DI DI
PB20C/SN 820 820 1K 1K LPDDR_BA1_3p3 PT17C/INITN PT17D/DONE [8] PB11A/PCLKT2_1 PB11B/PCLKC2_1 PB20D/SI/SISPI/IO0 PT15D/PROGRAMN
Bank0 Bank2 R177 R177 DI DI
1K 1K
R176 R176 DI DI
1K 1K
VCC18
R178 R178 DI DI
U4A U4C 1K 1K
TDO TDI PB9D PB9B/PCLKC2_0 PT9B PT10B PT11A PT11B PT12A/PCLKT0_1 PT12C/SCL/IO2/PCLKT0_0 TCK PB4D PB6B PB6C/MCLK/CCLK PB11C PB11D PT9A PT10A TMS PB4A PB4C/CSSPIN PB6A PB6D/SO/SPISO/IO1 PT12B/PCLKC0_1 PT12D/SDA/IO3/PCLKC0_0 PB4B PB9C PB9A/PCLKT2_0
LCMXO2-1200-CSBGA132 LCMXO2-1200-CSBGA132
R175 R175 DI DI
B5 B6 P7 A2 A3 A6 P2 P3 A4 B4 P6 B7 B8 B3 A7 P4 N6 C4 C8 N7 N3 N2 N5 C6 N4 M3 M5 M4 1K 1K LVCMOS33 Open Drain LVCMOS33 Voltage Devider MISO LPDDR_RASn LPDDR_CASn LPDDR_CSn LPDDR_WEn XO2_IO_0 SDA PM_IN1 SCL PM_IN2 XO2_IO_1 Interface between LVCMOS33 and LPDDR1.8V XO2_SPI_CLK XO2_TMS XO2_TDI XO2_TCK XO2_IN3_1_N XO2_IN1_1_N XO2_IN3_1_P XO2_IN1_1_P XO2_OUT3_P XO2_OUT2_P XO2_OUT1_P XO2_OUT1_N XO2_OUT2_N XO2_OUT3_N XO2_CLKIN_1_N XO2_CLKOUT_N PM_SMBA_OUT3 XO2_CLKIN_1_P XO2_CLKOUT_P XO2_SPI_CS0 XO2_TDO_PIN 4 4 PM_IN1 PM_IN2 XO2_TDI XO2_TMS XO2_TCK SCL SDA XO2_OUT2_P XO2_OUT1_P XO2_IN1_1_P XO2_OUT3_P XO2_IN3_1_P XO2_OUT1_N XO2_OUT3_N XO2_OUT2_N XO2_IN3_1_N XO2_IN1_1_N XO2_SPI_CS0 XO2_SPI_CLK XO2_SPI_OUT XO2_CLKIN_1_P XO2_CLKOUT_P XO2_CLKOUT_N XO2_CLKIN_1_N XO2_TDO_PIN [9] [9] [9] [6,13] [4,7] [4,7] [8] [9] [4] [11] [11] [11] [4] [11] PM_SMBA_OUT3 [11] [11] [6,7,13] [6,7,13] [7,8] [7,8] [9] [9] [11] [11] [13] [4] MachXO2 Bank 0 MachXO2 Bank 2 C78 3300pF DI DI J9 1 2 3 Jumper_2way LVDS_COMP_N R180 10K R181 10K PWM_FB_Delta_Sigma DI DI XO2_IO_0 XO2_IO_2 XO2_IO_3 XO2_IO_7 XO2_IO_9 XO2_IO_0 XO2_IO_1 XO2_IO_4 XO2_IO_7 XO2_IO_8 XO2_IO_1 XO2_IO_4 XO2_IO_5 XO2_IO_8 XO2_IO_2 XO2_IO_3 XO2_IO_5 XO2_IO_9 XO2_IO_6 XO2_IO_6 DI DI DNI DNI DI DI DI DNI DNI DNI DNI DI DI DNI DI DNI DI DI DI DI DNI DNI 7 4 1 2 2 41R 41R 41R 4 3 62R 31R 51R 4 31R 5 3 2R 5 1 1 1 3R 3R 4R 5 2 1R 4 R R R R R R R R 04 03 08 07 0 03 0 00 09 0 00 05 00 02 02 0 0 08 0 03 R165 0 R166 0 ADC_IN AUDIO_IN IO12 5 5 XO2_GPIO_8 XO2_GPIO_9 XO2_GPIO_3 XO2_GPIO_6 XO2_GPIO_0 XO2_GPIO_1 XO2_GPIO_2 XO2_GPIO_5 XO2_GPIO_7 XO2_GPIO_4 XO2_IN1_2_P XO2_IN1_2_N XO2_IN0_2_N XO2_IN2_2_P XO2_IN2_2_N XO2_IN0_2_P XO2_IN3_2_N XO2_IN3_2_P AUDIO_IN XO2_CLKIN_2_N XO2_CLKIN_2_P XO2_ADC_IN LVDS_COMP_P_VREF R41 10K R53 10K XO2_GPIO_0 XO2_GPIO_7 XO2_GPIO_3 XO2_GPIO_4 XO2_GPIO_5 XO2_GPIO_8 XO2_GPIO_1 XO2_GPIO_2 XO2_GPIO_6 XO2_GPIO_9 XO2_IN2_2_P XO2_IN0_2_P XO2_IN3_2_P XO2_IN1_2_P XO2_IN2_2_N XO2_IN0_2_N XO2_IN1_2_N XO2_IN3_2_N DI DI XO2_CLKIN_2_P XO2_CLKIN_2_N [7] [7] [7] [7] [7] [7] [7] [7] VCCIO33 [7] [7] [10] [10] [10] [10] [10] [10] [10] [10] [10] [10] ADC Delta-Sigma Interface ADC Delta-Sigma Resistor Header Mux between Prototype and Video Channel 2 (7:1LVDS) D C B A
23 MachXO2-1200HC Control Development Kit User Guide
Appendix B. Bill of Materials Table 1. Bill of Materials
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer 1 19 C1, C7, C12, C14, C17, C26, C37, C39, 0_001uF SM_C_0201 C50, C55, C71, C113, C114, C125, C131, C132, C135, C137, C139 2 23 C2, C5, C6, C15, C18, C24, C25, C32, 0_01uF SM_C_0201 C34, C36, C38, C40, C41, C51, C52, C56, C72, C91, C117, C124, C130, C136, C138 3 18 C3, C9, C13, C20, C21, C22, C43, C49, 10uF SM_C_0603 C1608Y5V0J106Z TDK C60, C62, C111, C118, C120, C121, C122, C127, C129, C140 4 2 C4, C11 12pF SM_C_0603 5 32 C8, C10, C16, C19, C42, C44, C45, C46, 0_1uF SM_C_0603 C47, C57, C58, C59, C61, C63, C64, C69, C74, C81, C89, C99, C105, C107, C109, C110, C112, C115, C116, C123, C128, C133, C134, C141 6 2 C23, C29 18pF cc0402 C0402C180K3GACTU Kemet 7 3 C27, C30, C31 0.1uF cc0402 C0402C104K4RACTU Kemet 8 1 C28 10u cc0603 ECJ-1VB0J106M Panasonic 9 4 C33, C106, C142, C143 10uF SM_C_0805 JMK212BJ106KD-T TAIYO YUDEN 10 2 C35, C83 1uF SM_C_0805 11 7 C48, C82, C85, C104, C119, C126, C145 0.1uF cc0402 C0402C104K4RACTU Kemet 12 2 C53, C65 22uF SM_C_0805 LMK212BJ226MG-T TAIYO YUDEN 13 4 C54, C66, C70, C73 10uF SM_C_0805 14 1 C67 10uF SM_C_0603 15 1 C68 0_1uF SM_C_0603 16 13 C75, C76, C77, C79, C80, C84, C90, 0_1uF SM_C_0201 C92, C96, C97, C98, C100, C103 17 1 C78 3300pF SM_C_0603 18 8 C86, C87, C88, C93, C94, C95, C101, 0_1uF SM_C_0201 C102 19 1 C108 0_01uF SM_C_0201 EMK107BJ103K TAIYO YUDEN 20 1 C144 4u7 cc0603 ECJ-1VB0J475K 21 8 D1, D2, D3, D4, D7, D8, D9, D10 LED SM_D_0603 LTST-C190CKT LITE ON 22 2 D5, D6 LED_Green SM_D_0603 LTST-C190KGKT LITE ON 22a 1 D11 LED_Green SM_D_0603 LTST-C190KGKT LITE ON 23 1 D12 LED SM_D_0603 LTST-C190CKT LITE ON 24 15 IO2, IO3, IO4, IO5, IO9, IO10, IO11, IO12, T POINT R TP IO13, IO14, IO16, IO17, IO18, IO19, IO20 25 3 IO7, IO8, IO15 T POINT R TP 26 2 J1, J8 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M 26a 1 J13 (not installed) 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M 27 2 J2, J3 DVI_I DVI_I 74320-1004 Molex 27a 1 J10 (not installed) DVI_I DVI_I 74320-1004 Molex 28 1 J4 CON40A 2x20x100mil TSW-120-07-G-D Samtec 29 1 J5 USB_MINI_B TYPE_B UX60-MB-5ST Hirose 30 1 J6 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc. 30 1 J9 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc. 31 1 J7 XO2 JTAG HD XO2_JTAG_HD 32 1 J11 PWR_JACK PWR_CON RAPC712 Switchcraft 33 1 J12 PHONEJACK SM MJ1-3510-SMT CUI STEREO 34 1 L3 600ohm 500mA FB0603 BLM18AG601SN1D Murata 35 4 MH1, MH2, MH13, MH16 M_HOLE1 IW_MNT0 SJ-5003 (BLACK) 36 4 Q1, Q3, Q6, Q8 BSS138LT1 SOT_23 BSS138LT3G ON Semi 37 2 Q2, Q5 2N7002E SM_SOT23 2N7002ET1G ON_Semi
24 MachXO2-1200HC Control Development Kit User Guide
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer 38 1 Q4 2N2369A 2N2369A_SOT23 MMBT2369A Fairchild 39 1 Q7 ZDT758 SM_8_DUAL_PNP ZDT758 Diodes/Zetex 40 2 RN1, RN4 RN2_4_470 RN2_4_470_0603 TC164-JR-07470RL Yageo 41 1 RN2 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi 42 1 RN3 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi 43 45 R1, R7, R18, R19, R20, R21, R32, R41, 10K SM_R_0402 R43, R44, R45, R46, R47, R53, R73, R81, R94, R97, R115, R116, R117, R118, R119, R120, R121, R123, R124, R125, R126, R127, R128, R132, R151, R158, R159, R163, R164, R180, R181, R200, R233, R236, R239, R242, R244 44 1 R2 1M SM_R_0603 45 48 R3, R5, R8, R10, R11, R15, R16, R24, 0 SM_R_0402 R25, R26, R28, R29, R30, R33, R35, R40, R42, R52, R57, R92, R96, R98, R100, R104, R105, R106, R109, R110, R113, R155, R156, R161, R168, R169, R172, R173, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218 46 5 R4, R67, R195, R196, R232 1K SM_R_0603 47 68 R6, R9, R12, R13, R14, R17, R23, R34, 0 SM_R_0402 R36, R37, R38, R39, R49, R50, R51, R61, R62, R70, R71, R75, R76, R78, R82, R83, R87, R93, R95, R99, R102, R103, R107, R108, R111, R112, R131, R137, R138, R139, R140, R141, R142, R143, R144, R152, R153, R154, R157, R165, R166, R167, R170, R171, R174, R186, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R247, R248 48 7 R22, R48, R101, R237, R243, R245, 10K SM_R_0402 R246 49 4 R27, R64, R114, R122 470 SM_R_0603 ERJ-3EKF4700V Panasonic ECG 50 1 R31 510, 1% SM_R_0603 51 9 R54, R55, R65, R66, R84, R85, R88, 4_7K SM_R_0603 R89, R205 52 1 R56 2k2 cr0402 TNPW04022K20BEED Vishay/Dale 53 1 R58 (not installed) 0 SM_R_0805 54 1 R59 1 SM_R_0805 55 2 R60, R219 220 SM_R_0603 56 2 R63, R68 0 SM_R_0603 57 3 R69, R187, R188 820 SM_R_0402 58 8 R74, R175, R176, R177, R178, R182, 1K SM_R_0402 R183, R240 59 1 R79 100K SM_R_0603 60 2 R80, R86 68 SM_R_0402 61 2 R90, R91 4_7K SM_R_0402 62 5 R129, R130, R133, R134, R135 100 SM_R_0603 63 8 R136, R146, R184, R185, R191, R194, 100 SM_R_0603 R201, R206 64 1 R145 330 SM_R_0603 65 1 R147 2_2K SM_R_0603 66 2 R148, R235 2 SM_R_0805 67 2 R149, R162 1000K SM_R_0603 68 1 R150 10K SM_R_0603 69 1 R160 680K SM_R_0603 70 2 R179, R198 200 SM_R_0603 71 4 R189, R190, R192, R193 3_92K SM_R_0603 72 2 R197, R204 2K SM_R_0603
25 MachXO2-1200HC Control Development Kit User Guide
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer 73 1 R199 12k cr0402 RC0402FR-0712KL Yageo 74 4 R202, R203, R241, R249 10k cr0402 RC0402FR-0710KL Yageo 75 0 R240 2k2 cr0402 RC0402FR-072K2L Yageo 76 1 SW1 SWDIP_4 SMD_8check 3-5435640-5 Tyco 77 1 SW2 SW DIP_2 SP_75 195-2MST CTS 78 1 S1 XO2 Global Reset SMT_SW EVQ-Q2K03W Panasonic 79 1 U1 microSD Socket SM_SD 460DE08C3 MULTICOMP 80 1 U2 TFP401A HTQFP_100 TFP401APZPG4 TI 80 1 U9 (not installed) TFP401A HTQFP_100 TFP401APZPG4 TI 81 1 U3 TFP410 HTQFP_64 TFP410PAP TI 82 1 U4 LCMXO2-1200HC- CSBGA132 LCMXO2-1200HC- Lattice Semi CSBGA132 CSBGA132 83 1 U5 STG3693QTR QFN STG3693QTR STMicro- electronics 84 1 U6 MT46H16M16LFBF SM/60VFBGA MT46H16M16LFBF Micron 85 1 U7 ispPAC-POWR1014A TQFP_48 ispPAC-POWR1014A- Lattice 01TN48I 86 1 U8 CMA-4544PF-W 2 Solder Pins (TH) CMA-4544PF-W CUI Inc 87 1 U10 DS90CR288A TSSOP_56 DS90CR288AMTD/NOP National B Semi 88 1 U11 NCP1117ST33 SOT_223 NCP1117ST33T3G ONSemi 89 1 U12 NCP1117ST18 SOT_223 NCP1117ST18T3G ONSemi 90 1 U13 MCP6L71R SOT_23_5_MC MCP6L71RT-E/OT Microchip 91 1 U14 AT25DF041A-SH-B SOIC8 AT25DF041A-SH-B Atmel 92 1 U15 AT25DF041A-MH-B UDFN AT25DF041A-MH-B Atmel 93 1 U16 AD8604ARZ 14_SOIC AD8604ARZ Analog Devices 95 1 U17 (not installed) Value MRA08A_M LP3879MR-1.2 National 96 1 U18 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI 96 1 U19 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI 97 1 U20 FT2232HL tqfp64_0p5_12p2x12 FT2232HL FTDI p2_h1p6 98 1 U21 93LC56-SO8 so8_50_244 93LC56T-I/SN Microchip 99 1 X1 (not installed) CTS-CB3LV-3C-25MHz SMD 7.00mm x CB3LV-3C-25M0000 CTS 5.00mm 100 1 X2 HCM49 24.000MABJ-UT SMD HCM49 24.000MABJ-UT Citizen Finetech 101 1 X3 12 MHZ crystal_4p_3p2x2p5 7M-12.000MAAJ-T TXC CORP 102 1 XO2_Control_board_RevE_PCB 305-PD-11-XXX
26 MachXO2-1200HC Control Development Kit User Guide
Appendix C. Limitations • It is recommended to have a 1 kOhm pull up on MachXO2 pin MCLK (signal XO2_SPI_CLK)
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