Framework for Simulation of the Verilog/SPICE Mixed Model: Interoperation of Verilog and SPICE Simulators Using HLA/RTI for Model Reusability

Framework for Simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability

Moon Gi Seok∗, Dae Jin Park, Geun Rae Cho, Tag Gon Kim† Department of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) 373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea Email:[email protected]∗, [email protected]†

Abstract—Designing a mixed-signal integrated hardware re- Verilog Procedural quires the mixed simulation for legacy digital blocks and analog Interface (VPI) circuits, which are usually represented by the Verilog descrip- Verilog SPICE SPICE Procedural Interface (SPI) tion language for digital blocks and the SPICE circuit netlist Model Model VPI Adaptor Module of analog circuits. Without model translations or source-level ` ` SPI Adaptor Module modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based Verilog SPICE on the different SPICE languages, parameters and primitives, Simulator Simulator this paper proposes a simulation framework whose concept is Discrete Event Digital Signal Continuous ` Analog Signal connecting a legacy Verilog and proper SPICE simulator for Time Time the target SPICE model using a run-time infrastructure (RTI) FOM based on high level architecture (HLA) and adapters that are Adaptor Adaptor Discrete Event Discrete Event ` Event ` Event ` of simulators through HLA. For the interoperation, to exchange Time Time HLA/RTI analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, Fig. 1: Overall proposed Verilog/SPICE mixed model signal-event converters. To synchronize different time advance Simulation Framework policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and are based on different versions of the SPICE language, the set IEEE-std HLA interface. The proposed framework was applied of component primitives, parameters and so on [1], [2]. to the digitally controlled buck converter simulation. Without model translation, to reuse Verilog models and I.INTRODUCTION various SPICE models that are are dependent on target SPICE simulator, this paper proposes a mixed-signal simulation Verilog and SPICE have long performed the design of the framework that reuses a Verilog simulator and a target SPICE analog and digital circuit, respectively. As such, there is a simulator by connecting them with the run-time infrastructure huge legacy of SPICE circuit netlists (models) and Verilog (RTI) [3] as shown in Fig 1. The RTI is implemented event- models. The fast design and implementation of a mixed-signal based middleware that is based on the high-level architecture circuit, which consists of analog and digital blocks, requires (HLA) [3], which is the standard modeling and simulation a combined legacy Verilog-SPICE model or a customized architecture defined under IEEE std 1516-2010 and provides Verilog-SPICE mixed model based on legacy models. HLA service interfaces for time management and data ex- To simulate the Verilog-SPICE mixed models, there are change among joined simulators. For the inter-operation and several typical approaches, which includes simulating single- integration of a Verilog and a SPICE simulator with RTI, an type SPICE or Verilog models after translation, simulating adapter is proposed, which is a library as pluggable agent. For Verilog-AMS models after the behavior-level conversion of the interoperation, the adapter converts digital/analog signals SPICE parts, and simulating the mixed models with a Verilog- to events or reversely based on user-defined signal-event con- AMS simulator that supports referencing SPICE models. The verters to exchange the different types of digital/analog signals approach of model translation and conversion has the dis- through RTI. The adapter also performs time synchronization advantages of translation overheads and a low translation procedures based on the pre-simulation concept [4] to resolve compatibility from the SPICE model to the Verilog model. The the different time advance policies between the discrete-event- other approach has the disadvantage of no or low compatibility based Verilog simulator and the continuous-time-based SPICE when referencing SPICE models because referencing SPICE simulator. For the integration, the adapter provides modules models is optional and not standardized since SPICE models that are based on the Verilog/SPICE procedural interfaces and perform internal interoperations between adapters based on support SPI, but legacy Verilog simulators that support VPI HLA interfaces. The Verilog procedural interface (VPI) is one can be utilized without modifications. of the Verilog standard programming interfaces that is defined in IEEE std 1364-2005 [5], and the SPICE procedural interface Interoperation methods using RTI between a discrete event (SPI) is the proposed SPICE external interface to access and simulator and continuous-time simulator are researched in modify the model data and control simulation flows. The [4], [11]. Those researches proposed the HDEVSimHLA or coupling information between the Verilog and SPICE model is adapter for data conversion and time synchronization between described in federate object model (FOM). Following proposed different-type simulators. The proposed framework utilizes the frameworks, various combined legacy Verilog/SPICE models adapter concept to integrate simulators and RTI, but shows can be simulated utilizing various Verilog simulators and SPI- specific integration and time synchronization procedures based supported SPICE simulators as changing model-dependent on the HLA1516-2005 interface, VPI, and SPI. In previous signal-event converters signal converters and FOM. research, the continuous signals are converted into events by the one-side adapter for a continuous simulator, but in the The rest of the paper is organized as follows: Section II proposed framework, adapters for both Verilog and SPICE sim- presents several related works with the Verilog-SPICE simu- ulator perform digital/analog signal-event conversion to apply lation. Section III describes the overall simulation framework delay and rising/falling time to both digital/analog signals. The and its simulation method. Section IV applies the proposed proposed framework also provides hierarchical FOM modules simulation framework to design a digitally controlled buck for the convenient description of coupling information of the converter. Section V will conclude the paper. target mixed models.

II.RELATED WORK

In recent years, some efforts have been made to translate III.VERILOG/SPICESIMULATIONFRAMEWORKUSING the Verilog or SPICE model to the other-type model for RTI type matching. These studies have the advantages of reusing a legacy Verilog or SPICE simulator and the translation As shown in Fig. 1, the proposed simulation framework compatibility is high from Verilog models to circuit-level consists of a Verilog/SPICE simulator, RTI, the adapter, and SPICE models after synthesis of Verilog model [6]. However, the federate object model (FOM) [3], [12] which describes simulating translated overall SPICE models demands large publishing or subscribing signal interaction (event) classes amounts of simulation time, and transition compatibility from for coupling information between the Verilog and the SPICE SPICE models to Verilog models is low because Verilog is model. a high-level description language [7], [8]. In addition, some efforts enable the Verilog-SPICE mixed model to be simulated The adapter is a library for the interoperation and in- by a Verilog-AMS simulator after converting SPICE parts into tegration of Verilog/SPICE simulators through RTI. For the the behavior-level Verilog-A models, but the conversion work interoperation, digital/analog signal-event conversions and time is done manually and the converted models can be low-fidelity synchronization procedures are described in III-A and III-B. models. These translation or conversion approaches cause high For the integration, the adapter provides the VPI and SPI overhead when the mixed models are frequently changed. adapter modules, and specific procedures of Verilog/SPICE simulators with VPI and SPI modules are described in III-C Some Verilog-AMS simulators have been tried to simu- and III-D. For the convenient description of coupling informa- late the Verilog-SPICE mixed model by enabling referencing tion between the Verilog and SPICE model, the hierarchical SPICE model optionally. From the perspective of reusing the FOM modules for the mixed-signal simulation are proposed in legacy SPICE models, the compatibility of referencing various III-E. SPICE models is low or not possible because Verilog-AMS referencing SPICE models is not standard and SPICE models are implemented based on the different versions of the SPICE language, the set of component primitives, parameters, and so A. Signal-Event Conversion in the adapter on. The problem of referencing the SPICE model in Verilog- AMS model is well specified in [1]. The signal-event conversion in the adapter exchanges digital/analog signals through RTI, which is the event-driven Some studies have been conducted on the distributed middleware, and events are transferred in the HLA interaction simulation of multiple discrete-event Verilog and continuous- form. How signals and events are converted into each other is time SPICE simulators using a combined optimistic and con- computed in the user-implemented converter, which consists servative synchronization method with an ad-hoc connection of the following conversion functions: [9], [10]. This research focused on maximizing concurrency of the distributed simulation to avoid the idleness of multiple DE Convert: Digital signal to event conversion function, computing resources and needs the modifications of both IP × SD → ED Verilog and SPICE simulators to exchanging data, handle ED Convert: Event to digital signal conversion function, events, and rollback procedures. On the contrary, the proposed EA → IS × SD framework focused on reusing legacy models, and systematic AE Convert: Analog signal to event conversion function, integration of simulators and RTI using the standard and pro- IP × SA → EA posed interfaces rather than the ad-hoc approach. The proposed EA Convert: Event to analog signal conversion function, framework needs the extension of the SPICE simulator to ED → IS × SA where: For pre-simulation based time synchronization, the adapter IP : set of publishing instances in model provides the functions for the Verilog and SPICE simulator to instance = get and inform current or next event time, as shown Table I. IS: set of subscribing instances in model SD: set of discrete time signal (DTS), DTS = TABLE I: Adapter Functions for Time Synchronization SA: set of piecewise continuous-time signal (PCTS), PCTS = Function Description ED: set of digital signal events setVerilogNextEvTime Function for Verilog simulator to inform SPICE simulator of the next Verilog event time EA: set of analog signal events getVerilogNextEvTime Function for SPICE simulator to receive next Verilog event time getNextGlobalEvTime Function for Verilog simulator to get next global event time from RTI Verilog Simulator SPICE Simulator Signal to Adaptor setCurSPICETime Function for SPICE simulator to inform RTI of SPICE RTL: current time, which is the minimum of next Verilog V Signal from Ve-Pub Ve-Pub ... Adaptor event time and SPICE event time t RTL: e Analog Signal a Event SP-Pub V ed Digital Signal Using the provided functions, overall time synchronization SP-Pub ... Event and signal exchange procedures are as shown in Fig. 3. clk t t t t t t Time t t t t t Time 1 2 3 4 5 1 2 3 4 5 Signal-Event :Verilog Simulator Tv_cur : Verilog Current Time Ts_cur : SPICE Current Time Digital Signal Analog Signal Converters ` ` Tv_nev : Verilog Next event Time Ts_ev : SPICE Event Time Verilog Adaptor SPICE Adaptor ... :Verilog :SPICE :SPICE :RTI ev@T ev@Tv_nev Adaptor Adaptor Simulator DE_Convert:Ve-Pub × ퟏ(풕ퟐ) → 풆풅(t2) EA_Convert: 퐞풅 풕ퟐ → Ve−Pub × 퐕Ve−Pub[풕ퟐ, 풕ퟑ) v_cur Process × V [풕 , 풕 ] → 풆 getVerilogNextEvTime() ED_Convert: 풆퐚(풕ퟒ) → SP-Pub× 1(풕ퟓ) AE_Convert: SP-Pub SP−Pub ퟑ ퟒ 퐚(t4) exchange- Events@ T able v_cur ` Event (Interaction) ` Event (Interaction) alt [Digital Signal Value Changed] RTI DE_Convert send(ED) recv(E ) Global Simulation time: t1, t2, t3, t4, t5 ... D

setVerilogNextEvTime send(Tv_nev) recv(T ) v_nev Tv_nev Fig. 2: Analog/Digital Signal Conversion in the adapter (Tv_nev) EA_Convert getNextGlobalEvTime NMRA(Tv_nev) (Tv_nev) Analog Signal Compute numerical alt AE_Convert If digital signals of publishing model instances are changed [Analog Signals meets defined thresholds] integration or analog signals of model instances meet the defined thresh- send(ES) until min(T setCurSPICETime v_nev old, the signals are converted into events based on the defined TARA(Ts_cur) and Ts_ev) (Ts_cur) conversion functions and are transfered to the adapter of the alt SPICE event is sent from SPICE adaptor other simulator. The receiving adapter converts events into recv(ES) Grant Time Grant Time digital/analog signals as shown in Fig. 2. The rising/falling Grant Time time and delay information can be contained in the event ED_Convert min(Tv_nev , Ts_ev) which is specified in the FOM, so timing information can Digital Signal be contained in the sending and receiving side. In the user- implemented signal-event converters, obtaining and reflecting send Send Interaction NMRA Next Message Request Available digital signal values are conducted using VPI value processing recv Recv Interaction TARA Time Advance Request Available functions like vpi get value and vpi put value functions, and obtaining and reflecting analog signal values are conducted Fig. 3: Time Synchronization and Signal Exchange using SPI value processing functions like spi get value and Procedures spi put value. To get the NVevT, the the SPICE simulator calls B. Time Synchronization Procedure in the adapter getVerilogNextEvTime and waits for the NVevT until the Verilog simulator calls setVerilogNextEvTime. For adaptors, In the time advance perspective, the Verilog simulation NVevT and signal events are transferred using sendInterac- time advances discretely based on the timestamp of events, tion/receiveInteraction HLA APIs. After calling setVerilogNex- but the SPICE simulation time advances continuously based tEvTime and getNextGlobalEvTime, the Verilog simulator waits on the continuous solver. To resolve the different time ad- to get the next global event time from the RTI, which is the vance policies of the Verilog/SPICE simulator, the adapter minimum timestamp between the next Verilog event and the performs a time synchronization procedure based on the pre- SPICE event time. Internally, getNextGlobalEvTime utilizes simulation concept [4], which advances global simulation time the nextMessageRequestAvailable (NMRA) HLA API. After to the minimum timestamps of future Verilog/SPICE events. the SPICE simulator receives NVevT, it executes numerical To obtain future SPICE events, the SPICE model is simulated integration routines to update its simulation time until the through the minimum timestamp of Verilog future events, minimum period of NVevT and SPICE event time. After which is called the next Verilog event time (NVevT). If a the SPICE simulator executes integration routines, the SPICE SPICE event is generated during the simulation, the global simulator calls the setCurSPICETime to inform RTI. Then, simulation time advances the SPICE event time; and, if not, these time synchronization and signal exchange procedures are the global simulation time advances to the NVevT. repeated during simulation. Verilog Simulator VPI Adaptor Module Adaptor SPICE Simulator SPI Adaptor Module Adaptor Iterative Numerical Integration Event ... tcur tv_nev SPI_TSync List VPI_RegisterTSync ... Register 훿 훿’ events@Tv_cur events@Tv_nev Call GetNextEvTime Verilog Next VPI_TSyncSUbSigCB Tcur : SPICE Current Simulation Time T : Verilog Current Simulation Time T : SPICE Event Time Event Time v_cur at the current time s_ev Tv_nev : Verilog next event time Tv_nev : Verilog Next Event Time [Tcur == SPI_TSync scheduled time] Tv_nev ← Verilog Next Event Time Call Ts_ev ← ∞ VPI_RegisterTSync VPI_PubSignalCB Call SPI_SubSignalCB SPI_SubSignalCB Process events@T Verilog v_cur Call DE_Convet Verilog Event Call EA_Convet [Publishing signal Compute Numerical Event value is changed] Integration 훿 훿 VPI_TSyncSubSigCB (Tcur ← Tcur + ’, ’ ≤ Tv_nev-Tcur, ) SPI_PubSignalCB Verilog Next SPICE Call VPI_PubSignalCB call SetNextEvTime Event Time Call AE_Convet Call SPI_PubSignalCB Event [SPICE Event call GetNextEvTime Re-Compute Numerical Generated] SPICE Ts_ev ← Call VPI_TSyncSubSigCB Global Next Integration (Tcur ← Ts_ev) Event Time Event Time [Tcur = Tv_nev] call ED_Convert [SPICE Event Generated & Ts_ev < Tcur] Register T ← Next event time v_cur SPICE SPI_TSync@min(Ts_ev , Tv_nev) Global Register Event Event Time VPI_RegisterTSync Call SetSPICEEvTime

(a) Verilog Simulator-VPI adapter Module Overall Procedures (b) SPICE Simulator-SPI adapter Module Overall Procedures

Fig. 4: Simulators-VPI/SPI adapter Module Procedures for Interoperation

C. Verilog Simulator and VPI adapter Module event time, VPI TSyncSubSigCB registers VPI RegisterTSync to be called at next event time, and when VPI RegisterTSync Verilog provides the IEEE std 1364-2005 Verilog program- is called at the next event time, VPI RegisterCB registers ming language interface (PLI) to invoke a C language function VPI TSyncSubSigCB to be called after processing next events. during Verilog simulation. The adapter provides a module The repeat registrations for time synchronization and signal- to plug itself into the Verilog simulator and the module is event conversion are shown in Fig. 4(a). developed following the Verilog procedural interface (VPI) which is one of the Verilog PLI. The module is called a VPI adapter module and provides the $VPI ADPInitialize and D. SPICE Simulator and SPI adapter Module $VPI ADPEnd tasks. There is no standard external interface for SPICE similar to the Verilog PLI. To replace SPICE simulators based on $VPI ADPInitialize leads the adapter to perform initial various SPICE models to interoperate with the Verilog sim- processes for the HLA simulation and register three call- ulator through RTI, it needs to define an external interface of back functions for the interoperation, as shown TABLE II. SPICE simulators to access and modify analog signals and $VPI ADPEnd leads the adapter to perform processes to finish control simulation flow. The proposed simulation framework the HLA-based simulation. recommends the external interface, which is named the SPICE procedural interface (SPI) after VPI. The SPI provides the TABLE II: VPI Callback Functions for Interoperation following basic callback types to implement callback functions as below. Callback Name Callback Type(Description) VPI RegisterTSync cbNextSimTime(Callback shall occur before processing events@[next event time]) TABLE III: SPI Callback Types VPI PubSignalCB cbValueChange(Callback shall occur when the value of publishing net/wire is changed) Callback Type Name Description VPI TSyncSubSigCB cbReadOnlySynch(Callback shall occur after cbBeforeSimStart callback shall occur before the start of the processing events@[current time]) simulation cbBeforeSimScheduled callback shall occur before the execution of numerical integration routine at the scheduled The $VPI ADPInitialize registers VPI PubSignalCB to time cbBeforeSimInteration callback shall occur before every execution send digital signal events whenever values of publishing of the numerical integration routine net/wire are changed. Interactions for digital signal events are cbAfterSimIteration callback shall occur after every execution of described in the model-specific FOM modules. To perform the numerical integration routine cbAfterSimEnd callback shall occur after the end of the the time synchronization and reflect SPICE signal events as simulation described in section III-B, $VPI ADPInitialize initially registers VPI TSyncSubSigCB to be called after processing current Verilog events. To invoke VPI TSyncSubSigCB at the next Based on the SPI callback types, SPI adapter module provides callback functions as shown in TABLE IV to be and publishing node and subscribing voltage source for the pluggable into the SPICE simulator and registered before the SPICE model. These FOM modules are essential for the RTI SPICE simulation. before running the simulation, and the information in the model-specific FOM module are utilized by the adapter to perform initial HLA services like publishing or subscribing TABLE IV: SPI Callback Functions for Interoperation interaction classes and obtains the names of the coupling port in the VPI/SPI adapter modules and signal-event converters. Callback Name Callback Type SPI ADPInitialize cbBeforeSimStart SPI TSync cbBeforeSimScheduled IV. EXPERIMENTATION SPI SubSignalCB cbBeforeSimIteration SPI PubSignalCB cbAfterSimIteration The proposed framework is applied to a digitally controlled SPI ADPEnd cbAfterSimEnd buck converter [13] simulation. The digitally-controlled buck converter consists of a digital controller, plant, A/D converter and digital pulse width modulation (PWM). In this paper, the After registration of the callback functions of the SPI components of the buck converter are modeled as shown in adapter module, the signal-event conversion and time synchro- Fig 6. nization procedures of the callback functions are shown in Fig. 4(b). u[k] = u[k-1]+K1e[k]+k2e[k-1]+k3e[k-2] V E. FOM and Coupling Relation dd PWM The federate object model (FOM) describes the publihsing V L 93.5UH ref V or subscribing signal interactions (event) classes of the Verilog (2.7v) Digital out and SPICE models. In IEEE1516-2010 [3], the XML-based Controller C FOM [12] is introduced, and the FOM can be constructed (PID controller) RL 100UF 33.5K by aggregating FOM modules to improve the reusability and development efficiency. Using the modular FOM concept, the A/D Converter proposed simulation framework utilizes two FOM modules composed of the reusable base FOM module and the model- specific FOM module, as shown Fig. 5. Fig. 6: Verilog/SPICE model of a Digital-Controlled Buck Converter ...... CILS HLAinteractionRoot The digital controller is modeled as a Verilog model and the BaseFOM.xml Vcntl Vout BuckConverter.xml plant is modeled as a SPICE model. The switching frequency DSE of the digital controller is 60kHz. The A/D converter, which Vcntl 8 ... converts analog voltage into 256(2 ) discrete levels, and digital DigitalController PWM are modeled as the S-E converters and perform the Publishing and Publishing Node, ASE Plant conversion between signal and event as Fig. 7. Subscribing Subscribing net/wire Voltage Source Vout ...... … Event Model-specific FallingTime SPICE simulator SPICE Simulator FOM Module HLAfloat64BE Signal HLAinteractionRoot V Neither HLAreliable Value Base FOM Module TimeStamp HLAfloat64BE ASE PublishSubscribe … DSE t TimeStamp ... PWM A-D Converter RisingTime VNevT V ...... ref - - - - Verilog simulator Fig. 5: Modular FOM and Coupling Definition

Verilog simulator The base FOM module contains general information for t the HLA-based simulation and interaction class for the analog signal event (ASE), digital signal event (DSE), and NVevT. Fig. 7: Signal-Event Conversion in A-D Converter and PWM Based on the ASE and DSE interaction class, analog and digital signal events contain the rising/falling time as well as The utilized Verilog simulator for the experiment is Ca- a value information on the sending-side. The model-specific dence NCSim, and the SPICE simulator is extended from the FOM module contains model-specific interaction classes which open-source based NGSPICE 2.5 [14] to support SPI. The are inherited class from the ASE, DSE base classes and utilized RTI is Pitch RTI 4.0 [15]. simulation options like a federation name and federates name. The model-specific interaction classes represent the name of Using the proposed simulation framework, the transient the publishing or subscribing net/wire for the Verilog model response of the SPICE model and pulse-width computation of REFERENCES SPICE Simulator [1] D. Potop-Butucaru, C. Lallement, and A. Vachoux, “VHDL-AMS SPICE Plant -> and Verilog-AMS as alternative hardware description languages for Verilog efficient modeling of multidiscipline systems,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, no. 2, pp. 204–225, Feb 2005. Adapter Verilog [2] Accellera, “Verilog-AMS Language Reference Manual.” A/D -> Converter SPICE [3] “IEEE Standard for Modeling and Simulation (M&S) High Level ` Architecture (HLA)– Framework and Rules,” IEEE Std 1516-2010 ` RTI (Revision of IEEE Std 1516-2000), Aug 2010. [4] C. Sung and T. G. Kim, “Framework for simulation of hybrid systems: PWM <300us~800us> Interoperation of discrete event and continuous simulators using hla/rti,” Adapter in Principles of Advanced and Distributed Simulation (PADS), 2011 IEEE Workshop on, June 2011, pp. 1–8. SPICE -> Verilog [5] “IEEE Standard for Verilog Hardware Description Language,” IEEE Std Digital Controller 1364-2005 (Revision of IEEE Std 1364-2001), 2006. Verilog Simulator Verilog -> SPICE [6] A. Lalchandani and N. Lam, “Circuit level netlist generation,” Jan. 24 1995, uS Patent 5,384,710. [Online]. Available: http://www.google.com/patents/US5384710 [7] K. J. Singh and P. A. Subrahmanyam, “Extracting rtl models from Fig. 8: Verilog/SPICE Model Simulation Result transistor netlists,” in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, Nov 1995, pp. 11–17. [8] R. Bryant, “Extraction of gate level models from transistor circuits the Verilog model are shown in Fig. 8. Using the framework, by four-valued symbolic analysis,” in Computer-Aided Design, 1991. SPICE models that on the NGSPICE simulator and any Verilog ICCAD-91. Digest of Technical Papers., 1991 IEEE International model can be interoperated with additional user-defined S- Conference on, Nov 1991, pp. 350–353. E converters without the source-level modification. If other [9] D. Lungeanu and C. Shi, “Distributed event-driven simulation of SPICE simulators are extended to support the SPI, any legacy VHDL-SPICE mixed-signal circuits,” in Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on, 2001, pp. 302– SPICE model dependent on those extended SPICE simulators 307. can be interoperated with any Verilog model. [10] D. Lungeanu and C.-J. Shi, “Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchro- V. CONCLUSION nization,” in Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on, Nov 1999, pp. 500–504. This paper proposes a simulation framework for the mixed [11] S. Y. Lim and T. G. Kim, “Hybrid Modeling and Simulation Methodol- Verilog/SPICE model using the RTI. To reuse the Verilog and ogy based on DEVS formalism,” in SUMMER COMPUTER SIMULA- various SPICE models that are described based on the different TION CONFERENCE. Society for Computer Simulation International; SPICE language, primitives and parameters, the proposed sim- 1998, 2001, pp. 188–193. ulation framework follows the concept,which reuses a Verilog [12] W. Wenguang, X. Yongpinq, C. Xin, L. Qun, and W. Weiping, “High level architecture evolved modular federation object model,” Systems simulator and a target SPICE simulator and connects them Engineering and Electronics, Journal of, vol. 20, no. 3, pp. 625–635, using RTI and adapters. Adapters enable those simulators to June 2009. interoperate with the other simulator and integrate with the [13] A. Prodic and D. Maksimovic, “Mixed-signal simulation of digitally RTI. For interoperation, adapters convert digital or analog controlled switching converters,” in Computers in Power Electronics, signals to events or are reversely based on the user-defined con- 2002. Proceedings. 2002 IEEE Workshop on, June 2002, pp. 100–105. version functions, and perform time-synchronizing procedures [14] “Ngspice circuit simulator.” [Online]. Available: http://www.ngspice.org based on the pre-simulation concept. For integration, adapters [15] “Pitch technologies.” [Online]. Available: http://www.pitch.se/prti provide modules to be plugged into the simulator and the modules are designed based on the VPI, HLA compliant with the IEEE standard, and SPI that is proposed in this paper. The coupling information between the Verilog and SPICE models are described in the hierarchical FOM modules that consist of the base FOM module and model-specific FOM module to reuse the base FOM module. Using the simulation framework, various Verilog-SPICE mixed models can be simulated as changing model-dependent signal-event converters, the model- specific FOM and target SPICE simulator that supports the SPI. The framework was applied to the digitally-controlled buck converter experiment to demonstrate the interoperation of the Verilog-SPICE mixed model.

ACKNOWLEDGEMENT This work was supported by Defense Acquisition Program Administration and Agency for Defense Development under the contract UD140022PD, Korea.