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Framework for Simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability Moon Gi Seok∗, Dae Jin Park, Geun Rae Cho, Tag Gon Kimy Department of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) 373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea Email:[email protected]∗, [email protected] Abstract—Designing a mixed-signal integrated hardware re- <Mixed Verilog/SPICE Model> Verilog Procedural quires the mixed simulation for legacy digital blocks and analog Interface (VPI) circuits, which are usually represented by the Verilog descrip- Verilog SPICE SPICE Procedural Interface (SPI) tion language for digital blocks and the SPICE circuit netlist Model Model VPI Adaptor Module of analog circuits. Without model translations or source-level ` ` SPI Adaptor Module modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based Verilog SPICE on the different SPICE languages, parameters and primitives, Simulator Simulator this paper proposes a simulation framework whose concept is Discrete Event Digital Signal Continuous ` Analog Signal connecting a legacy Verilog and proper SPICE simulator for Time Time the target SPICE model using a run-time infrastructure (RTI) FOM based on high level architecture (HLA) and adapters that are Adaptor Adaptor <Verilog-SPICE pluggable libraries to enable the interoperation and integration Coupling Information> Discrete Event Discrete Event ` Event ` Event ` of simulators through HLA. For the interoperation, to exchange Time Time HLA/RTI analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, Fig. 1: Overall proposed Verilog/SPICE mixed model signal-event converters. To synchronize different time advance Simulation Framework policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and are based on different versions of the SPICE language, the set IEEE-std HLA interface. The proposed framework was applied of component primitives, parameters and so on [1], [2]. to the digitally controlled buck converter simulation. Without model translation, to reuse Verilog models and I. INTRODUCTION various SPICE models that are are dependent on target SPICE simulator, this paper proposes a mixed-signal simulation Verilog and SPICE have long performed the design of the framework that reuses a Verilog simulator and a target SPICE analog and digital circuit, respectively. As such, there is a simulator by connecting them with the run-time infrastructure huge legacy of SPICE circuit netlists (models) and Verilog (RTI) [3] as shown in Fig 1. The RTI is implemented event- models. The fast design and implementation of a mixed-signal based middleware that is based on the high-level architecture circuit, which consists of analog and digital blocks, requires (HLA) [3], which is the standard modeling and simulation a combined legacy Verilog-SPICE model or a customized architecture defined under IEEE std 1516-2010 and provides Verilog-SPICE mixed model based on legacy models. HLA service interfaces for time management and data ex- To simulate the Verilog-SPICE mixed models, there are change among joined simulators. For the inter-operation and several typical approaches, which includes simulating single- integration of a Verilog and a SPICE simulator with RTI, an type SPICE or Verilog models after translation, simulating adapter is proposed, which is a library as pluggable agent. For Verilog-AMS models after the behavior-level conversion of the interoperation, the adapter converts digital/analog signals SPICE parts, and simulating the mixed models with a Verilog- to events or reversely based on user-defined signal-event con- AMS simulator that supports referencing SPICE models. The verters to exchange the different types of digital/analog signals approach of model translation and conversion has the dis- through RTI. The adapter also performs time synchronization advantages of translation overheads and a low translation procedures based on the pre-simulation concept [4] to resolve compatibility from the SPICE model to the Verilog model. The the different time advance policies between the discrete-event- other approach has the disadvantage of no or low compatibility based Verilog simulator and the continuous-time-based SPICE when referencing SPICE models because referencing SPICE simulator. For the integration, the adapter provides modules models is optional and not standardized since SPICE models that are based on the Verilog/SPICE procedural interfaces and perform internal interoperations between adapters based on support SPI, but legacy Verilog simulators that support VPI HLA interfaces. The Verilog procedural interface (VPI) is one can be utilized without modifications. of the Verilog standard programming interfaces that is defined in IEEE std 1364-2005 [5], and the SPICE procedural interface Interoperation methods using RTI between a discrete event (SPI) is the proposed SPICE external interface to access and simulator and continuous-time simulator are researched in modify the model data and control simulation flows. The [4], [11]. Those researches proposed the HDEVSimHLA or coupling information between the Verilog and SPICE model is adapter for data conversion and time synchronization between described in federate object model (FOM). Following proposed different-type simulators. The proposed framework utilizes the frameworks, various combined legacy Verilog/SPICE models adapter concept to integrate simulators and RTI, but shows can be simulated utilizing various Verilog simulators and SPI- specific integration and time synchronization procedures based supported SPICE simulators as changing model-dependent on the HLA1516-2005 interface, VPI, and SPI. In previous signal-event converters signal converters and FOM. research, the continuous signals are converted into events by the one-side adapter for a continuous simulator, but in the The rest of the paper is organized as follows: Section II proposed framework, adapters for both Verilog and SPICE sim- presents several related works with the Verilog-SPICE simu- ulator perform digital/analog signal-event conversion to apply lation. Section III describes the overall simulation framework delay and rising/falling time to both digital/analog signals. The and its simulation method. Section IV applies the proposed proposed framework also provides hierarchical FOM modules simulation framework to design a digitally controlled buck for the convenient description of coupling information of the converter. Section V will conclude the paper. target mixed models. II. RELATED WORK In recent years, some efforts have been made to translate III. VERILOG/SPICE SIMULATION FRAMEWORK USING the Verilog or SPICE model to the other-type model for RTI type matching. These studies have the advantages of reusing a legacy Verilog or SPICE simulator and the translation As shown in Fig. 1, the proposed simulation framework compatibility is high from Verilog models to circuit-level consists of a Verilog/SPICE simulator, RTI, the adapter, and SPICE models after synthesis of Verilog model [6]. However, the federate object model (FOM) [3], [12] which describes simulating translated overall SPICE models demands large publishing or subscribing signal interaction (event) classes amounts of simulation time, and transition compatibility from for coupling information between the Verilog and the SPICE SPICE models to Verilog models is low because Verilog is model. a high-level description language [7], [8]. In addition, some efforts enable the Verilog-SPICE mixed model to be simulated The adapter is a library for the interoperation and in- by a Verilog-AMS simulator after converting SPICE parts into tegration of Verilog/SPICE simulators through RTI. For the the behavior-level Verilog-A models, but the conversion work interoperation, digital/analog signal-event conversions and time is done manually and the converted models can be low-fidelity synchronization procedures are described in III-A and III-B. models. These translation or conversion approaches cause high For the integration, the adapter provides the VPI and SPI overhead when the mixed models are frequently changed. adapter modules, and specific procedures of Verilog/SPICE simulators with VPI and SPI modules are described in III-C Some Verilog-AMS simulators have been tried to simu- and III-D. For the convenient description of coupling informa- late the Verilog-SPICE mixed model by enabling referencing tion between the Verilog and SPICE model, the hierarchical SPICE model optionally. From the perspective of reusing the FOM modules for the mixed-signal simulation are proposed in legacy SPICE models, the compatibility of referencing various III-E. SPICE models is low or not possible because Verilog-AMS referencing SPICE models is not standard and SPICE models are implemented based on the different versions of the SPICE language, the set of component primitives, parameters, and so A. Signal-Event Conversion in the adapter on. The problem of referencing the SPICE model in Verilog- AMS model is well specified in [1]. The signal-event conversion in the adapter exchanges dig- ital/analog

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