Experiences and Challenges of CAN Transceivers in Up- Integrated System Basis Chips

iCC 2005 CAN in Automation Experiences and challenges of CAN transceivers in up- integrated system basis chips Wayne Chen, Narasimhan Trichy, Kannan Soundarapandian, Sameer Pendharkar, John Carpenter, and James Kohout Texas Instruments, Dallas, TX This paper will discuss the experiences and challenges with the implementation of up- integrated CAN transceivers found on system-basis chips (SBCs) for the automotive market segment. These SBCs exist in an extremely harsh environment, factors such as system interoperatibility, enhanced electrostatic protection, and electromagnetic interference need to be understood and designed in the integrated component to help reduce issues at system level. This is further complicated as the needs for up- integration forces a less than idea silicon process selection to maintain cost goals for the SBC. Detailed discussion of lessons learned include the silicon process development of ESD robust structures at the device level using a lateral-DMOS silicon controller reticifier; the addition of clamp structures to protect the device during short circuit conditions when a CAN choke is used; the influence of fault protection structures on the robustness of the receiver to electromagnetic interference during direct power injection testing; the future market trends for system-on-a-chip development and the impact of process selection to ensure the feasibility of an up- integrated transceiver; and system power up/down issues to minimize bus distrubances. The paper will conclude with future challenges related to up-integrated CAN transceivers. I. System Basis Chips (SBCs) 1 shows an SBC with several of the building blocks. Note that the CAN Over the last decade, the automotive transceiver utilizes only a fraction of the industry trend has been to move to highly die area needed for the IC. Although the up-integrated, smart power Integrated transceiver serves an important Circuits (ICs), also known as system basis communications function, the circuitry chips. Systems previously containing alone is not sufficient to drive process multiple ICs, each providing a specific definition. function, now contain one or two system- on-a-chip ICs containing a wide range of analog, power, and digital functions. Like GPIO and K-line CAN Transceiver Wheel many ICs today, they have a digital core (2) Sensors comprised from a standard cell library 10-bit ADC similar to a digital application specific IC (ASIC). They also include analog building blocks such as operation amplifiers, comparators, data converters, and Core Logic Solenoid Solenoid Drivers voltage/current references. Somewhat Drivers more unique is that power circuits are also incorporated into the IC to add the ability Voltage to control motors, switches, and solenoids, NVM & and to generate power supplies, both Current Charge Pump Biases switching and linear, for internal and Watch- dog external circuitry. On a single piece of Regulators Fault Monitor silicon, one can find low power circuitry biased only with few microamperes of Figure 1: Example System Basis Chip current that may be next to a power device switching several amps of current. Figure 09-1 iCC 2005 CAN in Automation II. The Challenge the standard recommends protection to short circuit faults from battery and ground, To build an up-integrated CAN transceiver as well as shorted load conditions, the use on a highly integrated IC is a challenge as of chokes to improve radiated emissions the semiconductor technology that is can cause higher than expected transient chosen is not based solely for the voltages along the CAN bus which the transceiver. Higher levels of integration transceiver must tolerate without failure. force semiconductor process development engineers to choose fabrication steps and create components that offer higher levels III. ESD Protection of digital integration with high precision Insufficient ESD protection on the CAN analog devices and high voltage power bus pins is one of the leading causes of devices. The addition of power devices failures and device returns. As the bus also benefits CAN transceiver design as pins are the means of communication higher voltage components allow the between different modules within the car, it common-mode range specification to be is susceptible to mishandling during met. assembly or maintenance as the pins are However, the process must also be a low- exposed to an unprotected environment. cost solution. To achieve this goal, a Although every company quality target is junction isolated process is used instead of zero DPPM (defective parts per million), the more expensive dielectric isolated automotive companies insist on it. process. Junction isolation requires fewer Defective parts can come during the process steps, and is hence less assembly process, initial testing, or field expensive to manufacture. However, failures. The failures due to ESD dielectric isolation benefits from the lack of exposure must be reduced or eliminated, active parasitic components which and increasing protection levels is one of complicate circuit design and often cause the methods that can be implemented on unsuspected operation. These parasitic ICs. components often become active if the node is allowed to traverse above or below the supplies, thereby forward biasing PN 30 A ESD Model junctions . Furthermore, it is important to 30 Amp Peak Resd realize that these PN junctions can be the Current!! Cesd base emitter junction of NPN or PNP 8kV IEC transistors. Figure 2 shows a CMOS HBM: 15 A Resd=1.5kohm, Cesd=100pF cross-section with the numerous parasitic IEC: components that exist. Resd=300ohm, Cesd=150pF 8kV HBM Parasitic NPN formed Parasitic PNP formed if NMOS drain goes if PMOS drain goes below ground above supply 50 ns 100 ns NMOS PMOS sourcedrain ground supply drain source Figure 3: IEC and HBM ESD model comparison. n+n+ p+ n+ p+ p+ There are two main models for the ESD event: human body model and the N-well International Electrotechnical Commission p-sub (IEC). Although human body is the most Figure 2: CMOS cross-section with active parasitic familiar to IC manufactures, IEC is more components important to system engineers. The IEC Regardless of these process technology strike is much more severe due to the challenges, the automotive environment higher capacitance and voltage, as well as requires a robust transceiver design. the requirement that the strike occur when While needing to meet the ISO11898 the device is both powered-on and –off. standard, additional requirements are IEC is presently a focus as it is believed to needed in the areas of electrostatic be representative of actual ESD events in discharge protection (ESD) and the field. Figure 3 illustrates the electromagnetic immunity (EMI). While differences between the HBM and IEC 09-2 iCC 2005 CAN in Automation ESD model, as well as the transient were to fire while the bus was shorted to current waveform for an 8kV strike. battery, then there would be no way to Car makers and tier-1 suppliers (module unlatch the SCR. Under these conditions, suppliers to the carmakers) have the SCR would be destroyed. This can be continued to increase demands on ESD protected, but it is then important to performance. European companies have understand situations that could cause the been steadily increasing performance SCR to trigger. requirements from 8kV to 15kV over the past few years, with the Japanese Source Drain manufactures requesting as high as 25kV. Lpoly Traditional ESD structures that clamp the output voltage to protect internal circuitry nsd have been tried. However, it is important p- to keep in mind that for a 25kV IEC ESD strike, it is expected that currents of 45 psd nsd amps are expected to exist for 50nsec. n-well Although ESD structures are able to handle this amount of energy (<30uJ), it is Figure 4a: Standard LDMOS cross-section difficult to create a traditional clamp Drain structure that has sufficiently low Source Lpoly resistance to protect the internal circuitry. The characteristic of a good ESD psd nsd protection device is a low impedance when p- conducting under ESD strike, completely inactive during normal operating condition, psd nsd fast turn on and capability to turn off the n-well low impedance path at the conclusion of the ESD strike. An SCR, if it can be successfully turned off without latch up or Figure 4b: SCR-LDMOS cross-section other problems in the IC, is a very attractive ESD protection device because IV. Inductive kicks – another problem of the very low impedance in the on state. This is accomplished by allowing the One aspect of the CAN bus that can cause voltage to “snap-back” once the triggering excessive voltage transients is the voltage is reached, enough margin is inductance associated with the wiring gained to offset any issues caused by under short circuit conditions. Figure 5 parasitic on-resistance. shows a system under short circuit The device is built in a bipolar conditions and the current circuit complimentary MOS (BiCMOS) process. i configuration to protect against positive The SCR structure is based on the voltage transients. As the driver is turned standard LDMOS device with on, CANL goes into current limit, characteristics which have been reported establishing a current in the inductor. in [ii]. Figures 4a and 4b compares the When the driver turns off, inductance in cross sections of the standard 60V the wiring tries to maintain the same level LDMOS device and the new SCR-LDMOS of current and since the CANL node is now device. As can be seen from Figure 4b, high-impedance, the voltage on CANL current flowing underneath the drain side rises until the energy in the inductor is p-region can forward bias the p-n junction removed. As the inductance of the line is on the drain side, thus helping trigger the small, it does not have significant amounts pnpn SCR structure. Details of this of energy.

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