Chicken Or the Egg Computational Data Attacks Or Physical Attacks
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OS Structures and System Calls
COS 318: Operating Systems OS Structures and System Calls Kai Li Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) Outline Protection mechanisms OS structures System and library calls 2 Protection Issues CPU Kernel has the ability to take CPU away from users to prevent a user from using the CPU forever Users should not have such an ability Memory Prevent a user from accessing others’ data Prevent users from modifying kernel code and data structures I/O Prevent users from performing “illegal” I/Os Question What’s the difference between protection and security? 3 Architecture Support: Privileged Mode An interrupt or exception (INT) User mode Kernel (privileged) mode • Regular instructions • Regular instructions • Access user memory • Privileged instructions • Access user memory • Access kernel memory A special instruction (IRET) 4 Privileged Instruction Examples Memory address mapping Flush or invalidate data cache Invalidate TLB entries Load and read system registers Change processor modes from kernel to user Change the voltage and frequency of processor Halt a processor Reset a processor Perform I/O operations 5 x86 Protection Rings Privileged instructions Can be executed only When current privileged Level (CPR) is 0 Operating system kernel Level 0 Operating system services Level 1 Level 2 Applications Level 3 6 Layered Structure Hiding information at each layer Layered dependency Examples Level N THE (6 layers) . MS-DOS (4 layers) . Pros Level 2 Layered abstraction -
Segmentation, Protected Mode
Copyright Notice CS 410/510 • These slides are distributed under the Creative Commons Languages & Low-Level Programming Attribution 3.0 License • You are free: Mark P Jones • to share—to copy, distribute and transmit the work Portland State University • to remix—to adapt the work • under the following conditions: Fall 2018 • Attribution: You must attribute the work (but not in any way that suggests that the author endorses you or your use of the work) as follows: “Courtesy of Mark P. Jones, Portland State University” Week 3: Segmentation, Protected Mode, Interrupts, and Exceptions The complete license text can be found at http://creativecommons.org/licenses/by/3.0/legalcode !1 2 General theme for the next two weeks Diagrams and Code • In a complex system … • There are a lot of diagrams on these slides • Many of these are taken directly from the “Intel® 64 and App App App App App IA-32 Architectures Software Developer’s Manual”, Operating System Operating System particularly Volume 3 Microkernel • There is a link to the full pdf file in the Reference section Hardware • There is also a lot of code on these slides • Remember that you can study these more carefully later if • Question: how can we protect individual programs from you need to! interference with themselves, or with one another, either directly or by subverting lower layers? • General approach: leverage programmable hardware features! 3 4 Taking stock: Code samples ... so far vram video RAM simulation vram.tar.gz hello boot and say hello on bare metal, via hello.tar.gz GRUB simpleio a simple library for video RAM I/O Segmentation bootinfo display basic boot information from (or: where do “seg faults” come from?) GRUB baremetal.tar.gz mimg memory image bootloader & make tool example-mimg display basic boot information from mimgload example-gdt basic demo using protected mode segments (via a Global Descriptor Table) prot.tar.gz example-idt context switching to user mode (via an Interrupt Descriptor Table) 5 6 BASIC EXECUTION ENVIRONMENT • General-purpose registers. -
COS 318: Operating Systems OS Structures and System Calls
COS 318: Operating Systems OS Structures and System Calls Jaswinder Pal Singh Computer Science Department Princeton University (http://www.cs.princeton.edu/courses/cos318/) Outline u Protection mechanisms l Lead to … u OS structures u System and library calls 2 Protection Issues u CPU l Kernel has the ability to take CPU away from users to prevent a user from using the CPU forever l Users should not have such an ability u Memory l Prevent a user from accessing others’ data l Prevent users from modifying kernel code and data structures u I/O l Prevent users from performing “illegal” I/Os u Question l What’s the difference between protection and security? 3 Architecture Support: Privileged Mode An interrupt or exception (INT) User mode Kernel (privileged) mode • Regular instructions • Regular instructions • Access user memory • Privileged instructions • Access user memory • Access kernel memory A special instruction (IRET) 4 Privileged Instruction Examples u Memory address mapping u Flush or invalidate data cache u Invalidate TLB entries u Load and read system registers u Change processor modes from kernel to user u Change the voltage and frequency of processor u Halt a processor u Reset a processor u Perform I/O operations 5 Monolithic u All kernel routines are together, linked in single large executable l Each can call any other l Services and utilities User User program program u A system call interface u Examples: l Linux, BSD Unix, Windows, … u Pros l Shared kernel space l Good performance Kernel u Cons (many things) l Instability: crash in any procedure brings system down l Inflexible / hard to maintain, extend 6 Layered Structure u Hiding information at each layer u Layered dependency u Examples Level N l THE (6 layers) . -
Memory Management Algorithms and Implementation in C/C++
Everything about Internet Technology! Chose your section ● Auctions ● Network Marketing ● Business ● Online Promotion ● Computers ● Search Engines ● Domain Names ● Site Promotion ● Downloads ● Software ● eBay ● Technology ● Ebooks ● Video Conferencing ● Ecommerce ● VOIP ● Email Marketing ● Web Design ● Internet Marketing ● Web Development ● HTML ● Web Hosting ● JavaScript ● WIFI ● MP3 Memory Management Algorithms and Implementation in C/C++ by Bill Blunden Wordware Publishing, Inc. Library of Congress Cataloging-in-Publication Data Blunden, Bill, 1969- Memory management: algorithms and implementation in C/C++ / by Bill Blunden. p. cm. Includes bibliographical references and index. ISBN 1-55622-347-1 1. Memory management (Computer science) 2. Computer algorithms. 3. C (Computer program language) 4. C++ (Computer program language) I. Title. QA76.9.M45 .B558 2002 005.4'35--dc21 2002012447 CIP © 2003, Wordware Publishing, Inc. All Rights Reserved 2320 Los Rios Boulevard Plano, Texas 75074 No part of this book may be reproduced in any form or by any means without permission in writing from Wordware Publishing, Inc. Printed in the United States of America ISBN 1-55622-347-1 10987654321 0208 Product names mentioned are used for identification purposes only and may be trademarks of their respective companies. All inquiries for volume purchases of this book should be addressed to Wordware Publishing, Inc., at the above address. Telephone inquiries may be made by calling: (972) 423-0090 This book is dedicated to Rob, Julie, and Theo. And also to David M. Lee “I came to learn physics, and I got Jimmy Stewart” iii Table of Contents Acknowledgments......................xi Introduction.........................xiii Chapter 1 Memory Management Mechanisms. 1 MechanismVersusPolicy..................1 MemoryHierarchy......................3 AddressLinesandBuses...................9 Intel Pentium Architecture . -
DOS INTERRUPTS DOSINTS.DOC Page 1 of 117 Page 2 of 117 DOSINTS.DOC Contents
DOS INTERRUPTS DOSINTS.DOC Page 1 of 117 Page 2 of 117 DOSINTS.DOC Contents THE LEGAL WORDS .................................................................................................................................... 13 THE INTERRUPTS ........................................................................................................................................ 14 INT 00 - internal - DIVIDE ERROR ................................ ................................ ................................ ................................ ................................ ............ 14 INT 01 - internal - SINGLE-STEP ................................ ................................ ................................ ................................ ................................ ............... 14 INT 02 - hardware - NMI (NON-MASKABLE INTERRUPT) ................................ ................................ ................................ ................................ 14 INT 03 - ONE-BYTE INTERRUPT ................................ ................................ ................................ ................................ ................................ ............. 14 INT 04 - internal - OVERFLOW ................................ ................................ ................................ ................................ ................................ .................. 14 INT 05 - PRINT-SCREEN KEY ................................ ................................ ................................ ............................... -
Hardware Details Os Design Patterns
HARDWARE DETAILS OS DESIGN PATTERNS CS124 – Operating Systems Winter 2015-2016, Lecture 3 2 Operating System Components • Operating systems commonly provide these components: • Last time: User(s) • Applications can’t access operating system state or Applications code directly User Applications • OS code and state are System Applications stored in kernel space Command-Line Services Support GUI • Must be in kernel mode to access this data Operating System • Application code and System Calls state is in user space Program Protection Execution Filesystems Communication Security Resource Error • How does the application Allocation I/O Services Accounting Detection interact with the OS? Computer Hardware 3 Operating Modes and Traps • Typical solution: application issues a trap instruction • A trap is an intentional software-generated exception or interrupt • (as opposed to a fault; e.g. a divide-by-zero or a general protection fault) • During OS initialization, the kernel provides a handler to be invoked by the processor when the trap occurs • When the trap occurs, the processor can change the current protection level (e.g. switch from user mode to kernel mode) • Benefits: • Applications can invoke operating system subroutines without having to know what address they live at • (and the location of OS routines can change when the OS is upgraded) • OS can verify applications’ requests to prevent misbehavior • e.g. check arguments to system calls, verify process permissions, etc. 4 IA32: Operating Modes and Traps • On IA32, programs use the int -
Scribe Notes for Tuesday 11/5/13 Meena Boppana, Namya Mahajan, Lisa Zacarias
Scribe Notes for Tuesday 11/5/13 Meena Boppana, Namya Mahajan, Lisa Zacarias ● OS01 ○ Attack to erase welcome’s code using memset (sets it all to 0’s) ■ The 0’s erased the permissions and made it inaccessible, so we get pagefaults ■ How do we fix it? ● We can’t protect one process against another process without making it inaccessible to every other process except the kernel ● Since otherwise we might prevent it from reaching its own code as well, we should fix it by setting a second level pagetable ● Allocate space for hello’s new pagetable ● Memset first level pagetable to 0’s (we’ll only ever need the first entry, and we set it to point to the top of the new second level table) ● Take away user permissions then add them back for the first entry (which is the program’s own code) ○ Give each process its own physical page to make it seem like each process has control of the entire kernel ■ You can map x in process 1 and x in process 2 and not have a conflict ■ We do this with virtual addresses (VA’s) ■ Mapping from one virtual address to a physical address ● %cr3 → control register ○ Holds the address of the current process's L1 page table ● The offset is the location in the physical page that the process wants to access ○ It’s the least significant 12 bits of the VA ○ You can’t change the offset when you translate ● Identity mapping — mapping the virtual address to the same physical address ● The Pagetable Level 1 Index (PTL1) is the most significant (top) 10 bits of the VA ● The Pagetable Level 2 Index (PTL2) is the next most significant -
Download It to a Target System Where It Is Executed As the Local OS
ENABLING USER-MODE PROCESSES IN THE TARGET OS FOR CSC 159 OPERATING SYSTEM PRAGMATICS A Project Presented to the faculty of the Department of Computer Science California State University, Sacramento Submitted in partial satisfaction of the requirements for the degree of MASTER OF SCIENCE in Computer Science by Michael Bradley Colson SPRING 2018 © 2018 Michael Bradley Colson ALL RIGHTS RESERVED ii ENABLING USER-MODE PROCESSES IN THE TARGET OS FOR CSC 159 OPERATING SYSTEM PRAGMATICS A Project by Michael Bradley Colson Approved by: __________________________________, Committee Chair Dr. Weide Chang __________________________________, Second Reader Dr. Yuan Cheng ____________________________ Date iii Student: Michael Bradley Colson I certify that this student has met the requirements for format contained in the University format manual, and that this project is suitable for shelving in the Library and credit is to be awarded for the project. __________________________, Graduate Coordinator ___________________ Dr. Jinsong Ouyang Date Department of Computer Science iv Abstract of ENABLING USER-MODE PROCESSES IN THE TARGET OS FOR CSC 159 OPERATING SYSTEM PRAGMATICS by Michael Bradley Colson One of the main responsibilities of an Operating System (OS) is to ensure system stability and security. Most OSes utilize mechanisms built into the CPU hardware to prevent user-mode processes from altering the state of the system or accessing protected spaces and hardware I/O ports. A process should only read from or write to memory addresses in its address space. In order to accomplish the above, the CPU is typically designed to operate in two or more modes with different privilege levels. The OS typically runs in the mode with highest privilege level, which enables it to execute any instruction and gives it access to all the memory in the system. -
An X86 Protected Mode Virtual Machine Monitor for the MIT Exokernel by Charles L
An x86 Protected Mode Virtual Machine Monitor for the MIT Exokernel by Charles L. Coffing Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degrees of Bachelor of Science in Computer Science and Engineering and Master of Engineering in Computer Science at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY May 1999 © Charles L. Coffing, NICMXCIX. A rights reserved. The author hereby grants to MIT permission to reproduce and distribute publicly paper and electronic copies of this thesis and to grant others the right to do so. MASSACHUSETTS NE OF TECHN 0 Author .............................. ... ......... Department of Electrical Engineering Computer Science A/- May 21, 1999 Certified by ............. ...................Fsh M. Frans Kaashoek Associate otessor z hes " ervisor Accepted by....... ........... Arthur C. Smith Chairman, Department Committee on Graduate Students An x86 Protected Mode Virtual Machine Monitor for the MIT Exokernel by Charles L. Coffing Submitted to the Department of Electrical Engineering and Computer Science on May 21, 1999, in partial fulfillment of the requirements for the degrees of Bachelor of Science in Computer Science and Engineering and Master of Engineering in Computer Science Abstract This thesis presents the design and implementation of an x86 virtual machine mon- itor that allows multiple operating systems to run concurrently under xok, MIT's x86-based exokernel. The monitor and modified xok demonstrate how to share sev- eral processor-defined structures, such as the GDT, LDT, and IDT, between multiple operating systems. Xok was modified to allow controlled modifications to these struc- tures. Linux was used as the reference guest operating system. -
The Page-Fault Weird Machine: Lessons in Instruction-Less Computation
The Page-Fault Weird Machine: Lessons in Instruction-less Computation Julian Bangert, Sergey Bratus, Rebecca Shapiro, Sean W. Smith Abstract not unique to either the x86 Memory Management Unit (MMU) or to the Intel architecture, but that similarly Trust Analysis, i.e. determining that a system will not complex architectures have similarly interesting behav- execute some class of computations, typically assumes ior outside their “main” instruction set. that all computation is captured by an instruction trace. Although our proof-of-concept represents neither a We show that powerful computation on x86 processors vulnerability in IA32, nor an exploit for x86 processors, is possible without executing any CPU instructions. We but we believe it continues the line of research that orig- demonstrate a Turing-complete execution environment inated in exploit development—namely, exposing unex- driven solely by the IA32 architecture’s interrupt han- pected (and unexpectedly powerful) programming mod- dling and memory translation tables, in which the pro- els within the targeted environments, where program- cessor is trapped in a series of page faults and double ming happens via maliciously crafted data rather than faults, without ever successfully dispatching any instruc- with native binary code. We show that CPUs carry within tions. The “hard-wired” logic of handling these faults is them a “weird machine” programming model which does used to perform arithmetic and logic primitives, as well not rely on any actual CPU instructions. as memory reads and writes. This mechanism can also We believe that understanding such unexpected “weird perform branches and loops if the memory is set up and machine” execution models is necessary in order to work mapped just right. -
5.14. EXCEPTION and INTERRUPT REFERENCE the Following Sections Describe Conditions Which Generate Exceptions and Interrupts
INTERRUPT AND EXCEPTION HANDLING 5.14. EXCEPTION AND INTERRUPT REFERENCE The following sections describe conditions which generate exceptions and interrupts. They are arranged in the order of vector numbers. The information contained in these sections are as follows: Exception Class Indicates whether the exception class is a fault, trap, or abort type. Some exceptions can be either a fault or trap type, depending on when the error condition is detected. (This section is not applicable to interrupts.) Description Gives a general description of the purpose of the exception or inter- rupt type. It also describes how the processor handles the exception or interrupt. Exception Error Code Indicates whether an error code is saved for the exception. If one is saved, the contents of the error code are described. (This section is not applicable to interrupts.) Saved Instruction Pointer Describes which instruction the saved (or return) instruction pointer points to. It also indicates whether the pointer can be used to restart a faulting instruction. Program State Change Describes the effects of the exception or interrupt on the state of the currently running program or task and the possibilities of restarting the program or task without loss of continuity. 5-22 Vol. 3 INTERRUPT AND EXCEPTION HANDLING Interrupt 0—Divide Error Exception (#DE) Exception Class Fault. Description Indicates the divisor operand for a DIV or IDIV instruction is 0 or that the result cannot be repre- sented in the number of bits specified for the destination operand. Exception Error Code None. Saved Instruction Pointer Saved contents of CS and EIP registers point to the instruction that generated the exception. -
Porting Linux to X86-64
Porting Linux to x86-64 Andi Kleen SuSE Labs [email protected] Abstract Certain unprivileged programs can be run in com- patibility mode in a special code segment, which al- ... lows to execute existing IA32 programs unchanged. Some implementation details with changes over the Other programs can run in long mode and exploit all existing i386 port are discussed. new features. The kernel and all interrupts run in long mode. The main new feature is support for 64bit ad- 1 Introduction dresses, so that more than 4GB of memory can be directly addressed.All registers and other structures x86-64 is a new architecture developed by AMD. It is dealing with addresses have been enlarged to 64bit. an extension to the existing IA32 architecture. The There have been 8 new integer registers added (R8- main new features over IA32 are 64bit addresses, 16 R16), so that there is a total of 16 general purpose 64bit integer register and 16 SSE2 registers. This 64bit registers now. Without address prefix the code paper describes the Linux port to this new architec- usually defaults to 32bit accesses to registers and ture. The new 64bit kernel is based on the existing memory, except for the stack which is always 64bit i386 port. It is ambitious in as that it tries to ex- aligned and jumps. 32bit operations on 64bit reg- ploit new features, not just do a minimum port, and isters do zero extension. 64bit immediates are only redesigns parts of the i386 port as necessary. The supported by the new movabs instruction. x86-64 kernel is developed by AND and SuSE as a A new addressing mode, RIP-relative, has been free software project.