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Formal Specification of the X86 Instruction Set Architecture

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Formal Specification of the X86 Instruction Set Architecture View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Scientific documents from the Saarland University, Formal Specification of the x86 Instruction Set Architecture Dissertation zur Erlangung des Grades Doktor der Ingenieurswissenschaften (Dr.-Ing.) der Naturwissenschaftlich-Technischen Fakultäten der Universität des Saarlandes Ulan Degenbaev Saarbrücken, Februar 2012 ii Tag des Kolloquiums: 6. Februar 2012 Dekan: Prof. Dr. Holger Hermanns Vorsitzender des Prüfungsausschusses: Prof. Dr. Sebastian Hack 1. Berichterstatter: Prof. Dr. Wolfgang J. Paul 2. Berichterstatter: Dr. habil. Peter-Michael Seidel Akademischer Mitarbeiter: Dr. Art Tevs Hiermit erkläre ich, dass ich die vorliegende Arbeit ohne unzulässige Hilfe Dritter und ohne Benutzung anderer als der angegebenen Hilfsmittel angefertigt habe. Die aus anderen Quellen oder indirekt übernommenen Daten und Konzepte sind unter Angabe der Quelle gekennzeichnet. Die Arbeit wurde bisher weder im In- noch im Ausland in gleicher oder ähnlicher Form in anderen Prüfungsverfahren vorgelegt. Saarbrücken, im Februar 2012 iii iv Abstract In this thesis we formally specify the x86 instruction set architecture (ISA) by develop- ing an abstract machine that models the behaviour of a modern computer with multiple x86 processors. Our model enables reasoning about low-level system software by pro- viding formal interpretation of thousand pages of the processor vendor documentation written in informal prose. We show how to reduce the problem of ISA formalization to two simpler problems: mem- ory model specification and instruction semantics specification. We solve the former problem by extending the classical Total Store Ordering memory model with caches, translation-lookaside buffers, memory fences, locks, and other features of the x86 pro- cessor. In order to make instruction semantics specification readable and compact, we design a new domain-specific language. The language has intuitive syntax for defining registers and instructions, so that any programmer should be able to understand the specifica- tion. Although our language is external and not embedded into a formal proof system, the language is based on the same principles as embedded, monadic domain-specific languages. Thus, it is possible to translate specifications from our language to formal proof systems. Zusammenfassung In dieser Arbeit spezifizieren wir den x86-Befehlssatz durch die Definition einer ab- strakten Maschine, die das Verhalten eines modernen Computers mit mehreren x86- Prozessoren modeliert. Unser Modell bietet eine formale Interpretation der Prozes- sorherstellerdokumentationen, die über Tausend Seiten von informellen Spezifikatio- nen enthalten. Wir zeigen, wie das Problem der Befehlssatz-Formalisierung in zwei einfachere Prob- leme zerlegt werden kann: Spezifikation von dem Speichermodell und Spezifikation von der Maschinenbefehlsemantik. Wir lösen das erste Problem durch die Erweiterung des klassischen “Total Store Ordering” Speichermodells mit Caches, Translation-Lookaside Buffers, Memory Fences und Locks. Um die Maschinenbefehlsemantikspezifikation lesbar und kompakt zu machen, entwer- fen wir ein neue domänenspezifische Sprache. Die Sprache hat intuitive Syntax zur Definition von Registern und Maschinenbefehlen, so dass jeder Programmierer in der Lage sein sollte, die Spezifikation zu verstehen. Obwohl unsere Sprache nicht in ein formales Beweissystem eingebettet ist, basiert sie auf den gleichen Grundsätzen wie eingebette monadische domänenspezifische Sprachen. So ist es möglich, Spezifikatio- nen aus unserer Sprache in ein formales Beweissystem zu übertragen. v vi Acknowledgments I would like to thank my supervisor Professor Wolfgang Paul for the guidance and en- couragement. I owe my graditute to many people in the Verisoft XT group for valuable suggestions, stimulating discussions, and friendly atmosphere. Special thanks to Christian Müller, Ernie Cohen, Eyad Alkassar, Mark A. Hillebrant, and Norbert Schirmer. vii viii CONTENTS 1 Introduction 1 1.1 Motivation.................................... 1 1.2 The Problem................................... 2 1.3 Related Work .................................. 2 1.4 Methodology .................................. 7 1.5 Scope of the model............................... 10 1.6 Outline...................................... 11 I Abstract Machine 13 2 Notation 15 2.1 Relations..................................... 16 2.2 Functions .................................... 16 2.3 Conventions for memory accesses ...................... 17 3 Model Overview 19 3.1 Instruction execution.............................. 19 3.2 Abstract x86 machine ............................. 24 4 Environment 27 5 Cache 29 5.1 MOESI protocol................................. 29 5.2 Memory types.................................. 32 5.3 Cache model .................................. 32 6 Store Buffer 37 6.1 Forwarding and writing ............................ 37 6.2 Transitions ................................... 38 7 Load Buffers 41 7.1 Loading code .................................. 42 7.2 Loading data .................................. 42 7.3 Flushing..................................... 44 ix 8 Translation-Lookaside Buffer 45 8.1 Page Tables ................................... 46 8.2 Creating and dropping walks......................... 48 8.3 Extending walks ................................ 48 8.4 Loading translations into the Core...................... 50 8.5 Flushing..................................... 52 9 Core 53 9.1 Core configuration............................... 53 9.2 Overview of transitions ............................ 57 9.3 Instruction border ............................... 59 9.4 RESET, INIT, HALT............................... 62 9.5 Memory accesses................................ 64 9.6 Fetch and decode................................ 65 9.7 Execution .................................... 66 9.8 VMEXIT ..................................... 71 9.9 Serializing.................................... 71 9.10 Jump to interrupt service routine....................... 72 10 Local APIC 77 10.1 Maskable interrupts .............................. 78 10.2 INIT, NMI, SIPI................................. 81 10.3 Interprocessor interrupts ........................... 83 10.4 Miscellaneous.................................. 86 10.5 Register accesses................................ 88 10.6 IPI Delivery ................................... 89 II Inside Processor Core 95 11 DSL Syntax and Semantics 97 11.1 Source Code Structure............................. 99 11.2 Types.......................................101 11.3 Registers.....................................105 11.4 Expressions...................................106 11.5 Functions ....................................109 11.6 Actions......................................109 11.7 Instructions...................................110 12 Registers 113 12.1 General-Purpose Registers ..........................113 12.2 Control Registers................................113 12.3 Segment Registers...............................118 12.4 Descriptor Table Registers ..........................120 12.5 Task Register ..................................120 12.6 Virtualization Registers ............................120 12.7 Instruction Registers..............................121 12.8 Memory Type Registers ............................122 12.9 Fast System Call ................................126 12.10 APIC Base Address...............................128 x 12.11 Time-Stamp Counters .............................128 13 Architecture 129 13.1 Operating Modes................................129 13.2 Exceptions....................................132 13.3 Address spaces.................................134 13.4 Memory System Interface...........................134 13.5 Reading and Writing the Virtual Memory ..................136 13.6 Page Tables ...................................137 13.7 Segment Descriptors..............................140 13.8 Gate Descriptors ................................144 13.9 Descriptor Tables................................146 13.10 Protection....................................149 13.11 Privilege Level Change.............................151 13.12 Segmentation Translation...........................152 13.13 Segment Register Access ...........................154 13.14 Task State Segment ..............................157 14 Instruction Fetch and Decode 161 14.1 Instruction Format...............................161 14.2 Opcode......................................161 14.3 Prefixes .....................................162 14.4 ModRM byte ..................................165 14.5 SIB byte.....................................165 14.6 Displacement..................................166 14.7 Immediate Operand ..............................167 14.8 Opcode Table ..................................167 14.9 Instruction Fetch................................169 14.10 Operand Width .................................172 14.11 Memory Operand Address Width.......................173 14.12 Memory Operand Address...........................174 14.13 Operand Decode ................................175 15 Stack and Stack Operations 179 15.1 Inner Stack ...................................180 16 Far Control Transfer 183 16.1 Far Jump.....................................184 16.2 Far Procedure Call...............................186 16.3 Control Transfer to an Interrupt Handler ..................193 16.4 Far Return....................................195 16.5 Task Switch...................................198
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