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CPU Registers Reading Assignment • Microcontrollers and Microcomputers: Chapter 3, EEL 4744C: Microprocessor Applications Chapter 4 • Software and Hardware Engineering: Chapter 2 Or Lecture 2 • Software and Hardware Engineering: Chapter 4 Programming Model, Address Mode, Plus HC12 Hardware Introduction • CPU12 Reference Manual: Chapter 3 • M68HC12B Family Data Sheet: Chapter 1, 2, 3, 4 Dr. Tao Li 1 Dr. Tao Li 2 CPU Registers • Accumulators – Registers that accumulate answers, e.g. the A Register EEL 4744C: Microprocessor Applications – Can work simultaneously as the source register for one operand and the destination register for ALU operations Lecture 2 • General-purpose registers – Registers that hold data, work as source and destination register for data transfers and source for ALU operations Part 1 • Doubled registers CPU Registers and Control Codes – An N-bit CPU in general uses N-bit data registers – Sometimes 2 of the N-bit registers are used together to double the number of bits, thus “doubled” registers Dr. Tao Li 3 Dr. Tao Li 4 CPU Registers (2) CPU Registers (3) • Pointer registers • Segment registers – Registers that address memory by pointing to specific – In some architectures, memory addressing requires memory locations that hold the needed data that the physical address be specified in 2 parts – Contain memory addresses (without offset) • Segment part: specifies a memory page • Offset part: specifies a particular place in the page • Stack pointer registers – Pointer registers dedicated to variable data and return • Condition code registers address storage in subroutine calls – Also called flag or status registers • Index registers – Hold condition code bits generated when – Also used to address memory instructions are executed, e.g. overflow in ADD – An effective memory address is found by adding an offset to the content of the involved index register Dr. Tao Li 5 Dr. Tao Li 6 1 Register Transfers Condition Code Register (CCR) • MOV A, B • Also called flag or status registers – B is the source, A is the destination • Contain bits that are set or reset due to • ADD A, B instructions – Add (A) to (B), then transfer the answer from ALU to – ALU, load or move can all modify the CCR A • Register transfer language • Most processors also provide instructions that – Register name in () means “content” of the register modify the CCR directly – “” means replacement, e.g. (A) (B) • What are the “bit” in the CCR? Dr. Tao Li 7 Dr. Tao Li 8 Condition Code Register (2) Condition Code Register (3) • Carry bit • Carry bit for multiple-byte ADD/SUB – Set to 1 if there is a carry/borrow out of the most – Carry from the less significant bytes is added into the ADD/SUB of the next more significant bytes significant bit during an ADD or SUB • Overflow • Example: 00110010 11001001 + 00011011 10110110 – A carry of 1 from the LSB’s is added into the MSB’s – The result is too large to be represented by available bits • What if we try to add two numbers that are • Underflow encoded in 2’s-complement bits?! – The result is too small to be represented by available bits • Example: 10010011 (-10910) +/- 10110011 (-7710) • Examples: 10010011 (147 ) +/- 10110011 (179 ) 10 10 – Give 1 01000110 (-18610) and 1 11100000 (-3210) – ADD gives overflow, SUB gives underflow, setting the – The ADD results in overflow, the SUB has no carry (or borrow) bit to 1 problem Dr. Tao Li 9 Dr. Tao Li 10 Condition Code Register (4) Conditional Code Register (5) • Example: 10010011 (-10910) +/- 10110011 (-7710) • Conclusion: carry/borrow bit can not be used to – Produce 1 01000110 (-18610) and 1 11100000 (-3210) indicate overflow/underflow for 2’s-complment! – In 2’s-complement number encoding, the ADD had an overflow, the SUB was OK • A separate bit is needed to indicate overflow for • Examples: 10010011 (147 ) +/- 10110011 (179 ) 2’s-complement numbers 10 10 – Produce 1 01000110 (326 ) and 1 11100000 (-32 ) – Overflow occurs if the 2 operands have the same sign 10 10 – In unsigned binary encoding, the ADD had an overflow, AND the result is of different sign the SUB had an underflow – Overflow cannot occur if the 2 operands have opposite signs • We notice that the bit patterns remain the same, also – Which one is the sign bit? The most significant bit, not the hardware remain the same. The hardware can the carry/borrow bit provide overflow flag bit for 2’s-complement Dr. Tao Li 11 Dr. Tao Li 12 2 Condition Code Register (6) Condition Code Register (7) • Sign bit • Symbols for flags – Most significant bit of the number (not the carry bit) – Carry: C – Gives the sign only of signed number encoding is used – Overflow: V – Sign: S • Zero bit – Zero: Z – Set to 1 if the result of an operation equals to zero – Parity: P – Otherwise it is reset to 0 or false • Parity bit • Using the CCR – Even-parity: set if result has an even number of 1’s – CCR is attached to the sequence controller – Odd-parity: set if result has an odd number of 1’s – For use by the conditional branch instructions – Useful for checking errors in long-haul data transmission – Results of operations will set or reset C, V, S, or Z – Parity-even/parity-odd works with conditional branches – Conditional branch instructions checks C, V, S, or Z Dr. Tao Li 13 Dr. Tao Li 14 Condition Code Register (8) • The Programmer’s Model – The set of registers the programmer can manipulate and must manage to program the processor EEL 4744C: Microprocessor Applications – Include accumulator, data registers, memory addressing registers, stack point registers, condition code registers, etc. Lecture 2 – Also include memory locations used for data storage Part 2 Addressing Modes Dr. Tao Li 15 Dr. Tao Li 16 Addressing Terminology Addressing Terminology (2) • Physical address • Logical address – The actual address supplied to the memory – Used when the complete physical is not needed or – Number of bits in physical address determines the possible maximum number of memory locations that can be – The offset address is one kind of logical address addressed • Effective address • Segment address – One that is calculated by the processor – Gives the location of a segment of memory (e.g. block, – Can be a physical or a logical address page, etc.) that is smaller than the full memory • Auto-increment/-decrement • Offset address – Provide efficient addressing for stepping through data tables – One that is calculated from the start of a segment of memory – Registers that address memory tend to have these capabilities Dr. Tao Li 17 Dr. Tao Li 18 3 Addressing Terminology (3) Memory Architectures • RAM • Linear addressing – Stands for random access memory – Instructions specify the full physical address – Memories that can be read from and written to – Favored by Motorola processors • ROM – Motorola MC68020 used 32-bit addresses, giving a – Stands for read only memory 4GB addressable memory size • Memory map – Shows which addresses are used for which purposes – May show which addresses contain ROM, RAM, and Linear addressing memory which have no memory installed at all map for an n-bit address • I/O map – Similar to a memory map for I/O functions Dr. Tao Li 19 Dr. Tao Li 20 Memory Architectures (2) Memory Architectures (3) • Segmented addressing • Segmented addressing (continued) – Reduces the number of bits needed to specify an address – Physical address is computed by shifting the segment – Favored by Intel processors with 16B to 64KB segments register contents left by 4 bits, then adding the offset – Intel 8086 used 20-bit addresses, 16 bits for segment – Allows efficient allocation of memory to code and data address and 16 bits for offset address – Special techniques needed to exceed page boundary Segmented Variable sized addressing segments used in a memory map – segmented memory Intel 8086 architecture Dr. Tao Li 21 Dr. Tao Li 22 Addressing Modes Addressing Modes (2) • Register addressing • Direct (absolute) memory addressing – When operands are held in the registers, e.g. MOV A, B – Instruction specifies the address of the data – Register addressing instructions are the fastest and use the fewest bits compared to others – The data address (in the instruction) can be the full – Some call it inherent addressing also physical address, or an offset address, depending on the memory architecture in use • Immediate addressing – 2 variations: direct addressing, reduced direct addressing – Used for constant values know when the program is Full address Offset written – Data (i.e. constant values) can immediately follow the instruction Dr. Tao Li 23 Dr. Tao Li 24 4 Addressing Modes (3) Addressing Modes (4) • Register indirect addressing • Register indirect addressing with auto- – Also called pointer register addressing increment and auto-decrement – Instruction contains address of the register that contains – For stepping through a table of data using register the address of the needed data indirect addressing mode – A 2-level addressing mode – The register pointing to the data must be in- /decremented Level 2 – Pre- and post- incrementing/decrementing are Level 1 Level 1 Level 2 Index Index available • Essentially the same as register indirect addressing except each pointer register can have its contents incremented or decremented Dr. Tao Li 25 Dr. Tao Li 26 Addressing Modes (5) Addressing Modes (6) • Memory indirect • Indexed addressing addressing – Finds a memory location based on an index – Instruction contains – Instruction contains the starting address of the array, memory address of the the index register contains the offset to reach the address
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