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Intel Architecture Software Developer's Manual

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Intel Architecture Software Developer's Manual Intel Architecture Software Developer’s Manual Volume 2: Instruction Set Reference NOTE: The Intel Architecture Software Developer’s Manual consists of three volumes: Basic Architecture, Order Number 243190; Instruction Set Reference, Order Number 243191; and the System Programming Guide, Order Number 243192. Please refer to all three volumes when evaluating your design needs. 1999 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel’s Intel Architecture processors (e.g., Pentium®, Pentium® II, Pentium® III, and Pentium® Pro processors) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting Intel's literature center at http://www.intel.com. COPYRIGHT © INTEL CORPORATION 1999 *THIRD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. TABLE OF CONTENTS CHAPTER 1 ABOUT THIS MANUAL 1.1. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE 1-1 1.2. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE 1-2 1.3. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE 1-3 1.4. NOTATIONAL CONVENTIONS. 1-5 1.4.1. Bit and Byte Order. .1-5 1.4.2. Reserved Bits and Software Compatibility . .1-6 1.4.3. Instruction Operands . .1-7 1.4.4. Hexadecimal and Binary Numbers . .1-7 1.4.5. Segmented Addressing . .1-7 1.4.6. Exceptions. .1-8 1.5. RELATED LITERATURE . 1-9 CHAPTER 2 INSTRUCTION FORMAT 2.1. GENERAL INSTRUCTION FORMAT . 2-1 2.2. INSTRUCTION PREFIXES . 2-1 2.3. OPCODE . 2-2 2.4. MODR/M AND SIB BYTES . 2-2 2.5. DISPLACEMENT AND IMMEDIATE BYTES . 2-3 2.6. ADDRESSING-MODE ENCODING OF MODR/M AND SIB BYTES . 2-3 CHAPTER 3 INSTRUCTION SET REFERENCE 3.1. INTERPRETING THE INSTRUCTION REFERENCE PAGES . 3-1 3.1.1. Instruction Format . .3-1 3.1.1.1. Opcode Column . .3-2 3.1.1.2. Instruction Column . .3-3 3.1.1.3. Description Column . .3-5 3.1.1.4. Description . .3-5 3.1.2. Operation. .3-6 3.1.3. Intel C/C++ Compiler Intrinsics Equivalent . .3-9 3.1.3.1. The Intrinsics API . .3-9 3.1.3.2. MMX™ Technology Intrinsics. .3-10 3.1.3.3. SIMD Floating-Point Intrinsics . .3-10 3.1.4. Flags Affected . .3-11 3.1.5. FPU Flags Affected . .3-12 3.1.6. Protected Mode Exceptions. .3-12 3.1.7. Real-Address Mode Exceptions . .3-12 3.1.8. Virtual-8086 Mode Exceptions. .3-13 3.1.9. Floating-Point Exceptions . .3-14 3.1.10. SIMD Floating-Point Exceptions - Streaming SIMD Extensions Only . .3-14 i TABLE OF CONTENTS 3.2. INSTRUCTION REFERENCE . 3-16 AAA—ASCII Adjust After Addition . .3-17 AAD—ASCII Adjust AX Before Division . .3-18 AAM—ASCII Adjust AX After Multiply . .3-19 AAS—ASCII Adjust AL After Subtraction. .3-20 ADC—Add with Carry. .3-21 ADD—Add . .3-23 ADDPS—Packed Single-FP Add . .3-25 AND—Logical AND . .3-30 ANDNPS—Bit-wise Logical And Not For Single-FP. .3-32 ANDPS—Bit-wise Logical And For Single FP . .3-34 ARPL—Adjust RPL Field of Segment Selector . .3-36 BOUND—Check Array Index Against Bounds . .3-38 BSF—Bit Scan Forward . .3-40 BSR—Bit Scan Reverse. .3-42 BSWAP—Byte Swap . .3-44 BT—Bit Test . .3-45 BTC—Bit Test and Complement . .3-47 BTR—Bit Test and Reset . .3-49 BTS—Bit Test and Set . .3-51 CALL—Call Procedure. .3-53 CBW/CWDE—Convert Byte to Word/Convert Word to Doubleword . .3-64 CDQ—Convert Double to Quad . .3-65 CLC—Clear Carry Flag . .3-66 CLD—Clear Direction Flag. .3-67 CLI—Clear Interrupt Flag . .3-68 CLTS—Clear Task-Switched Flag in CR0 . .3-70 CMC—Complement Carry Flag . .3-71 CMOVcc—Conditional Move . .3-72 CMP—Compare Two Operands . .3-76 CMPPS—Packed Single-FP Compare . .3-78 CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands. .3-87 CMPSS—Scalar Single-FP Compare . .3-90 CMPSS—Scalar Single-FP Compare (Continued) . .3-98 CMPXCHG—Compare and Exchange. .3-100 CMPXCHG8B—Compare and Exchange 8 Bytes . .3-102 COMISS—Scalar Ordered Single-FP Compare and Set EFLAGS . .3-104 CPUID—CPU Identification . .3-111 CVTPI2PS—Packed Signed INT32 to Packed Single-FP Conversion . .3-119 CVTPS2PI—Packed Single-FP to Packed INT32 Conversion. .3-123 CVTSI2SS—Scalar Signed INT32 to Single-FP Conversion . .3-127 CVTSS2SI—Scalar Single-FP to Signed INT32 Conversion . .3-130 CVTTPS2PI—Packed Single-FP to Packed INT32 Conversion (Truncate) . .3-133 CVTTSS2SI—Scalar Single-FP to Signed INT32 Conversion (Truncate) . .3-137 CWD/CDQ—Convert Word to Doubleword/Convert Doubleword to Quadword. ..
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