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Floating-Point IP Cores User Guide

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Floating-Point IP Cores User Guide Floating-Point IP Cores User Guide Updated for Intel® Quartus® Prime Design Suite: 20.1 Subscribe UG-01058 | 2021.09.13 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. About Floating-Point IP Cores.........................................................................................6 1.1. List of Floating-Point IP Cores..................................................................................6 1.2. Installing and Licensing Intel FPGA IP Cores.............................................................. 8 1.3. Design Flow.......................................................................................................... 9 1.3.1. IP Catalog and Parameter Editor.................................................................. 9 1.3.2. Specifying the IP Core Parameters and Options (Intel Quartus Prime Pro Edition).................................................................................................. 11 1.3.3. Generating IP Cores (Intel Quartus Prime Standard Edition)...........................15 1.4. Upgrading IP Cores.............................................................................................. 15 1.4.1. Migrating IP Cores to a Different Device...................................................... 19 1.5. Floating-Point IP Cores General Features.................................................................20 1.6. IEEE-754 Standard for Floating-Point Arithmetic.......................................................20 1.6.1. Floating-Point Formats..............................................................................21 1.6.2. Special Case Numbers.............................................................................. 22 1.6.3. Rounding................................................................................................ 22 1.7. Non-IEEE-754 Standard Format............................................................................. 23 1.8. Floating-Points IP Cores Output Latency..................................................................23 1.9. Floating-Point IP Cores Design Example Files........................................................... 23 1.10. VHDL Component Declaration.............................................................................. 25 1.11. VHDL LIBRARY-USE Declaration........................................................................... 25 2. FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP Core.................................................................................................................... 26 2.1. FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP Features.......................................................................................................26 2.2. FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP Output Latency............................................................................................. 26 2.3. FP_ACC_CUSTOM Intel FPGA IP Resource Utilization and Performance.........................26 2.4. FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP Signals........................................................................................................ 27 2.5. FP_ACC_CUSTOM Intel FPGA IP or Floating Point Custom Accumulator Intel FPGA IP Parameters...................................................................................................29 3. ALTFP_ADD_SUB IP Core.............................................................................................. 30 3.1. ALTFP_ADD_SUB Features.....................................................................................30 3.2. ALTFP_ADD_SUB Output Latency........................................................................... 30 3.3. ALTFP_ADD_SUB Truth Table................................................................................. 30 3.4. ALTFP_ADD_SUB Resource Utilization and Performance.............................................31 3.5. ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers......... 32 3.5.1. ALTFP_ADD_SUM Design Example: Understanding the Simulation Results........32 3.6. ALTFP_ADD_SUB Signals...................................................................................... 33 3.7. ALTFP_ADD_SUB Parameters.................................................................................34 4. ALTFP_DIV IP Core....................................................................................................... 36 4.1. ALTFP_DIV Features............................................................................................. 36 4.2. ALTFP_DIV Output Latency....................................................................................36 4.3. ALTFP_DIV Truth Table..........................................................................................37 4.4. ALTFP_DIV Resource Utilization and Performance..................................................... 37 4.5. ALTFP_DIV Design Example: Division of Single-Precision........................................... 38 Floating-Point IP Cores User Guide Send Feedback 2 Contents 4.5.1. ALTFP_DIV Design Example: Understanding the Simulation Results.................38 4.6. ALTFP_DIV Signals............................................................................................... 39 4.7. ALTFP_DIV Parameters......................................................................................... 41 5. ALTFP_MULT IP Core.................................................................................................... 42 5.1. ALTFP_MULT IP Core Features................................................................................42 5.2. ALTFP_MULT Output Latency..................................................................................42 5.3. ALTFP_MULT Truth Table....................................................................................... 42 5.4. ALTFP_MULT Resource Utilization and Performance................................................... 43 5.5. ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers........ 44 5.5.1. ALTFP_MULT Design Example: Understanding the Simulation Waveform.......... 44 5.6. Parameters......................................................................................................... 45 5.7. ALTFP_MULT Signals.............................................................................................45 6. ALTFP_SQRT................................................................................................................. 47 6.1. ALTFP_SQRT Features...........................................................................................47 6.2. Output Latency....................................................................................................47 6.3. ALTFP_SQRT Truth Table....................................................................................... 48 6.4. ALTFP_SQRT Resource Utilization and Performance...................................................48 6.5. ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers.......... 49 6.5.1. ALTFP_SQRT Design Example: Understanding the Simulation Results.............. 49 6.6. ALTFP_SQRT Signals.............................................................................................50 6.7. ALTFP_SQRT Parameters.......................................................................................51 7. ALTFP_EXP IP Core....................................................................................................... 52 7.1. ALTFP_EXP Features.............................................................................................52 7.2. Output Latency....................................................................................................52 7.3. ALTFP_EXP Truth Table..........................................................................................52 7.4. ALTFP_EXP Resource Utilization and Performance..................................................... 53 7.5. ALTFP_EXP Design Example: Exponential of Single-Precision Format Numbers..............53 7.5.1. ALTFP_EXP Design Example: Understanding the Simulation Results................ 53 7.6. ALTFP_EXP Signals...............................................................................................55 7.7. ALTFP_EXP Parameters......................................................................................... 56 8. ALTFP_INV IP Core....................................................................................................... 57 8.1. ALTFP_INV Features............................................................................................. 57 8.2. Output Latency....................................................................................................57 8.3. ALTFP_INV Truth Table..........................................................................................57 8.4. ALTFP_INV Resource Utilization and Performance..................................................... 58 8.5. ALTFP_INV Design Example: Inverse of Single-Precision Format Numbers ...................58 8.5.1. ALTFP_INV Design Example: Understanding the Simulation Results.................58 8.6. Ports.................................................................................................................. 60 8.7. Parameters........................................................................................................
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