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Floating-Point IP Cores User Guide

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Floating-Point IP Cores User Guide Floating-Point IP Cores User Guide Last updated for Quartus Prime Design Suite: 16.1 Subscribe UG-01058 101 Innovation Drive 2016.12.09 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Contents About Floating-Point IP Cores........................................................................... 1-1 List of Floating-Point IP Cores...................................................................................................................1-1 Installing and Licensing IP Cores.............................................................................................................. 1-2 Design Flow.................................................................................................................................................. 1-3 IP Catalog and Parameter Editor................................................................................................... 1-3 Generating IP Cores (Quartus Prime Pro Edition).....................................................................1-6 Generating IP Cores (Quartus Prime Standard Edition)......................................................... 1-11 Upgrading IP Cores................................................................................................................................... 1-12 Migrating IP Cores to a Different Device................................................................................... 1-14 Floating-Point IP Cores General Features..............................................................................................1-16 IEEE-754 Standard for Floating-Point Arithmetic................................................................................1-16 Floating-Point Formats................................................................................................................. 1-16 Special Case Numbers................................................................................................................... 1-18 Rounding.........................................................................................................................................1-18 Non-IEEE-754 Standard Format............................................................................................................. 1-18 Floating-Points IP Cores Output Latency.............................................................................................. 1-19 Floating-Point IP Cores Design Example Files......................................................................................1-19 VHDL Component Declaration...............................................................................................................1-21 VHDL LIBRARY-USE Declaration......................................................................................................... 1-21 ALTERA_FP_MATRIX_INV IP Core................................................................ 2-1 ALTERA_FP_MATRIX_INV Features.....................................................................................................2-1 ALTERA_FP_MATRIX_INV Output Latency........................................................................................ 2-1 ALTERA_FP_MATRIX_INV Resource Utilization and Performance.................................................2-1 ALTERA_FP_MATRIX_INV Functional Description...........................................................................2-2 Cholesky Decomposition Function............................................................................................... 2-3 Triangular Matrix Inversion........................................................................................................... 2-5 Matrix Multiplication...................................................................................................................... 2-5 Matrix Inversion Operation............................................................................................................2-5 ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format Numbers.................................................................................................................................................. 2-6 ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation Results...... 2-7 Sample Matrix Data..................................................................................................................................... 2-8 ALTERA_FP_MATRIX_INV Signals..................................................................................................... 2-10 ALTERA_FP_MATRIX_INV Parameters..............................................................................................2-11 ALTERA_FP_MATRIX_MULT IP Core.............................................................3-1 ALTERA_FP_MATRIX_MULT Features.................................................................................................3-1 ALTERA_FP_MATRIX_MULT Output Latency....................................................................................3-1 ALTERA_FP_MATRIX_MULT Resource Utilization and Performance.............................................3-1 ALTERA_FP_MATRIX_MULT Functional Description.......................................................................3-2 Altera Corporation TOC-3 ALTERA_FP_MATRIX_MULT Signals................................................................................................... 3-3 ALTERA_FP_MATRIX_MULT Parameters............................................................................................3-5 ALTERA_FP_ACC_CUSTOM IP Core.............................................................. 4-1 ALTERA_FP_ACC_CUSTOM Features.................................................................................................. 4-1 ALTERA_FP_ACC_CUSTOM Output Latency......................................................................................4-1 ALTERA_FP_ACC_CUSTOM Resource Utilization and Performance.............................................. 4-1 ALTERA_FP_ACC_CUSTOM Signals.....................................................................................................4-3 ALTERA_FP_ACC_CUSTOM Parameters..............................................................................................4-4 ALTFP_ADD_SUB IP Core................................................................................ 5-1 ALTFP_ADD_SUB Features...................................................................................................................... 5-1 ALTFP_ADD_SUB Output Latency..........................................................................................................5-1 ALTFP_ADD_SUB Truth Table.................................................................................................................5-1 ALTFP_ADD_SUB Resource Utilization and Performance.................................................................. 5-2 ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers................... 5-3 ALTFP_ADD_SUM Design Example: Understanding the Simulation Results.......................5-3 ALTFP_ADD_SUB Signals.........................................................................................................................5-4 ALTFP_ADD_SUB Parameters................................................................................................................. 5-6 ALTFP_DIV IP Core........................................................................................... 6-1 ALTFP_DIV Features.................................................................................................................................. 6-1 ALTFP_DIV Output Latency..................................................................................................................... 6-1 ALTFP_DIV Truth Table............................................................................................................................ 6-2 ALTFP_DIV Resource Utilization and Performance..............................................................................6-3 ALTFP_DIV Design Example: Division of Single-Precision................................................................. 6-4 ALTFP_DIV Design Example: Understanding the Simulation Results....................................6-4 ALTFP_DIV Signals.................................................................................................................................... 6-6 ALTFP_DIV Parameters............................................................................................................................. 6-7 ALTFP_MULT IP Core........................................................................................7-1 ALTFP_MULT IP Core Features............................................................................................................... 7-1 ALTFP_MULT Output Latency................................................................................................................. 7-1 ALTFP_MULT Truth Table........................................................................................................................ 7-1 ALTFP_MULT Resource Utilization and Performance..........................................................................7-2 ALTFP_MULT Design Example: Multiplication of Double-Precision Format Numbers................. 7-3 ALTFP_MULT Design Example: Understanding the Simulation Waveform..........................7-3 Parameters.....................................................................................................................................................7-4
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