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ADSP-2126X SHARC Processor Hardware Reference, Revision ADSP-2126x SHARC® Processor Hardware Reference Includes ADSP-21261, ADSP-21262 ADSP-21266, ADSP-21267 Revision 5.0, August 2010 Part Number 82-002002-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .............................................................. xxxi Intended Audience ....................................................................... xxxi Manual Contents ........................................................................ xxxii What’s New in This Manual ...................................................... xxxiv Technical or Customer Support .................................................. xxxiv Registration for MyAnalog.com ............................................. xxxv EngineerZone ........................................................................ xxxv Social Networking Web Sites ................................................ xxxvi Supported Processors .................................................................. xxxvi Product Information ................................................................. xxxvii Analog Devices Web Site ..................................................... xxxvii VisualDSP++ Online Documentation ................................. xxxvii Technical Library CD ......................................................... xxxviii Conventions .............................................................................. xxxix INTRODUCTION Design Advantages ........................................................................ 1-1 Architectural Overview ................................................................. 1-4 ADSP-2126x SHARC Processor Hardware Reference iii Contents Processor Core ........................................................................ 1-5 Processing Elements ............................................................ 1-5 Program Sequence Control ................................................. 1-6 Processor Internal Buses ...................................................... 1-9 Processor Peripherals ............................................................. 1-10 Dual-Ported Internal Memory (SRAM) ............................. 1-10 I/O Processor ................................................................... 1-11 Digital Audio Interface (DAI) ........................................... 1-13 Development Tools ..................................................................... 1-13 Differences From Previous SHARCs ............................................ 1-13 Processor Core Enhancements ............................................... 1-14 Processor Internal Bus Changes ............................................. 1-15 Memory Organization Enhancements .................................... 1-15 Parallel Port Enhancements ................................................... 1-15 I/O Architecture Enhancements ............................................ 1-15 Instruction Set Enhancements ............................................... 1-16 PROCESSING ELEMENTS Numeric Formats .......................................................................... 2-3 IEEE Single-precision Floating-point Data Format ................... 2-3 Extended-precision Floating-Point Format ............................... 2-5 Short Word Floating-Point Format .......................................... 2-5 Packing for Floating-Point Data .............................................. 2-6 Fixed-Point Formats ................................................................ 2-7 Setting Computational Modes .................................................... 2-11 iv ADSP-2126x SHARC Processor Hardware Reference Contents 32-Bit Floating-Point Format (Normal Word) ........................ 2-11 40-Bit Floating-Point Format ................................................. 2-13 16-Bit Floating-Point Format (Short Word) ........................... 2-13 32-Bit Fixed-Point Format ..................................................... 2-14 Rounding Mode .................................................................... 2-14 Using Computational Status ........................................................ 2-15 Arithmetic Logic Unit (ALU) ...................................................... 2-16 ALU Operation ..................................................................... 2-16 ALU Saturation ..................................................................... 2-17 ALU Status Flags ................................................................... 2-18 ALU Instruction Summary .................................................... 2-19 Multiply Accumulator (Multiplier) .............................................. 2-22 Multiplier Operation ............................................................. 2-22 Multiplier Result Register (Fixed-Point) ................................. 2-23 Multiplier Status Flags ........................................................... 2-26 Multiplier Instruction Summary ............................................ 2-27 Barrel Shifter (Shifter) ................................................................. 2-29 Shifter Operation .................................................................. 2-30 Shifter Status Flags ................................................................ 2-34 Shifter Instruction Summary .................................................. 2-35 Data Register File ........................................................................ 2-37 Alternate (Secondary) Data Registers ........................................... 2-39 Multifunction Computations ...................................................... 2-40 Secondary Processing Element (PEy) ............................................ 2-44 ADSP-2126x SHARC Processor Hardware Reference v Contents Dual Compute Units Sets ...................................................... 2-45 Dual Register Files ................................................................ 2-47 Dual Alternate Registers ........................................................ 2-48 SIMD and Status Flags .......................................................... 2-48 SIMD (Computational) Operations ....................................... 2-49 PROGRAM SEQUENCER Instruction Pipeline ...................................................................... 3-4 Instruction Cache ......................................................................... 3-5 Bus Conflicts .......................................................................... 3-5 Block Conflicts ....................................................................... 3-7 Using the Cache ...................................................................... 3-8 Optimizing Cache Usage ......................................................... 3-9 Branches and Sequencing ............................................................ 3-11 Conditional Branches ............................................................ 3-12 Delayed Branches .................................................................. 3-13 Loop and Status Stacks and Sequencing ....................................... 3-16 Conditional Sequencing .............................................................. 3-18 Core Stalls .................................................................................. 3-21 Execution Stalls ..................................................................... 3-23 DAG Stalls ........................................................................... 3-24 Memory Stalls ....................................................................... 3-24 IOP Register Stalls ................................................................ 3-24 DMA Stalls ........................................................................... 3-24 Loops and Sequencing ................................................................ 3-25 vi ADSP-2126x SHARC Processor Hardware Reference Contents Restrictions on Ending Loops ................................................ 3-27 Restrictions on Short Loops ................................................... 3-28 Loop Address Stack ............................................................... 3-31 Loop Counter Stack .............................................................. 3-32 Reading From LCNTR in a LOOP .................................... 3-36 SIMD Mode and Sequencing ...................................................... 3-36 Conditional Compute Operations .......................................... 3-38 Conditional Branches and Loops ........................................... 3-38 Conditional Data Moves .......................................................
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