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Plastic Ball Grid Array (PBGA) Thermal Cycle Reliability Evaluation

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Plastic Ball Grid Array (PBGA) Thermal Cycle Reliability Evaluation National Aeronautics and Space Administration Plastic Ball Grid Array (PBGA) Thermal Cycle Reliability Evaluation Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California http://nepp.nasa.gov National Aeronautics and Space Administration Plastic Ball Grid Array (PBGA) Thermal Cycle Reliability Evaluation NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.29 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov i This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. ©2017 California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity. The author extends his appreciation to program managers of the National Aeronautics and Space Administration Electronics Parts and Packaging (NEPP) Program, including Michael Sampson, Ken LaBel, and Dr. Douglas Sheldon for their continuous support and encouragement. ii OBJECTIVES AND PRODUCTS The objective of this task is to evaluate thermal cycle behavior of advanced plastic ball grid array (PBGA) — commercial-off-the-shelf (COTS) —packages and assemblies. The most advanced and high-density PBGAs come in the flip-chip ball grid array (FCBGA) configurations with inputs/outputs (I/Os) of more than 2000 with 1-mm pitch. PBGAs with lower than 1-mm pitch have generally lower than 1000 I/Os. Wafer-level packages (WFLPs); however, come in both higher I/Os and lower pitches. Understanding the process issues, quality indicators, quality assurance (QA) control parameters, and reliability under harsher thermal cycle environments is important for low-risk infusion of these advanced electronics packages. This report presents the test matrix for various PBGA packages; PCB design, assembly parameters, and assembly reliability characterizations under two thermal cycle conditions. It covers a gamut of area-array packaging technologies including PBGAs, fine-pitch BGAs (FPBGAs), WFLPs, and 3D-stack BGAs. A number of these BGA packages were not available in daisy-chain format, and support from the package suppliers enabled purchase or in-kind contribution to this activity. The new array packages required much longer lead-time for delivery (nearly nine months) and thus created its associated challenges. However, collaboration allowed developing a comprehensive test matrix and inclusion of numerous advanced package types for board-level thermal cycle evaluation. The report presents the test matrix approaches, the description of the packages, the board materials and layup and surface finishes, assembly approaches, and thermal cycle test result to 200 cycles under two severe conditions. Thermal cyclings were performed in the range of -55 to 100°C and thermal shock (TS) cycle conditions in the range of -65°C to 150°C. X-ray, Optical, and SEM images for the as assembled and after 200 thermal cycles are presented. Daisy-chain resistances changes were monitored per IPC 9701 [14], and additional evaluations were performed after 200 TS cycles by X-sectioning of a number of PBGA assemblies to confirm no-failure or failure observation. Furthermore, a dye-and pry technique was also performed to evaluate crack propagation of a large section of assemblies for failure analysis characterization. The qualification guidelines based on the test results will facilitate NASA projects’ use of very dense and newly available field programmable gate array (FPGA) and memory packages, allowing greater processing power in a smaller board footprint and a lower system weight. Key Words: Ball grid array, BGA, fine pitch BGA, FPGA, wafer level package, WLF, 3D stack, solder joint reliability, thermal cycle, thermal shock cycle, ENEPIG iii TABLE OF CONTENTS Objectives and Products ............................................................................................................................................ iii 1.0 Backround ........................................................................................................................................................... 1 1.1 Purpose ........................................................................................................................................................ 1 1.2 Area-Array Packaging Technology ............................................................................................................... 1 1.2.1 Advantages of PBGAs ....................................................................................................................... 2 1.2.2 Disadvantages of PBGAs .................................................................................................................. 2 1.3 Chip Scale Package (CSP) .......................................................................................................................... 3 1.4 Wafer Level Packages (WLPs) or Wafer Level Chip Scale Packages (WLCSPs) ....................................... 4 2.0 Experimental Approaches .................................................................................................................................. 5 2.1 Test Matrix ................................................................................................................................................... 5 2.2 Package Styles ............................................................................................................................................ 5 2.3 PCB Design and Surface Finish ................................................................................................................... 7 2.4 PCB Optical Inspection: ENEPIG vs. HASL PCB Finish .............................................................................. 9 2.5 Assembly Parameters ................................................................................................................................ 10 2.6 Optical Inspection after Assembly .............................................................................................................. 11 2.7 X-ray Characterization after Assembly ....................................................................................................... 12 3.0 Thermal Cycle and Shock Cycle Test Results (–55/100°C/ –65/150°C) ........................................................ 18 3.1 Test Condition/Results (–55/100°C) .......................................................................................................... 18 3.2 Test Condition/Results (–65/150°C) .......................................................................................................... 21 4.0 Conclusions ....................................................................................................................................................... 29 5.0 Acronyms and Abbreviations .......................................................................................................................... 31 6.0 References ......................................................................................................................................................... 32 iv 1.0 BACKROUND 1.1 Purpose Extensive work had been carried out to address reliability of the previous generations of conventional wire- bonded PBGA and FPBGA assemblies [1-11]. The previous work included process optimization, assembly reliability characterization, and the use of inspection tools, including X-ray and optical microscopy, for quality control and damage detection due to environmental exposures. This investigated thermal cycle reliability of the new generation of PBGAs—the current and near future area-array packaging technologies. The down selected PBGAs for evaluation included a large-size FCBGA with 1924 balls and 1-mm pitch (distance between centers of the two adjacent balls) as well as numerous other PBGA- and FPGA-package styles. It also includes, lower-pitch chip-scale packages (CSPs) and WLPs, as low as 0.3-mm pitch with ball counts as high as 1600 balls, and a 3D-stack BGA package. This report presents test matrix design, package daisy-chain patterns, detailed design of PCB, test vehicle design, and detailed information with representative images of various PBGA package styles. Numerous approaches for assembly of these packages were also implemented. After successful assembly of a number of test vehicles, they were subjected to 200 thermal cycles (TC) or shock cycles (TS). They were subjected to TC in the range of -55 to 100°C using single chamber and TS cycles in the range of -65°C to 150°C using two chambers. X-ray, optical, and SEM images for the as assembled and after 200 thermal cycles are presented. In addition to daisy-chain resistance evaluation monitoring, evaluation was also performed by X-sectioning of a number of PBGA assemblies
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