RF Front-End Circuits and Architectures for Iot/LTE-A/5G Connectivity

Wireless Communications and Mobile Computing

RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity

Lead Guest Editor: Yan Li Guest Editors: Donald Y. C. Lie, Chaojiang Li, Dixian Zhao, and Christian Fager RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity Wireless Communications and Mobile Computing

RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity

This is a special issue published in “Wireless Communications and Mobile Computing.” All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Editorial Board

Javier Aguiar, Spain Maria Fazio, Italy Imadeldin Mahgoub, USA Wessam Ajib, Canada Mauro Femminella, Italy Pietro Manzoni, Spain Muhammad Alam, China Manuel Fernandez-Veiga, Spain Álvaro Marco, Spain Eva Antonino-Daviu, Spain Gianluigi Ferrari, Italy Gustavo Marfia, Italy Shlomi Arnon, Israel Ilario Filippini, Italy Francisco J. Martinez, Spain Leyre Azpilicueta, Mexico Jesus Fontecha, Spain Davide Mattera, Italy Paolo Barsocchi, Italy Luca Foschini, Italy Michael McGuire, Canada Alessandro Bazzi, Italy A. G. Fragkiadakis, Greece Nathalie Mitton, France Zdenek Becvar, Czech Republic Sabrina Gaito, Italy Klaus Moessner, UK Francesco Benedetto, Italy Óscar García, Spain Antonella Molinaro, Italy Olivier Berder, France Manuel García Sánchez, Spain Simone Morosi, Italy Ana M. Bernardos, Spain L. J. García Villalba, Spain Kumudu S. Munasinghe, Australia Mauro Biagi, Italy José A. García-Naya, Spain Enrico Natalizio, France Dario Bruneo, Italy Miguel Garcia-Pineda, Spain Keivan Navaie, UK Jun Cai, Canada A.-J. García-Sánchez, Spain Thomas Newe, Ireland Zhipeng Cai, USA Piedad Garrido, Spain Wing Kwan Ng, Australia Claudia Campolo, Italy Vincent Gauthier, France Tuan M. Nguyen, Vietnam Gerardo Canfora, Italy Carlo Giannelli, Italy Petros Nicopolitidis, Greece Rolando Carrasco, UK Carles Gomez, Spain Giovanni Pau, Italy Vicente Casares-Giner, Spain Juan A. Gomez-Pulido, Spain Rafael Pérez-Jiménez, Spain Luis Castedo, Spain Ke Guan, China Matteo Petracca, Italy Ioannis Chatzigiannakis, Greece Antonio Guerrieri, Italy Nada Y. Philip, UK Lin Chen, France Daojing He, China Marco Picone, Italy Yu Chen, USA Paul Honeine, France Daniele Pinchera, Italy Hui Cheng, UK Sergio Ilarri, Spain Giuseppe Piro, Italy Ernestina Cianca, Italy Antonio Jara, Switzerland Vicent Pla, Spain Riccardo Colella, Italy Xiaohong Jiang, Japan Javier Prieto, Spain Mario Collotta, Italy Minho Jo, Republic of Korea Rüdiger C. Pryss, Germany Massimo Condoluci, Sweden Shigeru Kashihara, Japan Junaid Qadir, Pakistan Daniel G. Costa, Brazil Dimitrios Katsaros, Greece Sujan Rajbhandari, UK Bernard Cousin, France Minseok Kim, Japan Rajib Rana, Australia Telmo Reis Cunha, Portugal Mario Kolberg, UK Luca Reggiani, Italy Igor Curcio, Finland Nikos Komninos, UK Daniel G. Reina, Spain Laurie Cuthbert, Macau Juan A. L. Riquelme, Spain Abusayeed Saifullah, USA Donatella Darsena, Italy Pavlos I. Lazaridis, UK Jose Santa, Spain Pham Tien Dat, Japan Tuan Anh Le, UK Stefano Savazzi, Italy AndrédeAlmeida,Brazil Xianfu Lei, China Hans Schotten, Germany Antonio De Domenico, France Hoa Le-Minh, UK Patrick Seeling, USA Antonio de la Oliva, Spain Jaime Lloret, Spain Muhammad Z. Shakir, UK Gianluca De Marco, Italy Miguel López-Benítez, UK Mohammad Shojafar, Italy Luca De Nardis, Italy Martín López-Nores, Spain Giovanni Stea, Italy Liang Dong, USA Javier D. S. Lorente, Spain Enrique Stevens-Navarro, Mexico Mohammed El-Hajjar, UK Tony T. Luo, Singapore Zhou Su, Japan Oscar Esparza, Spain Maode Ma, Singapore Luis Suarez, Russia Ville Syrjälä, Finland Reza Monir Vaghefi, USA Jie Yang, USA Hwee Pink Tan, Singapore Juan F. Valenzuela-Valdés, Spain Sherali Zeadally, USA Pierre-Martin Tardif, Canada Aline C. Viana, France Jie Zhang, UK Mauro Tortonesi, Italy Enrico M. Vitucci, Italy Meiling Zhu, UK Federico Tramarin, Italy Honggang Wang, USA Contents

RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity Yan Li ,DonaldY.C.Lie , Chaojiang Li, Dixian Zhao ,andChristianFager Editorial(2pages),ArticleID1438060,Volume2018(2018)

A Review of 5G Power Amplifier Design at cm-Wave and mm-Wave Frequencies D. Y. C. Lie ,J.C.Mayeda,Y.Li,andJ.Lopez Review Article (16 pages), Article ID 6793814, Volume 2018 (2018)

A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications Sizheng Chen, Tingting Shi, Lei Ma, Cheng Kang, Na Yan ,andHaoMin Research Article (10 pages), Article ID 9130910, Volume 2018 (2018)

A 0.45 W 18% PAE E-Band Power Amplifier in 100 nm InGaAs pHEMT Technology Dixian Zhao and Yongran Yi Research Article (6 pages), Article ID 8234615, Volume 2018 (2018)

Digital Predistortion of Ultra-Broadband mmWave Power Amplifiers with Limited Tx/Feedback Loop/Baseband Bandwidth Chao Yu , Qianyun Lu, Honglei Sun, Xingwang Wu, and Xiao-Wei Zhu Research Article (11 pages), Article ID 4510243, Volume 2018 (2018)

A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO Lei Ma, Na Yan ,SizhengChen,YangziLiu,andHaoMin Research Article (8 pages), Article ID 4968391, Volume 2018 (2018)

A Novel Quadrature-Tracking Demodulator for LTE-A Applications Kang-Chun Peng and Chan-Hung Lee Research Article (8 pages), Article ID 8712414, Volume 2018 (2018) Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 1438060, 2 pages https://doi.org/10.1155/2018/1438060

Editorial RF Front-End Circuits and Architectures for IoT/LTE-A/5G Connectivity

Yan Li ,1 Donald Y. C. Lie ,2 Chaojiang Li,3 Dixian Zhao ,4 and Christian Fager5

Anokiwave Inc., Austin, USA Texas Tech University, Lubbock, USA GlobalFoundries, Burlington, USA Southeast University, Nanjing, China Chalmers University of Technology, Gothenburg, Sweden

Correspondence should be addressed to Yan Li; [email protected]

Received 12 September 2018; Accepted 12 September 2018; Published 1 October 2018

Copyright © 2018 Yan Li et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Te concepts of Internet-of-Tings (IoT) and Internet-of- special issue. Te accepted papers cover a wide range of Everything (IoE) (e.g., smart city) have been driving the research subjects in RF/mmWave circuits and architectures evolution of wireless communications. With ever-increasing to meet the increasing demands of 5G and beyond. demand for higher data rates, service carriers have improved Te paper entitled “A Review of 5G Power Amplifer the existing 4th-generation (4G) networks with carrier aggre- Design at cm-Wave and mm-Wave Frequencies” by Dr. D. Y. gation and multi-input multi-output (MIMO) antenna tech- C. Lie et al.surveyedsomeadvanced5Gpoweramplifer(PA) niques, the key features of LTE-Advanced (LTE-A). To evolve designs in various device technologies including wideband beyond 4G, the 5th-generation (5G) networks need to be Doherty PA in GaAs and in SiGe; stacked PA on SOI scalable, versatile, and energy-smart for the hyperconnected CMOS; diferential bulk CMOS PA with neutralization cap IoE world. By employing advanced modulation schemes, and transformers; CMOS DPA (digital PA); fully monolithic massive MIMO, beamforming, and mmWave carriers, the GaN PA; highly integrated RFFE with LNA, PA, phase shifer, 5G connectivity is expected to achieve signifcantly enhanced data rate (10 Gbps peak data rate), universal coverage, spec- switches for phased-array MIMO, and so forth. Tese PA tral/spatial diversity/efciency, and/or minimized latency designs present potential solutions for successful cmWave (sub-1ms). and mmWave 5G front-end IC designs. Te emerging connectivity applications have imposed Te paper entitled “A Low Power Impedance Transparent new yet stringent specs to the design of RF front-ends. Receiver with Linearity Enhancement Technique for IoT Furthermore, due to various market factors, designers are Applications” by S. Chen et al. presented a reconfgurable facing additional complexities such as multiband, multimode receiver (Rx) with tunable channel fltering and narrow- (2G/3G/4G/LTE-A/5G, WiFi, Bluetooth, GPS, etc.), small band input matching at the Rx input. Te passive mixer form factor while balancing cost competitiveness, ever-better and active feedback LNA are used in the receiver to further performance, and longer battery life. Overcoming these transfer the baseband impedance to Rx input. A 3rd-order challenges requires high performance innovative solutions. active-RC flter is designed with current-efcient feedforward Te motivation of this special issue is to publish the compensated OTA. Te digital-to-time converter (DTC) state-of-the-art RF circuit and architecture solutions to assisted fractional-N all-digital phase-locked loop (ADPLL) help address the design challenges of the IoT/LTE-A/5G is codesigned with the receiver to meet the IoT require- connectivity. Afer a rigorous two-round review process, 6 ments. By utilizing blocker fltering and derivative superposi- outstanding papers have been accepted for inclusion in this tion techniques, the proposed receiver architecture achieves 2 Wireless Communications and Mobile Computing outstanding performances for low power IoT applications, such as IEEE 802.11ah and NB-IoT. Te paper entitled “A 0.45 W 18% PAE E-Band Power Amplifer in 100 nm InGaAs pHEMT Technology” by Dr. D. Zhao and Y. Yi presented a fully integrated PA using a 4-way zero-degree combiner (in each unit PA) and a 2- 2 way �/2 combiner to improve the output power. Te 5 mm GaAs PA outperforms the CMOS PAs for output power while achieving low cost, high yield, and easy foundry access comparing to InP and GaN PAs. Terefore, the proposed design provides attractive solutions for future long-haul point-to-point communications at E-band. Te paper entitled “Digital Predistortion of Ultra- Broadband mmWave Power Amplifers with Limited Tx/Feedback Loop/Baseband Bandwidth” by C. Yu et al. proposed a novel DPD technique to signifcantly reduce the bandwidth requirements for the transmitter (Tx), feedback loop, and baseband in the context of ultra-broadband mmWave scenarios. Tis proposed technique will provide the capability of linearizing mmWave PAs with afordable resources for ultra-broadband signals, which can largely extend the DPD regime into 5G mmWave era. Te paper entitled “A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO” by L Ma et al. presented a complementary Class-C digitally controlled oscillator (DCO) with diferential transistor pairs. Te transistors are dynamically biased by feedback loops separately to ensure the robust oscillation start-up with low power consumption. By employing three switched capacitor arrays and a fractional capacitor array dithered by sigma-delta modulator, 51.5% frequency tuning range, and less than 0.1 ppm frequency resolution are achieved. In the paper entitled “A Novel Quadrature-Tracking Demodulator for LTE-A Applications” by K.-C. Peng and C.-H. Lee, the demodulator uses a novel quadrature phase- locked loop (QPLL) to simultaneously track the I/Q phases of the received signal, thus reducing its sensitivity to the quadrature imbalance in a system. Te 2.1∼2.5 GHz QPLL- based demodulator can efectively demodulate an 18 Mbps LTE-A signal with a quadrature imbalance of up to 15 degrees. Such a quadrature-tracking ability makes the proposed architecture well suited to LTE-A systems or even more advanced communication systems. Yan Li Donald Y. C. Lie Chaojiang Li Dixian Zhao Christian Fager

Conflicts of Interest We, the Guest Editorial team, as a whole do not have any conficts of interest or private agreements with companies that would afect, or are perceived to afect, the neutrality or objectivity of research. Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 6793814, 16 pages https://doi.org/10.1155/2018/6793814

Review Article A Review of 5G Power Amplifier Design at cm-Wave and mm-Wave Frequencies

D. Y. C. Lie ,1 J. C. Mayeda,1 Y. Li,2 and J. Lopez1,3

1 Department of Electrical and Computer Engineering, Texas Tech University, Lubbock, TX, USA 2Qorvo Phoenix Design Center, Phoenix, AZ, USA 3NoiseFigure Research LLC, Lubbock, TX, USA

Correspondence should be addressed to D. Y. C. Lie; [email protected]

Received 12 November 2017; Accepted 28 January 2018; Published 4 July 2018

Academic Editor: Jesus Fontecha

Copyright © 2018 D. Y. C. Lie et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Te 5G wireless revolution presents some dramatic challenges to the design of handsets and communication infrastructures, as 5G targets higher than 10 Gbps download speed using millimeter-wave (mm-Wave) spectrum with multiple-input multiple-output (MIMO) antennas, connecting densely deployed wireless devices for Internet-of-Everything (IoE), and very small latency time for ultrareliable machine type communication, etc. Te broadband modulation bandwidth for 5G RF transmitters (i.e., maximum possibly even above 1 GHz) demands high-power efciency and stringent linearity from its power amplifer (PA). Additionally, the phased-array MIMO antennas with numerous RF front-ends (RFFEs) will require unprecedented high integration level with low cost, making the design of 5G PA one of the most challenging tasks. As the centimeter-wave (cm-Wave) 5G systems will probably be deployed on the market earlier than their mm-Wave counterparts, we will review in this paper the latest development on 15 GHz and 28 GHz 5G cm-Wave PAs extensively, while also covering some key mm-Wave PAs in the literature. Our review will focus on the available options of device technologies, novel circuit and system architectures, and efciency enhancement techniques at power back-of for 5G PA design.

1. Introduction fxed wireless deployment, as Verizon has proposed its own 5G specifcation as “Verizon 5G wireless technology” or Te Fifh-Generation (5G) mobile networks is bringing in the “V5G”. On the other hand, in March 2017, 3GPP published its latest wireless revolution, enabling wireless download speed frst study item reports on the 5G New Radio (NR), the next exceeding 10 Gbps for eMBB (enhanced Mobile Broadband) generation 5G cellular network standard, and the likely global applications, with 100x more wireless connected devices than 5G standard for a new OFDM-based air interface designed 4G for mMTC (massive machine type communication) to to support the wide variation of 5G device-types, services, enable IoE (Internet-of-Everything), and sub-1 ms latency for deployments, and spectrum. Te biggest diference in V5G instant actions with UR/LL, mMTC (ultrareliable machine and 5G NR is the application focus: V5G is limited to fxed type communication) [1]. It will be extremely challenging wireless access at 28 GHz, but the 5G NR is targeting all to achieve those aggressive 5G performance metrics all at wireless communications applications (fxed and mobile) for once, and thus the 5G revolution is expected to be happening all frequencies. V5G intended to deploy a high density of in stages. In the prestandard 5G era at 2014, a benchmark cm-Wave/mm-Wave small cells (i.e., base stations) that will 5 Gbps speed was already achieved in a live over-the-air communicate with commercial box set UEs, such as a wireless test network from Ericsson using an innovative new radio MODEM or a cable box. With the billions of wirelessly interface concept in combination with advanced MIMO connected devices available for 5G, it becomes particularly technology with wider bandwidths and shorter transmission critical that one must minimize the power consumption time intervals at 15 GHz. For the higher frequency cm- of individual wireless devices and back station/base station Wave/mm-Wave 5G to take place, it will probably start from (BST) as well as the overall 5G system power consumption 2 Wireless Communications and Mobile Computing

Figure 1: An example of a highly integrated 2D RF FEM array with phased-array 5G MIMO antennas and the steered radiation beam.

to achieve the critical reduction in energy usage spec by 30 GHz. In this paper, we will focus on surveying the latest almost 90% over existing 4G networks [2]. Instead of only key development and design examples on the cm-Wave 5G PA using the sub-6 GHz spectra like the 2G/3G/4G cellular design (i.e., at 15 and 28 GHz), since the cm-Wave 5G devices networks have done in the past, at least some of the 5G and networks will most likely be deployed earlier than their devices and networks will also operate at the higher cm-Wave mm-Wave counterparts. In a particular case, Qualcomm is and mm-Wave frequencies to beneft from larger available accelerating mobile deployments for smartphones based on spectrum bandwidth, smaller-sized massive MIMO phased- 5G NR Release-15 specifcation, where the cm-Wave RF front- array antennas for 3-Dimensional Beamforming (3DBF). end design is optimized in a smartphone form factor, with It is well-known the performance of a radio-frequency multi-MIMO, adaptive beamforming, and beam tracking, power amplifer (RF PA) can ofen dominate the overall supporting 5G NR interoperability testing and over-the- transmitter (TX) performance, as its power-added efciency air trials [8]. Many other companies are devoting lots of (PAE) dictates the power and heat dissipation for the entire resources in realizing the 5G revolution as well, where we TX. For enhanced user experience and massive MIMO believe the sub-6 GHz bands and the cm-Wave frequencies antennas at cm-Wave/mm-Wave frequencies, the 5G system will be utilized frst. Note the 15-GHz band was expected to will require more PAs to be integrated in the RF front-end be allocated for 5G, but in WRC15 it was not assigned as a modules (FEMs), making the design of a 5G PA more critical candidate band. than that of a 4G PA. To any successful commercial 5G Te outline of this paper is as follows. Section 2 discusses � application, the output power ( OUT), linearity, reliability, the device technology choices for 5G PAs. Sections 3 and cost, and form factors of a PA are all very important. 4 present some latest design examples of 5G PAs at 15 GHz Figure 1 illustrates an example of attractive 5G FEM and 28 GHz, respectively. Section 5 presents several efciency IC array design in cm-Wave/mm-Wave for phased-array enhancement techniques at power back-of for both cm-Wave MIMO antennas. Te 5G PA, low-noise amplifer (LNA), T/R and mm-Wave PAs, including dynamic supply modulations, switches, phase shifer, and various passives are all integrated all-digital architecture, and broadband Doherty PA with into the FEM IC as shown in Figure 1, whose architecture digital tuning. is rather diferent from their 3G/4G counterparts and also with a much higher level of IC integration. In some cases 2. The Choice of Device Technologies 5G PA the antennas may be directly packaged on top of the FEM IC on the wafer-scale to achieve even higher integration with Today, the majority of handset PAs are still designed in reasonable performance [3, 4]. Te high integration require- III–V semiconductor devices technologies because of their ment of FEM ICs and massive antenna systems may favor superior frequency responses, breakdown robustness, and silicon-based technologies for 5G mobile products, even faster time-to-market than silicon-based counterparts [9, 10]. � though GaAs or GaN FEMs usually have better performances Since today’s base station PAs require rather high OUT,they than their silicon counterparts [3–7]. In addition to the are largely designed in low-cost silicon LDMOS (Laterally high integration requirement, as the TX operation frequency Difused MOSFETs) for sub-3.5 GHz bands, and in GaAs or � moves to cm-Wave/mm-Wave frequencies, it has been well- GaN at higher frequencies, depending on the exact OUT recognized as a very difcult task to design a high-efciency requirements [11, 12]. For example, GaN devices are capable linear PA to overcome the overheating issue for successful of operating at a RF power density of 6–8 W/mm of gate massive MIMO realization. Note that we consider the 15 GHz periphery at 4G cellular bands and can deliver an impressive and 28 GHz devices as operating at cm-Wave but not mm- power density of 3.6 W/mm at 86 GHz in continuous-wave � Wave frequencies in this review, even though the industry (CW) operation [11]. In a separate work, OUT of 3.6 Watt ofen “mis-labels” those devices as “mm-Wave devices” for at 83 GHz was achieved in pulse mode [11] that silicon- marketing purpose. For example, Qualcomm’s 5G New Radio based PA technologies (LDMOS, SiGe, and CMOS) simply (NR) demonstrated an impressive “5G mm-Wave” prototype cannot match. However, silicon-based RF PAs do have the phone in A.D. 2017 operating at 28 GHz, but it should really advantages in ofering higher monolithic integration with be called as cm-Wave prototype as it never operates above added functionalities (e.g., on-chip digital control/selection Wireless Communications and Mobile Computing 3

� Table 1: Projected 5G small cells RF OUT requirements for cm-Wave/mm-Wave frequencies (estimated). � RF Number of RF OUT Per Potential PA Cell Type � OUT(dBm) Users PA (dBm) Technologies Femtocell 0–24 1 to 20 <20 CMOS/SOI, SiGe, GaAs Picocell 24–30 20 to 100 <20 CMOS/SOI, SiGe, GaAs Microcell 30–40 100 to 1000 <27 GaAs, GaN, CMOS/SOI, SiGe Macrocell 40–47 1000+ >27 GaN, GaAs

on power detection, adaptive matching, and digital pre- 3 distortion (DPD)), which can translate to lower cost and GaN (high power) 2 smaller sizes attractive for broadband multimode multiband GaAs PHEMT GaN (low power) 5G handsets with massive MIMO, as suggested in Figure 1. MMIC Actually, SiGe PAs are already in billions of RF FEMs for 10

WLAN and 3G/4G handsets today, even though III–V based SiGe 16-way PAs still dominate the handset PA market. For the next few 1 CMOS SOI 4-stack [IMS’09] [ISSCC’13] CMOS SOI 4-stack InP/MHEMT years, the sub-6 GHz “5G-like” LTE-Advanced systems with CMOS 8-way [TMTT’15] MMIC MIMO will be tested frst to pave the way for the above- Output Power (W) −1 CMOS SOI 4-stack [TMTT’14] CMOS 4-way 6 GHz mobile networks to come. Because of the higher cm- Diferential Silicon PAs [ISSCC’14] Wave/mm-Wave carrier frequency and the massive MIMO −2 technologies to be deployed, an individual “true-5G” handset 1110 100 000 � Frequency (GHz) or small-cell PA is expected to have lower OUT requirements than those currently used in 4G LTE applications. As an Figure 2: Recently published RF PA performances in silicon and example, Table 1 shows our estimated � requirements for � OUT III–V technologies in the literature with OUT versus frequency 5G small cells and large cells applications. One can see the [6]. Note even the state-of-the-art silicon PAs (in the “dashed 5G PAs used in femtocells and picocells both have fairly low rectangular box”) have difculties reaching Watt level RF output at � < OUT requirements per PA (i.e., 20 dBm), which means they mm-Wave frequencies. could be realizable by silicon-based PAs. A 5G macrocell, on the other hand, will probably need to utilize GaN or GaAs � PAs due to their larger OUT requirements. Power efciency, � robustness, and cost will eventually determine the preferred higher OUT and PAE requirements. Cost and integration device technology for a given 5G PA application. level will also be critical factors in deciding the preferred To see which PA device technologies can be the optimal technology for a given 5G PA implementation. Nakatani 2 oneforagiven5Gapplications,wehaveplottedquitea et al. recently reported an impressive 15 GHz 5 × 5mm few data points corresponding to the literature’s latest cm- FEM IC that integrates a three-stage PA, a two-stage LNA, Wave/mm-Wave PAs in Figure 2 for various PA technologies. and a T/R switch in a 0.15 �mGaAstechnologyfor5G We have shown several best silicon-based PAs, where CMOS wideband massive MIMO [23]. Te fnal stage of the PA is SOI stacked PAs with power combining and stacked SiGe PA designed with a novel Doherty confguration using an output � � demonstrated the best OUT for mm-Wave silicon PAs [5–22]. parasitic capacitance ( ��) compensation method as shown � ∼ For applications where OUT needs to be above 3to10Watts in Figure 3. Doherty topology was chosen to mitigate the at 15GHz and above, Figure 2 indicates that state-of-the-art PA’s efciency degradation at large power back-of; however, silicon PAs still have difculties competing with their III–V it is difcult to design a Doherty PA with high PAE over counterparts, being not able to exceed a few Watts RF output broadband due to the frequency-dependent �/4 inverter at cm-Wave/mm-Wave frequencies while the GaAs/GaN PAs required for output load modulation. For a conventional can. Note most reported GaN X/Ku-bands PAs were for high- Doherty PA, it is well-known that the main amplifer (main) power defense or aerospace applications, but here we expect and auxiliary amplifer (Aux) matching circuits are directly GaN PA can be also be very attractive for the 5G PA market connected at the extrinsic reference plane of the transistors � ∼ � at OUT 3–10 Watts level. (containing output parasitic cap ��). Te matching networks transform the transistor’s output impedance to 50 Ω,anda 3. 5G PA Designed at 15 GHz �/4 inverted transmission line (TL) is connected afer main, in Several Device Technologies which can vary the load at intrinsic nodes depending on � OUT levels. A conventional Doherty PA thus can realize � � As mentioned above, the estimated OUT requirements for high PAE at large OUT back-of for narrow-band signals. 5G small cells (femtocells and picocells) are fairly low per However, for the proposed wideband 15 GHz Doherty PA in PA (i.e., <20 dBm), meaning that they could be realizable by Figure 3, the frequency-dependent matching is removed with � � silicon-based PAs according to Figure 2. A 5G macrocell, on �� neutralization using the shunt inductors ( res)through the other hand, may need to be GaN or GaAs PAs due to their resonance. Afer the resonator tank of the main amplifer 4 Wireless Communications and Mobile Computing

25.1 dBm and a peak PAE of 32.4% at 13.5 GHz. Te small- signal −3 dB bandwidth is 2.6 GHz (∼20%). Te PA provides � the best combination of saturated OUT and PAE reported to date for 15 GHz CMOS PAs. Note most reported GaN X/Ku-bands PAs were for high- power defense or aerospace applications, but we expect GaN � ∼ PAcanbeveryattractiveforthe5GPAmarketat OUT 3–10 Watts level per PA. A high-efciency two-stage fully integrated 15 GHz PA designed in a low-cost 0.25 �mGaN/SiC Figure 3: A simplifed equivalent circuit of the output portion of the process was reported recently and shown in Figure 6 [26]. � wideband 15 GHz Doherty PA in a 0.15 mGaAstechnology[23],© Postlayout simulation shows that the PA has a high small- 2017 IEEE. signal gain �21 of 24 dB, �12 = −41.2 dB, �22 = −10.0 dB, and � − � 11 = 12.3 dB at 15 GHz. Its peak PAE reaches 36.6% at OUT = 34 dBm for CW input. Postlayout simulations also suggest that dynamic supply modulation from 28V to 10V may modestly improve the PA’s efciency at power back-of. When the PA is driven with 5/10/20 MHz LTE 16 QAM modulated signals, the simulated output spectra and adjacent channel � leakage ratio (ACLR) at OUT,Linear =29.6dBmpassedtheLTE spectrum emission mask (SEM) without any predistortion, and the wider modulated signal bandwidth from 5 MHz to 20 MHz does not noticeably worsen the PA linearity in the RF + digital cosimulations. State-of-the-art literature survey

2 suggests this highly efcient and linear 15 GHz GaN PA Figure 4: A prototype 64-element array panel (80 × 80 mm )with � ∼ × 2 � may be quite attractive for 5G PA applications at OUT its RF FEM (5 5mm ) for 5G cm-Wave applications in a 0.15 m 1 Watt level, as the GaN PA has the smallest die size (1.78 GaAs technology [23, 24], © 2017 IEEE. 2 × 0.78 mm ), the 2nd highest peak PAE (i.e., 36.6%), and is the only one reported passing the output SEM specs with LTE 16 QAM input (�� = 15.0%), even though it is in Figure 3, a �/4 inverted TL is connected for the load designed with the lowest device �� of ∼27 GHz. However, � modulation at the intrinsic node depending on its OUT.Te measurement data is required to corroborate the postlayout � characteristic impedance opt in Figure 3 is the optimum simulation results. � impedance for high OUT performance. Simulations suggest the bandwidth for efective load modulation for high PAE 4. 5G PA Designed at 28 GHz attheintrinsicnodecanbe+/−10% at 15 GHz. Measured in Several Technologies data shows the fnal stage Doherty PA and the three-stage PA achieved a drain efciency (DE) at 8 dB back-of of 22% and Te work in [27] is one of the earliest examples from the � 12%, respectively, at DD =4Vat14.5–15.0GHz. industry that reports the design and its measured results Apictureofthe15GHzRFFEMpackagedina32-lead of a fully integrated 28 GHz FEM IC, which is designed � � /� QFN using the above 3-stage GaAs PA is shown in Figure 4, in a 0.15 m GaAs pHEMT process (nominal � max = together with the prototyped 64 elements array panel for 65/95 GHz, drain-to-gate breakdown voltage = 12 V). Te die 5G massive MIMO BST/small-cell applications [23, 24]. Te picture of the FEM IC is shown in Figure 7, which includes a FEM includes all RF active components (LNA, PA, phase three-stage PA, a three-stage LNA, and a single-pole, double- shifer, switch, etc.), RF passive components (antenna, flters, throw T/R switch. Te PA consists of three common-source combiner/divider, etc.), power management, and control ICs. stages with gate peripheries of 160 �m, 300 �m, and 750 �m. Te RF substrate is a multilayer PCB with RF passives in its Measured device data suggested a maximum power density internal layer. Each IC and external interface are mounted of 630 mW/mm, and thus the output stage gate periphery on its surface, while on the back the corresponding antenna was calculated to achieve 26 dBm ��,1 �� on die, which can elements are separated by a distance of �/2. achieve 30 dBm linear EIRP (equivalent isotropically radiated For silicon-based cm-Wave 5G PAs, as indicated in power) in uplink, assuming these FEM ICs are used in a four Figure 2, recent literature shows CMOS SOI stacked PAs elements array. Te gate peripheries of the driver stages were with/without power combining and stacked SiGe PA have selected to maintain high PAE with sufcient gain to drive the � demonstrated the best OUT [15–22]. An example is given in last stage into compression. All stages were biased in Class Figure 5, where a three-stage, 4-stack FET CMOS 15 GHz 5G AB mode to optimize gain/efciency trade-of; however, no PA is reported [25]. Te design of the PA uses 512 multigate- measured linearity data was reported in this study. Te output cells to form a 4-stack output device with 614 �mefective matching network was designed from nonlinear load-pull gate width. Te high-power output stage, together with the simulation for optimum power and PAE, while the interstage two-stage cascode pre-drivers achieve more than 30 dB linear matching networks were designed to conjugately match two � > gain centered around 13.5 GHz. Te PA achieves OUT devices for maximum gain, using a combination of shunt Wireless Communications and Mobile Computing 5

(a) (b)

(c)

Figure 6: (a) Schematic for the two-stage 15 GHz fully integrated GaN PA MMIC design ([26]); (b) Postlayout simulations on the PA’s �- parameters; and (c) postlayout RF/digital cosimulated PA spectrum output with LTE 16 QAM 20 MHz input at 15 GHz. ��,1 = ��,2 =28V.

MIM (metal-insulator-metal) capacitors, shunt microstrip A frst linear bulk CMOS PA targeting the low-power transmission lines (TLs), and series microstrip TLs to create 28 GHz 5G mobile user equipment (UE) integrated phased- bandpass flters and enhance frequency stability. Te DC bias array transceivers application is reported in [28–30]. Te network also included a resistive, multiband reject flter to output stage of the PA is frst optimized for PAE at a desired help stabilize the PA. error vector magnitude (EVM) and range. Next, inductive 6 Wireless Communications and Mobile Computing

(a) (b)

Figure 8: Schematic of the 28 GHz PA in 28 nm bulk CMOS: (a) two-stage transformer-coupled design; (b) push-pull stage with capacitive � � neutralization capacitor � (cross-coupled) and single-ended source degeneration inductor deg [28], © 2017 IEEE.

source degeneration in the optimized output stage is used Next, a state-of-the-art 28 GHz 32-element phased-array in a two-stage transformer-coupled PA shown in Figure 8. transceiver IC designed in a 0.13 �m SiGe BiCMOS process Te design purposely broadens the interstage impedance (��/� = 200/280 GHz) with concurrent dual-polarized max ∘ matching bandwidth to help reducing distortion. A small beams and 1.4 beam steering resolution for 5G communi- 14 pH inductive degeneration is selected in this PA design, cation was reported recently by Sadhu et al.[31](Figure9). � which lowered device power gain at OUT =12dBmfrom10 Te reported RFIC supports concurrent and independent � to 8 dB and reduced its PAE at the same OUT from 48% to dual-polarized 16-element beams (H and V) operation in 44% in measured test devices. It is possible that unwanted loss either TX or RX mode and can be integrated in a volume- � resistance in series with the 14 pH deg also contributed to the efcient antenna-in-package array. A new T/R switch at the � � PAE degradation. Te chosen deg, however, did not degrade shared antenna interface enables high OUT without much PA’s � signifcantly. Te authors had also minimized the PAE degradation of the PA, and a TL-based phase shifer OUT ∘ ∘ ground path impedance for the test device of by using a achieves <1 RMS error and <5 phase steps for precise wide and stacked metal mesh surrounding the device for beam control and also minimizes the number of circuit grounding. Te die picture of this 28 GHz PA is shown in components. As shown in Figure 10, each TX/RX signal path Figure 9. Te 28 nm bulk CMOS PA achieves +4.2 dBm linear shares an antenna, a passive phase shifer, and a passive � − OUT with 9% PAE (at EVM = 25 dBc) using a 250 MHz 64 combiner/splitter between the TX and RX in TDD (time QAM OFDM input (PAPR ∼ 9.6dB). Te PA also achieves division duplex) operation using 3 TX/RX switches. Without � 35.5%/10% PAE for CW input at OUT,sat/9.6 dB back-of. getting into the design details of the entire phased-array SoC, TeseareamongthehighestmeasuredPAEvaluesreported we will only focus on the discussion on the RF front-end for K- and Ka-band CMOS PAs. T/R IC portion of the SoC design, which contains the PA, Wireless Communications and Mobile Computing 7

(a) (b)

VGAs (variable gain amplifers), LNA, phase shifer, and T/R the TX-mode insertion loss to improve its PAE (Figure 11). switches. Additionally, in the RX mode, the output admittance of the Each RFFE IC as shown in Figure 10 includes a T/R of-state PA presents a low conductance real part in parallel switch that minimizes the insertion loss of the TX mode. In a with a high susceptance inductive part. Tis proposed design, traditional T/R switch, each �/4 TL-based switch is in series however, utilizes two switched capacitors to resonate out the with the PA or the LNA, resulting in similar insertion losses inductive part, achieving a high real TX input impedance to in TX versus RX modes. In this proposed design, the �/4 maximize the RX signal fow to the LNA. Te simulated TX switch at the output of the cascode PA is eliminated to avoid impedances for diferent states of the 2-bit switched capacitor 8 Wireless Communications and Mobile Computing

Figure 11: Conceptual schematic of a traditional T/R switch (TOP LFET) versus the proposed T/R switch (TOP RIGHT) with more detailed schematic of the proposed T/R switch with mode selection (BOTTOM) [31], © 2017 IEEE. are compared to a traditional switch impedance on the Smith I2 +Q2 Chart shown in Figure 11. Te removal of the �/4 switch in this Envelope � � Detection  () TX design improves OUT,1 dB and OUT,Sat by 1.2 dB, while Amplitude Envelope itonlydegradestheRXNF(noisefgure)by0.6dB.Tis I � > Modulator measured data indicates OUT,Sat 16 dBm per signal path > LTE/ and PA + switch peak efciency 20%, while still maintaining LO WiMAX ∘ a 6 dB NF for the LNA + switch block. Te authors calculated Baseband 0 j(t+＝) RF Out that an additional 1.2 dB TX loss per path of the traditional Generator A(t)e SiGe PA T/Rswitchapproachwouldhaveconsumed2.35W(or23%) Q more power in the FE IC than the proposed design to achieve Envelope-Tracking PA System the same � , . OUT Sat Figure 12: A simplifed block diagram of an entire ET-PA system So far we have discussed various circuit architectures [32]. for 5G cm-Wave PAs at diferent integration levels, where GaN, GaAs, CMOS, and SiGe BiCMOS technologies have � all been used. It is expected that the OUT requirement, as well as the cost and robustness of the 5G FEM, will all be considerably worsen the average PAE of a PA. Terefore, important in deciding the optimal device technology and both Doherty PA and supply-modulated PA are regarded RFFE IC architecture for a given 5G cm-Wave/mm-Wave PA very attractive for efciency enhancement for 5G PA design. design. Since it is the average PAE but not the peak PAE of the We will focus on the supply modulation techniques in this PA that determines the power and heat dissipation, efciency section, while discussing some more broadband Doherty 5G enhancement techniques at power back-of shall be discussed PA techniques in the next section to conclude. next. Figure 12 shows a simplifed transmitter block diagram using the envelope-tracking (ET) technique for supply mod- 5. 5G PA Efficiency Enhancement ulation to improve PAE at power back-of [32]. Te design Techniques at Power Back-Off uses a linear-assisted envelope modulator (EM, also known as envelope amplifer), where the RF input signal into the PA 5.1. With Dynamic Supply Modulation. Te 5G waveforms are contains both AM (amplitude modulation) and PM (phase with high PAPR and similar to 4G/WLAN, these waveforms modulation) components. Li et al. presented a detailed design will inevitably degrade PA’s efciency at power back-of and examplebyapplyingtheETtechniquestohaverealizedthe Wireless Communications and Mobile Computing 9

Buck Converter Linear Bufer Operational VDD Amplifer pMOS VCC (Op-Amp) Vsw + RFC RFC nMOS RFOUT RF - OUT Delay L

Ctank Ltank Ltank Ctank Ilin ISW CB CB Shifed Envelope + Rsense Iload RFIN RFIN- CE CE Vout Rload

PA RF Input RF Out V Lgnd V bias-CE bias-CE On-Chip

(a) (b)

50 12 PAE @ P1dB 40 10 PAE @ 3dB back-of 30 8 PA Modulator PAE @ 6dB back-of

PAE (%) PAE 20 6 EVM (%) @ P1dB 10 4

23.5dBm 24.2dBm 24.3dBm 0 2 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 Center Frequency (GHz) (c) (d)

Figure 13: (a) Simplifed circuitry schematic of the diferential cascode SiGe PA used in [33]; (b) simplifed block diagram of our CMOS envelope modulator with its connection to the diferential cascode SiGe PA on the same die; (c) chip micrograph of the world-frst single- × 2 � chip ET-PA (1.1 1.5 mm ); (d) measured overall PAE and EVM (at 1 dB) of the single-chip ET-PA for the LTE 16 QAM 5 MHz signal at 0.8/1.75/2.4 GHz. world-frst fully monolithic single-chip silicon ET-PA with fltering to achieve optimal high-efciency ET-PA design for high-efciency and broadband performance, covering sev- broadband wireless applications [38]. eral cellular frequency bands [33]. An envelope-tracked SiGe Another example to illustrate supply-modulated PA can cascode PA with an integrated CMOS envelope modulator for improve its efciency of cm-Wave 5G PA applications is 3 GPP LTE transmitters is shown in Figure 13 for this work. shown in Figure 14, where a highly efcient and linear two- Te entire single-chip ET-PA delivers the linear output power stage fully integrated GaN PA operating at 15 GHz (the same of 24.3 dBm with the overall system PAE of 42% at 2.4 GHz for design shown in Figure 6) is used to illustrate the point; the 3 GPP LTE 16 QAM modulation. Additionally, it exhibits however for brevity we will not include here the on-going a highly efcient broadband characteristic for multiband work on optimizing the entire ET-PA system design, which applications. Compared to the fxed-supply cascode PA, this requires the codesign of the EM with the cm-Wave GaN single-chip ET-cascode PA meets the LTE spectral mask PA. SPICE simulations show that this 2-stage PA achieves � � and error vector magnitude (EVM) spec at close to its 1 dB an output 1 dB compression OUT,1 dB =32.2dBmwitha compression without predistortion. Te SiGe PA and the 28.2 dB gain and 30.0% PAE for CW operation at 15 GHz. � CMOS envelope modulator are both designed and fabricated Its PAE reaches 38.7% at OUT =34.0dBmwithagain in the TSMC 0.35 �m SiGe BiCMOS process on the same of 22.0 dB. Postlayout SPICE simulations also suggest that die. Tis work represents an essential integration step towards dynamic supply modulation from 28 V to 10 V as shown achieving a fully monolithic ET-PA for wideband wireless in Figure 14 can signifcantly improve the PA’s efciency at applications, paving the way for a potential single-chip 5G power back-of, where the PAE improvement at 6 dB back- cm-Wave ET-PAs in the future. Note, besides DPD, one of is around 10%. When the PA is driven with 5/10/20 MHz can apply envelope-shaping such as DC shifing and/or AC LTE 16 QAM modulated signals, the wider modulated signal 10 Wireless Communications and Mobile Computing

Figure 14: Postlayout simulation of a 15 GHz 2-stage GaN PA as Figure 15: An integrated 10 GHz PA, buck 100 MHz switching the DC power supply voltage of the 2nd stage changes from 28 V to powersupply,andUHFcascodePApackagedinacomplete5× 10 V to illustrate the potential efciency improvement using supply 6 cm circuit, designed to efciently track a signal with >300 MHz modulation [26]. envelope bandwidth [34], © 2017 IEEE.

bandwidth from 5 MHz to 20 MHz does not worsen the engineering could still achieve similar efciency as some of PA linearity considerably according to the RF/analog/digital the ET-PAs without DPD. As a matter of fact, in today’s cosimulations (data not shown) [26]. Note as the EM in an commercial market most of the low-/mid-tier handsets use ET-PA will consume signifcant power especially for high APT while the high-tier handsets use the full-blown ET to bandwidth input signal to satisfy PA’s linearity requirements, track the instantaneous power supply voltage dynamically the actual PAE enhancement for this GaN ET-PA needs to [39]. As signal PARs and bandwidths continue to raise in be measured against the exact linearity specs for a given 5G 5G, challenges remain on how to achieve a high-efciency waveform in the future as the enhancement is dependent on ET-PA, as the efciency of its supply modulator degrades PAPR and signal bandwidth. signifcantly with wider bandwidth. On the other hand, the � Not only can GaN devices ofer the highest OUT for APT-PA may become more realistic to provide power saving cm-Wave PA design as suggested in Figure 2, they can for 5G applications. also ofen deliver the highest peak PAE compared to GaAs An interesting approach for improving the envelope- and silicon devices. In order to improve on the envelope- tracking speed of supply modulator is to use multiple tracking bandwidth of an ET-PA above 100–500 MHz (note converters in parallel, with time ofsets between them. By the envelope bandwidth is at least twice greater than the RF coordinating the inputs of � switchers, the output bandwidth signal bandwidth due to the nonlinear �-� to polar transfor- can ideally be increased by a factor of �. For example, Florian mation [32, 33, 38]), we can also take advantage of the faster et al. have reported an ET transmitter architecture based on GaN devices for the broadband supply modulator design. the combination of a novel 3-bit supply modulator and digital For example, a recent study reports that a buck converter predistortion (DPD) [35]. Te proposed power converter (i.e., a “switcher”) can be integrated with gate drivers in a is shown in Figure 16, which is based on a direct digital- Qorvo 0.15 �m RF GaN-on silicon carbide (SiC) technology, to-analog conversion (DAC) architecture that implements which have demonstrated over 90% peak efciency at up the binary-coded sum of isolated DC voltages, allowing the to 200 MHz switching frequency and supply up to 15 Watt synthesis of an output envelope waveform with voltage levels peak power [39]. Furthermore, to show the potential ET- in a binary distribution. Tis design provides a better voltage PA integration required for some 5G PA applications, a GaN resolution with respect to typical multilevel switched-sources MMIC that integrated a fast dynamic supply and RF PA is topologies as there are 8 levels, which enables the correction showninFigure15,wherea10WPAoperatingat10GHzis of the residual discretization error in the ET transmitter by combinedonthesamediewitha100MHzbuckconverter using DPD of the RF signal. Tis design has demonstrated with drive circuitry and also with a UHF cascode PA. Tis that one can successfully remove the low-efciency linear ET-PA is packaged with connectors for all the input and Op-Amp shown in Figure 13(b), potentially improving the control signals, and the only of-chip component is a flter overall efciency of the ET-PA signifcantly. Te proposed that determines the bandwidth division between the buck and ET-PA has been tested with an L-band 30-W lateral-difused cascode circuits [34]. MOSRFhigh-poweramplifer(RFHPA)with1.4and10MHz Another supply modulation technique simpler than ET LTE signals, where the EM achieved 92% and 83% efciency, is average power tracking (APT), in which the supply mod- respectively, and the overall efciencies of the transmitter ulator only responds to the peak of the envelope at each system are 38.3% and 23.9% at 5.5 and 1.9 W of average RF � average OUT level. As reported in [40] for a multiband output power, respectively. Figure 16(b) shows the measured LTE handset SiGe PA, the APT-PA with optimal waveform normalized amplitude of the time-domain signal envelope Wireless Communications and Mobile Computing 11

(a) (b)

Figure 16: (a) Architecture of the proposed ET transmitter in [35]; (b) measured normalized amplitude of the time-domain signal envelope at the HPA input and output under ET operation with and without DPD and corresponding time-domain dynamic bias provided by the power-DAC at the HPA drain bias port, © 2015 IEEE. at the HPA input and output under ET operation with cellular and WLAN specs have been reported [36]. Te �/� and without DPD; one can see that, in order to keep the digital bit streams directly feed to the input of DPA with no fdelity of the tracked envelope waveform, DPD is highly CORDIC transformation; a 2D DPD look-up table (LUT) is desired and this will consume more power at the baseband, developed in the digital front-end (DFE) to improve linearity. adding more overhead for developing the power-DAC based Te predistorted baseband signal is upsampled to about ET-PA. Note the proposed power converter is designed 800 MHz before it reaches the DPA to suppress far-out noise. using very fast discrete GaN-based power switches with an Te sampling clock of the DFE is derived directly from RF aggressively compact circuit layout to minimize losses at high carrier frequency �� through a confgurable frequency divider operating frequencies, and the proposed direct power-DAC instead of using a PLL (phase-locked loop), and a DIV-2 uses a binary asymmetric cascaded multilevel structure to circuit is used to generate the �/� LO signals. Te critical perform ET on the PA with a fairly high supply voltage building block, DPA, is shown in Figure 17. Its RF output is of 48 V (plus a DC ofset voltage around 6V). Terefore, taken by combining the currents from �-PA and �-PA, and the proposed technique in Figure 16 can be rather useful each �/�-PA is split into multiple power cells, controlled by to defense/aerospace and 5G base station applications, but 13-bit baseband signals BB to select the proper number of itisnotclearwhetheritwillbeattractivefor5Ghandset power cells. Since the RF output contains quantized baseband applications yet. info, the DPA is not just a PA, as its output combines modulation and digital-to-analog conversion (DAC) as well. 5.2. With Digital-Intensive Design Methods Current-mode Class-D topology is used in this design of switching pairs, where a transformer-compatible matching 5.2.1. Digitally Controlled Power-DAC Architecture: Digital network is used to approximate zero-voltage switching (ZVS). PA (DPA) with Power Combining. Digitally assisted and For the DPD, a training sequence is applied as DPA input digital-intensive RF TX can beneft from the fast nm- to characterize its quasistatic profle, and a 2D-LUT can be CMOS/BiCMOS devices to provide functional fexibility iteratively built-up through the loop-back path using gradient with high integration and power combining and tuning search. In normal transmission mode, the 32 × 32-point done digitally, making them very attractive for multimode 2D-LUT is used to map the baseband �/� input into DPA broadband applications with on-chip digital predistortion �/� control bits. Te 2D-DPD can correct nonlinearity, �/� (DPD)[41,42].Forsub-6GHzbandapplications,recent mismatch, and carrier leakage. Te entire TX IC is only 2 � all-digital RF transmitters using CMOS digital PA (DPA) 0.7 mm in a QFN package, with OUT,Sat of 24.7 dBm and and a direct quadrature architecture that can meet both peak DPA drain efciency of 37%. For an 802.11 g 54 Mb/s 12 Wireless Communications and Mobile Computing

� � signal, the maximum OUT,Linear is 18.8 dBm for the TX linearization architecture achieves ��,�� =23,3dBmat IC with −25 dB EVM and 17% DPA drain efciency. Te 42.5 GHz, a highly linear digital control word (DCW) to measured spurious emission is −133 dBc/Hz at WCDMA output amplitude profle (Diferential Nonlinearity (DNL) band 1 at 2.17 GHz with no external fltering. When tested = 0.5 LSB; INL 1 LSB using end-point ft) and low AM-PM with 80 MHz 256-QAM OFDM input, the all-digital TX IC distortion [19]. It was also able to improve the PA’s PAE at � − achieves OUT,Linear of 15.7 dBm with 33 dB EVM, showing 6 dB back-of considerably by reaching an excellent ratio of �� great promise for broadband wireless standards, such as LTE −6 dB / Peak =67.7%. and IEEE 802.11ac, and possibly for the cm-Wave/mm-Wave 5G applications. 5.2.2. Broadband Doherty 5G PA Using Digital Tuning. As To validate this kind of digital-intensive DPA/power- mentioned in Section 3 earlier, Doherty PA is a highly DAC design methodology can also work at mm-Wave fre- promising design topology for enhancing the 5G PA’s PAE quencies, a novel highly linear direct digital-to-mm-Wave at power back-of, even though it has been used mainly DACs PA architecture that can simultaneously achieve high as a narrow-band PA efciency enhancement technique in � OUT,Sat (through large-scale on-chip power combining), the past. However, due to its relative design simplicity and good linearization (through dynamic load modulation), and good performance, most cellular base stations today use the improved back-of efciency (through supply-switching and Doherty PA architecture instead of the slightly superior ET- load modulation) has been recently reported [19]. Tis PA architecture, except for the cases where the PA output digitally controlled, supply-switched, and load modulated power must change over a large dynamic range (say, >10 dB), switching PA architecture shown in Figure 18 uses several which Doherty PA typically cannot handle as well as ET- switching mm-Wave PA unit-cells that can be individually PA [39]. Te existing silicon mm-wave Doherty PAs in turned ON or OFF with a digital control bit. Tese PAs are theliteraturemostlyhaveverylimitedPAEenhancement power-combined using a nonisolating power combiner to atpowerback-of,mainlyduetolossyDohertypower make an overall linear mm-Wave DAC with high back-of combiners, and/or nonoptimized main/auxiliary PA design efciency, through the load modulation of the combiner and operation [37, 43]. As described in Section 3, [19] reported an turning OFF some of the PAs. A lumped �/4 combiner that efcient 15 GHz PA operation over wideband frequency with enables eight-way power combining with a high 75% mea- a Doherty confguration using a parasitic output capacitance sured efciency at 45 GHz is designed using lumped spiral neutralization technique for the fnal stage PA. In addition, inductor with higher characteristic impedance to enable one- Hu et al. [37] have recently reported a fully integrated step, low-loss, eight-way power combining. Using the power 28/37/39 GHz multiband Doherty PA for 5G massive MIMO combiner codesigned with stacked 45 nm SOI CMOS PAs applications. Te PAE for the 5G Doherty PA at the power results in an eight-way combined PA array with ��,�� = back-of levels are improved, and its bandwidth is also broad- 27 dBm and a broadband 1 dB bandwidth from 33 to 46 GHz. ened by the low-loss transformer-based Doherty parallel Another 45 nm SOI CMOS PA prototype, a 42.5 GHz 3- power combiner. Tis new transformer-based combiner is bit digital to mm-Wave PA array using the above-described based on the concept reported by [34] where three �/4 Wireless Communications and Mobile Computing 13

(a) (b)

Figure 18: (a) Digitally controlled, load modulated power-DAC architecture for linear and highly efciency mm-Wave PA design [19]; (b) schematic of the 33–46 GHz watt-class PA array prototype; (c) schematic of the two-stage 45 nm SOI CMOS stacked PA unit-cell used in the watt-class PA array prototype; (d) chip microphotograph of the 33–46 GHz watt-class PA array prototype. Chip dimensions are 3.2 mm × 1.3 mm without pads © 2013 IEEE.

lines are used to provide optimum impedance seen by the with little limitation on the modulation rate. A prototype device output at the fundamental frequency across the wide is implemented in 0.13 �m SiGe BiCMOS and it achieved − � frequency range of +/ 23% at 2.2 GHz. In the design of Hu +16.8/+17.1/+17 dBm peak OUT, with 20.3/22.6/21.4% peak et al., however, they took it to the next level of integration PAE at 28/37/39 GHz. It also amplifes 3 Gb/s 64-QAM input by using two transformers absorbing these three �/4 lines with high-efciency and reasonable linearity in all these three to achieve compact and true Doherty load modulation. 5G bands (Figure 19). What is particularly interesting in that design is the adop- For5Gsystems,theuseofwidebandwidth(>100 MHz) tion of a digital-intensive tuning scheme, where a power- and massive MIMO are key technologies. Terefore, we dependent uneven-feeding scheme is used to adaptively expect that the efciency enhancement technique of Doherty provide optimum main/auxiliary PA operation as shown PA design may have good adaptability of digital-intensive PA in Figure 19. At the input, an on-chip transformer-based to wide bandwidth and massive MIMO. diferential quadrature hybrid was used, while nine-section In the end, we would like to mention that it is not varactor-loaded transmission lines are deployed both for the entirely clear if 5G PAs in the handsets would be required main and for the auxiliary paths. Unlike the conventional to go to 28 GHz cm-Wave range in the next couple of years Doherty PA where one relies on an adaptive biasing circuit as the standard is still evolving. As an example, one 5G � on the auxiliary peaking amplifer to turn it on for higher in startup PHAZR has developed a solution known as Quadplex, levels, the input conductance of this Class-C auxiliary PA can whose technology uses mm-Wave frequencies (24–40 GHz) � be tuned to increase signifcantly at higher in,whilethatof for the downlink and the sub-6 GHz frequencies (3.5 GHz the Class AB main PA remains almost identical. In addition, or 5 GHz) for the uplink, which the company and their one also performs dynamically modulation of the auxiliary collaborators believe this technology can “uniquely enable � driver load to achieve larger power gain when in increases. high-performance, cost-efective, and power-efcient 5G sys- Terefore, these tunings enable the rapid increase of auxiliary tems” [44]. Additionally, some latest 5G modulation meth- PAoutputcurrenttoobtainanoptimumDohertyoperation ods, such as the advanced nonorthogonal multiple access 14 Wireless Communications and Mobile Computing

(a)

(b)

(c)

Figure 19: (a) A simplifed schematic showing the proposed digitally intensive broadband Doherty transmitter in 0.13 �m SiGe BiCMOS [37]; (b) CW measured small-signal �-parameters and large-signal ��/�1�� data, indicating dual-mode PA operation covering three 5G bands; (c) chip micrograph.

(NOMA) scheme that serve multiple users at the same PAs. Tese PAs are designed in various device technologies: time/frequency/code but with diferent power levels, will GaAs,GaN,SiGe,bulkCMOS,andCMOSSOI.Wecovered complicate the MIMO 5G PA design optimization to achieve wideband Doherty PA in GaAs and in SiGe; stacked PA on the overall highest TX power efciency under various output SOI CMOS; diferential bulk CMOS PA with neutralization power levels and users clustering scenarios [45]. cap and transformers; CMOS DPA; fully monolithic GaN PA; highly integrated RFFE with LNA, PA, phase shifer, 6. Conclusions switches for phased-array MIMO, and so forth. Tese PA designs presented potential solutions for successful 5G cm- In this paper, we have briefy surveyed some recent advanced Wave front-end IC designs, where unprecedented high PAE � and promising design trends on cm-Wave and mm-Wave 5G at both peak OUT and power back-of with good linearity Wireless Communications and Mobile Computing 15 are required, while broadband operation and dense low-cost [9] D.Y.C.Lie,“MicrowaveScienceandTechno.,Vol.2010,pp.1-7”. integration suitable for massive MIMO are also critical for the [10] D. Y. Lie, J. C. Mayeda, and J. Lopez, “A short survey on recent market adoption. For handsets and small cells/BST where the highly efcient cm-Wave 5G linear power amplifer design,” � maximum OUT,Linear requirement is low, typically varying in Proceedings of the 2017 IEEE 60th International Midwest ∼4dBm to ∼36 dBm, silicon-based PAs can be attractive Symposium on Circuits and Systems (MWSCAS),pp.13–16, for highly integrated solutions with digital-intensive opera- Boston, MA, USA, August 2017. � [11] Y. Niida, Y. Kamada, T. Ohki et al., “3.6 W/mm high power tions. For applications requiring higher OUT, on the other hand, GaAs and GaN technologies may still be largely used density W-band InAlGaN/GaN HEMT MMIC power ampli- to achieve higher PA efciency. We also discussed some fer,” in Proceedings of the IEEE Topical Conference on Power techniques specifcally for back-of efciency enhancement, Amplifers for Wireless and Radio Applications, (PAWR ’16),pp. 24–26, USA, January 2016. namely, using the dynamic supply modulations, all-digital PA [12] J. J. Komiak, “Microwave and millimeter wave power ampli- architecture, and Doherty PA with digital tuning. We believe fers: Technology, applications, benchmarks, future trends,” these techniques will continue to be explored extensively to in Proceedings of the 2016 IEEE International Symposium on pave the road to the 5G deployment. Radio-Frequency Integration Technology (RFIT),pp.1–4,Taipei, Taiwan, August 2016. Conflicts of Interest [13] Z. Popovic, “GaN power amplifers with supply modulation,” in Proceedings of the 2015 IEEE MTT-S International Microwave Te authors declare that there are no conficts of interest Symposium (IMS2015),pp.1–4,Phoenix,AZ,USA,May2015. regarding the publication of this paper. [14] T. Kaneko, K. Shiikuma, and K. Kunihiro, “GaN HEMT high efciency power amplifers for 4G/5G mobile communication Acknowledgments base stations,” in Proceedings of the 2014 Asia-Pacifc Microwave Conference, (APMC ’14), pp. 994–997, November 2014. Te authors wish to acknowledge the funding support of DoD [15]A.EzzeddineandH.Huang,“Tehighvoltage/highpower (Department of Defense), including the DARPA Microscale FET (HiVP),” in Proceedings of the Radio Frequency Integrated Power Conversion Program and TTU Keh-Shew Lu Regents Circuits (RFIC) Symposium, pp. 215–218, IEEE, PA, USA, 2003. Chair Endowment. Tey also like to thank Ms. D. Wang, [16] S. Pornpromlikit, “A Watt-Level Stacked-FET Linear Power Dr.N.Cahoon,Dr.A.Joseph,andDr.D.Harameat Amplifer in Silicon-on-Insulator CMOS,” IEEE Transactions on GlobalFoundries for IC fabrication. Finally, they like to thank Microwave Teory and Techniques,vol.58,no.1,pp.57–64,Jan Professor C. Kuo and Mr. J.-Y. Lai at National Chiao-Tung 2010. University (NCTU), Taiwan, for the support on the GaN IC [17]H.-T.Dabag,P.M.Asbeck,andJ.F.Buckwalter,“Linear design kit and fabrication. operation of high-power millimeter-wave stacked-FET PAs in CMOS SOI,” IEEE MWSCAS, pp. 686–689, 2012. References [18] H.-T.Dabag,B.Hanaf,F.Golcuk,A.Agah,andJ.F.Buckwalter, “Analysis and design of stacked-FET millimeter-wave power [1] http://www.3gpp.org/. amplifers,” IEEE Transactions on Microwave Teory and Tech- [2] M. Agiwal, A. Roy, and N. Saxena, “Next generation 5G wireless niques, vol. 61, no. 4, pp. 1543–1556, 2013. networks: A comprehensive survey,” IEEE Communications [19] R. Bhat, A. Chakrabarti, and H. Krishnaswamy, “Large-scale Surveys and Tutorials, vol. 18, no. 3, pp. 1617–1655, 2016. power combining and mixed-signal linearizing architectures for [3] P. Asbeck, IEEE RFIC Symp., WSB Woskshop “Highly Efcient watt-class mmwave CMOS power amplifers,” IEEE Transac- 5G PA Design”, San Francisco, (2016). tions on Microwave Teory and Techniques,vol.63,no.2,pp. [4]T.Kamgaing,A.A.Elsherbini,S.N.Oster,B.M.Rawlings, 703–718, 2015. and K.-O. Lee, “Ultra-thin dual polarized millimeter-wave [20] J. A. Jayamon, J. F.Buckwalter, and P.M. Asbeck, “APMOS mm- phased array system-in-package with embedded transceiver wavepowerampliferat77GHzwith90mWoutputpowerand chip,” in 2007 IEEE/MTT-S International Microwave Sympo- 24% efciency,” IEEE Radio Freq. Integr. Circuits Symp, pp. 262– sium,Phoenix,AZ,USA,2015. 265, 2016. [5]D.Y.Lie,J.Tsay,T.Hall,T.Nukala,J.Lopez,andY.Li,“Recent [21] B. Hanaf, O. Gürbüz,H.Dabag,S.Pornpromlikit,G.Rebeiz, progress on high-efciency CMOS and SiGe RF power amplifer and P. Asbeck, “A CMOS 45 GHz power amplifer with output design,” in Proceedings of the 2016 IEEE Topical Conference on power > 600 mW using spatial power combining,” IEEE MTT-S PowerAmplifersforWirelessandRadioApplications(PAWR), Int. Microw. Symp. Dig,pp.1–3,2014. pp.15–17,Austin,TX,USA,January2016. [22]H.-T.Dabag,B.Hanaf,O.D.Gürbüz,G.M.Rebeiz,J.F. [6]D.Y.Lie,J.Tsay,T.Hall,T.Nukala,andJ.Lopez,“High- Buckwalter, and P. M. Asbeck, “Transmission of signals with efciency silicon RF power amplifer design – current status and complex constellations using millimeter-wave spatially power- future outlook,” in Proceedings of the 2016 IEEE International combined CMOS power amplifers and digital predistortion,” Symposium on Radio-Frequency Integration Technology (RFIT), IEEE Trans. Microw. Teory Tech,vol.63,no.7,pp.2364–2374, pp. 1–4, Taipei, Taiwan, August 2016. July 2015. [7] Y. Li, O. Ortiz, and E. Spears, “A highly integrated multiband [23] K. Nakatani, Y. Komatsuzaki, S. Shinjo et al., “A highly inte- LTE SiGe power amplifer for envelope tracking,”in Proceedings grated RF frontend module including Doherty PA, LNA and of the 2015 IEEE Radio Frequency Integrated Circuits Symposium switch for high SHF wide-band massive MIMO in 5G,” in (RFIC), pp. 131–134, Phoenix, AZ, USA, May 2015. Proceedings of the 2017 IEEE Topical Conference on Power [8] https://www.qualcomm.com/invention/technologies/5g-nr/ Amplifers for Wireless and Radio Applications, (PAWR ’17),pp. mmwave. 37–39,Phoenix,AZ,USA,January2017. 16 Wireless Communications and Mobile Computing

[24] S. Shinjo, K. Nakatani, J. Kamioka et al., “Highly integrated RF [38] R. Wu, Y.-T. Liu, J. Lopez, C. Schecht, Y. Li, and D. Y. C. frontend module for high SHF wide-band massive MIMO in Lie, “High-efciency silicon-based envelope-tracking power 5G, and switching-mode amplifers beyond 4G,” in Proceedings amplifer design with envelope shaping for broadband wireless of the 2017 International Symposium on VLSI Design, Automa- applications,” IEEE Journal of Solid-State Circuits,vol.48,no.9, tion and Test (VLSI-DAT),pp.1–4,Hsinchu,Taiwan,April2017. pp. 2030–2040, 2013. [25] N. Rostomyan, J. A. Jayamon, and P. Asbeck, “15 GHz 25 dBm [39] P.Asbeck and Z. Popovic, “ET Comes of Age: Envelope tracking Multigate-Cell Stacked CMOS Power Amplifer with 32 % PAE for higher-efciency power amplifers,” IEEE Microwave Maga- and ≥ 30 dB Gain for 5G Applications,”in Proceedings of the 11th zine,vol.17,no.3,pp.16–25,2016. European Microwave Integrated Circuits Conference, (EuMIC [40] Y.Li,J.Ortiz,andE.Spears,“AhighlyintegratedmultibandLTE ’16), pp. 265–268, London, UK, October 2016. SiGepowerampliferforenvelopetracking,”inProceedings of [26] J.C.Mayeda,D.Y.Lie,andJ.Lopez,“Ahighlyefcientandlinear the IEEE Radio Frequency Integrated Circuits Symposium, (RFIC 15 GHz GaN power amplifer design for 5G communications,” ’15), pp. 131–134, USA, May 2015. in Proceedings of the 2017 Texas Symposium on Wireless and [41] R. B. Staszewski, “All-digital PLL and transmitter for mobile Microwave Circuits and Systems (WMCS),pp.1–4,Waco,TX, phones,” IEEE J. Solid-State Circuits,vol.40,no.12,pp.2469– USA, March 2017. 2482, 2005. [27] J. Curtis, H. Zhou, and F. Aryanfar, “AFully Integrated Ka-Band [42] M. S. Alavi, R. B. Staszewski, L. C. de Vreede, and J. R. Long, “A Front End for 5G Transceiver,” in Tech. Dig. IEEE MTT-S Int. Wideband 2 13-bit All-Digital I/Q RF-DAC,” IEEE Transactions Microw. Symp. Dig, pp. 1–3, San Francisco, CA, USA, 2016. on Microwave Teory and Techniques, vol. 62, no. 4, pp. 732–752, [28]S.Shakib,H.-C.Park,J.Dunworth,V.Aparin,andK.Entesari, 2014. “A Highly Efcient and Linear Power Amplifer for 28-GHz 5G [43] A. Grebennikov and J. Wong, “A dual-band parallel doherty Phased Array Radios in 28-nm CMOS,” IEEE Journal of Solid- power amplifer for wireless applications,” IEEE Transactions on State Circuits,vol.51,no.12,pp.3020–3036,2016. Microwave Teory and Techniques, vol. 60, no. 10, pp. 3214–3222, [29]S.Shakib,H.Park,J.Dunworth,V.Aparin,andK.Entesari, 2012. “28GHz efcient linear power amplifer for 5G phased arrays [44] http://phazr.net/technology/. in 28nm bulk CMOS,” in Proceedings of the 2016 IEEE Inter- [45]Z.Ding,Y.Liu,J.Choietal.,“ApplicationofNon-Orthogonal national Solid-State Circuits Conference (ISSCC),pp.44-45,San Multiple Access in LTE and 5G Networks,” IEEE Communica- Francisco, CA, USA, January 2016. tions Magazine, vol. 55, no. 2, pp. 185–191, 2017. [30]S.Shakib,H.-C.Park,J.Dunworth,V.Aparin,andK.Entesari, “A 28GHz efcient linear power amplifer for 5G phased arrays in 28nm bulk CMOS,” in Proceedings of the 63rd IEEE International Solid-State Circuits Conference, (ISSCC),pp.352- 353, USA, February 2016. [31] B. Sadhu, Y.Tousi, J. Hallin et al., “A28GHz 32-element phased- array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication,”in Proceedings of the 2017 IEEE International Solid- State Circuits Conference - (ISSCC), pp. 128-129, San Francisco, CA, USA, Feburary 2017. [32]J.Lopez,Y.Li,J.D.Poppetal.,“Designofhighlyefcient wideband RF polar transmitters using the envelope-tracking technique,” IEEE Journal of Solid-State Circuits,vol.44,no.9, pp. 2276–2294, 2009. [33]Y.Li,J.Lopez,P.-H.Wu,W.Hu,R.Wu,andD.Y.C.Lie, “A SiGe envelope-tracking power amplifer with an integrated CMOS envelope modulator for mobile WiMAX/3GPP LTE transmitters,” IEEE Transactions on Microwave Teory and Techniques,vol.59,no.10,pp.2525–2536,2011. [34] Z. Popovic, “Amping Up the PA for 5G,” IEEE Microwave Magazine,vol.18,no.3,pp.137–149,2017. [35] C. Florian, T. Cappello, R. P. Paganelli, D. Niessen, and F. Fil- icori, “Envelope Tracking of an RF High Power Amplifer With an 8-Level Digitally Controlled GaN-on-Si Supply Modulator,” IEEE Transactions on Microwave Teory and Techniques,vol.63, no.8,pp.2589–2602,2015. [36] C. Lu, H. Wang, C. H. Peng et al., “A 24.7 dBm all-digital RF transmitter for multimode broadband applications in 40 nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 332-333, 2013. [37] S. Hu, F. Wang, and H. Wang, “A 28 GHz/37 GHz/39 GHz multibandlinearDohertypowerampliferfor5Gmassive MIMO applications,” in Proceedings of the 2017 IEEE Interna- tional Solid- State Circuits Conference - (ISSCC),pp.32-33,San Francisco, CA, USA, Feburary 2017. Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 9130910, 10 pages https://doi.org/10.1155/2018/9130910

Research Article A Low Power Impedance Transparent Receiver with Linearity Enhancement Technique for IoT Applications

Sizheng Chen, Tingting Shi, Lei Ma, Cheng Kang, Na Yan , and Hao Min

State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

Correspondence should be addressed to Na Yan; [email protected]

Received 3 November 2017; Revised 8 March 2018; Accepted 12 April 2018; Published 14 May 2018

Academic Editor: Christian Fager

Copyright © 2018 Sizheng Chen et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

A low power receiver with impedance transparent RF front end is presented. By using the 4-path passive mixer and the active feedback of LNA, the baseband impedance profle is further transferred to receiver input. While a LO-defned input matching is formed by RF front end, the linearity of entire receiver chain is improved. Furthermore, derivative superposition technique is employed to cancel the distortion of the CMOS LNA. A 3rd-order active-RC flter is designed with current-efcient feedforward compensated OTA. And a digital-to-time converter (DTC) assisted fractional-N all-digital phase-locked loop (ADPLL) is codesigned with receiver to meet the IoT requirements. Te presented receiver is fabricated in 55 nm CMOS technology with an 2 active area of 2.3 mm and power consumption of 20 mW.Measurement results show that the receiver achieves 5.3 dB NF with 78 dB gain from 0.6 to 1 GHz, the RX out-of-band IIP3 is +8 dBm, and in-band IIP3 is −10 dBm, and the ADPLL achieves −94 dBc/Hz in-band PN and −120.5 dBc/Hz at 1 MHz ofset.

1. Introduction at the cost of large power dissipation and poor LO-to-RF isolation [5]. Others proposed a noise-cancelling receiver to Te need for low power and low cost transceivers has been achieve very low noise fgure by employing two paths of growing with the expansion of portable wireless devices and downconversion which increases the hardware complexity wireless sensor networks. Because of big market potential and [6], but extra calibration is needed to provide precise gain and design challenges, narrow-band (NB) receivers have become phase matching. the focus of industry and academic researches recently. Mod- In this work, an impedance transparent receiver architec- ern wireless protocols are released, such as the emerging NB- ture is proposed which only uses one downconversion path. IoT [1] and the IEEE 802.11ah [2], to support IoT applications. Te proposed reconfgurable RF front end employs an active Additionally, NB-IoT has been included as an important part feedback LNA to transfer the baseband flter character to the of future ffh-generation (5G) mobile communication [3]. input of receiver, which can attenuate out-of-band interferers. Diferent techniques are proposed in recent researches to realize the low power and low cost receiver for IoT By using the impedance mapping of passive mixer and the protocols. Because of the superior performance (better noise feedback of LNA, a LO-defned input matching is formed. To and linearity) of NB LNAs, multiple narrow-band receivers further improve the linearity of RX, a linearity enhancement areemployedtocovertheentirebandoftheoperation.To technique called “derivative superposition [7]” is employed in provide high-Q frequency selectivity, each NB RX uses of- the CMOS LNA. chip components, which increases the entire area and cost [4]. Tis paper proposes a low power impedance transparent Reconfgurable receiver is able to select signals over a wide receiver with linearity enhancement technique. Te descrip- operation band. And one of the common challenges of these tion of the system architecture is given in Section 2; the receivers is out-of-band interference. Academic researches design of the building blocks is shown in Section 3; the have focused on using passive mixer to suppress the out- measured results are described in Section 4 and conclusions band blockers. A mixer-frst receiver has an excellent linearity areprovidedinSection5. 2 Wireless Communications and Mobile Computing

Table 1: Main specifcations of receiver for IoT protocols. band is in range of −60 to −80 dBm. For example, according to [9], the LO leakage of mixer-frst RX is about −48 dBm Parameters NB-IoT without calibration in 28 nm CMOS technology. ∼ RF frequency 699 915 MHz (2) Providing a gain in frst stage is a power efciency Channel bandwidth 180 kHz method to realize high sensitivity receiver. Due to lack of Max. receive level −25 dBm LNA, lots of current is burned in baseband transimpedance Sensitivity <−109 dBm amplifer (TIA) to make the NF less than 8 dB in mixer-frst Noise fgure <7dB receiver [5]. P-1dB >−25 dBm Becauseofthenarrow-bandprofle,the1/fnoiseand ∗ OB-IIP3 >+7.75 dBm DC ofset could degrade the sensitivity. A passive mixer is In-band IIP3 >−15.4 dB employed for its superiority on 1/f noise. And a DC ofset ∗ cancellation circuit is designed. Range 2 of NB-IoT protocol. Besides, it is difcult to achieve both high linearity and low power for RF front end, especially without the help of 2. System Description of-chip device (e.g., SAW,BAW). Compared with traditional method of using passive mixer at LNA output only, the 2.1. System Specifcations for the Receiver. Based on the proposed receiver is further mapping the impedance of mixer IoT protocols [8], main specifcations of the receiver are to the RX input with active feedback LNA to realize the input summarized in Table 1. Low power and low cost are the key LO-defned impedance matching. Te in-band of RX could features of IoT application. And the system specifcations are be a problem due to the incremental gain of LNA. So the briefy reviewed as follows. derivative superposition technique is utilized to cancel this distortion in LNA. 2.1.1. Noise Figure. Sensitivity level of a receiver is very key requirement in a communication system because most of 2.2. Receiver Architecture. Te proposed receiver architecture the other specifcations are defned based on it. For the NB- is a suitable solution for IoT applications as shown in Fig- IoT application with 180 kHz transmission bandwidth, the ure 1, consisting of an impedance transparent receiver front sensitivity level is around −109 dBm. Te SNR is 2.5 dB min end, a 3rd-order active-RC flter, a fractional-N frequency to cover all possible TBS (Transport Block Set) with QPSK synthesizer, and SPI interface to confgure the system. Te modulationandcoderate1/3.Basedontherequirements local frequency generator consists of a divide-by-two circuit above, the noise fgure of the receiver can be expressed as to generate a 25% duty-cycle LO from an on-chip all-digital NF = Sensitivity phase-locked loop. A DTC-assisted fractional-N ADPLL with (1) a TDC is employed in this work. Self-biased CMOS inverters − (−174 +10 + )−� . dBm log BW SNRmin � are used to provide rail-to-rail swing to the gate of passive mixer. Compared with the traditional 50% duty-cycle LO, �� is implementation and production margin. BW is the the 25% duty-cycle LO scheme [9] provides isolation timely transmission bandwidth in Hz. Assuming I� is 3 dB, it can be calculated that NF = 6.94 dB. between I-andQ-current-path. Terefore, conversion gain reduction and subsequent NF increase are prevented. 2.1.2. Nonlinearity. For RX nonlinearity, there are in-band and out-of-band IIP3 requirements. Te in-band IIP3 of the 2.3. Noise Analysis of Receiver RF Front End. Te receiver RX is corresponding to the 1-dB compression point (P1dB). RF front end comprises an LNA, two separate passive mixers Since the maximum input level of the NB-IoT receiver is for in-phase (�) and quadrature-phase (�),andasingle-pole −25 dBm, the P1dB is −25 dBm. So the in-band IIP3 is flter as a TIA which changes the current signal to voltage −15.4 dB, which is 9.6 dB higher than P1dB. Te out-of- signal. Te passive mixer is implemented with 4 nMOS band IIP3 is determined by out-of-band blocking parameters. transistors, which are connected with the output of LNA. According to [8], the interferer power is −30 dBm in range 2 According to [10], the output of 4-path passive mixer can be (60∼85 MHz frequency ofset from desire signal), while the written as signal power is 6 dB above the reference sensitivity (about +∞ − �� (�−(�/4)�) 109 dBm). Te IIP3 estimated with 2.5 dB SNR is as follows � = ∑ � � LO MIXER,current � (where � is the power of signal): �=−∞ signal (3) 3� −(� − SNR) 1 −��(�/4) �� 3= in signal = 7.75 . (2) �� = � sin �( ). OB-IIP 2 dBm 4 4 � For the sensitivity requirement of the protocol, LNA-frst MIXER,current is the current gain of 4-path passive mixer architecture should be employed. Compared with mixer-frst and �� is the coefcients of the Fourier series. Te receiver receiver, the LNA is added for two reasons. conversion gain and NF can be calculated as follows: (1)LO-to-RFisolationcanbeimprovedbyaddingthe 1 � (� ) LNA, which is one of the most challenging things in mixer- � = ⋅� ⋅ �,LNA LO ⋅� ⋅� RX RF 2 �,LNA � (� )+� −1 � (4) frst receiver. Te allowable emission level within receiver �,LNA LO sw Wireless Communications and Mobile Computing 3

Quadrature-phase

In-phase TIA 3rd-order active-RC flter Vout, Q

LNA −+ Vout, I RS +−

Antenna

RPA DCO LO + Loop Bufer FCW Σ Filter − REF ΣΔ

SPI DTC ADPLL

+ TDC DFF /4 25% LOGEN

Figure 1: Proposed receiver architecture.

�2 impedance transparent afects the linearity of the RX, the =1+ �,LNA NF �� ⋅�2 beneft of a flter is added before or afer LNA is analyzed as � �,LNA 2 showninFigure3. � ⋅� +∞ � To simplify analysis, only the nonlinearity of LNA and + �� (∑ −� ) � ⋅� � (�� )+� mixer are considered. Te flter has two rejections as shown � RX RF �=0 �,LNA LO sw � � (5) in Figure 4, blocker1 and blocker2 for diferent blockers at 2 2 � (1 + � /� ) � 1 and � 2. A1 and A2 represent the amplitudes of + �,TIA � �,LNA blocker blocker 4�� ⋅�2 the two blockers. For a memoryless nonlinear system, the � RX RF � input/output characteristic can be modeled as a polynomial [11]. + � . Ten output IM3 of this cascaded receiver stages (LNA � ⋅�2 � RX RF andmixer)isasfollows: �2 � � � � =� � 1 2 �,LNA is the transconductance of the LNA. �,LNA and IM3,baseband LNA MIXER �2 2 ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟IIP3,LNA ��, are, respectively, the output impedance and output LNA � Output IM3 of LNA current noise of the LNA. sw is the mixer switch on- (6) � �2 � resistance. And � is the feedback resistance of TIA. Te OTA +�3 � 1 2 . �2 LNA MIXER �2 noise is modeled by �,TIA asshowninFigure2.Sincethe ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟IIP3,MIXER thermal noise of passive mixer switches is white noise, all Output IM3 of MIXER partsofharmonicsoftheLOwillbefoldedintobaseband � � which is shown in third part of (5). From this equation, we LNA and MIXER arethegainoftheLNAandthemixer can see that the LNA stage decreases the noise contribution stage, respectively. In case one, the flter is added afer the from mixer and TIA. LNA. Te resulting IM3 is as follows: �2 � � =� � 1 2 2.4. Impedance Transparent Profle. Compared with conven- IM3,baseband LNA MIXER �2 ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟IIP3,LNA tional architecture of just employing passive mixer at LNA Output IM3 of LNA output, the high-Q fltering profle of passive mixer is further (7) �3 � �2 � transferred to the input of the receiver in our proposed RF + LNA MIXER 1 2 . �2 � �2 front end. So it can relax the requirement on LNA linearity ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟blocker1 blocker2 IIP3,MIXER while achieving a relatively low NF. To fgure out how the Output IM3 of MIXER 4 Wireless Communications and Mobile Computing

a−1 a a a −2 −3 −4 a−5 a−6 a−7 a−8

f，／ 2f，／ 3f，／ 4f，／ 5f，／ 6f，／ 7f，／ 8f，／

4kTR３Ｑ ZO,，．！ nw，／ + R３Ｑ Quadrature-phase In-phase 4kTRF All parts of harmonics of the LO will be folded V Q into baseband out,

LNA R Vout, I S 4kTRS 2 I n,，．！ ∘ ∘ 2 0 180 V n,４）！

TIA Antenna Figure 2: Noise sources inside the RF front end.

Case 2 Case 1 Quadrature-phase In-phase Vout, Q

LNA V I RS out,

0∘ 180∘

Antenna TIA

Figure 3: Two cases to analyze the efect of impedance transparent.

From (7), we can see that blockers are not attenuated at Blocker2 Blocker1 the input of LNA. But the IM3 levels from the mixer stage are signifcantly reduced, which helps to improve the IM3 level ＜ＦＩ＝Ｅ？Ｌ1 FＭＣＡＨ；Ｆ H

by a few dB. Terefore, the RX IIP3 is limited by LNA stage in ＜ＦＩ＝Ｅ？Ｌ2 this case. By adding the flter in case two, the IM3 at baseband H is calculated as

F＜ＦＩ＝Ｅ？Ｌ2 F＜ＦＩ＝Ｅ？Ｌ1 F，／ f � � �2 � � = LNA MIXER 1 2 Figure 4: Te rejection of the flter for two diferent blockers. IM3,baseband �2 � �2 ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟blocker1 blocker2 IIP3,LNA Output IM3 of LNA improvement due to the smaller voltage swing is ΔIM3,the (8) �3 � �2 � entail IIP3 improvement is + LNA MIXER 1 2 . 2 2 1 ⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟⏟� 1� 2 � 3, Δ 3 ( ) =� ( ) + � ( ) blocker blocker IIP MIXER IIP dB blocker1 dB 2 blocker2 dB Output IM3 of MIXER 1 (9) + Δ ( ) . 2 IM3 dB Inthiscase,itcanbeshownthatIM3levelfromboththe If the blocker 1 is attenuated by 10 dB and blocker 2 is LNA stage and mixer stage is attenuated. So the IIP3 of the attenuated by 6 dB, while ΔIM3 is 3 dB, the IIP3 improvement entire receiver is signifcantly improved. If the blocker IM3 is about 14.5 dB. Wireless Communications and Mobile Computing 5

In our proposed receiver front end, an active feedback 200 −2 LNA is used to further map the bandpass fltering character- 180 −4 istic of 4-path passive mixer to the input of RX, which has the same efects as case 2. So it has a suitable tradeof between 160 −6 noise and out-of-band attenuation early in the receiver chain. According to N-path fltering theory, the frequency 140 −8 (dB) response of the flter is centered at the LO frequency. Because (Ohm) 120 −10 S11

of the reciprocal character of passive mixer, the RF signal is Z11 down converted to baseband. Afer being shaped by baseband 100 −12 load, it is up converted back to RF, which transfers the load response to LO frequency. Te input impedance of the mixer 80 −14 � canbecalculatedasfollows(where sw is the switch on- � � 60 −16 resistance, baseband isthebasebandimpedance,and sh is 7 8 9 10 11 ×108 equivalent resistance of harmonic mixing) [5]: Frequency (Hz)

Figure 5: Simulated Z11 and S11 of receiver RF front end. 2 � � (�) =� + � (�−� ) �� . mixer sw �2 baseband LO � sh (10) V＄＄ V＂）！３０ V＄＄ V＂）！３０＃V＄＄ SotheLNAloadimpedancecanbeshowntobeconsisting －1 of the output impedance of LNA and the baseband impedance ０－1０＃ upconverted by the passive mixer. Te input stage of receiver V ＄＄ 2 is a CMOS LNA with a shunt-shunt feedback [12]. With the M negative feedback, the impedance properties at the baseband I＂）！３ canbemappedtotheLNAinputas Aux CF RF ２＆ＣＨ transistor －1． M3 ２＆ＩＯＮ 1/��2 +��, －1 � = � LNA . ．＃ in 1+� ⋅� �� (�) (11) �1 �,LNA � mixer

V＂）！３． V � � ＂）！３．＃ �,LNA and �,LNA are feedback resistance and load Feedback Path resistance of LNA, respectively. ��1 and ��2 are the transcon- IIP3 Comp. ductance of main amplifer transistor and feedback tran- � (�) sistor, respectively. mixer is the input impedance of Figure 6: Schematic of the presented CMOS LNA. passive mixer, which has a bandpass impedance characteristic.SincetheinputresistanceofactivefeedbackLNAis inversely proportional to the LNA gain, making the baseband �=� +� +� +� +� +� impedancefurthertransferredtotheLNAinput.Tein- �� 1 �� 2 �� band impedance is matched to 50 Ohms, making the input � � 2+� 2 � =1+ 1 � ( � ) + � impedance matched at LO frequency only; thus the power of 2 ��1 1+�� (1 + � ) out-of-band blockers are refected at RX input. Te reduction � � in the voltage gain out of band causes the impedance to � � + 2 [1 − � ] increase instead which means that the shape of the impedance 1+� � (1 + � ) (12) isinversetotheshapeoftheimpedanceattheoutputofthe � � � LNA. Simulated s-parameters and input impedance of the 1 2+� 2 + ( � ) front end using steady-state analysis are shown in Figure 5. ��1�� 1+�� 2 �� 3. Building Block Designs +�� [1 − ] . �� (1 + ��) 3.1. LNA. Comparing with mixer-frst receiver, LNA-frst architecture has better noise and LO-to-RF isolation perfor- Tere is a negative item in the equation above, so the mance. And impedance transparent character is discussed noise factor can be optimized with the degree of freedom in Section 2.2. A feedback bufer is added between the LNA brought by the active feedback. Te layout parasitic is also output and input, which is used to further map the bandpass signifcantly afecting the NF. Te noise of gate resistances is fltering characteristic of 4-path passive mixer to the input of directly amplifed to the output; low resistance metal layers LNA.SincethereceivernoisefgureisdominatedbytheLNA, should be used for gate connections. it should be carefully designed. According to [12], the noise AsshowninFigure6,mainampliferwithCMOS fgureofLNAcanbecalculatedas structureisusedinLNA,whichincreases2xcurrent 6 Wireless Communications and Mobile Computing

C0 R1

R 1 RQ 2nC0

C1 C C2 R 1 R＇；ＣＨ1 ＇；ＣＨ2 R2 +− OP1 OP2 OP3 −+ R＇；ＣＨ1 R ＇；ＣＨ2 R2 C1 C1 C2

R1 RQ

R1 0.5r 16

r8 r8

2r 4 2r 4

4r 2 4r 2

8r 1 8r 1 0.5(R − r) 0.5(R − r) R − r 2(R − r) 4(R − r) R − rR−r 2(R − r) 4(R − r)

Figure 7: Te proposed architecture of 3rd-order Butterworth low-pass active-RC flter.

efciency. CMOS LNA can also cancel out the second order Feedforward stage Input stage Output stage nonlinearity by properly sizing. A linearization technique called “derivative superposition” [7, 15] is used to improve the linearity of LNA because it determines the linearity of whole RX. Te third derivatives (g3) of drain current from the main and auxiliary transistors are added to cancel I＜Ｃ；Ｍ V VＣＪＪ V VＩＪ distortion. Because g3’s sign is diferent at the moderate and ＣＨＨＩＨ strong inversion region, zero g3 can be created by proper biasingthetransistors.Teauxiliaryinverteronlycontains weak-inversion transistors, resulting in much smaller power consumption than the common feedforward technique. Figure 8: Schematic of two-stage feedforward compensated opamp. 3.2. Filter. Figure 7 is the proposed 3rd-order Butterworth low-pass flter. Te flter consists of two main stages. For higher linearity, the Tow-Tomas biquad flter is arranged afer a frst-order flter. Programmable resistor and capacitor in Figure 9. Te low-pass feedback circuit will make the flter arrays are designed to adjust gain and compensate for process indicate high-pass feature at relatively low frequency. variations. Feedforward compensated amplifer has less power dis- 3.3. ADPLL. Based on the blocking requirement, the code- sipation than miller-compensated opamps when reaching sign between the RF front end and ADPLL is necessary. the same design index [16]. A typical two-stage feedforward Te LO phase noise at 1 MHz ofset should be less than compensated amplifer is used in this work, as shown in −116 dBc/Hz with 6 dB margin. Both of the efects of recip- Figure 8. To further lower power and area, local common- rocal mixing of the blocker and the white noise introduced mode feedback circuit is applied. To meet the demand of to signal band are considered. A DTC-assisted fractional- ripple (<0.2dB),theGBWofop1,op2,andop3inFigure6 N ADPLL is employed with a time-amplifed TDC, as are 400 MHz, 200 MHz, and 200 MHz, respectively. showninFigure10.TeTDCemploystimeamplifer(TA) For high gain flter, it is necessary to eliminate input DC realizing fne resolution. DTC is used with phase prediction ofset. Te DC ofset cancellation (DCOC) circuit is shown algorithmtoreducethedetectionrangeofTDC.Δ ∑-DTC Wireless Communications and Mobile Computing 7

5dBm.AndthereceivedsignalissweptfromFLO −100 MHz DCOC C to FLO +100 MHz. It shows that S11 <−10 dB over a R d1 d2 Rd1 −+ 0.6–0.9 GHz RF range. Te matching point is tunable with LO frequency and forms a narrow-band matching character +− R R which can improve the linearity of the receiver. d2 C d1 d1 Figure 14 shows the measured baseband noise fgure of the receiver. We measured a minimum noise fgure of 5.3 dB at 1 MHz with the LO frequency of 900 MHz. Both thesimulatedandmeasuredNFareingoodagreement.Te R 1 simulated result is about 1 dB lower than the measured one.

RQ Te NF discrepancy is mainly due to layout parasitic which can lower the transconductance of LNA and the inaccuracies C 1 C2 of the noise model in simulation. R＇；ＣＨ2 R2 +− +− Te OB-IIP3 is measured at LO frequency of 900 MHz. OP2 OP3 −+ −+ Two blockers with −25 dBm input power are injected. IIP3 R＇；ＣＨ2 R2 C1 C2 is measured at diferent frequency ofsets. Figure 15 shows the test result of the OB-IIP3. It shows that due to the RQ efect of impedance mapping, with the increase of the ofset

R1 frequency, IIP3 increases. Te highest point of linearity is mainly limited by the on-resistance of mixer and the linearity Figure 9: DCOC circuit of two-stage low-pass flters. of LNA. Te slope of the change in linearity is mainly limited by the capacitance size before the TIA. Te in-band IIP3 is about −10 dBm, and the out-band IIP3 is +8 dBm at 60 MHz ofset. can be cascaded with DTC to suppress the spur induced Te OB-IIP2 is measured at LO frequency of 900 MHz by DTC quantization. Autocontroller algorithm and gear- − shif technique helps to reduce the locking time to less than as the IIP3 test method. Two blockers with 25 dBm input 20 us. power are injected. And two blockers are separated by 1MHz, TDC and DCO are the most power-consuming blocks with an ofset from LO frequency. Figure 16 shows the in the traditional ADPLL, so some techniques are used to test result of the IIP2. It shows that, due to the efect of lower power dissipation of these parts. Firstly, TDC snapshot impedancemapping,withtheincreaseoftheofsetfrequency, is utilized to reduce the sampling rate from CKV to CKVS IIP2 increases. Te out-band IIP2 is greater than +39 dBm (=FREF),andtheDTCcanreducetheTDCdetection without any calibration. Tis IIP2 is limited by the mixer range, which contributes to a prominent power reduction. mismatch and second nonlinearity of the gain stages. Since Secondly, a low-supply structure DCO is designed in this a CMOS LNA architecture is used in this work, IIP2 is work, which consumes just 900 uW at 1.5–2.05 GHz. A TA- improved in the proposed receiver. Te measured result of TDC is designed to achieve high quantization to improve in- this impedance transparent receiver is summarized in Table 2 band phase noise. Te DCO is followed by an inductor-less 2x with comparisons of prior arts. Te proposed low power divider to provide a reasonable input frequency for the phase RX architecture has a suitable noise fgure and linearity ∘ digitization circuits. Te divider generates four 90 -spaced for IoT application and shows a good out-of-band blocker phases. tolerance.

4. Measured Results 5. Conclusion TischipisfabricatedinSMIC55nm1P7MCMOStech- A low power impedance transparent receiver for IoT appli- nology. Figure 11 shows the die photograph of the receiver. cation is proposed in this paper. A reconfgurable receiver Te core area of the chip is 2.3 mm × 1 mm, and the ADPLL withtunablechannelflteringandnarrow-bandinputmatch- occupied 1 mm × 1.2 mm due to the inductor of DCO. ing at RX input is presented. Passive mixer and active As shown in Figure 12, the in-band phase noise is feedback LNA are used in the receiver to further map about −95 dBc/Hz and the out-band phase noise is about the baseband impedance to RF input. A 3rd-order active- −120 dBc/Hz at 1 MHz frequency ofset, which can satisfy the RCflterisemployedinthereceiverformeetingtheIoT requirement of NB-IoT protocol [8]. Te rms jitter is about requirements. Te flter achieves a relatively low power with 1.1 ps which is integrated from 1 kHz to 10 MHz. Te whole the use of current-efcient feedforward compensated OTA. power consumption of ADPLL is about 4 mW. Digital controlled resistor and capacitor arrays are fexible Te measured S11 of the receiver with diferent LO for gain and bandwidth tuning. A DTC-assisted fractional-N frequency is shown in Figure 13. Using the SPI the ADPLL ADPLL is employed with a time-amplifed TDC. By utilizing was set up to LO frequency, respectively (1.2 GHz/1.4 GHz/ blocker fltering and derivative superposition techniques, the 1.6 GHz/1.8 GHz/2 GHz). Ten the LO power was expected as proposed RX achieves NF of 5.3 dB with +8 dBm OB-IIP3 8 Wireless Communications and Mobile Computing

Table 2: Comparison with prior arts.

Parameter Tis work [13] [14] [5] [6] Selectiveinputmatching Yes No No Yes Yes LNA with Mixer Noise Architecture Balun LNA Current mode LNA active feedback frst cancelling Operation frequency 0.6∼1 GHz 0.75∼0.96 GHz 1.0–5.2 GHz 0.1–2.4 GHz 0.08–2.7 GHz Gain 78 dB 20∼104 dB 23 dB 40–70 dB 72 dB Noise fgure 5.3 dB 5.1/4 dB 6.5 dB 7 dB @ 2 GHz 1.9 dB IB-IIP3 −10 dBm −6.2dBm@MinGain - −67 dBm −18 dBm OB-IIP3 +8 dBm - −1.5 dBm +25 dBm +13.5 dB IIP2 39 dBm 45 dBm @ Min Gain - +56 dBm +85 dBm Technology 55nmCMOS 180nmCMOS 130nmCMOS 65nmCMOS 40nmCMOS 16 mW RX 13 mW RX Core power 25 mW @1.7V 37–70 mW 35.1–78 mW +4 mW ADPLL +22 mW LO

1.5∼2.05 GHz Loop Filter PI Filter IIR Filter ／４７C DCO DCO RPA Output FCW PHR_I + fR ／４７M /2 + PHE KM Divider Σ PHR_F Snap Shot − NTW f CKR R ／４７F   F DTC K ΣΔ Eps PHV

CTRL EN CKR DTC CKVS /4 TDC Σ 1 Divider DFF FREF FREF_dly DFF VPA CKR CKR CKV CKV

Figure 10: ADPLL architecture.

−6

LO-deﬁned S11 −7 Narrow-band input matching

−8

Figure 11: Die photograph of the chip in 55 nm CMOS. (dB) −9 S11

−10

−11 S11 < −10 dB

0.6 0.8 1 RF Frequency (GHz) Figure 13: Measured S11 of the receiver with diferent LO frequency.

while consuming 16 mW. Te ADPLL in-band phase noise is about −95dBc/Hzandtheout-bandphasenoiseisabout Figure 12: Measured phase noise of the frequency synthesizer. −120 dBc/Hz at 1 MHz frequency ofset, while consuming Wireless Communications and Mobile Computing 9

20 4 mW.Te proposed receiver architecture can be used for low power IoT application, such as IEEE 802.11ah and NB-IoT. Tested NF @ Vout, I 15 Conflicts of Interest Simulated NF @ Vout, I Te authors declare that there are no conficts of interest ．＆ = 5.3 1 10 dB @ MHz regarding the publication of this paper. F，／ = 900 MHz NF (dB) Acknowledgments 5 TisworkissupportedbyNationalNaturalScienceFounda- tion of China (nos. 61574045 and 61774048), National Science and Technology Major Project (no. 2016ZX03001012-003), 0 and National High Technology Research and Development 5 6 7 10 10 10 Program (no. 2015AA016601-005). Frequency (Hz) Figure 14: Measured baseband noise fgure of the receiver (FLO = 900 MHz). References

10 [1] R. Ratasuk, B. Vejlgaard, N. Mangalvedhe, and A. Ghosh, “NB- IoT system for M2M communication,”in Proceedings of the 2016 IEEE Wireless Communications and Networking Conference, 5 WCNC 2016,April2016. IIP3 = +8.1 dBm [2] M. Park, “IEEE 802.11ah: Sub-1-GHz license-exempt operation @ 80 MHz ofset for the internet of things,” IEEE Communications Magazine,vol. 0 53,no.9,pp.145–151,2015. Tone 1 Tone 2 −25 dBm −25 dBm [3] J.-P. Bardyn, T. Melly, O. Seller, and N. Sornin, “IoT: Te (dBm) era of LPWAN is starting now,” in Proceedings of the 42nd −5

IIP 3 European Solid-State Circuits Conference, ESSCIRC 2016,pp.25– RX 30, September 2016. Δf Δf [4] H.Hedayati,W.-F.A.Lau,N.Kim,V.Aparin,andK.Entesari,“A −10 1.8 dB NF blocker-fltering noise-canceling wideband receiver withsharedTIAin40nmCMOS,”IEEE Journal of Solid-State Circuits,vol.50,no.5,pp.1148–1164,2015. −15 900 920 940 960 980 [5] C. Andrews and A. C. Molnar, “A passive mixer-frst receiver with digitally controlled and widely tunable RF interface,” IEEE Frequency (MHz) Journal of Solid-State Circuits,vol.45,no.12,pp.2696–2708, F，／ = 900 MHz 2010. Figure 15: Measured IIP3 at 900 MHz for diferent frequency ofsets. [6] D. Murphy, A. Hafez, A. Mirzaei et al., “A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise fgure,” in Proceedings of the 59th International Solid-State Circuits 40 Conference (ISSCC ’12),pp.74-75,SanFrancisco,Calif,USA, February 2012. 35 IIP2=+39dBm [7] V. Aparin and L. E. Larson, “Modifed derivative superposition @ 45 MHz ofset 30 method for linearizing FET low-noise amplifers,” IEEE Trans- Tone 1 & 2 actions on Microwave Teory and Techniques,vol.53,no.2,pp. −25 dBm 25 571–580, 2005.

(dBm) [8] Technical Report for BS and UE Radio Transmission and 20 RX Reception (Release 13), document TS 36.802, 3GPP. IIP 2 Δf [9] S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, 15 and B. Nauta, “Te Blixer, a wideband balun-LNA-I/Q-mixer topology,” IEEE Journal of Solid-State Circuits,vol.43,no.12, 10 pp. 2706–2715, 2008. [10] A. Mirzaei, H. Darabi, J. C. Leete, and Y. Chang, “Analysis 0 900 910 920 930 940 950 and optimization of direct-conversion receivers with 25% duty- cycle current-driven passive mixers,” IEEE Transactions on Frequency (MHz) Circuits and Systems I: Regular Papers,vol.57,no.9,pp.2353– F，／ = 900 MHz 2366, 2010. Figure 16: Measured IIP2 at 900 MHz for diferent frequency [11] R. Behzad, RF Microelectronics,vol.2,PrenticeHall,NewJersey, ofsets. USA, 1998. 10 Wireless Communications and Mobile Computing

[12] J. Borremans, P. Wambacq, C. Soens, Y. Rolain, and M. Kuijk, “Low-area active-feedback low-noise amplifer design in scaled digital CMOS,” IEEE Journal of Solid-State Circuits,vol.43,no. 11, pp. 2422–2433, 2008. [13] Z.Song,X.Liu,X.Zhao,Q.Liu,Z.Jin,andB.Chi,“ALow-Power NB-IoT Transceiver With Digital-Polar Transmitter in 180-nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers,vol.64,no.9,pp.2569–2581,2017. [14] J. Kim and J. Silva-Martinez, “Low-power, low-cost CMOS direct-conversion receiver front-end for multistandard applications,” IEEE Journal of Solid-State Circuits,vol.48,no.9,pp. 2090–2103, 2013. [15] Y. S. Youn, J. H. Chang, K. J. Koh, Y. J. Lee, and K. H. Yu, “A 2GHz 16dBm IIP3 low noise amplifer in 0.25�mCMOS technology,” in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 452–507, San Francisco, CA, USA. [16] N. Krishnapura, A. Agrawal, and S. Singh, “A high-IIP3 third-order elliptic flter with current-efcient feedforward- compensated opamps,” IEEE Transactions on Circuits and Sys- tems II: Express Briefs,vol.58,no.4,pp.205–209,2011. Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 8234615, 6 pages https://doi.org/10.1155/2018/8234615

Research Article A 0.45 W 18% PAE E-Band Power Amplifier in 100 nm InGaAs pHEMT Technology

Dixian Zhao and Yongran Yi

National Mobile Communication Research Laboratory, School of Information Science and Engineering, Southeast University, Nanjing 211189, China

Correspondence should be addressed to Dixian Zhao; [email protected]

Received 21 October 2017; Revised 27 January 2018; Accepted 27 February 2018; Published 29 March 2018

Academic Editor: Enrico M. Vitucci

Copyright © 2018 Dixian Zhao and Yongran Yi. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Tis paper describes a fully integrated power amplifer (PA) in 100 nm InGaAs pHEMT process for E-band point-to-point communications. Te device size and biasing conditions are optimized to enhance the overall performance at millimeter-wave frequencies. Te complete PA consists of two unit PAs and each unit PA has four stages to improve the gain while ensuring stability from dc to the operating frequencies. A 4-way zero-degree combiner (in the unit PA) and a 2-way �/2 combiner are used to boost 2 the output power. Occupying 5 mm , the proposed PA achieves an output power of 0.45 W with 17.9% PAE at 74 GHz.

1. Introduction 1W�OUT duetothehighbreakdownvoltagewhileInPPAs [6] achieve PAE as high as 40% thanks to the high ��/�MAX. Tere is an increasing need of E-band technology for future Nevertheless, GaAs technology [8–10] has the advantages 5G network infrastructure, such as wireless backhaul. In of relatively low cost, high yield, and easy foundry access, wireless backhaul systems, highly directional antennas are ofering an attractive alternative for E-band applications. employed at both transmitter and receiver sides to compensate for the path loss [1, 2]. For example, FCC Part 101 Rules In this paper, we report a fully integrated E-band PA in [3] require a minimum antenna gain of 43 dBi to ensure the 100 nm InGaAs pHEMT technology. Circuit optimizations E-band radio equipment transmitting “pencil beams” to ease have been applied to active device, unit PA, layout foorplan, and power combining structures to enhance the gain, output interference analysis and spatial coordination of links. Nev- 2 ertheless, for a multi-Gbps link exceeding multikilometer power, efciency, and stability. Te proposed 5 mm PA dem- distance, a watt-level power amplifer (PA) is required to onstrates a measured power gain of 20.6 dB and an output ensure 99.99% weather availability worldwide [1, 2]. Such power of 26.5 dBm with 17.9% PAE. Section 2 details the circuit optimizations regarding the transistor biasing, amplifer output power (�OUT)requirementassignsnewtaskforthe fully integrated power amplifers (PAs) at millimeter-wave stage, and power combining structure. Section 3 shows the (mm-Wave) frequencies. measurement results with the conclusion given in Section 4. Although the ever-increasing speed of MOS transistors provides new opportunities to mm-Wave designers, the low 2. Design Considerations and breakdown voltage limits the output power of E-band CMOS Circuit Implementation PAs to about 0.1 W [2, 4, 5]. Te work in [6] demonstrated an E-band SiGe PA with 27.3 dBm �OUT,butitmaysufer Te power amplifer prototype was designed in a commercial additional loss in the packaging due to the placement of 100 nm InGaAs pHEMT process (��/�MAX = 130/200 GHz) the output pads at the center of the die. Terefore, watt- with a breakdown voltage of 8 V and saturated output power level E-band PAs still remain in the domain of compound density of about 600 mW/mm at a normal supply voltage semiconductors. At E-band, GaN PAs [7] deliver more than of 4 V. Te wafer thickness is 50 �m. In this work, the PA 2 Wireless Communications and Mobile Computing

8.5 22

8 20 7.5 (dBm) 7 3＞＂ Gain (dB) Gain 18 P 6.5

6 16 −0.45 −0.45 2 2 −0.35 −0.35 V 3 V 3 ＇ (V) (V) ＇ (V) (V) −0.25 4 V＄＄ −0.25 4 V＄＄ (a) (b)

40 40

39 (%) 30 3＞＂ FOM 38 ０！％

20 37 −0.45 −0.45 2 2 −0.35 −0.35 V 3 V 3 ＇ (V) (V) ＇ (V) (V) −0.25 4 V＄＄ −0.25 4 V＄＄ (c) (d)

Figure 1: Single-stage PA metrics versus transistor biasing at 75 GHz: (a) gain, (b) �3 dB,(c)PAE3 dB,and(d)FOM= Gain (dB)+�3 dB (dBm)+ 10 log[PAE3 dB (%)]. simulations were performed in ADS based on the PDK enhanced output power at 4 V. As the PA operates at a large models while all the passive devices were characterized with fraction of ��/�MAX, the limited power gain has a direct ADS momentum. impact on the PAE. As a result, PAE3 dB peaks at �DD of 2 V and �G of −0.45 V despite the fact that the PA achieves 2 dB � � 2.1. Transistor Design: Optimum Biasing. In this work, the more 3 dB at DD of 4 V. Such issue becomes even severe transistor’s biasing voltages are optimized based on the afer including the loss of matching circuits. In this design, we following PA fgure-of-merit (FOM), given by chose the biasing points based on the FOM which equals the sumofthepowergain,�3 dB,andPAE3 dB.Figure1(d)shows � � − FOM = Gain (dB) +�3 dB (dBm) that the FOM peaks at DD of 3 V and G of 0.35 V,giving the (1) power gain, �3 dB,andPAE3 dB of 7.8dB, 19.5 dBm, and 31.6%, +10log [PAE3 dB (%)], respectively, at 75 GHz. Besides, an important feature for the 50 × 4 �mtransistor where gain, �3 dB,andPAE3 dB represent the power gain under under such biasing confguration is that the gain match and power match, the 3 dB compressed output power (�3 dB), and power match can be nearly achieved simultaneously, which the PAE at �3 dB (PAE3 dB), respectively. Figure 1 shows the signifcantly reduces the design eforts. Note that though 25 × simulated power gain, �3 dB,PAE3 dB,andthecalculatedFOM 4 �m transistor shows relatively high maximum small-signal versus diferent gate voltage (�G)anddrainvoltage(�DD)at gain, it is potentially unstable at E-band and shows 3 dB � × � 75 GHz. In the design, the device size of 50 m 4(i.e.,50 m lower �OUT than 50 �m one which will complicate the power fnger width, four fngers) is selected to balance the power combining network for the same �OUT requirement. gain and output power. Te ideal lossless input and output matching circuits are retuned for each biasing condition for 2.2. Unit PA Design: Gain, Power, and Stability. Using the fair comparison. From Figure 1, it is obvious that the PA optimum device size and bias confgurations, a fully inte- has increased gain at a supply voltage of 2 V and it shows grated unit PA is designed, as shown in Figure 2, where the Wireless Communications and Mobile Computing 3

V＞＞ V＞＞ Bond wire CＩﬀ-＝ＢＣＪ Vg Cc Cd V＞＞ V＞＞ Vg

∘ Vg Rg 90

４，g RＩ＞＞

Out

RＩ＞＞４，7

C1 In ４， 2 ４，3 M1 ４，6 C2 ４， C ４，1 5 3 M2 ４，4 M4 M3

M1 M2 M3 M4 C1 C2 C3 50 Ｇ × 2 50 Ｇ × 2 50 Ｇ × 2 50 Ｇ × 4 46fF 80fF 87fF

４，1 ４，2 ４，3 ４，4 ４，5 ４，6 ４，7 36 Ω, 48∘ 36 Ω, 26∘ 95 Ω, 32∘ 65 Ω, 15∘ 95 Ω, 12∘ 36 Ω, 40∘ 30 Ω, 25∘

Figure 2: Simplifed schematic of the E-band unit power amplifer. details of the device parameters are also summarized. Te driver stages and output stage are very limited, such design unit PA consists of four stages to achieve more than 20 dB methodology ensures that the PA output stage can be driven power gain and thus relax the input power requirement. To into saturation while three driver stages consume relatively provide sufcient driving power and in order not to saturate lowdcpower[12]. prior to the output stage, the total transistor width of three As the transistor has much higher power gain at low driver stages is scaled down by a factor of two progressively. frequencies, the stability there becomes a big concern. Sim- A 4-way zero-degree transmission-line (T-line) combiner ulation predicts that the unit PA is potentially unstable in the [11] is employed to sum up �OUT of the four 50 �m × 4 rangeof25GHz.Totacklethis,�� is introduced at each stage devices in the PA output stage. Compared to Wilkinson to close the loop and thereby signifcantly reduce the power combiner, the zero-degree combiner signifcantly reduces the gain at low frequencies where the �/4 dc-feeding T-lines show chip area and insertion loss while transforming the 100 Ω relatively low impedance and �� shows high impedance. load to the optimum load impedance of each 50 �m × 4 Consequently, the unit PA is unconditionally stable from dc device. Te port isolation is not a major constraint here as to the operating frequencies and the in-band performance is all the combiner inputs have no phase diference. Te 350 �m not degraded at all. �/4 T-lines are used as RF choke to feed the supply and the T-lines in grey (TL�) are used to distribute the supply 2.3. Power Enhancement: Half-Wavelength T-Line Combiner. networks for the amplifer stages at lower side. Both TL� and To further enhance the output power, the complete PA com- �odd (see Figure 2) can help to reduce the gain of internal bines �OUT of two unit PAs using �/2 T-line power combiner, loops and thus eliminate potential oscillations. Te capacitor shown in Figure 3. A characteristic impedance (��)of70Ω �� provides a short to ground in the range of operating is chosen to balance the insertion loss and bandwidth. In frequencies. Extensive EM simulations have been performed this case, compared to Wilkinson and zero-degree combiners on the complete passive circuits to take into account the [11], the �/2 T-line combiner is compact and straightforward mutual couplings between all the passive components. Te to implement and has relatively broad bandwidth. More simulated �5 dB and PAE5 dB for the unit PA equal 24.9 dBm importantly, it is not sensitive to the process variations while and 22%, respectively. Note that, at �5 dB,thePAoutput covering a distance as long as 700 �m between the outputs of stage is compressed by roughly 3 dB while the three driver the two unit PAs. Including output GSG pads, the insertion stages are compressed by 2 dB. As the power gains of both loss of the �/2 T-line combiner is 0.68–0.71 dB at 75 GHz for 4 Wireless Communications and Mobile Computing

30 Unit ０！）． PA 25 P5＞＂

75 Ω, 75 Ω, ∘ ∘ (sim) 180 180 20 S21

Unit S21 PA ０！／５４ 15 -parameters (dB) -parameters Figure 3: Power splitting and combining topologies based on �/2 S 10 T-lines. 5

0 60 70 80 90 Frequency (GHz)

(a) 0

−10

−20 S11 S22 −30 -parameters (dB) -parameters

S −40 Figure 4: Chip micrograph.

−50 S12 ∘ a ±20% variation in ��.Tocompensate180 phase diference, a �/2 T-line power divider is used at the input. −60 60 70 80 90 Frequency (GHz) 3. Measurement Results (b)

Te PA prototype is fabricated in a 100 nm InGaAs pHEMT Figure 5: (a) Measured �21, �5 dB,andsimulated�21;(b)measured process. Te chip micrograph is shown in Figure 4. Including � � � 2 11, 12,and 22. RF and dc pads, the chip occupies an area of 5 mm . Measurements are performed on a high-frequency probe station. Te input and output RF pads are accessed by GSG Te 2 dB diference in gain can be attributed to the process probes while dc pads are wire-bonded to a PCB. Te supply variation and mutual couplings between multiple stages. Te voltage for the PA is 3 V. inaccurate modelling of back vias could be another issue as Figure 5 shows the measured S-parameters. Te PA ADS momentum is a 2.5D electromagnetic (EM) simulator. achieves a peak �21 of 20.8 dB at 74 GHz with the 3 dB Table 1 compares the PA prototype to the state-of-the-art bandwidth of 7.5 GHz. Tanks to the optimum transistor E-band PAs in GaAs, InP, SiGe, and CMOS. Albeit diferent sizing and biasing, ensuring simultaneous gain match and technologies used, it can be seen that high output power power match, �22 is better than −10 dB from 71.5 to 78.5 GHz. will lead to relatively low efciency owing to the loss in the �11 is better than −10 dB from 71 to 77 GHz while �12 is smaller power combining network. Te work [6] in 250 nm InP with than −48 dB from 60 to 90 GHz. Te PA is unconditionally ��/�MAX of400/700GHzshowsanimpressivePAE.Tanks stable in the measured frequencies. In addition, the output to the proposed design techniques, this PAachieves both high spectrum is carefully checked from dc to 90 GHz and no output power and high efciency in 100 nm InGaAs pHEMT, oscillationappearsatthePAoutput.Telarge-signalbehavior competingwellwithprior-artsatE-band. ofthePAat74GHzisshowninFigure6.TePAachievesa � � � measured 1 dB, 3 dB,and 5 dB of 23.8, 25.5, and 26.5 dBm, 4. Conclusion respectively. PAE5 dB is 17.9%. From 71 to 79 GHz, the measured output power is more than 25 dBm (see Figure 5). An E-band PA has been implemented in 100 nm InGaAs Te measured and simulated results are in good agreement. pHEMT process. To enhance the single-stage amplifer Wireless Communications and Mobile Computing 5

Table 1: Performance summary and comparison.

Technology �DD (V) Frequency (GHz) Gain (dB) �5 dB (dBm) PAE5 dB (%) Tis work 100 nm GaAs 3.0 74 20.8 26.5 17.9 1 1 1 [8] 100 nm GaAs 4.0 83 15.0/18.7 28.5/26.5 N/A/15.0 2 [9] 100 nm GaAs 3.5 81 25.0 20.0 N/A 2 2 [10] 100 nm GaAs 4.0 76 15.0 23.0 8.0 [7] 140 nm GaN 14.0 93.5 16.3 33.3 19.0 [13] 250 nm InP 2.5 76 15.5 26.4 26.9 [14] 250 nm InP 2.5 81 22.0 21.1 40.0 3 3 [6] 90 nm SiGe 1.8 76 19.3 25.0 9.0 2 2 [15] 130 nm SiGe 2.5 84 27.0 18.0 9.0 [2] 40 nm CMOS 0.9 78 18.1 20.3 22.3 [4] 40 nm CMOS 1.8 73 25.3 21.5 16.5 [5] 65 nm CMOS 1.0 79 24.2 19.0 18.5 1 2 3 �4 dB and PAE4 dB. �SAT and PAESAT. Graphically estimated.

30 Foundation of Jiangsu Province (no. BK20160690), and the Gain Fundamental Research Funds for the Central Universities.

20 References

[1] J. Wells, Multigigabit Microwave and Millimeter-Wave Wireless P

(dB, dBm, %) dBm, (dB, 10 ／５４ Communications,ArtechHouse,Norwood,MA,USA,2010. PAE [2] D. Zhao and P. Reynaert, “An E-band power amplifer with broadband parallel-series power combiner in 40-nm CMOS,” 0 IEEE Transactions on Microwave Teory and Techniques,vol.63, −15 −10 −5 010155 no. 2, pp. 683–690, 2015. Input power (dBm) [3] FCC, “Fixed Microwave Services,” https://www.ecfr.gov/cgi- Figure 6: Measured and simulated (dashed) gain, output power, and bin/text-idx?SID=c7ae99179c50117778f4df6787b0fc&mc= PAEversusinputpowerat74GHz. true&node=pt47.5.101&rgn=div5#se47.5.101 1115. [4] D. Zhao and P. Reynaert, “A 40-nm cmos E-band 4-way power amplifer with neutralized bootstrapped cascode amplifer and performance, device size and biasing conditions are fne optimum passive circuits,” IEEE Transactions on Microwave tuned. A 4-way zero-degree combiner and a 2-way �/2 Teory and Techniques, vol. 63, no. 12, pp. 4083–4089, 2015. combinerareusedtoimprovetheoutputpower.Attention [5] K.-Y. Wang, T.-Y. Chang, and C.-K. Wang, “A 1V 19.3dBm has been paid to the PA stability in order to ensure no 79GHz power amplifer in 65nm CMOS,” in Proceedings of the oscillations appearing from dc to the operating frequencies. 59th International Solid-State Circuits Conference (ISSCC ’12), 2 Te 5 mm PA achieves an output power of 0.45W with pp.260-261,February2012. 17.9% PAE at 74 GHz. For future work, improvement can be [6] H.-C. Lin and G. M. Rebeiz, “A 70-80-GHz sige amplifer done to reduce the insertion loss of the output combiner with peak output power of 27.3 dBm,” IEEE Transactions on and thus further enhance the output power and efciency. Microwave Teory and Techniques,vol.64,no.7,pp.2039–2049, A highly efcient 16-way power combiner can also be inves- 2016. tigated to double the output power. At E-band, the GaAs [7]M.Micovic,A.Kurdoghlian,A.Margomenosetal.,“92-96 PA outperforms the CMOS PA regarding the output power GHz GaN power amplifers,” in Proceedings of the IEEE MTT-S while it achieves low cost, high yield, and easy foundry access International Microwave Symposium (IMS ’12), Junuary 2012. when compared to InP and GaN PAs. Terefore, GaAs PA [8] E. Camargo, J. Schellenberg, L. Bui, and N. Estella, “Power provides attractive solutions for future long-haul point-to- GaAs MMICs for E-band communications applications,” in point communications at E-band. Proceedings of the 2014 IEEE MTT-S International Microwave Symposium (IMS ’14),June2014. Conflicts of Interest [9]F.D.CanalesandM.Abbasi,“A75-90GHzhighlinearity MMIC power amplifer with integrated output power detector,” Te authors declare that they have no conficts of interest. in Proceedings of the 2013 IEEE MTT-S International Microwave Symposium Digest (MTT ’13),June2013. Acknowledgments [10] M. C. Rodriguez, J. Tarazi, A. Dadello et al., “Full ETSI E- band doubler, quadrupler and 24 dBm power amplifer,” in Pro- TisworkispartlyfundedbytheNationalNaturalScience ceedings of the 2012 IEEE Compound Semiconductor Integrated Foundation of China (no. 61674035), the Natural Science Circuit Symposium (CSICS ’12),October2012. 6 Wireless Communications and Mobile Computing

[11] W. Tai, L. R. Carley, and D. S. Ricketts, “A 0.7W fully integrated 42GHz power amplifer with 10% PAE in 0.13�m SiGe BiC- MOS,” in Proceedings of the 2013 60th IEEE International Solid- StateCircuitsConference(ISSCC’13), pp. 142-143, February 2013. [12] S. Cripps, RF Power Amplifer for Wireless Communications (Chapter 13.4 Multistage PA Design), Artech House, 2nd edition, 2006. [13] Z. Grifth, M. Urteaga, P. Rowell, and R. Pierson, “340- 440mW Broadband, High-Efciency E-Band PA’s in InP HBT,” in Proceedings of the 37th IEEE International Symposium on Workload Characterization, (CSICS ’15),October2015. [14]Z.Grifth,M.Urteaga,P.Rowell,andR.Pierson,“71-95GHz (23-40% PAE) and 96-120 GHz (19-22% PAE) high efciency 100-130 mW power amplifers in InP HBT,” in Proceedings of the 2016 IEEE MTT-S International Microwave Symposium (IMS ’16),May2016. [15]Y.ZhaoandJ.R.Long,“AWideband,dual-path,millimeter- wave power amplifer with 20 dBm output power and PAE above 15% in 130 nm SiGe-BiCMOS,” IEEE Journal of Solid-State Circuits,vol.47,no.9,pp.1981–1997,2012. Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 4510243, 11 pages https://doi.org/10.1155/2018/4510243

Research Article Digital Predistortion of Ultra-Broadband mmWave Power Amplifiers with Limited Tx/Feedback Loop/Baseband Bandwidth

Chao Yu , Qianyun Lu, Honglei Sun, Xingwang Wu, and Xiao-Wei Zhu

State Key Laboratory of Millimeter Waves, School of Information Science and Engineering, Southeast University, Nanjing 210096, China

Correspondence should be addressed to Chao Yu; [email protected]

Received 2 November 2017; Revised 9 January 2018; Accepted 13 February 2018; Published 19 March 2018

Academic Editor: Christian Fager

Copyright © 2018 Chao Yu et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

A novel digital predistortion (DPD) technique is proposed to linearize ultra-broadband millimeter wave (mmWave) power amplifers (PAs) by only employing very limited bandwidth resources for the Tx, feedback loop (FB), and baseband (BB). Compared to the conventional methods, the proposed method will comprehensively reduce the bandwidth requirements for the whole system, which will make the linearization afordable for mmWave PAs. To validate the proposed idea, a 4-carrier 320 MHz modulated signal was employed to excite a mmWave PA with the center frequency of 41 GHz. Experimental results have proven that the proposed method can efectively realize the PA linearization with very narrow Tx/FB/BB bandwidth, which largely extends the capability of DPD to the forthcoming 5G era.

1. Introduction DPDtechnique,manyefectivemodelshavebeenproposed in recent years [5], such as dynamic deviation reduction- Te ffh-generation (5G) communication systems have grad- based Volterra series model (DDR) [6], decomposed vec- ually attracted more and more attentions from both academia tor rotation-based model (DVR) [7, 8], memory polyno- andindustry.Sincewidebandspectrumresourceisrequired mial model (MP) [9], and generalized memory polynomial to support the ultimate goal of 10 Gbps [1], millimeter wave model (GMP) [10]. Usually, in baseband (BB) processing, (mmWave) frequency band is one of the most promising can- the DPD characteristics will be modeled by the nonlinear didates in 5G frequency plan, as shown in Figure 1(a). Many operators, which normally occupy multiple times the input countries have gradually released their drafs for the mmWave bandwidth. For example, the 5th-order nonlinear operator frequency band allocations around 28 GHz and 40 GHz [2]. will occupy 5x the input bandwidth. Tus, the bandwidth To fully exploit the advantage of mmWave technique, ultra- for the transmitter chain (Tx) should be wide enough to broadband modulated signal, for example, 500 MHz, will support such 5x the input bandwidth. Furthermore, in be employed to enable high-speed transmission. However, order to realize accurate model extraction, the bandwidth this change will place a huge burden on RF circuit design, of the PA output will also keep 5x the input bandwidth especially for the linearization of ultra-broadband mmWave to capture all major nonlinear distortion in the feedback power amplifers (PAs). loop (FB) [11]. Terefore, in narrow-band scenarios, these Usually, the PAs need to operate at nonlinear region to bandwidth requirements for Tx/FB/BB are afordable and achieve high efciency, which will incur not only the in- thus the DPD systems work well and have been widely band distortion, but also the out-of-band (OOB) spectrum deployed. regrowth [3]. To overcome this problem, the digital predis- However, with the mmWave era coming, the modulated torter (DPD) has widely become a crucial block in modern bandwidth has been quickly increased in 5G wireless systems wireless transmitters [4], as shown in Figure 1(b). Tis as shown in Figure 1(a). Suddenly, the DPD systems are module can efectively remove the nonlinear distortion with facing huge bandwidth limitation as shown in Figure 1(b). very high accuracy but low cost. With the development of NotonlywillthesystemrequiretheTxandfeedbackloop 2 Wireless Communications and Mobile Computing

4G 5G Transmitter Output ＆Ｌ？Ｋ. < 6 ＇（Ｔ＆Ｌ？Ｋ. > 6 ＇（Ｔ, mmWave PA (Tx) Input Baseband ＂７ ≤ 100 －（Ｔ＂７ ≥ 500 －（Ｔ (BB) Feedback loop (FB)

DPD system, limited BW resources

(a) (b)

Figure 1: (a) Te frequency and bandwidth of 5G scenario. (b) Te challenge on DPD system for ultra-broadband mmWave wireless communication system.

DPD DPD DAC Upconverter PA DAC Upconverter PA generation generation Tx, 5x BW Tx, 5x BW

Model Model extraction ADC Downconverter extraction ADC Downconverter

Baseband, 5x BW Feedback loop, 5x BW Baseband, 5x BW Feedback loop, reduced BW

(a) (b)

DPD DAC Upconverter PA DPD generation DAC Upconverter PA BPF generation Tx, 5x BW Tx, reduced BW Model Model extraction ADC Downconverter extraction ADC Downconverter Baseband, Feedback loop, 5x BW Baseband, 5x BW Feedback loop, reduced BW reduced BW

Figure 2: Available resources for DPD systems. (a) Conventional DPD system. (b) DPD system with reduced FB bandwidth. (c) DPD system with reduced Tx/FB bandwidth. (d) DPD system with reduced BB bandwidth. with wider bandwidth, but also the baseband processing 2. The Bandwidth Requirements on units, such as FPGA, will also need high bandwidth to deal DPD System with high-speed data. Apparently, it is not cost-efective for mmWave scenarios to directly employ the conventional In a DPD system, the bandwidth requirements usually methods. includethreeparts:theFB,theTx,andtheBB[12].In this section, we will provide a detailed analysis for these re- In this paper, a comprehensive solution for these three quirements. bandwidth limitations will be proposed to further extend the DPD’s capability into the linearization of mmWave PAs. 2.1. Conventional DPD System. Generally, in a conventional Te proposed technique only employs the limited Tx/FB/BB 1 ∼2 DPD system, the baseband bandwidth for the DPD modules bandwidth, that is, x x the original input bandwidth, but will require at least fve times the input signal bandwidth to can achieve similar linearization performance. Furthermore, fully generate sufcient nonlinear components for satisfac- this technique will be validated by an mmWave PA centered tory linearization performance [11], as shown in Figure 2(a). at41GHzandexcitedwithamodulatedsignalwith320MHz Tis is because the major part of the predistorted signal will bandwidth. include the components from the fundamental one to the Te rest of the paper is organized as follows. In Section 2, 5th-order one. Here, 500 MHz modulated signal is taken for the DPD system with reduced Tx/FB/BB bandwidth will example. Terefore, at least 2500 MHz bandwidth will be be discussed. Ten, a novel solution will be proposed and required for the predistorted input signal generation. Tis explained in detail in Section 3. Te experimental results willplaceahugeburdenonthebasebandbandwidth,since for the ultra-broadband scenarios are provided in Section 4, thebasebandisusuallyrealizedbydigitalcircuits,suchas followed by a conclusion in Section 5. FPGA. Wireless Communications and Mobile Computing 3

Table 1: Te bandwidth requirement for a 500 MHz modulated signal.

Sampling rate (MSPS) BW (MHz) (i) Conventional DPD system Tx 5x = 3200 5x = 2500 Feedback loop 5x = 3200 5x = 2500 Baseband 5x = 3200 5x = 2500 (ii) DPD system with reduced feedback loop bandwidth Tx 5x = 3200 5x = 2500 Feedback loop <1x = 640 <1x = 500 Baseband 5x = 3200 5x = 2500 (iii) DPD system with reduced Tx/FB bandwidth Tx 1x-2x = 640–1280 1x-2x = 500–1000 Feedback loop 1x-2x = 640–1280 1x-2x = 500–1000 Baseband 5x = 3200 5x = 2500

Later, a wideband Tx will be involved, in which the Te successful reduction on FB bandwidth has its own digital-to-analog converters (DACs) should be able to sup- reason. It is because the goal of the feedback loop is only port such wide bandwidth. Normally, due to the factor of to extract the right DPD coefcients, which provides the the flter roll-of, the sampling rate (Fs) for DACs will be possibility of utilizing the undersampled feedback signals. slightly higher than the bandwidth value. Here, we set the From Figure 2(b), it can be seen that the FB bandwidth can roll-of factor to 0.28, and the sampling rate for I/Q baseband be reduced by diferent schemes, while the remaining parts signal should be 3200 MSPS, accordingly. Te rest of RF of DPD operation will remain unchanged. In this scenario, if components should also support such bandwidth to keep the the 500 MHz modulated signal is taken again as an example, signal transmitted properly. the FB bandwidth can be decreased to less than the original Similarly, in the FB, due to the spectrum regrowth input signal, but the bandwidth for other parts will still be generated by the PA, enough nonlinear distortion should very wide. Te details can be found in Table 1(ii). be captured to correctly describe the output signal. Like the predistorted signal, the output with 5x the input bandwidth 2.3. DPD System with Reduced Tx/FB Bandwidth. As men- will be considered to be enough for model extraction. Also, tioned above, even if diferent methods have been conducted the analog-to-digital converters (ADCs) should be able to to reduce the bandwidth requirements in the feedback loop, capture the output with such bandwidth. Te details have the Tx bandwidth will still be very wide. Te reason is that beenlistedinTable1(i).Fromthistable,itcanbeseenthat the bandwidth of the predistorted input signal decides the the Tx/FB/BB will face the huge challenge for 5G scenarios; linearization bandwidth. In other words, if the compensation that is, the bandwidth requirement is too high. of the distortion within a specifed range is required, the predistorted input signal with such range of bandwidth is 2.2. DPD System with Reduced Feedback Loop Bandwidth. expected to be provided. From this point of view, the predis- To alleviate the bandwidth pressure, many researchers have torted signal should occupy at least 5x the input bandwidth started to focus on the bandwidth reduction on the feedback to realize the full-band linearization. Terefore, it might be loop [13–21], as shown in Figure 2(b). Guan et al. [13] pro- impossible to lower the Tx bandwidth requirement without posed a bandwidth-constrained least squares-based model changing the DPD structure. extraction method to reduce the feedback loop bandwidth. Recently, the band-limited DPD solution [22, 23] has Ma et al. [14] proposed a wideband DPD technique using been proposed to resolve the issue of the bandwidth of spectral extrapolation of band-limited feedback signal. Liu Tx/FB, and consequently only 1x-2xinputbandwidthwill et al. [15, 16] proposed a general DPD architecture using be sufcient for the linearization. It is because this method constrained feedback bandwidth for wideband PAs. Tao et employs a diferent DPD architecture by introducing a band- al. in [17] proposed a random demodulation based reduced passflteraferPAasshowninFigure2(c).Itisworth sampling rate method. Wang et al. in [18, 19] proposed a novel mentioning that this flter can be integrated together with method using low feedback sampling rate to obtain the DPD thePAdesign.Basedonthisstructure,thedistortioncanbe coefcients, which is the same as the ones calculated with divided into two parts: (1) the one within the flter bandwidth high sampling rates. Huang et al. in [20] proposed a DPD and (2) the one out of the flter bandwidth. Te former function synthesis method by using undersampled feedback can be removed by the predistorted input signal, while the signal. Wang et al. [21] proposed a low feedback sampling rate latter can be eliminated by the flter. Since the distortion digital predistortion technique to linearize a PA excited by a bandwidthtobecompensatedisreduced,thepredistorted 40 MHz signal with only 2.5 MSPS feedback sampling rate. input signal bandwidth can also be reduced. Terefore, the With the help of these methods, the bandwidth requirement Tx bandwidth can be narrowed to only support the flter for feedback loop has been signifcantly reduced. bandwidth. Besides, due to the flter operation, the feedback 4 Wireless Communications and Mobile Computing

consume huge baseband bandwidth. In particular, for the (·) ultra-broadband mmWave scenario, the situation becomes severer. g1 x(n) y(n) Toresolve this dilemma, let us rethink it. Te decomposed (·)3 piecewise technique in [25] substitutes high-order operators 3x g2 by several low-order operators. Terefore, if we employ a set (·)5 of linear piecewise segments to describe the PA nonlinear characteristics and build the DPD functions, the required 5x g3 nonlinearitycanbeintroducedbythepiecewisesegments and the operations on each segment will be linear. Tus it will Figure 3: Te issue of DPD model bandwidth requirements for not require high baseband bandwidth. baseband. Tis operation can be expressed as

� loop bandwidth can also be reduced to the same level. � (�) = ∑�� ⋅�� (�) , (1) Terefore, this method can realize the bandwidth reduction �=1 both on Tx and FB. Here, we take the same example. If the input signal is a 500 MHz signal, the bandwidth requirement where �(�) is the predistorted signal, ��(�) is the decomposed for both Tx and FB will be only 1x∼2x the input bandwidth, input signal, and each segment is weighted by the linear that is, 500–1000 MHz. Te detailed information has been operator ��. listed in Table 1(iii). From this table, this method still requires To further reduce the bandwidth requirements of Tx and high baseband bandwidth for DPD generation and model FB, in the proposed method, we are only focusing on the extraction. linearization of the in-band distortion and the nearby OOB distortion.Ten,weshouldembedtheflteringoperationinto 2.4.DPDSystemwithReducedBasebandBandwidth.As the piecewise operation at a low baseband bandwidth. discussed above, the baseband also needs high bandwidth to Terefore, we propose a novel method as shown in correctly generate the predistorted signal without aliasing. It Figure 4. Firstly, the original input signal will be processed might be afordable for conventional systems but will become in parallel: a huge burden in ultra-broadband mmWave scenarios. For better understanding, let us have a look at the �(1) (�) =�(�) , �=1,2,...,��, structure for DPD model. As shown in Figure 3, to correctly generate the high-order nonlinear components, the baseband 1 (2) �(2) (�) =�(�) ∗ (� + ), �=1,2,...,��, bandwidth should be upsampled to multiple times the input sinc 2 bandwidth frstly to avoid aliasing for further operations [6– (1) (2) 10]. Here, we take the Volterra series based model [24] as where � (�) and � (�) represent two parallel signals and an example. For 5th-order Volterra kernel, it will occupy the “sinc” function will be used later in memory efect 2500 MHz bandwidth, that is, 3200 MSPS, if the roll-of factor operation. Tis is because the description of memory efect is taken into consideration. Terefore, proper techniques in PA will usually require high data rate to achieve better should be developed to resolve this issue in the baseband as performance. Te “sinc” function is one of the best functions shown in Figure 2(d). to obtain the interpolated point without increasing the data Insummary,basedontheanalysisinthissection,the rate, which is only employed in the interim procedures for bandwidth requirement can be summarized in Table 1. From these two parallel signals. this table, with the increase of the bandwidth, the cost for the Ten, both of the signals will be decomposed into � DPD system gradually becomes unafordable. In particular, segments, and the threshold can be set as [�1,�2,�3,...,��−1], in the promising 5G mmWave frequency allocation, the depending on the PA’s nonlinearity, wideband modulated signal, for example, 500 MHz, will be a basic demand. Terefore, novel DPD architectures should � be developed. (1) (1) � (�) = ∑�� (�) , �=1,2,...,��, �=1 (3) 3. Proposed DPD � �(2) (�) = ∑�(2) (�) , �=1,2,...,��, In this section, a novel DPD system will be proposed to deal � with the Tx/FB/BB bandwidth limitations together. �=1 �(1)(�) �(2)(�) � 3.1. Proposed DPD Model Derivation. As described in pre- where � and � represent the th segments of the vious section, the nonlinear model should be employed to parallel signals, � isthenumberofpiecewisesegments,and correctly describe the PA’s behavior and also to form the �� is the number of samples. DPD function. Inside the nonlinear model, there are lots of Next, the flter operation can be included by separating nonlinear operators, such as 5th-order operator, which will the fnite impulse response (FIR) into two independent Wireless Communications and Mobile Computing 5

(1) (1) x(n) x (n) x1 (n) ℎ1(n) Mem . . . . g1(0)

Treshold (2) x1 (n) ℎ2(n)

g1(M) (1) x2 (n) ℎ1(n) y(n) Mem . . ＭＣＨc(n + 1/2) . . g2(0) (2) x2 (n) ℎ2(n) . t . . . 1 . . . g (M) . . . . . 2 . t . . . . . 2 . (1) ··· xN (n) ℎ1(n) t Mem . . N−1 . . gN(0) (2) . . x (n) (2) xN (n) ℎ2(n)

gN(M) Figure 4: Te proposed DPD model.

(1) (2) responses to reduce the infuence of the nonlinearity caused �� (�−�) =�� (�−�) +�� (�−�) , (6) by the piecewise operation, as expressed as

where ��(� − �) represents the �th segments of the �th ℎ1 (�) = 0.4sinc [0.4 ⋅ (2� − 1)] , memory depth combined signal, which is generated in the �−1 �−1 “Mem” block as shown in Figure 4. �∈[− , ], 2 2 (4) Finally, (1) can be reformulated as �−1 �−1 ℎ (�) = 0.4 [0.4 ⋅ (2�)] ,�∈[− , ], 2 sinc 2 2 � � � (�) = ∑ ∑ �� (�) �� (�−�) , (7) �=1 �=0 where ℎ1(�) and ℎ2(�) represent two FIR flter responses and � represents the truncated FIR response of the sinc function, and 0.4 is selected due to the roll-of factor. In this way, the where �(�) is the predistorted signal, ��(�) represents the flter operations can be embedded: DPD coefcients for the �th segments of the �th memory depth combined signal, � represents the memory depth, and (1) (1) �� (�) =�� (�) ∗ℎ1 (�) , � represents the number of piecewise segments. (5) Te whole DPD model can be illustrated as Figure 4. �(2) (�) =�(2) (�) ∗ℎ (�) , � � 2 Since the model structure is still linear-in-parameter, the linear identifcation methods, for example, least-square, are �(1)(�) �(2)(�) where � and � represent the convolution output still valid for the model extraction, as expressed below: of the �th segments of the parallel signals and the designed flters. Y = UC, Later, since the PA will exhibit the memory efect that is (8) required to be included, we can also process it based on the low bandwidth requirement; that is, where

�1 (1) ,...,�1 (1−�) ⋅⋅⋅ �� (1) ,...,�� (1−�) [ ] [ � (2) ,...,� (2−�) ⋅⋅⋅ � (2) ,...,� (2−�) ] [ 1 1 � � ] U = [ ] , [ . . ] (9) [ . d . ]

[�1 (��) ,...,�1 (�� − �) ⋅⋅⋅ �� (��) ,...,�� (�� − �)]

� C = [�1 (0) ⋅⋅⋅�1 (�) ⋅⋅⋅ �� (0) ⋅⋅⋅�� (�)] , (10)

� Y = [� (1) � (2) ⋅⋅⋅ �(��)] , (11) 6 Wireless Communications and Mobile Computing

A B C BW BW BW

Input Proposed DPD Output DAC Upconverter PA BPF A generation B C D Tx, reduced BW

Proposed model extraction ADC Downconverter BW Baseband, Feedback loop, reduced BW reduced BW

Figure 5: Proposed DPD architecture with reduced FB/Tx/BB bandwidth.

−1 C =(UHU) UHY, (12)

where C represents the coefcient matrix, Y represents the that the flter can be codesigned with the PA and integrated −1 output vector, and U represents the input matrix. (⋅) into the output matching network of PA. Since the PA output H denotes the matrix inverse operation and (⋅) is the conjugate will only occupy limited bandwidth (Point D), only this part transpose. will be required to be fed into the feedback loop, which To correctly obtain the DPD model coefcients, the will lead to a signifcant reduction on the bandwidth of input and the output of PA will be swapped for the model the feedback loop. Both the input and output signal will extraction. In the frst iteration, the input matrix U will be be sent into the model extraction block. In this module, calculated using the PA output signal �(�). For example, in all the processing bandwidth is also limited into a specifed (5), �(�) canbereplacedby�(�) to build (9), while the range. original input �(�) is utilized to construct the output vector In summary, in the proposed DPD architecture, all the �,insteadof�(�) in (11). From the second iteration, the input bandwidth requirements including the Tx, feedback loop, matrix U will still be calculated by PA output signal �(�),but and the baseband will be signifcantly reduced. Te detailed the output vector Y will be flled with the predistorted input performance can be found in Table 2. signal, instead of the original input �(�).Normally,forthe DPD operation, it will require several iterations to achieve 3.3. Complexity Analysis and Discussion. Sincethereareonly optimal performance. linear operations in the model, the computational cost will From Figure 4, only linear operations are involved in this be pretty low. Usually, the model complexity can be evaluated model and thus baseband bandwidth requirements can be in terms of the number of the coefcients. Terefore, for largely reduced, which makes the baseband afordable for the proposed model, the coefcient number mainly depends ultra-broadband mmWave scenario. on the number of the piecewise segments and the memory depth; that is, 3.2. Complete DPD Architecture. Basedontheproposed model, the complete DPD architecture can be constructed Coef. Num =�∗(�+1) , (13) as shown in Figure 5. Te original input signal (Point A) where � represents the number of piecewise segments and will be fed into the proposed DPD generation module and � � � then the predistorted input signal (Point B) will be generated represents the memory depth. Take =10and =5,for within limited BB bandwidth, that is, normally, 1x-2xinput example; there are only 60 coefcients in total. bandwidth as described above. Since the predistorted signal In summary, compared to the conventional model, the is limited to a specifed bandwidth, the DAC sampling rate proposed DPD architecture can provide the following advan- can be efectively reduced. And then this signal will be tages: upconverted and fed into the mmWave PA. Since the pre- (1) Low bandwidth requirements are required for the distorted input signal only occupies limited bandwidth, the whole DPD system, including Tx, FB, and BB, which Txbandwidthcanalsobelargelyreduced.Duetothismerit, make the ultra-broadband mmWave DPD afordable. only part of the distortion in PA output will be compensated (Point C). Terefore, a band-pass flter will be employed (2) Low complexity is required for model construction to suppress the remained out-of-band distortion, which is with linear operations only, which makes the imple- already at relatively low level. Te pass band will occupy mentation in FPGA simple. 1x-2x input bandwidth and 10–15 dB distortion suppression (3) Linear operation property will keep the computation should be enough for the stop band. It is worth mentioning for model extraction stable. Wireless Communications and Mobile Computing 7

Table 2: Te bandwidth requirement in proposed DPD system for a 500 MHz modulated signal.

Sampling rate (MSPS) BW (MHz) Tx 1x-2x = 640–1280 1x-2x = 500–1000 Feedback loop 1x-2x = 640–1280 1x-2x = 500–1000 Baseband 1x-2x = 640–1280 1x-2x = 500–1000

DC sources

Arbitrary waveform generator

Figure 7: Te upconverter module.

PC Signal analyzer

Vector signal generator mmWave Upconverter PA

Figure 6: Te test bench.

4. Experimental Results In this section, the test bench will be set up to validate the proposed idea in ultra-broadband mmWave scenarios. Figure 8: Te mmWave power amplifer.

4.1. Test Bench Setup. Te test bench was set up as shown in Figure 6. A wideband modulated signal was generated by interested bandwidth, compared to the conventional method the sofware Matlab in PC, downloaded into the arbitrary with 576 MHz bandwidth. waveform generator (Keysight M8190). Ten, it will be Te performance in detail has been listed in Table 3. upconverted by an in-house designed upconverter module Te adjacent channel power ratio (ACPR) for the proposed and fnally fed into an in-housed designed mmWave PA methodcanbeimprovedby15dB/16dB,comparedtotheone module @ 41 GHz. Te upconverter module in Figure 7 withoutDPD.Tenormalizedmeansquareerror(NMSE) covers a frequency range from 40.5 to 43.5 GHz and supports can be also optimized by 16 dB, which gives a good indication bandwidthupto800MHz.AndthePAmoduleasshown for the performance in time domain. in Figure 8 is fabricated by GaAs PHEMT MMIC (Hittite HMC 1016) with P1dB of 24 dBm. Ten, the output signal is 4.3. Test Case 2: 320 MHz 4-Carrier CA Signal. In this sce- captured by the spectrum analyzer (Keysight N9040B) with nario, a 320 MHz 4-carrier LTE signal with the 7.5dB PAPR the specifed observation bandwidth. is used as the test signal to evaluate the performance for forthcoming ultra-broadband mmWave scenario in 5G appli- 4.2.TestCase1:80MHz4-CarrierLTESignal. In this sce- cations. Te proposed model is also set with the threshold nario, a 4-carrier 80 MHz LTE signal with the peak-to- [0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9], memory length �=16, average power ratio (PAPR) of 7.5dB is employed as the with 170 coefcients. Te average output power is set at test signal. Te proposed model is set with the threshold 15 dBm and the observation bandwidth is set as 576 MHz for [0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9], memory length �=5, proposed method. However, due to the bandwidth limitation with only 60 coefcients. Te average output power is set at of the test bench, the conventional method will require very 15 dBm and the observation bandwidth is set as 144 MHz for large Tx/FB/BB bandwidth and thus was not carried out in proposed method and 576 MHz for conventional method for 320 MHz signal test. comparison. Figures 10(a) and 10(b) give an illustration for measured Figures 9(a) and 9(b) show the measured AM/AM and AM/AM and AM/PM characteristics. It can be seen that the AM/PM characteristics. It can be seen that the nonlinear dis- nonlinear distortion can be successfully compensated, but tortion can be efectively removed by the proposed method. there is still some memory efect lef. Tis is because the noise Figure 9(c) shows the performance comparison for foor for ultra-broadband mmWave test bench is pretty high, 80 MHz modulated signal between the proposed and conven- which will inevitably afect the DPD performance. Further tionaltechniques.Teproposedmethodwithonly144MHz investigations will be carried out in future work to optimize bandwidth can achieve the similar performance within the the noise foor performance. 8 Wireless Communications and Mobile Computing

1 40

Without DPD 0.8 20 Proposed DPD

0.6 0 0.4

Phase change (degree) Phase change −20 0.2 Without DPD Normalized output magnitude output Normalized Proposed DPD

0 −40 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Normalized input magnitude Normalized input magnitude (a) (b) 0 80 －

−20 Without DPD −40 Proposed DPD

−60 144 －

Power spectral (dB/Hz) density Power 184.32 －ＭＪＭ Conventional DPD −80 40.8 40.9 41 41.1 41.2 Frequency (GHz) (c) Figure 9: Measured performance for 80 MHz modulated signal. (a) AM/AM. (b) AM/PM. (c) Power spectral density.

Table 3: Measured performance for 80 MHz signal.

ACPR (dBc) NMSE (dB) NRMSE (%) Sampling rate (MSPS) Analysis BW (MHz) No DPD −32.25/−31.63 −18.47 6.8 NA NA Conv. DPD −46.96/−47.90 −33.15 1.88 737.28 576 Proposed DPD −47.64/−47.47 −34.63 1.66 184.32 144

Figure 10(c) shows the measured power spectrum density and proposed DPD can achieve similar performance, which with/without DPD. Te details can be found in Table 4. Te provides a validation for the proposed method. However, proposed method can achieve around 10/12 dB improvements the bandwidth requirements are diferent. Table 5 illustrates for ACPR value and 12 dB improvements for NMSE per- the bandwidth comparisons for both methods in detail. Te formance. It is noticeable that, by employing the proposed requirements for ADC/DAC sampling rates and Tx/FB band- DPD system, the 320 MHz signal @ 41 GHz can be efectively width are all the same. However, compared to the BL-DPD, linearized by only using 576 MHz bandwidth. Tis merit can the proposed method can further reduce the baseband rate reduce not only the requirement for Tx/FB, but also the to keep it at the same level as other bandwidth requirements, BB requirement, which will efectively overcome the main which proves that the proposed method can provide the bottleneckinthemmWaveDPDsystem. comprehensive bandwidth reduction for the Tx, feedback loop, and baseband. 4.4. Model Comparison. In this part, the proposed method will be compared with the band-limited DPD technique (BL- 5. Conclusion DPD) [22] for both 80-MHz and 320-MHz scenarios. Figure 11 shows the measured performance for both In this paper, a novel DPD technique was proposed to scenarios.FromFigure11,itcanbeseenthatbothBL-DPD signifcantly reduce the bandwidth requirements for the Wireless Communications and Mobile Computing 9

1 40

Without DPD 0.8 20 Proposed DPD

0.6 0 0.4

Phase change (degree) Phase change −20 0.2 Normalized output magnitude Proposed DPD Without DPD

0 −40 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 Normalized input magnitude Normalized input magnitude (a) (b) −10 320 － −20

−30 Proposed Without −40 DPD DPD

−50

−60 576 － Power spectral (dB/Hz) density Power −70 737.28 －ＭＪＭ −80 40.5 40.6 40.7 40.8 40.9 41 41.1 41.2 41.3 41.4 41.5 Frequency (GHz) (c)

Figure 10: Measured performance for 320 MHz modulated signal. (a) AM/AM. (b) AM/PM. (c) Power spectral density.

0 −10 80 － 320 － −20 −20 −30

−40 −40 −50 BL-DPD −60 −60 Power spectral density (dB/Hz) spectral density Power Power spectral density (dB/Hz) spectral density Power BL-DPD Proposed DPD −70 Proposed DPD

−80 −80 40.8 40.9 41 41.1 41.2 40.5 40.6 40.7 40.8 40.9 41 41.1 41.2 41.3 41.4 41.5 Frequency (GHz) Frequency (GHz) (a) (b)

Figure 11: Measured performance comparison for (a) 80 MHz modulated signal and (b) 320 MHz modulated signal. 10 Wireless Communications and Mobile Computing

Table4:Measuredperformancefor320MHzsignal.

ACPR (dBc) NMSE (dB) NRMSE (%) Sampling rate (MSPS) Analysis BW (MHz) No DPD −33.37/−33.88 −18.37 10.22 NA NA Proposed DPD −42.92/−45.04 −30.13 3.1 737.28 576

Table 5: Bandwidth comparison for BL-DPD and proposed DPD.

Baseband rate (MSPS) ADC sampling rate (MSPS) Tx BW (MHz) DAC sampling rate (MSPS) FB BW (MHz) 80 MHz scenario BL-DPD 737.28 184.32 144 184.32 144 Proposed DPD 184.32 184.32 144 184.32 144 320 MHz scenario BL-DPD 2949.12 737.28 576 737.28 576 Proposed DPD 737.28 737.28 576 737.28 576

Tx, feedback loop, and baseband in the context of ultra- [8] A. Zhu, “Decomposed vector rotation-based behavioral mod- broadband mmWave scenarios. Tis proposed technique eling for digital predistortion of RF power amplifers,” IEEE will provide the capability of linearizing an ultra-broadband Transactions on Microwave Teory and Techniques,vol.63,no. mmWave PA with afordable resources, which can largely 2, pp. 737–744, 2015. extend the DPD regime into 5G mmWave era. [9] J. Kim and K. Konstantinou, “Digital predistortion of wideband signalsbasedonpoweramplifermodelwithmemory,”IEEE Electronics Letters,vol.37,no.23,pp.1417-1418,2001. Conflicts of Interest [10] D. R. Morgan, Z. Ma, J. Kim, M. G. Zierdt, and J. Pastalan, “A generalized memory polynomial model for digital predistortion Te authors declare that there are no conficts of interest of RF power amplifers,” IEEE Transactions on Signal Processing, regarding the publication of this paper. vol.54,no.10,pp.3852–3860,2006. [11] F. M. Ghannouchi and O. Hammi, “Behavioral modeling and Acknowledgments predistortion,” IEEE Microwave Magazine,vol.10,no.7,pp.52– 64, 2009. Te authors would like to thank Keysight Technologies for [12] J. Wood, “System-level design considerations for digital pre- providing the sofware and hardware support. Tis work distortion of wireless base station transmitters,” IEEE Transac- was supported in part by the National Natural Science tions on Microwave Teory and Techniques,vol.65,no.5,pp. Foundation of China (NSFC) under Grant 61601117 and the 1880–1890, 2017. Natural Science Foundation of Jiangsu Province under Grant [13] L. Guan, C. Yu, and A. Zhu, “Bandwidth-constrained least BK20160698. squares-based model extraction for band-limited digital predistortion of RF power amplifers,” in Proceedings of the International Workshop on Integrated Nonlinear Microwave References and Millimetre-Wave Circuits, INMMIC ’12, Ireland, September 2012. [1] E. Dahlman, G. Mildh, S. Parkvall et al., “5G wireless access: [14] Y. Ma, Y. Yamao, Y. Akaiwa, and K. Ishibashi, “Wideband dig- Requirements and realization,” IEEE Communications Maga- ital predistortion using spectral extrapolation of band-limited zine, vol. 52, no. 12, pp. 42–47, 2014. feedback signal,” IEEE Transactions on Circuits and Systems I: [2] M.J.Marcus,“5Gand’iMTfor2020andbeyond’,”IEEE Wireless Regular Papers, vol. 61, no. 7, pp. 2088–2097, 2014. Communications Magazine,vol.22,no.4,2015. [15]Y.Liu,W.Pan,S.Shao,andY.Tang,“Newdigitalpredistortion [3] J. Wood, Behavioral Modeling and Linearization of RF Power for wideband power amplifers with constrained feedback Amplifers,ArtechHouse,Norwood,MA,USA,2014. bandwidth,” IEEE Microwave and Wireless Components Letters, vol. 23, no. 12, pp. 683–685, 2013. [4] F.-L. Guo, Digital Front End, Cambridge Univ. Press, UK, 2011. [16] Y. Liu, W. Pan, S. Shao, and Y. Tang, “A general digital predis- [5] L. Guan and A. Zhu, “Green communications,” IEEE Microw. tortion architecture using constrained feedback bandwidth for Mag,vol.15,no.7,pp.84–99,2014. wideband power amplifers,” IEEE Transactions on Microwave [6] A. Zhu, J. C. Pedro, and T. J. Brazil, “Dynamic deviation Teory and Techniques,vol.63,no.5,pp.1544–1555,2015. reduction-based Volterra behavioral modeling of RF power [17] W. Tao, H. Wang, C. Zhou, G. Li, and F. Liu, “A random amplifers,” IEEE Transactions on Microwave Teory and Tech- demodulation based reduced sampling rate method for wide- niques,vol.54,no.12,pp.4323–4332,2006. band digital predistortion,” in Proceedings of the Asia-Pacifc [7] W.Cao and A. Zhu, “AModifed Decomposed Vector Rotation- Microwave Conference, APMC ’15, China, December 2015. Based Behavioral Model with Efcient Hardware Implemen- [18] Z. Wang, S. Ibrahim, H. Su, and R. Farrell, “Generalised digital tation for Digital Predistortion of RF Power Amplifers,” IEEE predistortion of RF power amplifers with low-rate feedback Transactions on Microwave Teory and Techniques,vol.65,no. signal,” in Proceedings of the 46th European Microwave Confer- 7, pp. 24 43–2452, 2017. ence, EuMC ’16, pp. 831–834, UK, October 2016. Wireless Communications and Mobile Computing 11

[19] Z. Wang, L. Guan, and R. Farrell, “Undersampling Observation- Based Compact Digital Predistortion for Single-Chain Multi- band and Wideband Direct-to-RF Transmitter,” IEEE Transac- tions on Microwave Teory and Techniques,vol.65,no.12,pp. 5274–5283, 2017. [20] H. Huang, P. Mitran, and S. Boumaiza, “Digital Predistortion Function Synthesis using Undersampled Feedback Signal,” IEEE Microwave and Wireless Components Letters,vol.26,no. 10, pp. 855–857, 2016. [21]Z.Wang,W.Chen,G.Su,F.M.Ghannouchi,Z.Feng,and Y. Liu, “Low Feedback Sampling Rate Digital Predistortion for Wideband Wireless Transmitters,” IEEE Transactions on Microwave Teory and Techniques,vol.64,no.11,pp.3528–3539, 2016. [22] C. Yu, L. Guan, E. Zhu, and A. Zhu, “Band-limited volterra series-based digital predistortion for wideband RF power amplifers,” IEEE Transactions on Microwave Teory and Tech- niques,vol.60,no.12,pp.4198–4208,2012. [23] C.Yu,L.Guan,andA.Zhu,“Band-limitedVolterraseries-based behavioral modeling of RF power amplifers,” in Proceedings of the IEEE MTT-S International Microwave Symposium, IMS ’12, pp. 1–3, Canada, June 2012. [24] M. Schetzen, Te Volterra and Wiener Teories of Nonlinear Systems, Krieger, Melbourne, FL, USA, 2006. [25] A. Zhu, P. J. Draxler, C. Hsia, T. J. Brazil, D. F. Kimball, and P. M. Asbeck, “Digital predistortion for envelope-tracking power amplifers using decomposed piecewise volterra series,” IEEE Transactions on Microwave Teory and Techniques,vol.56,no. 10, pp. 2237–2247, 2008. Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 4968391, 8 pages https://doi.org/10.1155/2018/4968391

Research Article A 3.22–5.45 GHz and 199 dBc/Hz FoMT CMOS Complementary Class-C DCO

Lei Ma, Na Yan , Sizheng Chen, Yangzi Liu, and Hao Min

State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

Correspondence should be addressed to Na Yan; [email protected]

Received 3 November 2017; Revised 23 December 2017; Accepted 4 January 2018; Published 31 January 2018

Academic Editor: Chaojiang Li

Copyright © 2018 Lei Ma et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs.The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22 GHz to 5.45 GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8 mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3 MHz offset from a 5.054 GHz carrier frequency with the 3 1/𝑓 corner frequency of 260 KHz. The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.

1. Introduction of the differential transistor pairs synchronously reducing power consumption. The FTR and frequency resolution of the Combining the high spectral purity, wide FTR, and low power presented DCO are improved and optimized by employing consumption is still one of the most challenging targets in the the three capacitor arrays and the fractional array with SDM. design of frequency synthesizers, especially for the cellular The remaining paper is divided into three parts. Descrip- GSM/WCDMA/LTE applications. In recent years, ADPLLs tion of the presented complementary Class-C DCO is given are deeply researched and widely used in cellular applications in Section 2 and measurement results are shown in Section 3. because of their downscaled area, low power consumption, Conclusion is described in Section 4. andimprovedphasenoiseperformanceinadvancedCMOS technology [1, 2]. DCO is one of the most challenging design 2. Complementary Class-C DCO blocks because good phase noise performance should be ensured with low power consumption and it needs to satisfy 2.1. Architecture Description. Figure 1 shows the comple- thewideFTRandhigh-frequencyresolutionsimultaneously mentary Class-C DCO architecture. Two cross-coupled pairs in ADPLL. 𝑀1/𝑀2 and 𝑀3/𝑀4 provide negative resistance to recover Compared with traditional LC-tank oscillators, the dif- theenergylossesintheresonantload.Thecurrentmirror 𝑀 /𝑀 𝑀 /𝑀 ferential transistor pairs based Class-C oscillator delivers is made up of 1 2 and 1bias 2bias to provide the dc briefer and taller pulses and maximizes the output oscillation current bias, and it also has a high enough transconductance amplitude, which leads to a minimization of the phase initially by using the negative feedback to ensure a robust noise [3]. It means that the phase noise can be improved start-up oscillation. Moreover, in steady state, the bias voltage 𝑉 theoretically with the same current consumption. BN falls from its start-up value which maximizes the output This paper implements a wide FTR and high FoMT swing [4]. 𝑀5 works as a level shifter to provide dc bias 𝑉 𝑉 Class-C DCO based on 65 nm 1P9M CMOS process. Two voltages BP and 𝑇 through the common-mode negative feedback loops ensure the robust oscillation start-up of DCO feedback. LC-tank is composed of a tapped inductor and [4, 5], which is achieved by adjusting the DC biasing voltage three capacitor arrays. 2 Wireless Communications and Mobile Computing

VDD

M3 M4

I BP RB RB C B CB V BP

M5 VT

Coarse array OTW_C(7 bits) Encoder_C 89 bits

OTW_M(6 bits) Encoder_M 64 bits Medium array

OTW_FI(7 bits) Encoder_F 128 bits Fine array V OUT OTW_FF(10 bits) SDM 6-bits dTF Fractional array

CP I BN

V BN CB CB RB RB C tail

M M M M 2bias 1bias 1 2

Figure 1: Schematic view of Class-C DCO.

2.2. Design of Capacitor Arrays. DCO’s resonant frequency Equation (3) gives the 𝑠-domain open loop transfer 𝑓 𝛼 𝜌 𝑓 CKV can be tuned by switching the varactors between on- function of ADPLL [2], and are loop parameters, 𝑅 is 𝐶 𝑑 Δ𝐶 ̂ state and off-state as (1), in which 0,𝑘, 𝑘,and 𝑘 are the reference clock, and KDCO is the normalized gain of DCO. 𝑘 varactor’s off-state capacitance value, digitally controlled 𝐾 ≈ 3 th In coarse array, DCO C changes 4.85 times ( (5.45/3.22) ) signal, and Δ𝐶,separately.Δ𝐶 is the capacitance differential 𝐻 (𝑠) across the entire FTR, and ADPLL’s ol also changes with valuebetweentheon-stateandoff-stateand𝐶𝑝 is the whole 𝐾 DCO C as (3), which will result in instability of ADPLL loop. parasitic capacitance. Capacitor arrays include coarse array, Therefore, varactors with different Δ𝐶 valueareadoptedat medium array, and fine array and their corresponding FTS different frequency points realizing a constant 𝐾 to 𝐾 𝐾 𝐾 DCO C are DCO C, DCO M,and DCO F,respectively.Thecapacitor ensure the loop stability. arrays are constructed by PMOS varactor because of its high density capacitance. 1 1 𝐾 = − 1 DCO C,𝑖 𝑓 = . 2𝜋√𝐿𝐶 2𝜋√𝐿(𝐶+Δ𝐶 ) CKV 𝑖−1 2𝜋√𝐿{∑𝑁−1 (𝐶 + 𝑑 Δ𝐶 )+𝐶 } (1) 𝑘=0 0,𝑘 𝑘 𝑘−1 𝑝 1 1 (4) 𝐾 = − . 𝐾 DCO C,𝑖+1 2𝜋√𝐿𝐶 For coarse array, DCO C is proportional to the inductor 2𝜋√𝐿(𝐶−Δ𝐶) 𝐿 Δ𝐶 𝑓 𝑖 value , ,andthecubeof CKV as shown in (2): Δ𝑓 𝜕𝑓 Δ𝐶 2 3 Δ𝐶 𝑖 𝐾 (𝑖+1) 𝐾 𝐾 = =≈ ⋅ =2𝜋𝐿𝑓 (2) For LC-DCO, the th DCO C and the th DCO C can DCO C LSB 𝜕𝐶 LSB CKV LSB Δ𝐶 Δ𝐶 𝐶 𝑖 Δ𝐶 be calculated by (4), where 𝑖−1, 𝑖,and are the th , 𝑓𝑅 𝑓𝑅 𝐾 (𝑖+ 1) Δ𝐶 𝐻 (𝑠) =(𝛼+𝜌⋅ )⋅ ⋅ DCO C . the th , and all the capacitors of the coarse array, ol 𝑠 𝑠 𝐾̂ (3) 𝐾 𝐾 DCO respectively. In order to get constant DCO C, DCO,𝑖 should Wireless Communications and Mobile Computing 3

source and drain 𝑅𝑎,sothe𝑄 valueofPMOSvaractorin C1 depletion region is C3 C4 1 𝑄 = . P+ C2 P+ dep 𝜔(𝑅 +𝑅 )𝐶 (7) 𝑔 𝑎 min

However, when the PMOS varactor lies in inversion N-well region, the 𝑄 value can be inferred from [9] as the following equation shows: Inversion region Depletion region 12𝑘𝑝 (𝑉 −𝑉Tp) 𝑄 = GS . (8) inv 𝜔𝐶 𝐿2 Figure 2: Parasitic capacitance model in PMOS varactor. OX 𝑘 𝑉 In (8), 𝑝 isthegainfactorofPMOStransistor, GS is the voltage difference between gate and source, and 𝑉Tp is the 𝐾 be equal to DCO,𝑖+1,whichmeans threshold voltage for PMOS transistor. It can be concluded 𝑄 𝐿 that inv is inversely proportional to the square of . 1 1 Therefore, the 𝑄 value, symmetry, and 𝐶𝑝 are mainly 1− = −1. (5) determined by the coarse array. For the coarse array, it is √1+Δ𝐶𝑖−1/𝐶 √1−Δ𝐶𝑖/𝐶 difficult to trade off the 𝑄 valueandtheregionofFTR.Finally, 𝐾 the channel length of the coarse array is set to 600 nm. As From (5), it can be concluded that the linearity of DCO C showninthepostsimulationina65nmCMOSprocess,the only depends on Δ𝐶𝑖/𝐶. Finally, the coarse array is designed 𝑄 𝐶 ∼ 𝐾 valueishigherthan25andthe 𝑅 is about 7. Both of them according to (2) (5) with constant 24 MHz/LSB’s DCO C satisfy the phase noise and the FTR requirements. which is equal to the reference clock 24 MHz. 89 varactors However, for the medium and fine array, frequency reso- makeupthecoarsearraytocoverthewideFTRandtheyare lution is the most important design factor. 200 nm and 60 nm decoded from 7 bits coarse oscillator tuning word (OTW), channel length are chosen, respectively, for high-frequency asshowninFigure1;thepostfixes C, M, FI, and FF are, resolution and high 𝑄 value. Both of them are composed respectively,theOTWofcoarsearray,mediumarray,integral of unit cap array because their FTS varies a little with the fine array, and fractional fine array. change of frequency and these two arrays’ FTS have little For the wide FTR application, the coarse array has the Δ𝐶 effectontheloopstabilityofADPLL.TheFTRofmediumand varactors with the biggest in the resonant tank. For PMOS fine arrays should respectively cover several LSBs of coarse varactor shown in Figure 2, the relevant parasitic capacitance (1) andmediumarrayssothattheOTWofcurrentarraywill can be classified into three parts as shown in Figure 2: not overflow due to the process, voltage, and temperature the oxide layer capacitance between gate and channel: 𝐶1 = 𝑊𝐿𝐶 𝐶 (PVT) variations. In the process of ADPLL locking, OTW OX,where OX is the capacitance of gate oxide layer per 𝑊 𝐿 overflow means that medium tuning or fine-tuning period unit area and and are the gate width and gate length, cannot be finished and loss-of-lock may occur. According to respectively; (2) the depletion layer capacitance between 𝐶 =𝑊𝐿√𝑞𝜀 𝑁 /(4𝜑 ) 𝑞 thepossiblelargestfrequencyerrorduetoPVTvariations substrate and channel: 2 si nwell 𝐹 , where 𝜀 and the required frequency resolution of the current locking is a charge constant, si is the dielectric constant of silicon, 𝑁 𝜑 period, 6-bit medium arrays and 7-bit fine arrays are designed nwell is the doping concentration of N-well, and 𝐹 is the to cover 4 LSBs of 𝐾 and 8 LSBs of 𝐾 ,respectively. built-in potential; (3) the overlapping capacitance among DCO C DCO M 𝐶 𝐶 𝑊𝐶 𝐶 Finally, the locking process of ADPLL can be divided into gate, source, and drain: 3 and 4 equal to OV,where OV three frequency locking periods step by step without the is the overlapping capacitance per unit width. possibility of loss-of-lock due to OTW overflow. Therefore, when the PMOS varactor operates in inversion 𝐶 In order to improve the phase noise performance of the region, capacitance is maximized to max. When the PMOS DCO, MOS varactor is controlled digitally. As shown in varactor operates in depletion region, capacitance is mini- 𝐶 Figure 3, OTW (Oscillator Tuning Word) is decoded into the mized to min. thermal code to control the on/off states of MOS varactor So the capacitance ratio is with an inverting driver. The voltage level of digital control signal 𝑑𝑘 canbeadjustedby𝑉 and 𝑉 .Figure3also 𝐶 𝐿𝐶 +2𝐶 High Low 𝐶 = max = OX OV . shows the curve of a PMOS varactor capacitance versus 𝑅 𝐶 (6) 𝑉 𝑉 min 𝐿√𝑞𝜀 𝑁 /(4𝜑 )+2𝐶 GS (C-V curve). MOS varactors change linearly from 1 si nwell 𝐹 OV to 𝑉2 and 𝐴0 is the output amplitude of DCO. During the whole oscillation period, the original C-V curve has to be 𝐶 > √𝑞𝜀 𝑁 /(4𝜑 ) 𝐶 𝐿 Because OV si nwell 𝐹 , 𝑅 increases when transferred into the average C-V curve with red dashed is increased, and higher 𝐶𝑅 means the wider FTR. dotted line as shown in Figure 3. Therefore, in order to stop When PMOS varactor operates in depletion region, the PMOS varactor from inducing the noise on the 𝑑𝑘,the channel is not formed; the parasitic resistance only includes varactor must be working in the on/off states region of the gate resistance 𝑅𝑔 and metal contact parasitic resistance of average C-V curve. 4 Wireless Communications and Mobile Computing

Fine Middle Changeable unit Coarse V cap array High

ON OP ON

d OTW Decoder Coarse bank 89 dk d1

Unit cap array OP V OP Low ON

d Medium bank 64 On-state C d1 C MAX Unit cap array Off-state C AVER OP ON

CapPMOS C MIN d Fine bank 128+7 V V −A V V V +A GS d Include 1 0 1 2 2 0 1 SDM bits Figure 3: DCO capacitor array.

−150 comparesthephasenoisecontributionamongMASH1, MASH 1-1, and MASH 1-1-1 SDM; it can be seen that MASH 1- 1-1 SDM has the lowest in-band phase noise contribution and −200 the best noise shaping character. Moreover, their out-band phase noise contributions are almost the same. Therefore, 10- −250 bit OTW FF is dithered with MASH 1-1-1 SDM to control 6-bit fractional capacitor arrays to improve the frequency resolution and decrease the noise contribution. The phase −300 noise contribution of SDM to ADPLL is simulated with −

Phase (dBc/Hz) noise MATLAB as shown and it is below 150 dBc/Hz, which −350 means it affects in a small way the whole phase noise performance. In Figure 5, Eq1(𝑧),Eq2(𝑧),andEq3(𝑧) are the quantization noise of each accumulator. Therefore, the output −400 frequency of SDM can be deduced from 103 104 105 106 107 108 109 Frequency (Hz) 𝐶 = +(1−𝑧−1)∗ (𝑧) 1 OTWF F Eq1 MASH 1-1-1 𝐶 =− (𝑧) ∗𝑧−1 +(1−𝑧−1)∗ (𝑧) MASH 1-1 2 Eq1 Eq2 MASH 1 −1 −1 𝐶3 =−Eq2 (𝑧) ∗𝑧 +(1−𝑧 )∗Eq3 (𝑧) Figure 4: The comparison of phase noise contribution of SDM. 𝑓 out −3 −2 −3 −1 −2 −3 (9) =[𝐶1𝑧 +𝐶2 (𝑧 −𝑧 )+𝐶3 (𝑧 −2𝑧 +𝑧 )] ∗𝐾 The finite frequency tuning resolution introduces the DCO F quantization noise and contributes the output phase noise 3 =[ ∗𝑧−3 +𝑧−1 (1 − 𝑧−1) ∗ (𝑧)] of the ADPLL and hence a small tuning step is desired. The OTWF F Eq1 frequency resolution requirement is 0.1 ppm, but the smallest ∗𝐾 . FTS is limited by the smallest Δ𝐶 in 65 nm process. Figure 4 DCO F Wireless Communications and Mobile Computing 5

dTF1 DQ DQ DQ CK CK CK dTF2

OTW_FF C DQ D Q D 1 Carry_out TF3 (fraction) d TF4 C2 Carry_out CK CK CKQ d −1 −Eq1(z)z dTF5,6 10 bits −1 C3 Carry_out −Eq2(z)z D Q D Q D Q dTF7 −1 CK CK Q CK −Eq3(z)z

CKVD8

Figure 5: MASH 1-1-1 sigma-delta modulator.

1.2 1 0.8 0.6 V 4.5 1.2 0.4 OUT

Voltage (V) Voltage 0.2 0 3 0.9 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Time (ns) 1 V 1.5 0.6 0.8 BP

V IM1 (mA) 0.6 T V 0.4 BN 0 0.3 Output voltage (V) 0.2 Voltage (V) Voltage 0 −1.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 4.2 4.34.4 4.5 4.6 4.7 4.8 4.9 5 Time (ns) Time (ns) (a) (b)

Figure 6: Transient voltage waveform of Class-C DCO (a) and 𝑀1 current transient simulation result (b).

2.3. Class-C DCO’s Negative Feedback Loops. In Figure 1, 400 um 𝐼 𝑀 current BP is chosen to bias 5 providing a level shift voltage. 𝑉 A RC networkisusedtoprovideadcbiasvoltage,and BP is higher than the tank common-mode voltage, which permits a larger resonator swing before the 𝑀3/𝑀4 is pushed into thetrioderegion.Thisisthesametechniqueemployedto bias the 𝑀1/𝑀2.Moreover,ahighRC constant of the RC

um biasing network is used to low-pass filter the noise introduced to 𝑉 and 𝑉 , optimizing the phase noise [5]. 𝐶 not 520 BN BP tail 𝐼 only integrates the difference between BN and the current exhausted by the DCO but also filters the high-frequency 𝑀 /𝑀 noise contribution from 1bias 2bias,improvingthephase noise [4]. The simulated transient voltage of DCO is given in 𝑉 Figure 6(a); out is the oscillation output of DCO. Initially, 𝑀 /𝑀 𝐼 the 1bias 2bias arediode-connected(atDC)and BN is mirrored (multiplied by N)totheDCOcore,whichmakes both PMOS and NMOS cross-coupled MOSFET work in saturation region and provide a high transconductance to guarantee a robust start-up. As the oscillator amplitude is 𝐼 𝑀 /𝑀 Figure 7: Die photo of Class-C DCO. increased, the average current DC depleted by 1bias 2bias 6 Wireless Communications and Mobile Computing

−114.5

−115 Phase noise without SDM −115.5

−116 Phase noise with SDM

−116.5 3 −118.3 1/f corner frequency = 260 KHz dBc/Hz −114.8 dBc/Hz −117 −117.5 −118 Phase noise@1 (dBc/Hz) MHz −118.5 0 10 20 30 40 50 60 70 80 90 Coarse bank code (a) (b)

Frequency spectrum Frequency spectrum with SDM without SDM

(c)

Figure 8: Measurement results of phase noise @ 1 MHz offset versus Coarse Code (a) phase noise of Class-C DCO at 5.054 GHz (b)and frequency spectrum with/without SDM (c).

5.5 amplitude (red line), which minimizes the phase noise of 5 DCO. 4.5 5.445 3.31 GHz GHz Referring to the noise analysis in [10], the proposed 4 3.5 DCO’s noise from feedback loop can be inferred in (10), 3 V2 V2 V2 Frequency (GHz) Frequency where 𝑛𝑅 , 𝑛𝑟 ,𝑀5,and 𝑛𝐼 are, respectively, the white noise 0 102030405060708090 𝐵 0 𝐵 voltage power spectral density by bias resistor 𝑅𝐵,bias Coarse bank code 𝑀 𝑀 /𝑀 𝜔 25 MOSFET 5,andbiasMOSFET 1bias 2bias. 𝑝 is the 22.36 MHz 𝑔2 (𝜃 )Γ2 (𝜃 ) 24 single pole in the feedback loop. The nl 𝑐 osc 𝑐 is the 24.5 23 MHz amplification and frequency translation that the feedback (MHz) 22 loop noise must undergo first. Frequency step Frequency 0 102030405060708090 Coarse bank code 𝑁 FL Figure 9: Measurement results of frequency range and frequency 𝜃 /2 2 2 2 step of coarse array. 1 𝐶 2V𝑛𝑅 + V𝑛𝑟 + V𝑛𝐼 = ∫ 𝐵 0,𝑀5 𝐵 𝑔2 (𝜃 )Γ2 (𝜃 )𝑑𝜃 𝑇 1+𝜔2 nl 𝑐 osc 𝑐 𝑐 −𝜃𝐶/2 𝑝 (10) 2V2 + V2 + V2 increases and then the superfluous current will be integrated 𝑛𝑅𝐵 𝑛𝑟0,𝑀5 𝑛𝐼𝐵 2 𝐶 𝑉 𝑀 /𝑀 = 𝑔0𝑓 (𝑉 ). into tail reducing BN andguidingtheswitchingpair 1 2 1+𝜔2 fl OSC 𝑉 𝑝 toworkinClass-Cmode.Atthesametime, BP increases and pushes PMOS working in Class-C mode. 𝑉𝑇 is finally changed to the half value of the VDD to offer the common-mode Therefore, the total amount of phase noise can be deduced voltage of DCO and the same overdrive of PMOS and NMOS in (11) where 𝐾 is Boltzmann constant, 𝑇𝑘 is the absolute pairs. Figure 6(b) shows the transient simulation result of temperatureinKelvin,𝐶 is the capacitor in LC resonant bank, 𝑀 𝑀 𝑉 1’s current (blue line) when 1 operates at Class-C mode; OSC istheoscillationamplitudeofDCO,2R is the parasitics 𝛾 𝑓 (𝑉 ) the tall and short pulses maximize the output oscillation losses, and is the technology coefficient. cp OSC and Wireless Communications and Mobile Computing 7

7.5 480 7 410 6 MHz/[email protected] 460 KHz/[email protected] GHz 6.5 7.3 MHz/[email protected] 440 6 420 5.5

step (MHz/LSB) step 400 (KHz/LSB) 455 Frequency tuning Frequency KHz/[email protected] 0 10 20 30 40 50 60 70 380 Fine tuning step Fine tuning Medium tuning code 0 20406080100120 140 Fine bank code 1.8 170 1.62 MHz/[email protected] GHz 120 1.7 160 KHz/[email protected] GHz 1.5 MHz/[email protected] GHz 150 1.6 140 1.5 130

(KHz/LSB) 120 150 1.4 KHz/[email protected] GHz

step (MHz/LSB) step 110 Fine tuning step Fine tuning Frequency tuning Frequency 0 10 20 30 40 50 60 70 0 20 40 60 80 100 120 140 Medium tuning code Fine bank code (a) (b)

Figure 10: Measurement results of frequency range and frequency step of medium array (a) and fine array (b).

𝑓 (𝑉 ) 𝐾 10 fl OSC are, respectively, weighing factors of cross-coupled DCO F will be divided by 2 , so the final frequency resolu- MOSFETs and feedback loops. tion varies from 117 Hz to 444 Hz, which is less than 0.1 ppm. 𝐾𝑇 1 𝛾 When all the varactors change from on-state to off-state, the (Δ𝜔) = 𝑘 ( + 𝑔 𝑓 (𝑉 )) DCO will work from 3.22 GHz to 5.45 GHz, with the FTR of PN Δ𝜔2𝐶2𝑉2 𝑅 𝛼 0 cp osc osc 51.5%. 2 2 2 (11) Table 1 shows the comparison table of state-of-the-art LC- 2V𝑛𝑅 + V𝑛𝑟 + V𝑛𝐼 + 𝐵 0,𝑀5 𝐵 𝑔2𝑓 (𝑉 ). tank oscillators [2, 6–8]. Without the SDM, this DCO has 2 2 2 2 0 fl OSC Δ𝜔 𝐶 𝑉 (1 + 𝜔𝑝) achieved the frequency resolution of 120 KHz, which is close osc to other references, but it can be 117 Hz after SDM. Reference [8] is also a complementary Class-C DCO, but this work has 3. Measurement Results better performance than it. Reference [6] is traditional LC- The Class-C DCO was fabricated in a standard 65 nm CMOS DCO; this work shows higher FoM than it due to its Class-C process. Figure 7 offers the die photo of Class-C DCO; it mode. This design works at close frequency with [6–8] while 2 displaying wider FTR and better FoMT due to the design and occupies the area of 0.21 mm without PADs. Figure 8(a) optimization of capacitor arrays. shows that the different phase noise measurement results in 1 MHz frequency offset at the different resonant frequency, which changes with coarse array code from −118.3 dBc/Hz 4. Conclusion to −114.8 dBc/Hz. The phase noise measurement results of Class-C DCO with SDM and without SDM at 5.054 GHz are This paper presented a complementary Class-C digitally 3 shown in Figure 8(b); the 1/𝑓 corner frequency is about controlled oscillator (DCO) with differential transistor pairs. 260 KHz. Although SDM brings spurs, it can be seen that With three optimized capacitor arrays and a fractional array the phase noise performance with SDM is still better than dithered by SDM, the DCO works from 3.22 GHz to 5.45 GHz the phase noise performance without SDM. With SDM, it with51.5%FTRandlessthan0.1ppmfrequencyresolution. is −116 dBc/Hz and −126 dBc/Hz at 1 MHz and 3 MHz fre- Through two feedback loops, the start-up oscillation is quency offset, respectively. Figure 8(c) shows the frequency ensured and low power consumption is realized. The achieved spectrum of DCO at 3.34 GHz; it can be seen that SDM brings phase noise is −126dBc/Hzat3MHzoffsetfrom5.054GHz 3 spurs about 10 dBc at point 3 and point 4 on the frequency with the 1/𝑓 corner frequency of 260 KHz while consuming spectrum of DCO, but it can be suppressed by the loop only 2.8 mA at 1.2 V voltage supply. The final FoM and FoMT character of ADPLL. Figure 9 shows that the frequency and are 185.2 dBc/Hz and 199.4 dBc/Hz, respectively. 𝐾 DCO C changeversusthecoarsearraycode.Themeasured 𝐾 DCO C is around 24 MHz/LSB with a maximum deviation of 𝐾 Conflicts of Interest 1.64 MHz/LSB. Figure 10(a) displays the DCO M at different frequency points, the red line and the blue line show the The authors declare that there are no conflicts of interest 𝐾 at 3.32 GHz and 5.45 GHz, respectively, and 𝐾 DCO M DCO M regarding the publication of this paper. changes from 1.5 MHz/LSB to 7.4MHz/LSB across the whole 𝐾 𝑓 FTR because DCO M is proportional to the cube of CKV as 𝐾 (2) shows. Figure 10(b) gives the DCO F at different frequency Acknowledgments points, and it changes from 120 KHz/LSB to 455 KHz/LSB 𝐾 through the whole FTR, with the same reason of DCO M. ThisworkissupportedbytheNationalNaturalScienceFoun- After 10-bit SDM, fractional array’s frequency resolution dation of China (nos. 61574045 and 61774048), the National 8 Wireless Communications and Mobile Computing

Table 1: Comparison with the state of the art.

[2] [6] [7] [8] This work Technology 40nm 65nm 16nm 65nm 65 nm Freq. (GHz) 5.11 6.8 3.6 2.2 5.054 FTR (%) 64.6 20 22 9.1 51.5 Power (mW) 8 1 0.6 1.5 3.4

𝑓𝑚 (MHz) 1 3 10 3 3

PN@ 𝑓𝑚 (dBc/Hz) −130 −116 −134 −117 −126 Frequency resolution (Hz) 29 K 116 K 1.3 K - 120 K (wo SDM)/117 (wi SDM) 1 FoM (dBc/Hz) 187 183 188 173 185.2 2 FoMT (dBc/Hz) 203 189 195 172 199.4 1 =10 ((𝑓 /𝑓 )2(1/𝑃 ( ))) − 2 = 1 +20 ( /10) FoM log10 osc 𝑚 DC mW PN; FoMT FoM log10 FTR .

Science and Technology Major Project (no. 2016ZX03001012- IEEE International Symposium on Circuits and Systems, ISCAS 003), and the National High Technology Research and Devel- ’99, June 1999. opment Program (no. 2015AA016601-005). [10] S. Perticaroli, S. Dal Toso, and F. Palma, “A harmonic class-c cmos vco-based on low frequency feedback loop: Theoretical analysis and experimental results,” IEEE Transactions on Cir- References cuitsandSystemsI:RegularPapers,vol.61,no.9,pp.2537–2549, 2014. [1] S. Zheng and H. C. Luong, “A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wideband PM/AM modulator, and Linearized PA,” IEEE Journal of Solid-State Circuits, vol.50,no.7,pp.1645–1656,2015. [2]Y.Wu,M.Shahmohammadi,Y.Chen,P.Lu,andR.B. Staszewski, “A 3.5–6.8-GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH-TDC for low in-band phase noise,” IEEE Journal of Solid-State Circuits,vol.52,no.7, pp.1885–1903,2017. [3] A. Mazzanti and P.Andreani, “Class-C harmonic CMOS VCOs, with a general result on phase noise,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2716–2729, 2008. [4] L. Fanori and P.Andreani, “Ahigh-swing complementary class- CVCO,”inProceedings of the 39th European Solid-State Circuits Conference, ESSCIRC 2013, pp. 407–410, Romania, September 2013. [5] A. Mazzanti and P. Andreani, “A push-pull class-C CMOS VCO,” IEEE Journal of Solid-State Circuits,vol.48,no.3,pp. 724–732, 2013. [6] A. Elkholy, M. Talegaonkar, T. Anand, and P. K. Hanumolu, “A 6.75-to-8.25GHz 2.25mW 190fs𝑟𝑚𝑠 integrated-jitter PVT- insensitive injection-locked clock multiplier using All-Digital continuous frequency-tracking Loop in 65nm CMOS,” in Pro- ceedings of the 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, pp. 188-189, USA, February 2015. [7] C.-C. Li, M.-S. Yuan, C.-H. Chang et al., “A 0.2V trifilar- coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications,” in Proceedings of the 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, pp. 332-333, USA, February 2017. [8] T. Siriburanon, S. Kondo, K. Kimura et al., “A 2.2 GHz- 242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture,” IEEE Journal of Solid-State Circuits,vol.51,no.6, pp. 1385–1397, 2016. [9] P. Andreani and S. Mattisson, “2.4-GHZ CMOS monolithic VCObasedonanMOSvaractor,”inProceedings of the 1999 Hindawi Wireless Communications and Mobile Computing Volume 2018, Article ID 8712414, 8 pages https://doi.org/10.1155/2018/8712414

Research Article A Novel Quadrature-Tracking Demodulator for LTE-A Applications

Kang-Chun Peng and Chan-Hung Lee

Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, 2 Jhuoyue Rd., Nanzih, Kaohsiung City 811, Taiwan

Correspondence should be addressed to Kang-Chun Peng; [email protected]

Received 27 July 2017; Accepted 2 December 2017; Published 2 January 2018

Academic Editor: Chaojiang Li

Copyright © 2018 Kang-Chun Peng and Chan-Hung Lee. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

This work develops an advanced quadrature-tracking demodulation technique for coherently demodulating the orthogonal frequency-division multiplexing (OFDM) signal of LTE-A systems. To overcome the fact that traditional coherent demodulators are extremely sensitive to the quadrature imbalance of a system, especially an OFDM system, the proposed architecture uses a novel quadrature phase-locked loop (QPLL) to track simultaneously the in phase (I-phase) and the quadrature phase (Q-phase) of the received signal. This advanced quadrature-tracking demodulator is realized using TSMC 0.18 𝜇m CMOS technology and hybrid circuits. Experimental results indicate that the developed quadrature-tracking demodulator, which operates at 2.1∼2.5 GHz, can effectively demodulate an 18 Mbps LTE-A signal, even with a 15 degree quadrature imbalance.

1. Introduction quadrature imbalance significantly degrades the demodulation quality of an OFDM signal, which is extensively Most wireless communication systems use coherent demod- used in LTE-A systems [6, 7]. Although the conventional ulation, mainly because the quality of coherent demodulation Costas-coherent demodulator has two feedback loops for is much better than that of non-coherent demodulation demodulation, the single-VCO design prevents tracking of [1]. Traditional coherent demodulators are based on an RF more than one phase of a received signal. quadrature demodulator. But the RF coherent circuits are usually complex and power-hungry [2]. To simplify the We [8] previously presented an alternative coherent polar receiver’s circuitry, various phase-locked loop (PLL)-based demodulator without the quadrature imbalance problem of coherent demodulators are adopted in wireless communi- receiver. As presented in Figure 2, the received signal is cation systems. The most well-known PLL-based coherent divided into two paths. One of these paths uses injection- demodulator has the Costas architecture [1, 3–5]. As depicted locked oscillators (ILO) to extract the phase-modulated in Figure 1, this architecture uses a single PLL with two carriersignalandthephaseinformation.Theextracted feedback loops. These two feedback loops demodulate the phase-modulated carrier is then mixed with the received in-phase (I-phase) signal and quadrature-phase (Q-phase) signal along another path. The mixing cancels out the phase signals, respectively. The demodulated signals are combined, information of these two input signals, and then the envelope andthentunethevoltage-controlledoscillator(VCO)to information of the received signal is exported. The baseband track the frequency of the carrier signal. However, both the processor then recovers the baseband signal from both the traditional quadrature demodulator and the Costas-coherent demodulatedphaseandtheenvelopeinformation.However, demodulator face the problem of quadrature imbalance of the quadrature imbalance that is caused by the RF transmitter RF signal. Quadrature imbalance of RF signal arises from remains in the received signal. both the quadrature transmitter and the quadrature receiver. To overcome the quadrature imbalance problem, some Previous investigations have showed that a slight 2.5 degree works directly trimming or adjusting their RF circuits [9]. 2 Wireless Communications and Mobile Computing

Demodulated demodulation, the two tuning ports of the QVCO are shorted +1 I-data LPF tomaketheQPLLactasasinglePLLtolockthecarrier −1 frequency of the received signal. Since the effective detection range of a mixer-based phase detector is limited by ±90 BPSK degree [13], as depicted in Figure 4, an additional channel- QPSK/ + preset frequency synthesizer is required. The additional BPSK VCO LPF + QPSK − frequency synthesizer uses an all-digital phase-frequency detector (PFD) to detect a large phase variance of up to ±360 degree. Therefore, the QPLL can track both the frequency and ∘ 90 thephaseofthereceivedsignal.Afterthefrequencyofthe received signal has been locked, the channel-preset frequency +1 synthesizer is turned off to save power and the two VCO LPF −1 Demodulated tuning ports are disconnected, as presented in Figure 5. The Q-data QPLLcanthentrackinrealtimeanddemodulateboththe I-phase and the Q-phaseofthereceivedsignal.According Figure 1: Traditional Costas demodulator. to PLL theory, a PLL-based demodulator attenuates the demodulated signal within the loop bandwidth of the PLL [13]. Therefore, the proposed architecture is especially suited Digital signal to OFDM systems because the DC-subcarrier of the OFDM Mixer LPF processing signal, as depicted in Figure 6, is not used in the LTE-A A/D system, to mitigate the DC-offset problem [14]. Therefore, the 2nd ILO proposed advanced QPLL-based demodulation technique can coherently demodulate the OFDM signal without atten- BPF 1st ILO ∘ uation if the loop bandwidth of the PLL is designed to be less 90 A/D than the sub-carrier space. Mixer LPF Figure 2: Polar demodulator. 3. System Analysis To analyze the proposed quadrature-tracking demodulator in thetimedomain,thereceivedsignalisassumedtobe However, these are impractical. Another solution is based- on digital-signal process (DSP) technique. [10] and [11] 𝑟 (𝑡) =𝐼(𝑡) cos [(𝜔0 +Δ𝜔)𝑡+𝜃𝐼] respectivelyusesthepilotsignalandaspecialtonetotrainthe (1) +𝑄(𝑡) [(𝜔 +Δ𝜔)𝑡+𝜃 ], DSPinreceivertofindoutandthencorrectthequadrature sin 0 𝑄 imbalance. [9, 12] utilize adaptive algorithms to estimate the where 𝐼(𝑡) and 𝑄(𝑡) denote baseband signals, and Δ𝜔 is the quadrature error and then compensate demodulated signal. frequency error; 𝜃𝐼 and 𝜃𝑄 are the phase errors of the I- Although these adaptive algorithms theoretically can reduce phase signal and the Q-phase signal, respectively. After down- the quadrature imbalance to less than 1 degree, they take 5 mixing, the signal at nodes A and B in the circuit that is a very long computation time with about 10 iterations. To displayed in Figure 5 is derived as speed up the tracking process, this work proposes a novel 𝐼 (𝑡) quadrature-tracking demodulator which can real-time track 𝐴 (𝑡) = [(2𝜔 +Δ𝜔)𝑡+𝜃 +𝜃󸀠] 2 sin 0 𝐼 𝐼 the quadrature error. 𝐼 (𝑡) + (Δ𝜔𝑡 + Δ𝜃 ) 2 sin 𝐼 2. Quadrature-Tracking Demodulator 𝑄 (𝑡) 󸀠 + cos (Δ𝜔𝑡𝑄 +𝜃 −𝜃) To eliminate the extreme sensitivity of traditional coherent 2 𝐼 demodulation to the quadrature phase imbalance, this work 𝑄 (𝑡) − [(2𝜔 +Δ𝜔) +𝜃󸀠 +𝜃 ] proposes a novel quadrature phase-locked loop (QPLL)- 2 cos 0 t 𝐼 𝑄 based coherent demodulator. As depicted in Figure 3(a), the 𝐼 (𝑡) (2) proposed QPLL is based mainly on two identical PLLs with a 𝐵 (𝑡) = [(2𝜔 +Δ𝜔)𝑡+𝜃 +𝜃󸀠] channel-preset frequency synthesizer. Unlike the traditional 2 cos 0 𝐼 𝐼 Costas-coherent demodulator which uses a single-ended 𝐼 (𝑡) 󸀠 VCO, the QPLL-based demodulator utilizes a novel quadra- + cos (Δ𝜔𝑡𝐼 +𝜃 −𝜃𝑄) ture voltage-controlled oscillator (QVCO). As presented in 2 Figure 3(b), the QVCO is formed by cross-coupling two 𝑄 (𝑡) + (Δ𝜔𝑡 + Δ𝜃 ) identical differential VCOs. The tuning ports of these two 2 sin 𝑄 VCOs are independent of each other, rather than connected. One performs I-phase tracking in the QPLL while the other 𝑄 (𝑡) 󸀠 + sin [(2𝜔0 +Δ𝜔)𝑡+𝜃𝑄 +𝜃𝑄], performs Q-phase tracking. Under the initial condition of 2 Wireless Communications and Mobile Computing 3

Received Demodulated LPF OFDM Q signal signal × Loop filter

Channel- Coupling preset /N PFD frequency Coupling synthesizer 0∘ 90∘ VＮＯＨ？ Q QVCO _ V ＮＯＨ？_I 270∘ 180∘ × Loop filter Coupling Demodulated LPF I signal Coupling (a) (b)

Figure 3: Proposed (a) quadrature-tracking demodulator, and (b) QVCO.

Ve Magnitude Phase-frequency detector Subcarriers Subcarriers

e −2 −3/4 − −/4 /4  3/4 2

Mixer-based Frequency phase detector DC Figure 6: Sub-carrier spectrums of OFDM signal in LTE-A system. Figure 4: Effective phase-detection range of a mixer-based phase detector. are the I-phase and 𝑄-phase phase errors between the transmitter and the receiver. Since the loop bandwidth of E Demodulated Received LPF I the PLL must be narrower than the sub-carrier space of the OFDM signal signal A OFDM signal, the signal at nodes C and D of the circuit in × Loop filter Figure 5 are derived as C 𝐼 (𝑡) (Δ𝜔𝑡 + Δ𝜃 ) 𝐼 󵄨 󵄨 𝜋 𝐶 (𝑡) ≅ , for 󵄨Δ𝜔𝑡 𝐼+ Δ𝜃 󵄨 < ＭＣＨ(t +  ) /N PFD 2 4 I (4) 𝑄 (𝑡) (Δ𝜔𝑡 + Δ𝜃 ) 𝑄 󵄨 󵄨 𝜋 𝐷 (𝑡) ≅ , for 󵄨Δ𝜔𝑡 𝐼+ Δ𝜃 󵄨 <  2 4 ＝ＩＭ(t + Q) QVCO According to PLL theory, the negative-feedback mechanism D makes Δ𝜔, Δ𝜃𝐼,andΔ𝜃𝑄 equal zero. Under these conditions, × Loop filter B the QPLL-based demodulator locks both the frequency and Demodulated the phase of the received RF signal. LPF F Q signal To extract the demodulated baseband signals from the QPLL-based demodulator, two additional low-pass filters are Figure 5: Proposed demodulator under quadrature-tracking and demodulating conditions. used at the output of phase detectors. The cut-off frequency of the filter must exceed the top of the frequency band of the baseband signal. The signals at nodes E and F, shown in Figure 5 are derived as where 𝑄 (𝑡) Δ𝜃 =𝜃 −𝜃󸀠, 𝐸 (𝑡) = (Δ𝜔𝑡 + Δ𝜃 ) 𝐼 𝐼 𝐼 2 cos 𝑄 (3) 𝐼 (𝑡) Δ𝜃 =𝜃 −𝜃󸀠 − (Δ𝜔𝑡 + Δ𝜃 ), 𝑄 𝑄 𝑄 2 sin 𝐼 4 Wireless Communications and Mobile Computing

LPF Magnitude F (s)   Double-balanced 2 I_out n,VCO   mixer 20 ＦＩＡF2(s)He(s)   QVCO I_Rx I_e ++Kd F1(s) K/s − Loop filter

Loop Subcarriers Subcarriers  − filter Q_Rx + Kd F1(s) K/s + Q_e LPF  n, F2(s) Q_out VCO −f −f f f c n DC n c Figure 7: Linear phase model of proposed quadrature-tracking Frequency demodulator. Figure 8: Frequency response of proposed quadrature tracking demodulator. 𝐼 (𝑡) 𝐹 (𝑡) = (Δ𝜔𝑡 + Δ𝜃 ) 2 cos 𝐼 where 𝑄 (𝑡) 𝑠 + sin (Δ𝜔𝑡 𝑄+ Δ𝜃 ). 2 𝐻𝑒 (𝑠) = (9) 𝑠+𝐾V𝐾𝑑𝐹1 (𝑠) (5) is the error transfer function of the QPLL, and Since Δ𝜔, Δ𝜃𝐼,andΔ𝜃𝑄 arezerowhenthePLLlocksthe frequency and phase of the received signal, the demodulated 𝜙𝐼 𝑒 (𝑠) =𝜙𝐼 𝑒𝐹2 (𝑠) 𝐻𝑒 (𝑠) , 𝑄-phase signal and 𝐼-phase signal are found as (10) 𝜙𝑄 𝑒 (𝑠) =𝜙𝑄 𝑒𝐹2 (𝑠) 𝐻𝑒 (𝑠) . 𝑄 (𝑡) 𝐸 (𝑡) ≅ , 2 According to final value theory, the output quadrature errors (6) 𝜙 (𝑠) 𝜙 (𝑠) 𝐼 (𝑡) 𝐼 𝑒 and 𝑄 𝑒 arezerowhenthequadraturephaseerrors 𝐹 (𝑡) ≅ . 𝜙 𝜙 2 𝐼 𝑒 and 𝑄 𝑒 are constant [15]. Under these conditions, Eqs. (8), can be simplified as Equations (6) indicate that the novel demodulator can 𝜙 (𝑠) =[𝜙 (𝑠) +𝜙 −𝜙 (𝑠)]𝐹 (𝑠) 𝐻 (𝑠) effectively demodulate the received signal without distor- 𝐼 out 𝐼 𝐼 𝑒 𝑛,VCO 2 𝑒 tions, which would otherwise be caused by the quadrature- =[𝜙 (𝑠) −𝜙 (𝑠)]𝐹 (𝑠) 𝐻 (𝑠) , imbalance. 𝐼 𝑛,VCO 2 𝑒 (11) To further analyze the frequency response of the pro- 𝜙𝑄 out (𝑠) =[𝜙𝑄 (𝑠) +𝜙𝑄 𝑒 −𝜙𝑛,VCO (𝑠)]𝐹2 (𝑠) 𝐻𝑒 (𝑠) posed demodulator, a frequency domain linear model is 𝐹 (𝑠) 𝐹 (𝑠) developed, as presented in Figure 7. 1 and 2 represent =[𝜙𝐼 (𝑠) −𝜙𝑛,VCO (𝑠)]𝐹2 (𝑠) 𝐻𝑒 (𝑠) . the frequency responses of the loop filters. 𝐾V and 𝐾𝑑 represent the sensitivities of the QVCO and mixer-based Figure 8 plots the frequency response of 𝐹2(𝑠)𝐻𝑒(𝑠),where phase detector, respectively. 𝜙𝑛,VCO represents the phase noise 𝑓𝑛 represents the loop bandwidth of the QPLL and 𝑓𝑐 is the of the QVCO. cut-off frequency of the LPF. The 𝑓𝑛 should be designed to be narrower than the frequency gap between subcarriers to 𝜙𝐼 𝑅𝑥 (𝑠) =𝜙𝐼 (𝑠) +𝜙𝐼 𝑒, prevent distortion. 𝑓𝑐 should equal the channel bandwidth of (7) the system to enable channel selection. From the spectrum 𝜙𝑄 𝑅𝑥 (𝑠) =𝜙𝑄 (𝑠) +𝜙𝑄 𝑒 of the OFDM sub-carriers and the frequency response of represent the I-phase and Q-phase of the received signal, the demodulator in Figure 8, the proposed architecture can respectively, where 𝜙𝐼 𝑒 and 𝜙𝑄 𝑒 are the quadrature phase coherently demodulate the received OFDM signal without 𝜙 errors. 𝜙𝐼 out and 𝜙𝑄 out denote the phases of the demodulated any distortion. Moreover, the phase noise 𝑛,VCO from the signals, respectively, and are given by QVCO can be effectively suppressed by the demodulator in the loop bandwidth 𝑓𝑛,too. 𝜙𝐼 out (𝑠) =[𝜙𝐼 (𝑠) +𝜙𝐼 𝑒 −𝜙𝑛,VCO (𝑠)]𝐹2 (𝑠) 𝐻𝑒 (𝑠) Figures 9(a) and 9(b) presents the system-level simulation result of demodulated spectrum of traditional quadrature =[𝜙𝐼 (𝑠) −𝜙𝑛,VCO (𝑠)]𝐹2 (𝑠) 𝐻𝑒 (𝑠) +𝜙𝐼 𝑒 (𝑠) demodulator and the proposed quadrature tracking demod- (8) ulator, respectively. In the simulation, the modulation type 𝜙 (𝑠) =[𝜙 (𝑠) +𝜙 −𝜙 (𝑠)]𝐹 (𝑠) 𝐻 (𝑠) 𝑄out 𝑄 𝑄푒 𝑛,VCO 2 𝑒 is set to be OFDM with 64 sub-carriers. These results show that the demodulated spectrum of traditional quadrature =[𝜙𝐼 (𝑠) −𝜙𝑛,VCO (𝑠)]𝐹2 (𝑠) 𝐻𝑒 (𝑠) +𝜙𝐼 (𝑠) , 푒 demodulator is significantly degraded as the quadrature Wireless Communications and Mobile Computing 5

1.4 1.4

1.2 1.2 1 1 0.8 0.8

0.6 Magnitude Magnitude 0.6 0.4

0.4 0.2

0.2 0 0 1020304050607080 0 1020304050607080 Subcarrier Subcarrier

0 deg quadrature imbalance 0 deg quadrature imbalance 15 deg quadrature imbalance 15 deg quadrature imbalance (a) (b)

Figure 9: Demodulated spectrum of (a) traditional quadrature demodulator and (b) proposed quadrature tracking demodulator.

V＄＄

Vtune_Q Vtune_I I + I− Q + Q + Output_ Output_ Output_ Output_ I− I + Q + Q− Coupling port_ Coupling Coupling port_ Coupling Coupling port_ Coupling Coupling port_ Coupling (a) (b)

Figure 10: (a) Circuit and (b) CMOS chip of the QVCO. imbalance increasing from 0 degree to 15 degree. Under the to the original NMOS cross-coupled pair. The outputs of same condition, the demodulated spectrum of the proposed two identical differential VCOs then cross-couple to each quadrature tracking demodulator shows a very slight decline. other via the gates of the additional NMOSs. These internal and external couplings of the VCOs force the four outputs signal quadrature each other. Since the QPLL must separately 4. Experimental Results track the I-phase and the Q-phase of the received signal, the QVCO is designed to have two tuning ports, as presented The QVCO of the proposed demodulator was implemented in Figure 10(a). This architecture enables the quadrature of using TSMC 0.18 𝜇m CMOS technology. Figure 10(a) shows the QVCO to be slightly adjusted using the two independent the circuit design of the CMOS QVCO. Generally, a VCO tuning ports. with internal NMOS cross-coupled pairs has a wider oper- Figure 10(b) displays the implemented CMOS QVCO ating range but a poorer phase noise performance than the chip.Themeasuredpowerconsumptionislessthan8.9mW. one with internal PMOS cross-coupled pairs [18]. Based The operating range and output power of the CMOS QVCO on consideration of both the phase noise performance are measured and presented in Figure 11(a). The CMOS and operating range, the internal complementary cross- QVCO can operate from 2.1 to 2.5 GHz with a mean out- coupled pair is used. To realize quadrature outputs, external put power of around 2 dBm, which is sufficiently high to cross-coupling between two identical differential VCOs are drive passive double-balance mixers for phase detection. The required so four additional NMOS are designed to be parallel measured output power of the QVCO also exhibits very 6 Wireless Communications and Mobile Computing

Phase noise (dBc/Hz) 5＞＂ 10 ＞＂ 1 2.526 ＇（Ｔ RF atten /div Mkr −30 ＞＂＝ log Ref 5.00 ＞＂Ｇ 2.563 ＞＂Ｇ Top /Hz (1) −5.00 −50 −15.0 −25.0 −70 −35.0 − −45.0 90 −55.0 −110 −65.0 Magnitude (dBm) Magnitude −75.0 −130 −85.0 10 Ｅ（Ｔ 100 Ｅ（Ｔ 1 －（Ｔ 10 －（Ｔ Center 2.1855 ＇（Ｔ VBW 50 －（Ｔ Span 1.000 ＇（Ｔ Res BW 3.0 －（Ｔ Sweep 1.00 ＧＭ (1001ＪＮＭ) Frequency offset (a) (b)

Figure 11: Measured (a) operating range and output power, and (b) phase noise of CMOS QVCO of demodulator.

Table 1: Performance Comparison of 2.4 GHz QVCOs.

This work [16] [17] Process 0.18 𝜇m CMOS 0.18 𝜇m CMOS 0.18 𝜇mCMOS Supply voltage (V) 1.4 0.6 1.8 Power dissipation (mW) 5.5 14.4 14.8 Frequency (GHz) 2.4 2.4 2.4 Fractional bandwidth (%) 17.5 9.5 26.3 Output power (dBm) 2 −10 0 Phasenoise@1MHz(dBc/Hz) −113 −110∼−104 −112 Quadrature error (Degree) 6.9 2.64 5 FoM @1 MHz 173.2 166.4 168.3

good flatness of better than 2 dB over the wide operating range. Figure 11(b) plots the measured phase noise of the CMOS QVCO. The phase noise is lower than −113 dBc/Hz and −137dBc/Hzat1MHzand10MHzoffsetfrequency, respectively. Table 1 shows the performance comparison between 2.4 GHz CMOS QVCOs, where the figure of merit (FoM) is given by [19] Baseband 𝜔0 𝑃diss output (Q) FoM =−L (Δ𝜔) +20log ( )−10log ( ). (12) LPF Phase Δ𝜔 1𝑚𝑊 Testing board of detector CMOS QVCO The comparison shows that the implemented QVCO achieves a lowest phase noise and power consumption, and conse- Splitter RF quently results in a better FoM over the other QVCOs. input The proposed quadrature-tracking demodulator is imple- Loop filters mented with the designed CMOS QVCO, as presented in Figure 12. The channel-preset frequency synthesizer of the Phase Splitter LPF detector demodulator is implemented using a consumer IC PE3336, Baseband produced by Peregrine. The phase detectors are the ZX05- output (I) C42S+modelfromMini-Circuits.TheLPFsaretheSLP- 10.7+ model, also from Mini-Circuits, and have a 3 dB Channel-preset frequency bandwidthof14MHz.TheloopbandwidthoftheQPLLis synthesizer designedtobe10kHz.ThereceivedLTE-Asignalofthe receiver is generated using a Keysight MXA vector signal Figure 12: Implemented quadrature-tracking de-modulator. Wireless Communications and Mobile Computing 7

∘ ∘ 0∘ 15 quadrature 0∘ 15 quadrature quadrature quadrature imbalance imbalance imbalance imbalance

(a) (b)

∘ Figure 13: Demodulated (a) I-phase and (b) Q-phase baseband waveforms when received LTE-A signal has a quadrature imbalance of 15 .

30 Therefore, the SINAD is usually used to evaluate performance of RF receivers [20]. SINAD is defined as

𝑃𝑆 +𝑃𝑁 +𝑃𝐷 25 SINAD =10log 𝑃𝑁 +𝑃𝐷 (13) 𝑃DS 20 =10log (dB) ,

𝑃𝑁 +𝑃𝐷 SINAD (dB) SINAD where 𝑃𝑆, 𝑃DS, 𝑃𝑁,and𝑃𝐷 represents the power of the ideal 15 signal, distorted signal, noise, and distortion, respectively. The measured results show that the SINAD slightly degrade as 10 the quadrature imbalance increase from 0 degree to 15 degree. 0 3 6 9 12 15 As the quadrature imbalance is 15 degree, the SINAD of Quadrature imbalance (degree) the implemented quadrature-tracking demodulator is about 18.761 dB which is acceptable for most wireless communica- Figure 14: Measured SINAD of the implemented quadrature- tion applications. tracking demodulator. 5. Conclusion generator (VSG) with Keysight Signal Studio. The data rate of In this work, a novel quadrature tracking demodulator the LTE-A signal is set to be 18 Mbps. The sub-carrier space for LTE-A applications was implemented. The 2.1∼2.5 GHz is set to 156.25 kHz, which greatly exceeds the 10 kHz loop QPLL-based demodulator can effectively demodulate an bandwidth of the QPLL. 18 Mbps LTE-A signal with a quadrature-imbalance of up Figures 13(a) and 13(b) presents the demodulated I- to 15 degrees. This remarkable quadrature-tracking ability makes the novel demodulator well suited to LTE-A systems phase and Q-phase waveforms, respectively. To confirm or even more advanced communication systems. the quadrature-tracking performance of the implemented demodulator, the quadrature-imbalance of the LTE-A signal is manually adjusted in the signal studio. As the quadrature- Conflicts of Interest imbalance is increased from 0 degree to 15 degree, both the The authors declare that there is no conflicts of interest I-phase and the Q-phase waveforms are degraded slightly regarding the publication of this paper revealing that the implemented quadrature-tracking demodulator can effectively demodulate the LTE-A signal even if the ∘ signal has a 15 quadrature-imbalance. Acknowledgments Figure 14 shows the measured signal to noise and distor- The authors would like to thank the Ministry of Science tion ratio (SINAD) degradation of the implemented demodu- and Technology (101-2221-E-327-029) for providing research lator as a function of quadrature imbalance. Comparing with funding. The authors would also like to thank the National the well-known signal to noise ratio (SNR), SINAD further Chip Implementation Center, Hsinchu, Taiwan, for providing considers the combining effect of both noise and distortion. the CMOS foundry service. 8 Wireless Communications and Mobile Computing

References [17] S. Shin, K. Lee, and S. M. Kang, “low-power 2.4 GHz CMOS frequency synthesizer with differentially controlled MOS varac- [1] S. Haykin and M. Moher, Communication Systems,Wily,USA, tors,” in Proceedings of the 2006 IEEE International Symposium 5th edition, 2009. on Circuits and Systems, pp. 553–556, Island of Kos, Greece. [2] B. Razavi and RF. Microelectronics, Prentice Hall Inc. [18]K.C.PengandC.H.Lee,“A5GHzCMOSquadratureVCO [3] G. L. Do, “An ultra-fast carrier recovery versus traditional with precise quadrature phase,” in Proceedings of the 2012 synchronizers,” IEEE Transactions on Broadcasting,vol.42,no. Asia-Pacific Microwave Conference, APMC 2012,pp.1211–1213, 1,pp.42–49,1996. Taiwan, December 2012. [19] K. C. Peng and T. S. Horng, “Optimization of phase noise in a [4] J. P. Costas, “Synchronous communications,” Proceedings of the 2.3 - 3.5 GHz voltage-controlled oscillator using the impedance IEEE,vol.90,no.8,pp.1461–1466,2002. locus,” in Progress in Electromagnetics Research Symposium Dig, [5] S.-J. Huang, Y.-C. Yeh, H. Wang, P.-N. Chen, and J. Lee, “W- pp.913–917,2012. band BPSK and QPSK transceivers with Costas-loop carrier [20] Wikipedia contributors, “SINAD,” Wikipedia, The Free Ency- recovery in 65-nm CMOS technology,” IEEE Journal of Solid- clopedia, Available: https://en.wikipedia.org/wiki/SINAD. State Circuits,vol.46,no.12,pp.3033–3046,2011. [6] M. Buchholz, A. Schuchert, and R. Hasholzner, “Effects of tuner IQ imbalance on multicarrier-modulation systems,”in Proceed- ings of the ICCDCS 2000: 3rd IEEE International Conference on Devices, Circuits and Systems, pp. T65/1–T65/6, March 2000. [7] M. Rumney, LTE and the Evolution to 4G Wireless: Design and Measurement Challenges, John Wiley & Sons, West Sussex, UK, 2013. [8] C.-T. Chen, C.-H. Hsiao, T.-S. Horng, K.-C. Peng, and C.-J. Li, “Cognitive polar receiver using two injection-locked oscillator stages,” IEEE Transactions on Microwave Theory and Techniques, vol.59,no.12,pp.3484–3493,2011. [9] R.CherukuriandP.T.Balsara,“Code-aidedadaptivedecorrela- tor for IQ imbalance compensation in iterative receivers for flat fading channels,”in Proceedings of the Military Communications Conference, MILCOM 2007,USA,October2007. [10] L. Giugno, V. Lottici, and M. Luise, “Efficient compensation of I/Q phase imbalance for digital receivers,” in Proceedings of the 2005 IEEE International Conference on Communications, ICC 2005,pp.2462–2466,May2005. [11] C.-H. Hsu, C.-F. Wu, and C.-K. Wang, “FPGA prototype for WLAN OFDM baseband with STPE of I/Q mismatch self calibration algorithm,”in Proceedings of the 1st IEEE Asian Solid- State Circuits Conference, ASSCC 2005,pp.509–512,Taiwan, November 2005. [12] G. Vallant, M. Epp, W. Schlecker, U. Schneider, L. Anttila, and M. Valkama, “Analog IQ impairments in Zero-IF radar receivers: Analysis, measurements and digital compensation,” in Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2012,pp.1703– 1707,Austria,May2012. [13] K. C. Peng, ModulatedFrequencySynthesizers:DesignforWide- band and High Efficiency Modulation,VDMVerlag,Germany, 2009. [14] M. Rumney, LTE and the Evolution to 4G Wireless - Design and Measurement Challenges, Second Edition,JohnWiley&Sons, West Sussex, UK, 2008. [15] K.-C. Peng, C.-H. Lee, C.-H. Chen, and T.-S. Horng, “Enhance- ment of frequency synthesizer operating range using a novel frequency-offset technique for LTE-a and CR applications,” IEEE Transactions on Microwave Theory and Techniques,vol.61, no. 3, pp. 1215–1223, 2013. [16]C.T.Lu,H.H.Hsieh,andL.H.Lu,“Alow-powerquadrature VCO and its application to a 0.6-V 2.4-GHz PLL,” IEEE Transactions on Circuits and Systems I: Regular Papers,vol.57, no. 4, pp. 793–802, 2010.