USOO9026854B2
(12) United States Patent (10) Patent No.: US 9,026,854 B2 Jeong et al. (45) Date of Patent: May 5, 2015
(54) METHOD OF TESTING UNIVERSAL FLASH (56) References Cited STORAGE (UFS) INTERFACE AND MEMORY DEVICE IMPLEMENTING METHOD OF U.S. PATENT DOCUMENTS TESTING UFS INTERFACE 5,640,509 A 6/1997 Balmer et al. 6,671,836 B1* 12/2003 Lai et al...... T14f718 (71) Applicant: Samsung Electronics Co., Ltd., 7,111.208 B2 * 9/2006 Hoang et al...... T14f716 Suwon-si, Gyeonggi-do (KR) 2005/0262336 A1* 11/2005 Cherukuri et al...... 713/2 2010/0049465 A1* 2/2010 Pineda De Gyvez et al. 702/122 2010/0177811 A1* 7, 2010 Duerdodt et al...... 375,224 (72) Inventors: Ha-Neul Jeong, Suwon-si (KR): Woo-Seong Cheong, Suwon-si (KR) (Continued) (73) Assignee: Samsung Electronics Co., Ltd., FOREIGN PATENT DOCUMENTS Suwon-si, Gyeonggi-do (KR) JP 08-2621.16 11, 1996 JP 11-053897 2, 1999 (*) Notice: Subject to any disclaimer, the term of this KR 102OOOOO11182 2, 2000 patent is extended or adjusted under 35 OTHER PUBLICATIONS U.S.C. 154(b) by 207 days. UniPro Controller IP Core, 2009, Arasan Chip Systems, Inc., Version (21) Appl. No.: 13/647,415 1.2a. (Continued) (22) Filed: Oct. 9, 2012 Prior Publication Data Primary Examiner — Scott Baderman (65) Assistant Examiner — Paul Contino US 2013/OO9746O A1 Apr. 18, 2013 (74) Attorney, Agent, or Firm — Volentine & Whitt, PLLC (30) Foreign Application Priority Data (57) ABSTRACT A method is provided for performing a self-test on a memory Oct. 18, 2011 (KR) ...... 10-2011-O106635 device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical (51) Int. C. layer having a transmitting unit and a receiving unit. The G06F II/00 (2006.01) method includes generating a first signal; sending the first GI IC 29/02 (2006.01) signal from a test unit through the UFS link layer to the G06F II/22 (2006.01) transmitting unit in the UFS physical layer to be transmitted GI IC 29/56 (2006.01) to the receiving unit; receiving a second signal at the test unit (52) U.S. C. from the receiving unit in the UFS physical layer through the CPC ...... GI IC 29/022 (2013.01); G06F 1 1/221 UFS link layer, the second signal being the first signal (2013.01); GI IC 2029/5602 (2013.01) received by the receiving unit; and testing an operation per (58) Field of Classification Search formed by at least one of the UFS physical layer and the UFS CPC ...... G06F 11/263; G06F 1 1/277 link layer based on the first signal and the second signal. USPC ...... 714/32 See application file for complete search history. 32 Claims, 20 Drawing Sheets
BUS
TMODTRST HOSTFF ULL FLASH MEMORY UFS LINKLAYER
------NSIGIn NSIGOut TRST TMOD US 9,026,854 B2 Page 2
(56) References Cited Woolk, David. New MIPI Standards, Part 1: M-PHY, EDN Network. Jul. 1, 2011 retrieved on Jun. 18, 2014. Retrieved from the Internet U.S. PATENT DOCUMENTS FIG. 1 MDEV TMOD TRST - ULL FIG 2 TMOD TRES U.S. Patent May 5, 2015 Sheet 2 of 20 US 9,026,854 B2 FIG. 3 MDEV MP M-Phy. U.S. Patent May 5, 2015 Sheet 3 of 20 US 9,026,854 B2 FIG. 4 TMOD TRST Ctrl ME FLASH MEMORY U.S. Patent May 5, 2015 Sheet 4 of 20 US 9,026,854 B2 E U.S. Patent May 5, 2015 Sheet 5 of 20 US 9,026,854 B2 FIG. 6 TU TMOD TRST f FCU TOP XARB1 FLOW CONTROL UNIT re TEST OPERATION UNIT TRST SG1 SG2 FIG 7 TMOD TRST TARGET CONTROL SG1 SIG2 SG1 SG2 (HSIG) (HSIG) (DSG) (DSIG) U.S. Patent May 5, 2015 Sheet 6 of 20 US 9,026,854 B2 U.S. Patent May 5, 2015 Sheet 7 of 20 US 9,026,854 B2 FIG. 9 TMOD TRST TARGET CONTROL INTIALIZATION CONTROL UNIT U.S. Patent May 5, 2015 Sheet 8 of 20 US 9,026,854 B2 FIG 10 ULL UPL DME U.S. Patent May 5, 2015 Sheet 10 of 20 US 9,026,854 B2 FIG. 12 TMOD TRST TARGET CONTROL MESSAGE CONTROL UNIT U.S. Patent May 5, 2015 Sheet 11 of 20 US 9,026,854 B2 FIG. 13 UPL SG 1 DSG FIG. 14 UPL SG 1 HSG U.S. Patent May 5, 2015 Sheet 12 of 20 US 9,026,854 B2 FIG. 15 TMOD TRST TARGET CONTROL INTIALIZATION MESSAGE CONTROL CONTRO UNIT UNIT U.S. Patent May 5, 2015 Sheet 13 of 20 US 9,026,854 B2 FIG 16 TMOD TRST - HOST FLOW TARGET CONTROL CONTROL UNIT CONTROL UNIT UNIT UTL ULL UPL LBL U.S. Patent May 5, 2015 Sheet 16 of 20 US 9,026,854 B2 FIG. 19 UPL U.S. Patent May 5, 2015 Sheet 17 of 20 US 9,026,854 B2 03'0IJI |SH||CJOWN ||NTTOHINOOWOT TOHINOO ||N[] U.S. Patent May 5, 2015 Sheet 18 of 20 US 9,026,854 B2 L - - O ? H 2 O CD >- O > L d 9 U.S. Patent May 5, 2015 Sheet 19 of 20 US 9,026,854 B2 FIG. 22 CSYS U.S. Patent May 5, 2015 Sheet 20 of 20 US 9,026,854 B2 FIG. 23 US 9,026,854 B2 1. 2 METHOD OF TESTING UNIVERSAL FLASH configured to output a first signal and a receiving unit config STORAGE (UFS) INTERFACE AND MEMORY ured to receive the first signal via an LBL as a second signal. DEVICE IMPLEMENTING METHOD OF The UFS translator layer is for at least one of adding prede TESTING UFS INTERFACE termined information relating to the first signal to a header of the first signal, and detecting predetermined information CROSS-REFERENCE TO RELATED relating to the second signal in a header of the second signal. APPLICATIONS The UFS link layer is configured to pass the first signal from the UFS translator layer to the transmitting unit in the UFS A claim of priority under 35 U.S.C. S 119 is made to Korean physical layer and to pass the second signal from the receiv Patent Application No. 10-2011-0106635, filed on Oct. 18, 10 ing unit in the UFS physical layer to the UFS translator layer. 2011, in the Korean Intellectual Property Office, the entire The test unit is configured to test whether the UFS physical contents of which are hereby incorporated by reference. layer and the UFS link layer normally operate according to UFS protocol by generating and transmitting the first signal to BACKGROUND the UFS translator layer and receiving the second signal and 15 the detected predetermined information relating to the second The inventive concept relates to methods of testing a uni signal from the UFS translator layer. versal flash storage (UFS) interface, and memory devices According to another aspect of the inventive concept, a test performing the tests of a UFS interface using the methods, unit is coupled to a UFS link layer and a UFS physical layer and more particularly, where the test is performed at low cost of a memory device, the UFS physical layer including a and quickly adapts to changing technologies. transmitting unit configured to output a first signal and a In order for a host and a device to communicate, a link or receiving unit configured to receive the first signal via anLBL lane connecting the host and the device is formed and data is as a second signal. The test unit includes a flow control unit, transmitted or received through the link or lane. Thus, a test is a host control unit, and a target control unit. The flow control performed to check whether the link or lane is normally unit is configured to receive a test mode signal indicating one formed between the host and the device, and whether data is 25 of a host mode or a target mode for a testing an operation of normally transmitted and received through the link or lane. the memory device, and to generate a first arbitration signal in the host mode and a second arbitration signal in the target SUMMARY mode in response to the test mode signal, where the test unit operates as a host device external to the memory device in the Embodiments of the inventive concept provide methods of 30 host mode and operates as the memory device in the target testing a universal flash storage (UFS) interface and memory mode. The host control unit is for at least one of generating the devices performing tests using the method, where the test is first signal as a host signal and receiving the second signal as performed at low cost and quickly adapts to changing tech the host signal in the host mode, in response to the first nologies. arbitration signal. The target control unit is for at least one of According to an aspect of the inventive concept, a method 35 generating the first signal as a target signal and receiving the of performing a self-test on a memory device in a test mode is second signal as the target signal in the target mode, in provided, where the memory device includes a universal flash response to the second arbitration signal. The test unit is storage (UFS) link layer and a UFS physical layer having a configured to transmit the first signal to the UFS link layer in transmitting unit and a receiving unit. The method includes one of the host mode and the target mode, and to receive the generating a first signal; sending the first signal from a test 40 second signal from the UFS link layer in one of the host mode unit through the UFS link layer to the transmitting unit in the and the target mode, the UFS link layer passing the first and UFS physical layer to be transmitted to the receiving unit; second signals between the test unit and the UFS physical receiving a second signal at the test unit from the receiving layer, to test whether the UFS link layer and the UFS physical unit in the UFS physical layer through the UFS link layer, the layer normally operate according to UFS protocol based on second signal being the first signal received by the receiving 45 the first and second signals. unit; and testing an operation performed by at least one of the According to another aspect of the inventive concept, there UFS physical layer and the UFS link layer based on the first is provided a memory device including a UFS physical layer, signal and the second signal. a UFS link layer and a test unit. The UFS physical layer According to another aspect of the inventive concept, a includes a transmitting unit that outputs a first signal and a memory device having self-test capability in a test mode 50 receiving unit that receives the first signal as a second signal includes a universal flash storage (UFS) physical layer, a UFS according to a UFS protocol, in a test mode. The UFS link link layer and a test unit. The UFS physical layer includes a layer is for transmitting the first signal to the transmitting unit transmitting unit configured to output a first signal and a and receiving the second signal from the receiving unit receiving unit configured to receive the first signal via a according to the UFS protocol. The test unit is for testing loop-back line (LBL) as a second signal, according to UFS 55 whether the UFS physical layer and the UFS link layer nor protocol. The UFS link layer is configured to pass the first mally operate according to the UFS protocol by generating signal to the transmitting unit and to pass the second signal and transmitting the first signal to the UFS link layer and from the receiving unit, according to the UFS protocol. The receiving the second signal from the UFS link layer. test unit is configured to test whether the UFS physical layer The test unit may include a test operation unit for generat and the UFS link layer normally operate according to the UFS 60 ing the first signal and receiving the second signal in a host protocol by generating and transmitting the first signal to the mode in response to a first arbitration signal, or generating the UFS link layer and receiving the second signal from the UFS first signal and receiving the second signal in a target mode in link layer. response to a second arbitration signal. The test unit may According to another aspect of the inventive concept, a further include a flow control unit for generating the first memory device having self-test capability includes a UFS 65 arbitration signal in the host mode and generating the second physical layer, a UFS translator layer, a UFS link layer and a arbitration signal in the target mode, and transmitting the first test unit. The UFS physical layer includes a transmitting unit and second arbitration signals to the test operation unit. US 9,026,854 B2 3 4 The test operation unit may include a host control unit that the UFS link layer are successful, when the generating of the is activated in response to the first arbitration signal, gener first signal and receiving of the second signal are sequentially ating the first signal as a host signal and receiving the second performed. signal as the host signal in the host mode. The test operation The target control unit may be activated in response to the unit may further include a target control unit that is activated second arbitration signal, and control the initialization con in response to the second arbitration signal, generating the trol unit to generate the first signal as a target reset signal first signal as a target signal and receiving the second signal as constituting the target signal, and the host control unit may be the target signal in the target mode. activated in response to the first arbitration signal, and gen The host signal may be a signal playing roles as a host erate the first signal as a host reset signal constituting the host device communicable with the memory device, and the target 10 signal by receiving the target reset signal as the second signal signal may be a signal playing roles as the memory device. constituting the host signal. The test operation unit may further include a message The test unit may perform a test on a lane control operation control unit for performing a test on data transmission and of the UFS physical layer and UFS link layer as the target reception of the UFS physical layer and the UFS link layer, as control unit receives the first signal constituting the host sig 15 the target control unit receives the first signal constituting the nal generated by the host control unit as the second signal host signal generated by the host control unit as the second constituting the target signal, or as the host control unit signal constituting the target signal, or as the host control unit receives the first signal constituting the target signal gener receives the first signal constituting the target signal gener ated by the target control unit as the second signal constituting ated by the target control unit as the second signal constituting the host signal. the host signal. The target control unit may be activated in response to the The host control unit may be activated in response to the second arbitration signal to generate the first signal as a lane first arbitration signal, and control the message control unit to discovery standby notice signal constituting the target signal. generate the first signal as a host data signal constituting the The host control unit may be activated in response to the first host signal, and the target control unit may be activated in arbitration signal and may perform a lane discovery operation 25 response to the second arbitration signal, receive the host data by receiving the lane discovery standby notice signal as the signal as the second signal constituting the target signal, and second signal constituting the host signal, and generate the compare the first and second signals. Alternatively, the target first signal as a lane discovery complete signal constituting control unit may be activated in response to the second arbi the host signal. tration signal, and control the message control unit to gener The target control unit may end a lane discovery standby by 30 ate the first signal as a target data signal constituting the target receiving the lane discovery complete signal as the second signal, and the host control unit may be activated in response signal constituting the target signal, and generating a lane to the first arbitration signal, receive the target data signal as realignment standby notice signal constituting the target sig the second signal constituting the host signal, and compare nal as the first signal. The host control unit may perform a lane the first and second signals. The test unit may generate a test realignment operation by receiving the lane realignment 35 result that tests whether data transmission and reception of standby notice signal as the second signal constituting the the UFS physical layer and the UFS link layer are successful, host signal, and generating the first signal as a lane realign when the first and second signals are identical. ment complete signal constituting the host signal. The memory device may further include a UFS translator The target control unit may end a lane realignment standby layer for adding predetermined information to the first signal by receiving the lane realignment complete signal as the 40 generated as the target signal and transmitting the first signal Second signal constituting the target signal, and generating a to the UFS link layer, or for analyzing information included in lane termination standby notice signal constituting the target the second signal constituting the target signal from the UFS signal as the first signal. The host control unit may perform a link layer and transmitting the information to the test unit. lane termination operation by receiving the lane termination At least one of the UFS physical layer, the UFS link layer, standby notice signal as the second signal constituting the 45 and the test unit may be included in a controller of the host signal. The test unit may generate a test result that tests memory device. The memory device may be a memory card whether lane control of the UFS physical layer and the UFS or a solid state drive (SSD). The UFS physical layer may be a link layer are successful, when the generating of the first mobile industry processor interface (MIPI) M-Phy and the signal and receiving of the second signal are sequentially UFS link layer may be a MIPI Unipro, for example. Accord performed. 50 ing to other aspects of the inventive concept, the memory The test operation unit may further include an initialization provided may be provided in a computer system. control unit for performing tests on reset of the UFS physical layer and the UFS link layer, as the target control unit receives BRIEF DESCRIPTION OF THE DRAWINGS the first signal constituting the host signal generated by the host control unit as the second signal constituting the target 55 Exemplary embodiments will be more clearly understood signal, or as the host control unit receives the first signal from the following detailed description taken in conjunction constituting the target signal generated by the target control with the accompanying drawings, in which: unit as the second signal constituting the host signal. FIG. 1 is a block diagram of a memory device, according to The host control unit may be activated in response to the an embodiment of the inventive concept; first arbitration signal, and control the initialization control 60 FIG. 2 is a block diagram showing a universal flash storage unit to generate the first signal as a host reset signal consti (UFS) link layer and a UFS physical layer of FIG. 1, accord tuting the host signal. The target control unit may be activated ing to an embodiment of the inventive concept; in response to the second arbitration signal, and generate the FIG. 3 is a block diagram showing a lane formed between first signal as a target reset signal constituting the target signal a memory device and a host device, according to an embodi by receiving the host reset signal as the second signal consti 65 ment of the inventive concept; tuting the target signal. The test unit may generate a test result FIG. 4 is a block diagram of a memory device, according to that tests whether lane control of the UFS physical layer and an embodiment of the inventive concept; US 9,026,854 B2 5 6 FIG. 5 is a block diagram of a solid state drive (SSD) as the presence of stated features, integers, steps, operations, ele memory device of FIG. 1, according to an embodiment of the ments, and/or components, but do not preclude the presence inventive concept; or addition of one or more other features, integers, steps, FIG. 6 is a block diagram of a test unit of FIG. 1, according operations, elements, components, and/or groups thereof. As to an embodiment of the inventive concept; used herein, the term “and/or includes any and all combina FIG. 7 is a block diagram of a test operation unit of FIG. 6, tions of one or more of the associated listed items. Also, according to an embodiment of the inventive concept; expressions such as “at least one of when preceding a list of FIG. 8 is a flow diagram for describing a method of testing elements, modify the entire list of elements and do not modify a lane control operation in a memory device, according to an the individual elements of the list. embodiment of the inventive concept; 10 It will be understood that, although the terms “first”, “sec FIG. 9 is a block diagram of the test operation unit of FIG. ond', “third”, etc., may be used herein to describe various 6, according to another embodiment of the inventive concept; elements, components, regions, layers and/or sections, these FIGS. 10 and 11 are flow diagrams showing operations of elements, components, regions, layers and/or sections should an initialization control unit of FIG.9, according to embodi not be limited by these terms. These terms are only used to ments of the inventive concept; 15 distinguish one element, component, region, layer or section FIG. 12 is a block diagram of the test operation unit of FIG. from another region, layer or section. Thus, a first element, 6, according to another embodiment of the inventive concept; component, region, layer or section discussed below could be FIGS. 13 and 14 are flow diagrams showing operations of termed a second element, component, region, layer or section a message control unit of FIG. 12, according to embodiments without departing from the teachings of the inventive con of the inventive concept; cept. FIG. 15 is a block diagram of the test operation unit of FIG. Embodiments of the inventive concept are described herein 6, according to another embodiment of the inventive concept; with reference to schematic illustrations of idealized embodi FIG. 16 is a block diagram of a memory device according ments (and intermediate structures) of the inventive concept. to another embodiment of the inventive concept; AS Such, variations from the shapes of the illustrations as a FIG. 17 is a flow diagram showing operations of the UFS 25 result, for example, of manufacturing techniques and/or tol translator layer of FIG.16, according to an embodiment of the erances, are to be expected. Thus, embodiments of the inven inventive concept; tive concept should not be construed as limited to the particu FIG. 18 is a flow diagram showing a lane control operation lar shapes of regions illustrated herein but are to include utilizing the UFS translator layer of FIG. 16, according to an deviations in shapes that result, for example, from manufac embodiment of the inventive concept. 30 turing. FIG. 19 is a flow diagram showing a data transmission and FIGS. 1 and 2 are block diagrams of a memory device reception operation utilizing the UFS translator layer of FIG. MDEV, according to embodiments of the inventive concept. 16, according to an embodiment of the inventive concept. Referring to FIG. 1, the memory device MDEV includes a FIG.20 is a block diagram of the test unit of FIG. 15 and the universal flash storage (UFS) link layer ULL, a UFS physical UFS translator layer of FIG. 16, according to an embodiment 35 layer UPL, and a test unit TU. The UFS link layer ULL of the inventive concept; converts a first signal SIG1 and a second signal SIG2 accord FIG. 21 is a block diagram of a memory card, according to ing to a UFS protocol, and the UFS physical layer UPL an embodiment of the inventive concept; outputs (transmits) the first signal SIG1 and receives the FIG.22 is a block diagram of a computer system, according second signal SIG2 according to the UFS protocol. The UFS to an embodiment of the inventive concept; and 40 protocol is a standard providing a common interface for vari FIG. 23 is a block diagram of a network system including ous flash memories. a server system with a solid state drive (SSD), according to an As shown in FIG. 2, the UFS link layer ULL may be embodiment of the inventive concept. implemented as mobile industry processor interface (MIPI) Unipro, and the UFS physical layer UPL may be imple DETAILED DESCRIPTION OF THE 45 mented as MIPIM-phy, for example. MIPI Unipro is a com EMBODIMENTS munication protocol capable of Supporting fast communica tion speeds using fewer lines. The MIPI Unipro may be Embodiments will be described in detail with reference to realized by a physical adaptor layer L1.5, a data link layer L2. the accompanying drawings. The inventive concept, however, a network layer L3, a transaction layer L4, and device man may be embodied in various different forms, and should not 50 agement entity (DME) that controls the physical adaptor be construed as being limited only to the illustrated embodi layer L1.5, the data link layer L2, the network layer L3, and ments. Rather, these embodiments are provided as examples the transaction layer L4. The layers of MIPI Unipro sequen so that this disclosure will be thorough and complete, and will tially convert a signal into forms of a segment, a packet, and fully convey the concept of the inventive concept to those a frame, or into forms of a frame, a packet, and a segment, for skilled in the art. Accordingly, known processes, elements, 55 example. A header may be added to or removed from the first and techniques are not described with respect to some of the and second signals SIG1 and SIG2, according to converting embodiments of the inventive concept. Unless otherwise operations between the layers as the first and second signals noted, like reference numerals denote like elements through SIG1 and SIG2 pass through the layers. However, for ease of out the attached drawings and written description, and thus explanation, the first and second signals SIG1 and SIG2 are descriptions will not be repeated. 60 referred to by the same name regardless of the state of con The terminology used herein is for the purpose of describ version. ing particular embodiments only and is not intended to be FIG. 3 is a block diagram showing a lane formed between limiting of the inventive concept. As used herein, the singular a memory device and a host device, according to an embodi forms “a”, “an and “the are intended to include the plural ment of the inventive concept. forms as well, unless the context clearly indicates otherwise. 65 Referring to FIG. 3, MIPIM-phy forms a lane LA with an It will be further understood that the terms “comprises” and/ external host device HDEV. The memory device MDEV. or “comprising, when used in this specification, specify the according to an embodiment, transmits and receives a signal US 9,026,854 B2 7 8 to and from the external host device HDEV through the lane UFS physical layer UPL, the lane control operation, and the LA. The host device HDEV includes representative first data transmitting and receiving operation of the UFS link through third communication terminalsTRN1 through TRN3 layer ULL and the UFS physical layer UPL. Accordingly, the for each connected device. For example, the first communi test unit TU tests whether the UFS physical layer UPL and the cation terminal TRN1 of the host device HDEV may be UFS link layer ULL normally perform the above operations assigned to the memory device MDEV. by generating and transmitting the first signal SIG1 sent to the Each of the first through third communication terminals UFS link layer ULL and receiving the second signal SIG2 TRN1 through TRN3 of the host device HDEV includes at from the UFS link layer ULL in a test mode. The test unit TU least one pair of a transmitting unit TX and a receiving unit RX generates and outputs a test result TRST indicating test to transmit and receive signals to and from connected devices. 10 results. For example, the first communication terminal TRN1 of the The test unit TU, the UFS link layer ULL, and the UFS host device HDEV connected to the memory device MDEV physical layer UPL may be included in a memory controller includes two pairs TR1 and TR2 of a transmitting unit Tx and Ctrl of the memory device MDEV, for example, as shown in a receiving unit RX. When a connection between the host FIG. 4. The memory controller Ctrl of the memory device device HDEV and the memory device MDEV is initiated, the 15 MDEV controls data to be programmed to or read from rep MIPIM-phy of FIG. 2 may be connected to the pair TR1 or resentative flash memory MEM. Alternatively, the test unit the pair TR2 of the first communication terminal TRN1 of the TU may be included in the memory MEM. host device HDEV. Alternatively, if the memory device MDEV is realized by a A channel formed to transmit and receive signals to and solid state drive (SSD) as shown in FIG. 5, the test unit TU from the host device HDEV and the memory device MDEV may be included in a host interface HOST I/F , along with may be referred to as a lane. For example, referring to FIG.3, the UFS link layer ULL and the UFS physical layer UPL. the transmitting unit Tx and the receiving unit RX of the MIPI Alternatively, the test unit TU may be realized as a functional M-phy of the memory device MEDV are connected to the block separate from the host interface HOSTI/F including the transmitting unit Tx and the receiving unit Rx of the pair TR1 UFS link layer ULL and the UFS physical layer UPL. of the first communication terminal TRN1 of the host device 25 The SSD of FIG. 5 includes SSD controller SCTL and HDEV to form the lane L.A. memory MEM, and the host interface HOST I/F may be Referring again to FIG. 1, the UFS link layer ULL and the included in the SSD controller SCTL. The host interface UFS physical layer UPL interface data transmission and HOST I/F transmits a request of the host device HDEV or a reception between the memory device MEDV and a host process result of the SSD according to the request to the host device, such as the host device HDEV. An example of the host 30 device HDEV. Generally, the host interface HOST I/F inter device is provided by the host device HDEV of FIG. 5. In faces with the host device HDEV using any of various inter other words, a host device described hereinafter may be the face protocols, such as universal serial bus (USB), multime host device HDEV of FIG.5. The UFS link layer ULL and the dia card (MMC), peripheral component interconnect-express UFS physical layer UPL may convert application data having (PCI-E), serial advanced technology attachment (SATA), par a bit value transmitted from a processor (not shown) of the 35 allel advanced technology attachment (PATA). Small com memory device MDEV to an electric signal transmittable to puter system interface (SCSI), enhanced small device inter the host device HDEV through the lane LA of FIG.3, or may face (ESD), and intelligent drive electronics (IDE), for convert an electric signal received from the host device example. The host interface HOSTI/F may specifically inter HDEV to application data having a bit value usable in the face with the host device HDEV using the UFS protocol as processor of the memory device MDEV. 40 described above. In order to transmit and receive a signal (or data) to and The test unit TU may be activated in a test mode. In other from the host device HDEV, the UFS link layer ULL and the words, the test unit TU may test whether the reset operation, UFS physical layer UPL first reset, e.g., when the memory the lane control operation, and/or the data transmitting and device MDEV is powered on, and perform a lane control receiving operation is performed normally in the UFS link operation on a lane, such as a link start-up operation. The reset 45 layer ULL and the UFS physical layer UPL in the test mode. is an operation that includes initiating the UFS link layer ULL The test unit TU enters the test mode in response to receiving and the UFS physical layer UPL of the memory device a test mode signal TMOD. A test operation performed by the MDEV to communicate with the host device HDEV. The lane test unit TU will be described in detail below. control operation includes forming and controlling the lane The test mode signal TMOD may be externally received LA shown in FIG. 3, for example, for the memory device 50 and the test result TRST of the test unit TU may be externally MDEV to communicate with the host device HDEV. The lane transmitted. A user testing the memory device MDEV may control operation may include at least one of a lane discovery check the test mode signal TMOD and the test result TRST operation, a lane realignment operation, and a lane termina through a separate interface device (not shown). Alterna tion operation. When a lane is formed or changed (e.g., tively, a processor PROS may transmit the test mode signal realigned) for communication with the host device HDEV. 55 TMOD to the test unit TU and receive the test result TRST via the data is transmitted and received to and from the host a bus BUS. device HDEV through the formed or changed lane. In the depicted embodiment, the processor PROS is Accordingly, while testing whether communication included in the SSD controller SCTL, along with the host between the memory device MDEV and the host device interface HOST IVF. Moreover, the SSD controller SCTL HDEV is normally performed, the reset of the UFS link layer 60 further includes random access memory (RAM), a cache ULL and UFS physical layer UPL, as well as the lane control buffer (CBUF), and a memory controller Ctrl that are con operation and the data transmitting and receiving operation of nected to the hostinterface HOSTI/F and the processor PROS the UFS link layer ULL and the UFS physical layer UPL need through the bus BUS. When the test unit TU of FIG. 5 is to be tested. deactivated, i.e., when the memory device MDEV operates in Referring again to FIG. 1, the test unit TU included in the 65 a normal mode instead of the test mode, the processor PROS memory device MDEV performs a test on at least one opera of the SSD controller SCTL controls the SSD to operate tion from among the reset of the UFS link layer ULL and the according to a request NSIG. In of the host device HDEV US 9,026,854 B2 10 received through the receiving unit RX of the UFS physical generate and output the test result TRST according to the first layer UPL of the host interface HOST I/F. Also, the processor and second signals SIG1 and SIG2. Test operations in the PROS controls the SSD to transmit a process result NSI memory device MDEV will be described regardless of G. Out of the SSD regarding the request NSIG. In of the host whether the test result TRST is transmitted from the test device HDEV to the host device HDEV through the transmit operation unit TOP to the flow control unit FCU or the first ting unit Tx of the UFS physical layer UPL. and second signals SIG1 and SIG2 are transmitted from the Here, data required to operate the processor PROS may be test operation unit TOP to the flow control unit FCU. loaded in the RAM. Also, data to be transmitted to the In the host mode, the test unit TU operates as the host memory MEM or received from the memory MEM may be device HDEV that controls the memory device MDEV, and in temporarily stored in the cache buffer CBUF. The cache 10 the target mode, the test unit TU operates as the memory buffer CBUF may be a static RAM (SRAM), for example. device MDEV. The first and second signals SIG1 and SIG2 in Also, the processor PROS and the memory controller Ctrl of the host mode are signals operated on in the host device the SSD may be realized by one ARM processor, for example. HDEV generated by the test unit TU, whereas the first and FIG. 5 shows the memory device MDEV realized as an second signals SIG1 and SIG2 in the target mode are signals SSD, but the embodiments are not limited to this configura 15 operated on in the memory device MDEV generated by the tion. Various examples of realizing the memory device test unit TU. Details about the first and second signals SIG1 MDEV will be described in detail below. and SIG2 will be described in detail below. The test operation of the memory device MDEV, according FIG. 7 is a block diagram of the test operation unit TOP of to an embodiment, will now be described in detail. FIG. 6, according to an embodiment of the inventive concept. Referring again to FIG. 1, in the memory device MDEV. Referring to FIG. 7, the test operation unit TOP according the first signal SIG1 generated by the test unit TU is output to to the depicted embodiment includes a host control unit HCU the transmitting unit Tx of the UFS physical layer UPL. The and a target control unit TCU. The host control unit HCU first signal SIG1 output from the transmitting unit Tx of the generates the first signal SIG1 and receives the second signal UFS physical layer UPL is looped back to the receiving unit SIG2 in the host mode, in response to the first arbitration Rx of the UFS physical layer UPL. The memory device 25 signal XARB1. The host control unit HCU may include a MDEV may further include a loop-back line LBL connecting command set realized in the host device HDEV. The com the transmitting unit Tx and the receiving unit Rx of the UFS mand set may be stored in a register (not shown). Accord physical layer UPL to enable the loop-back of the first signal ingly, the first signal SIG1 generated by the host control unit SIG1 from the transmitting unit TX to the receiving unit Rx of HCU and the second signal SIG2 received by the host control the UFS physical layer UPL. In the depicted embodiment, the 30 unit HCU may be a host signal HSIG operated on in the host first signal SIG1 looped back from the transmitting unit Tx to device HDEV. In other words, the host control unit HCU the receiving unit Rx of the UFS physical layer UPL is generates or receives the first or second signal SIG1 or SIG2. referred to as the second signal SIG2. which is the host signal HSIG, to operate as the host device FIG. 6 is a block diagram of the test unit TU of FIG. 1, HDEV, so that the memory device MDEV simulates commu according to an embodiment of the inventive concept. 35 nication with the host device HDEV without being connected Referring to FIGS. 1 and 6, the test unit TU includes a flow to the host device HDEV. control unit FCU and a test operation unit TOP. The flow The target control unit TCU generates the first signal SIG1 control unit FCU receives the test mode signal TMOD, indi and receives the second signal SIG2 in the target mode, in cating a host mode or a target mode. In response, the flow response to the second arbitration signal XARB2. The target control unit FCU generates first arbitration signal XARB1 in 40 control unit TCU may include a command set realized in the the host mode and second arbitration signal XARB2 in the memory device MDEV. The command set may be stored in a target mode for controlling the test operation unit TOP, register (not shown). Accordingly, the first signal SIG1 gen accordingly. When the flow control unit FCU transmits the erated by the target control unit TCU and the second signal first arbitration signal XARB1 to the test operation unit TOP, SIG2 received by the target control unit TCU may be a target the test operation unit TOP generates the first signal SIG1 in 45 signal DSIG operated on in the memory device MDEV. the host mode and receives the second signal SIG2 in the host FIG. 8 is a signal flow diagram for describing a method of mode. Alternatively, when the flow control unit FCU trans testing a lane control operation in a memory device, accord mits the second arbitration signal XARB2 to the test opera ing to an embodiment of the inventive concept. More specifi tion unit TOP, the test operation unit TOP generates the first cally, in FIG. 8, the lane control operation includes a data lane signal SIG1 in the target mode and receives the second signal 50 discovery operation, a lane realignment operation, and a lane SIG2 in the target mode. The flow control unit FCU may be termination operation. However, the lane control operation is implemented by a state machine, for example, to perform a not limited to including all these operations, and may include mode Switch corresponding to the generating of the first sig alternative or additional operations. Hereinafter, the method nal SIG1 and the receiving of the second signal SIG2. of FIG. 8 will be described with reference to the illustrative As mentioned above, the test operation unit TOP generates 55 test unit TU shown in FIG. 7. However, the method may be the first signal SIG1 and receives the second signal SIG2 in performed by test units according to other embodiments, the host mode or the target mode, in response to the first without departing from the scope of the present teachings. arbitration signal XARB1 or the second arbitration signal Referring to FIGS. 7 and 8, the test unit TU first tests the XARB2, respectively. The test operation unit TOP may also data lane discovery operation, so as to test the lane control generate the test result TRST based on whether the generating 60 operation. The data lane discovery operation initiates a lane, of the first signal SIG1 and the receiving of the second signal such as the lane LA of FIG. 3, as the memory device MDEV SIG2 are normally performed, and may transmit the test result and the host device HDEV exchange information about an TRST to the flow control unit FCU, which may transmit the activated lane. In order to perform the data lane discovery test result TRST to the processor PROS or the like, as operation, the flow control unit FCU transmits the second described above. Alternatively, the test operation unit TOP 65 arbitration signal XARB2 to the target control unit TCU. The may transmit the first and second signals SIG1 and SIG2 to target control unit TCU generates the first signal SIG1 in the flow control unit FCU, and the flow control unit FCU may response to the second arbitration signal XARB2, which is a US 9,026,854 B2 11 12 target signal DSIG. Here, the signal generated by the target operation mode by being synchronized with the receiving of control unit TCU as the first signal SIG1 for the data lane the second signal SIG2 by the receiving unit RX of the UFS discovery operation may be a lane discovery standby notice physical layer UPL or the test unit TU. signal SIG1 Y1. DSIG for notifying the host that the Referring again to FIGS. 7 and 8, in order to switch from memory device MDEV is standing by for lane discovery. The the target mode to the host mode, the flow control unit FCU lane discovery standby notice signal SIG1 Y1. DSIG may transmits the first arbitration signal XARB1 to the host con include information about the activated lane in the memory trol unit HCU. Accordingly, the lane discovery standby notice device MDEV. The target control unit TCU may include a signal SIG2 Y1 HSIG constituting the second signal SIG2 is register (not shown) for storing the information about the transmitted to the host control unit HCU. The host control activated lane. 10 unit HCU generates a lane discovery complete signal In FIG. 8, a reference symbol of the target signal DSIG is SIG1 Y2 HSIG as the first signal SIG1, in response to the included in a reference symbol of the lane discovery standby lane discovery standby notice signal SIG2 Y1 HSIG consti notice signal SIG1 Y1. DSIG to show that the lane discovery tuting the second signal SIG2. The lane discovery complete standby notice signal SIG1 Y1. DSIG is a signal in the target signal SIG1 Y2 HSIG notifies the memory device MDEV mode, i.e., the target signal DSIG operated on in the memory 15 that the lane discovery operation is performed after the host device MDEV. Generally, reference symbols of signals show device HDEV performed the lane discovery operation in whether they are a target signal DSIG or a host signal HSIG. response to a lane discovery request of the memory device The lane discovery standby notice signal SIG1 Y1. DSIG MDEV. Here, information about a formed lane (for example, generated by the target control signal TCU is transmitted to information about which lane is used to connect the host the UFS link layer ULL. The UFS link layer ULL sends the device HDEV and the memory device MDEV) may be stored lane discovery standby notice signal SIG1 Y1. DSIG to the in a register (not shown) of the host control unit HCU. transmitting unit Tx of the UFS physical layer UPL by When the lane discovery complete signal SIG1 Y2 HSIG sequentially converting the lane discovery standby notice constituting the host signal HSIG is output from the transmit signal SIG1 Y1. DSIG to forms of segments, packets, and ting unit Tx of the UFS physical layer UPL, the lane discovery frames. 25 complete signal SIG1 Y2 HSIG is received by the receiving The transmitting unit Tx of the UFS physical layer UPL unit RX of the UFS physical layer UPL as the second signal converts the lane discovery standby notice signal SIG2 constituting the target signal DSIG. As described above, SIG1 Y1. DSIG in the form of frames to an electric signal, the flow control unit FCU switches the operation mode of the and outputs the electric signal. The lane discovery standby test operation unit TOP from the host mode to the target mode notice signal SIG1 Y1. DSIG output from the transmitting 30 before or at the same time the second signal SIG2 is received unit Tx of the UFS physical layer UPL is received by the by the receiving unit RX of the UFS physical layer UPL. Thus, receiving unit Rx of the UFS physical layer UPL through the the target control unit TCU receives a lane discovery com loop-back line LBL of FIG. 1. As described above, a signal plete signal SIG2 Y2 DSIG as the second signal SIG2, in received by the receiving unit Rx of the UFS physical layer response to the second arbitration signal XARB2 transmitted UPL through the loop-back line LBL in the test mode, where 35 from the flow control unit FCU to the target control unit TCU. the test unit TU is activated, is called the second signal SIG2. As such, the lane for communication between a memory A lane discovery standby notice signal SIG2 Y1 HSIG con device and a host device is initialized. For example, in the stituting the electric signal received by the receiving unit RX memory device MDEV, the lane LA is activated with respect of the UFS physical layer UPL is sent to the test unit TU to the host device HDEV, as shown in FIG. 3, and the host through the UFS link layer ULL after being sequentially 40 device HDEV is aware that the lane LA is activated with converted to forms of frames, packets, and segments. Since respect to the memory device MDEV. Thus, the memory converting operations in the UFS link layer ULL and UFS device MDEV and the host device HDEV are able to physical layer UPL are the same as those described above, exchange data through the lane LA. The target control unit details about the converting operations in the UFS link layer TCU and the host control unit HCU may each store informa ULL and UFS physical layer UPL will not be repeated while 45 tion about an activated lane in a register. describing the signal flow of the first and second signals SIG1 Referring again to FIGS. 7 and 8, the lane realignment and SIG2. operation is performed when the target control unit TCU In the depicted embodiment, the lane discovery standby receives the lane discovery complete signal SIG2 Y2 DSIG notice signal SIG2 Y1 HSIG is a host signal HSIG because as the second signal SIG2. The lane realignment operation is the flow control unit FCU switches the operation mode of the 50 performed to check information about the lane and to update test unit TU at the same time or before the second signal SIG2 lane information if the lane has changed, since a state of the is received by the receiving unit Rx of the UFS physical layer lane formed between the memory device MDEV and the host UPL. For example, the flow control unit FCU may switch the device HDEV may be changed. For example, the lane LA of operation mode from the target mode to the host mode before FIG. 3 formed between the memory device MDEV and the the receiving unit Rx of the UFS physical layer UPL receives 55 transmission unit Tx and the receiving unit Rx of the pair TR1 the lane discovery standby notice signal SIG2 Y1 HSIG as of the first communication terminal TRN1 of the host device the second signal SIG2. The flow control unit FCU may HDEV may be switched to the transmitting unit Tx and the include a timer (not shown) to Switch the operation mode receiving unit RX of the pair TR2 of the first communication between the target mode and the host mode. Here, the timer terminal TRN1 of the host device HDEV, and the lane realign may perform a timing operation on an average time for the 60 ment operation is performed to provide information required first signal SIG1 to be output from the test unit TU to the to transmit and receive signals between the memory device transmitting unit Tx of the UFS physical layer UPL. Alterna MDEV and the host device HDEV through the changed lane. tively, the flow control unit FCU may switch the operation In other words, the lane realignment operation is performed to mode by receiving information about the first signal SIG1 check whether information about the lane formed between being output from the transmitting unit Tx of the UFS physi 65 the memory device MDEV and the host device HDEV has cal layer UPL, but embodiments of the inventive concept are changed via the lane discovery operation, and if the informa not limited thereto. The flow control unit FCU may switch the tion has changed, to update the information. In the above US 9,026,854 B2 13 14 illustrative embodiment, if communication cannot be per test result TRST may show that the lane control operation in formed through a first lane formed via the lane discovery the UFS physical layer UPL and the UFS link layer ULL operation, the lane realignment operation may be performed Succeeded. such that the communication is performed between the host The lane control operation may be performed when the device HDEV and the memory device MDEV through a new UFS link layer ULL is reset. As described above, the resetting second lane. of the UFS link layer ULL may be performed when the The target control unit TCU generates a lane realignment memory device MDEV is turned on, for example. The lane standby notice signal SIG1 Y3 DSIG as the first signal SIG1 control operation of FIG.8 may be performed when the UFS constituting the target signal DSIG to check whether the lane link layer ULL according to an embodiment is reset. Alter realignment operation is normally performed in the memory 10 natively, the lane control operation of FIG. 8 may be per formed after the UFS link layer ULL is reset by the host device MDEV. The lane realignment standby notice signal control unit HCU and the target control unit TCU of FIG. 7. SIG1 Y3 DSIG includes the information about the lane FIG. 9 is a functional block diagram of the test unit TU of formed via the lane discovery operation. The lane realign FIGS. 6 and 7, according to an embodiment of the inventive ment standby notice signal SIG1 Y3 DSIG constituting the 15 concept. The test unit TU further includes an initialization first signal SIG1 is converted in the UFS link layer ULL and control unit ICU for testing a reset operation, along with the output through the transmitting unit Tx of the UFS physical host control unit HCU and the target control unit TCU, so that layer UPL. The receiving unit RX of the UFS physical layer the UFS link layer ULL is reset by the initialization control UPL receives the lane realignment standby notice signal unit ICU before the lane control operation of FIG.8. FIG. 10 SIG1 Y3 DSIG as the second signal SIG2 in the host mode, is a signal flow diagram for describing a method of testing a and the lane realignment standby notice signal reset operation in a memory device, according to an embodi SIG2 Y3 HSIG constituting the second signal SIG2 is con ment of the inventive concept. verted in the UFS link layer ULL and received by the host Referring to FIGS. 9 and 10, the initialization control unit control unit HCU. ICU of the test unit TU according to the depicted embodiment More particularly, the flow control unit FCU switches the 25 receives a first control signal XCON1 from the host control operation mode of the test operation unit TOP from the target unit HCU, which is activated in response to the first arbitra mode to the host mode before or at the same time the second tion signal XARB1 from the flow control unit FCU. The signal SIG2 is received by the receiving unit RX of the UFS initialization control unit ICU generates the first signal SIG1 physical layer UPL. Thus, the host control unit HCU is acti as a host reset signal SIG1 HSIG constituting the host signal vated in response to the first arbitration signal XARB1, 30 HSIG in response to the first control signal XCON1, and receives the lane realignment standby notice signal sends the host reset signal SIG1 HSIG to the UFS link layer SIG2 Y3 HSIG as the second signal SIG2, and generates a ULL. In response to the host reset signal SIG1 HSIG, the lane realignment complete signal SIG1 Y4 HSIG as the first DME of the UFS link layer ULL transmits host layer reset signal SIG1 constituting the host signal HSIG. The lane signals X1 HSIG and X2 HSIG requesting reset to the layers realignment complete signal SIG1 Y4 HSIG may include 35 L4 through L2 and to layer L1.5, respectively, of the UFS link lane information according to the lane realignment operation layer ULL. In FIG. 10, the same host layer reset signal between the host device HDEV and the memory device X1 HSIG is transmitted to each of the layers L2 through L4 MDEV. Here, the lane information checked through the lane of FIG.4, but this is only for convenience of illustration, and realignment operation may be stored in a register (not shown) different host layer reset signals may be transmitted to the of the host control unit HCU. The lane information according 40 layers L2 through L4, respectively. to the lane realignment operation may be identical to or newly The layers L1.5 through L4 perform the reset operation in updated from previous lane information. response to the corresponding host layer reset signals The lane realignment complete signal SIG1 Y4 HSIG X1 HSIG and X2 HSIG. When the reset operation is com constituting the host signal HSIG is output as the first signal pleted, the layer L1.5 transmits a host reset complete signal SIG1 through the transmitting unit Tx of the UFS physical 45 X3 HSIG to the DME. In response to the host reset complete layer UPL, and the receiving unit Rx of the UFS physical signal X3 HSIG, the DME sends the host reset signal layer UPL receives a lane realignment complete signal SIG1 HSIG constituting the first signal SIG1 to the transmit SIG2 Y4 DSIG as the second signal SIG2 in the target ting unit Tx of the UFS physical layer UPL, which transmits mode, constituting the target signal DSIG. the host reset signal SIG1 HSIG. The receiving unit Rx of the Upon receiving the lane realignment complete signal 50 UFS physical layer UPL receives the host reset signal SIG2 Y4 DSIG as the second signal SIG2, the target control SIG1 HSIG output from the transmitting unit Tx of the UFS unit TCU generates a lane termination standby notice signal physical layer UPL as the target reset signal SIG2 DSIG SIG1 Y5 DSIG as the first signal SIG1 constituting the tar constituting the second signal SIG2. Here, the test operation get signal DSIG. The lane termination standby notice signal unit TOP transmits a second control signal XCON2 to the SIG1 Y5 DSIG constituting the target signal DSIG is output 55 initialization control unit ICU, so that the second arbitration as the first signal SIG1 through the transmitting unit Tx of the signal XARB2 for operating the memory device MDEV in UFS physical layer UPL, and the receiving unit Rx of the UFS the target mode is transmitted to the target control unit TCU, physical layer UPL receives a lane termination standby signal and the initialization control unit ICU processes the host reset SIG2 Y5 HSIG as the second signal SIG2 in the host mode, signal SIG1 HISG as the target reset signal SIG2 DSIG. constituting the host signal HSIG. The host control unit HCU 60 Upon receiving the host reset signal SIG1 HSIG as the receives the lane termination standby notice signal target reset signal SIG2 DSIG, the initialization control unit SIG2 Y5 HSIG as the second signal SIG2 constituting the ICU generates the first signal SIG1 as a target reset signal host signal HSIG. The lane termination operation breaks the SIG1 DSIG constituting the target signal DSIG, in response lane between the host device HDEV and the memory device to the second control signal XCON2. The DME receives the MDEV during power-off. 65 target reset signal SIG1 DSIG from the initialization control When the generating of the first signal SIG1 and the receiv unit ICU and transmits target layer reset signals X1 DSIG ing of the second signal SIG2 are sequentially performed, the and X2 DSIG requesting reset to the layers L1.5 to L4 of the US 9,026,854 B2 15 16 UFS link layer ULL, respectively, in response to the target reception in the test unit TU of FIG. 12, according to embodi reset signal SIG1 DSIG. In FIG. 10, the same target layer ments of the inventive concept. reset signal X1. DSIG is transmitted to each of the layers L2 Referring to FIGS. 1, 12, and 13, the message control unit through L4 of FIG. 2, but this is only for convenience of MCU performs a test on data transmission and reception of illustration, and different target layer reset signals may be 5 the UFS physical layer UPL and the UFS link layer ULL. In transmitted to the layers L2 through L4, respectively. particular, the message control unit MCU generates the first The layers L1.5 through L4 perform the reset operation in signal SIG1 as target data signal SIG1 DSIG constituting the response to the corresponding target layer reset signals target signal DSIG, in response to the second control signal X1 DSIG and X2 DSIG. When the reset operation is com XCON2. The second control signal XCON2 is generated by pleted, the layer L1.5 transmits a target reset complete signal 10 the target control unit TCU activated by the second arbitration X3 DSIG to the DME, notifying that the reset operation is signal XARB2. completed in response to the target layer reset signal When the target data signal SIG1 DSIG constituting the X2 DSIG. In response to the target reset complete signal first signal SIG1 is output by the transmitting unit Tx of the X3 DSIG, the DME sends the target reset signal SIG1 DSIG UFS physical layer UPL, the receiving unit Rx of the UFS constituting the first signal SIG1 to the transmitting unit Tx of 15 physical layer UPL receives the target data signal the UFS physical layer UPL, which transmits the target reset SIG1 DSIG as the second signal SIG2 constituting the host signal SIG1 DSIG. The receiving unit Rx of the UFS physi data signal SIG2 HSIG. The target data signal SIG1 DSIG cal layer UPL receives the target reset signal SIG1 DSIG received through the receiving unit RX of the UFS physical output from the transmitting unit Tx of the UFS physical layer layer UPL as host data signal SIG2 HSIG is transmitted to UPL as the host reset signal SIG2 HSIG constituting the the message control unit MCU. The message control unit second signal SIG2. MCU compares the target data signal SIG1 DSIG as the first When the generating of the first signal SIG1 and the receiv signal SIG1 and the host data signal SIG2 HSIG as the sec ing of the second signal SIG2 are normally performed, the ond signal SIG2 to test whether data provided by the memory initialization control unit ICU generates the test result TRST 25 device MDEV is normally transmittable to the host device showing that the reset operation is normally performed. HDEV. In FIG. 10, the target layer reset signal SIG1 DSIG is Referring to FIGS. 1, 12, and 14, the message control unit generated after the host reset signal SIG1 HSIG is generated, MCU of the test unit TU generates the first signal SIG1 as the although the order in which target layer reset signal host data signal SIG1 HSIG constituting the host signal SIG1 DSIG and the host reset signal SIG1 HSIG are gener 30 HSIG, in response to the first control signal XCON1. The first ated is not limited thereto. For example, the host reset signal control signal XCON1 is generated by the host control unit SIG1 HSIG may be generated after the target layer reset HCU activated by the first arbitration signal XARB1. As signal SIG1 DSIG is generated as shown in FIG. 11, the described above, since the host control unit HCU is realized in description of which is otherwise substantially the same as a command set of the host device HDEV, the host control unit the description of FIG. 10 and therefore will not be repeated. 35 HCU may generate the first control signal XCON1 that con Alternatively, the flow control unit FCU may control only the trols the message control unit MCU to generate the host signal target control unit TCU to perform the reset operation by HSIG. setting that the host layer reset operation by the host control When the host data signal SIG1 HSIG constituting the first unit HCU is completed. signal SIG1 is output through the transmitting unit Tx of the The host layer reset signals X1 HSIG and X2 HSIG and/ 40 UFS physical layer UPL, the receiving unit Rx of the UFS or the target layer reset signals X1 DSIG and X2 DSIG of physical layer UPL receives the host data signal SIG1 HSIG FIGS. 10 and 11 may be signals PA LM RESET req, DL L as the second signal SIG2 constituting target data signal M RESET req, PA LM RESET req, and T LM RESE SIG2 DSIG. The host data signal SIG1 HSIG received Treq, for example, requesting reset of the layerS L1.5 through through the receiving unit Rx of the UFS physical layer UPL L4 in the UFS protocol. The host reset complete signal 45 as the target data signal SIG2 DSIG is transmitted to the X3 HSIG and/or the target reset complete signal X3 DSIG message control unit MCU. The message control unit MCU transmitted from the layer L1.5 of FIGS. 10 and 11 may be compares the host data signal SIG1 HSIG constituting the signal PA LM RESET.cnf L, for example, in the UFS pro first signal SIG1 and the target data signal SIG2 DSIG con tocol notifying that the reset on the UFS protocol is com stituting the second signal SIG2 to test whether data provided pleted. Although not described with reference to FIGS. 10 50 by the host device HDEV is normally transmittable in the and 11, according to the UFS protocol, when the DME memory device MDEV. receives the signal PA LM RESET.cnf L, for example, it In the method of FIG. 13 or 14, when the generated first may transmit signal PA LM ENABLE LAYER.req signal SIG1 and the received second signal SIG2 are identi requesting activation of each layer to the layer L1.5. Upon cal, the test result TRST about the data transmission and receiving the signal PA LM ENABLE LAYER.req, the 55 reception of the UFS physical layer UPL and the UFS link layer L1.5 may transmit signal PA LM ENABLE LAYER. layer ULL is generated as being Successful. cnf L notifying activation to the DME. The link start-up The test unit TU described above may include the initial operation described above with reference to FIG. 8, for ization control unit ICU as shown in FIG. 9, or the message example, may be performed after the DME receives the signal control unit MUC as shown in FIG. 12, but the test unit TU is PA LM ENABLE LAYER.cnf L. 60 not limited thereto. In other words, as shown in FIG. 15, the FIG. 12 is a functional block diagram of the test unit TU of test unit TU may include both the initialization control unit FIGS. 6 and 7, according to an embodiment of the inventive ICU and the message control unit MCU. If the test unit TU concept. The test unit TU further includes an message control includes both the initialization control unit ICU and the mes unit MCU for testing a data transmission and reception opera sage control unit MCU, the initialization control unit ICU tion, along with the host control unit HCU and the target 65 may perform the reset operation of FIG. 10 or 11 before the control unit TCU. FIGS. 13 and 14 are signal flow diagrams link start-up operation of FIG. 8 is performed, and the mes for describing methods of testing data transmission and sage control unit MCU may perform the message transmis US 9,026,854 B2 17 18 sion and reception operation of FIG. 13 or 14 after the link (RTT) received through the UFS link layer ULL, and generate start-up operation of FIG. 8 has ended, for example. the first signal SIG1 constituting the host signal HSIG with FIG.16 is a functional block diagram of the memory device data divided by sizes according to data reception units, for MDEV, according to another embodiment of the inventive example. The host control unit HCU and the target control concept. 5 unit TCU are enabled under control of the flow control unit Referring to FIG. 16, the memory device MDEV further FCU, using the first and second arbitration signals XARB1 includes a UFS translator layer UTL, e.g., as compared to the and XARB2, respectively, as described above. memory device MDEV of FIG. 1. FIG. 17 is a signal flow The memory device MDEV of FIG. 16 may test whether diagram for describing a method of utilizing the UFS trans the reset operation, the lane control operation, and/or the lator layer UTL of FIG. 16, according to an embodiment of 10 message transmission and reception operation are performed the inventive concept. normally through the UFS link layer ULL and the UFS physi Generally, the UFS translator layer UTL may receive the cal layer UPL, as discussed above. The memory device first signal SIG1 constituting the target signal DSIG from the MDEV of FIG. 16 also may test whether the lane control target control unit TCU of the test unit TU, add predetermined operation and/or the data transmission and reception opera information to the first signal SIG1, and then transmit the first 15 tion is performed normally through the UFS translator layer signal SIG1 with the predetermined information to the UFS UTL. FIGS. 18 and 19 are signal flow diagrams for describing link layer ULL. The UFS translator layer UTL may also the lane control operation and the data transmission and receive the second signal SIG2 constituting the target signal reception operation, respectively, utilizing the UFS translator DSIG from the UFS link layer ULL, analyze information layer UTL of FIG. 16, according to embodiments of the included in the second signal SIG2 constituting the target inventive concept. signal DSIG, and transmit the analyzed information and/or The lane control operation and the data transmission and the second signal SIG2 to the target control unit TCU of the reception operation in the memory device MDEV of FIG. 16 test unit TU. are respectively identical to those of FIGS. 8, 13 and 14, For example, referring to FIGS. 16 and 17, the host control except that the first and second signals SIG1 and SIG2 con unit HCU generates and sends first signal SIG1 HSIG(CMD) 25 stituting the target signal DSIG are also used for a conversion as the host signal HSIG, in response to first arbitration signal process through the UFS translator layer UTL, as shown in XARB1 in the host mode. The first signal SIG1 HSIG(CMD) FIGS. 18 and 19, for example. In other words, the first signal is looped back to the target control unit TCU through the UFS SIG1 constituting the target signal DSIG in FIG. 18 (e.g., physical layer UPL, the loop-back line LBL, the UFS link SIG1 Y1. DSIG, SIG1 Y3 DSIG, SIG1 Y5 DSIG), indi layer ULL and the UFS translation layer UTL. That is, the 30 cating the lane control operation in the memory device first signal SIG1 HSIG(CMD) generated as the host signal MDEV of FIG. 16, is transmitted to the UFS link layer ULL HSIG is received as a second signal SIG2 DSIG(CMD) con through the UFS translator layer UTL, and the second signal stituting the target signal DSIG by the receiving unit Rx of the SIG2 constituting the target signal DSIG (e.g., UFS physical layer UPL, and sent to the target control unit SIG2 Y2 DSIG, SIG2 Y4 DSIG) is transmitted to the test TCU through the UFS link layer ULL and the UFS translation 35 unit TU through the UFS link layer ULL and the UFS trans layer UTL. The first signal SIG1 HSIG(CMD) may have a lator layer UTL. Effectively the same process is applied to header that may include information about an OP code, data FIG. 19 showing a data transmission and reception operation size to be written, or the like, by the host control unit HCU, for in the memory device MDEV of FIG. 16, similar to that of example. In this case, the UFS translator layer UTL may FIG. 14, although the second signal SIG2 constituting the retrieve and decode the header information from the second 40 target signal DSIG (e.g., SIG2 DSIG) is transmitted to the signal SIG2 DISG(CMD) constituting the target signal DIG message control unit MCU of the test unit TU through the received from the UFS link layer ULL. The UFS translator UFS link layer ULL and the UFS translator layer UTL. Fur layer UTL transmits the decoded information and/or the sec ther details thereof will not be repeated herein. ond signal SIG2 DSIG(CMD) to the target control unit TCU. FIG. 20 is a functional block diagram of the test unit TU of Meanwhile, the target control unit TCU also receives the 45 FIG. 15 combined with the UFS translator layer UTL of FIG. second arbitration signal XARB2 from the flow control unit 16, according to an embodiment of the inventive concept. FCU. The target control unit TCU transmits the first signal Referring to FIG. 20, the test unit TU includes the flow SIG1 DSIG constituting the target signal DSIG to the UFS control unit FCU, the target control unit TCU, the host control translator layer UTL in response to the second signal unit HCU, the initialization control unit ICU, and the message SIG2 DSIG(CMD) constituting the target signal DSIG. As 50 control unit MCU. Operations of the flow control unit FCU, mentioned above, when the second signal SIG2 DSIG the target control unit TCU, the host control unit HCU, the (CMD) is a write command, for example, the UFS translator initialization control unit ICU, and the message control unit layer UTL may add information RTT about a data reception MCU of FIG. 20 are identical to those of FIG. 15. However, unit corresponding to the write command of the first signal the first signal SIG1 generated by the target control unit TCU, SIG1 DSIG constituting the target signal DSIG to the header. 55 the host control unit HCU, and the message control unit MCU The UFS translator layer UTL transmits a first signal of FIG. 20, and the second signal SIG2 received by the target SIG1 DSIG(RTT), including the information RTT, to the control unit TCU, the host control unit HCU, and the message UFS link layer ULL. The first signal SIG1 DSIG(RTT) is control unit MCU of FIG. 20, may be converted by the UFS looped back to the host control unit HCU through the UFS translator layer UTL. Illustrative converting operations by the physical layer UPL, the loop-back line LBL, and the UFS link 60 UFS translator layer UTL are described above. In FIG. 20, layer ULL as a second signal SIG2 HSIG(RTT). Accord connections between the first and second signals SIG1 and ingly, the first signal SIG1 DSIG generated as the target SIG2 of the host control unit HCU and the UFS translator signal DSIG is received as the second signal SIG2 HSIG layer UTL are not illustrated due to difficulty in illustration. (RTT) constituting the host signal HSIG by the receiving unit Notably, since a signal used to test the reset operation by Rx of the UFS physical layer UPL. 65 the initialization control unit ICU is not required to be con Although not shown in FIG. 17, the host control unit HCU verted by the UFS translator layer UTL, the first signal SIG1 may analyze the header of the second signal SIG2 HSIG generated by the initialization control unit ICU and the sec US 9,026,854 B2 19 20 ond signal SIG2 transmitted to the initialization control unit system SSYS may include a server for processing a request ICU may be transmitted to or received from the UFS link received from the terminals TEM1 through TEMn, and the layer ULL, instead of the UFS translator layer UTL. SSD for storing data corresponding to the request received According to a memory device according to the embodi from the terminalsTEM1 through TEMn. The SSD of FIG.23 ments of the inventive concept, production costs may be may be the SSD of FIG. 5, for example. In other words, the reduced since tests can be performed on reset operation, a SSD of FIG. 23 includes the SSD controller SCTL and the lane control operation, and a message transmission and recep memory MEM, and the SSD controller SCTL or the memory tion operation without having to use an expensive test device. MEM may include the test unit TU according to an embodi Also, according to the memory device, a test can still be ment of the inventive concept. Accordingly, using the server performed even when a newly defined standard is applied. 10 system SSYS of the network system NSYS of FIG. 23, a test FIG. 21 is a block diagram of a memory card MCRD, for communication with a host device may be performed at according to an embodiment of the inventive concept. low cost or by quickly adapting to changing technologies. The memory device MDEV may be realized as the memory Terminologies used herein are for descriptive purposes card MCRD of FIG. 21. The memory card MCRD includes a only, and are not used to limit meanings or ranges of claims. memory controller Ctrl and a memory MEM. The memory 15 For example, the initialization control unit ICU and the mes controller Ctrl writes data in or reads data from the memory sage control unit MCU are shown to be controlled by the host MEM in response to a request of an external host (not shown) control unit HCU or the target control unit TCU, but embodi received through an input/output unit I/O. Also, when the ments are not limited thereto. In other words, the initialization memory MEM of FIG. 21 is a flash memory device, as shown control unit ICU and the message control unit MCU of the in the illustrative embodiment, the memory controller Ctrl memory device MDEV may independently perform the reset may control erase operations of the memory MEM. In order operation and the message transmission and reception opera to perform Such control operations, the memory controller tion, respectively, without being controlled by the host con Ctrl of the memory card MCRD may include interface units trol unit HCU or the target control unit TCU. Here, the ini (not shown) respectively interfacing with the external host tialization control unit ICU and the message control unit and a memory device, and a RAM. According to the memory 25 MCU may each include a host command set or a target com card MCRD, a test for communication with the host device mand set. may be performed at a low cost or by quickly adapting to While the inventive concept has been particularly shown changing technologies. and described with reference to exemplary embodiments The memory card MCRD of FIG. 21 may be realized as a thereof, it will be understood that various changes inform and compact flash card (CFC), a microdrive, a Smart media card 30 details may be made therein without departing from the spirit (SMC), a multimedia card (MMC), a security digital card and scope of the following claims. (SDC), a memory stick, or a USB flash memory drive, for What is claimed: example. 1. A method of performing a self-test on a memory device FIG. 22 is a block diagram of a computing system device in a test mode, the memory device comprising a memory CSYS, according to an embodiment of the inventive concept. 35 controller coupled to a flash memory, the memory controller Referring to FIG. 22, the computing system device CSYS including a host interface, the method comprising: includes a processor CPU, a user interface UI, and a memory generating a first signal; device MDEV, which are electrically connected to abus BUS. sending the first signal from a test unit of the host interface The memory device MDEV includes a memory controller through a universal flash storage (UFS) link layer of the Ctrl and a memory MEM. N-bit data (where N is an integer 40 host interface to a transmitting unit in a UFS physical greater than or equal to 1) processed or to be processed by the layer of the host interface to be transmitted to a receiving processor CPU is stored in the memory MEM through the unit in the UFS physical layer; memory controller Ctrl. Also, the memory device MDEV. receiving a second signal at the test unit from the receiving included in the computing system device CSYS of FIG. 22. unit in the UFS physical layer through the UFS link may be a memory device MDEV as described above. Accord 45 layer, the second signal being the first signal received by ingly, the computing system device CSYS of FIG. 22 may the receiving unit; and perform a test for communication with the memory device testing an operation performed by at least one of the UFS MDEV at lost cost or by quickly adapting to changing tech physical layer and the UFS link layer based on the first nologies. signal and the second signal. The computing system device CSYS may further include a 50 2. The method of claim 1, further comprising: power supply device PS. Also, if the memory MEM is a flash generating a test result signal in response to receiving the memory, the computing system device CSYS may further second signal, the test result signal indicating whether include a volatile memory device, such as RAM. the operation has been performed normally by the at When the computing system device CSYS is a mobile least one of the UFS physical layer and the UFS link device, the computing system device CSYS may further 55 layer. include a battery and a modem Such as a baseband chipset for 3. The method of claim 1, further comprising: Supplying an operation Voltage. Also, the computing system determining one of a host mode and a target mode for device CSYS may further include an application chipset, a generating the first signal and receiving the second sig camera image processor (CIS), a mobile DRAM, or the like, nal, wherein the test unit operates as a host device exter although details thereof are not included as this would be 60 nal to the memory device in the host mode, and the test apparent to one of ordinary skill in the art. unit operates as the memory device in the target mode. FIG. 23 is a block diagram of a network system NSYS 4. The method of claim 3, wherein determining one of the including a server system SSYS including an SSD, according host mode and the target mode comprises: to an embodiment of the inventive concept. receiving a mode control signal at the test unit indicating Referring to FIG. 23, the network system NSYS may 65 one of the host mode and the target mode; include the server systemSSYS and terminals TEM1 through generating a first arbitration signal in response to the mode TEMn, which are connected through a network. The server control signal indicating the host mode, and at least one US 9,026,854 B2 21 22 of generating the first signal and receiving the second unit in response to a second control signal from the target signal at a host control unit in the host mode in response control unit, the DME sending target layer reset signals to the first arbitration signal; and to the plurality of layers of the UFS link layer to perform generating a second arbitration signal in response to the the reset operation and receiving a target reset complete mode control signal indicating the target mode, and at signal; least one of generating the first signal and receiving the sending the target reset signal constituting the first signal to second signalata target control unit in the target mode in the transmitting unit of the UFS physical layer to be response to the second arbitration signal. transmitted to the receiving unit in response to the target 5. The method of claim 4, wherein the operation comprises reset complete signal; and at least one of a reset operation for initializing the UFS link 10 receiving the target reset signal as the second signal at the layer and the UFS physical layer, a lane control operation for initialization control unit from the receiving unit in the providing a lane between the UFS physical layer and the host UFS physical layer. device, or a message transmission and reception operation for 11. The method of claim 5, whereintesting performance of transmitting and receiving data by the UFS link layer and the the message transmission and reception operation comprises: UFS physical layer. 15 generating and sending the first signal as a target data 6. The method of claim 5, wherein testing performance of signal from a message control unit to the transmitting the lane control operation comprises: unit of the UFS physical layer, via the UFS link layer, to generating and sending the first signal as a lane discovery be transmitted by the transmitting unit in the UFS physi standby notice signal in the target mode; cal layer in response to a second control signal from the receiving the second signal as the lane discovery standby target control unit; notice signal in the host mode to perform discovery of receiving the target data signal as the second signal at the the lane; and message control unit from the receiving unit in the UFS generating and sending the first signal as a lane discovery physical layer, and complete signal in the host mode. comparing the second signal and the first signal to test 7. The method of claim 6, wherein testing performance of 25 whether data provided by the memory device is nor the lane control operation further comprises: mally transmittable to the host device. generating and sending the first signal as a lane realign 12. The method of claim 5, whereintesting performance of ment standby notice signal in the target mode in the message transmission and reception operation comprises: response to the lane discovery complete signal; and generating and sending the first signal as a host data signal receiving the second signal as the lane realignment standby 30 from a message control unit to the transmitting unit of notice signal in the host mode to perform lane realign the UFS physical layer, via the UFS link layer, to be ment; and transmitted by the transmitting unit in the UFS physical generating and sending the first signal as a lane realign layer in response to a first control signal from the host ment complete signal in the host mode. control unit; 8. The method of claim 7, wherein testing performance of 35 receiving the host data signal as the second signal at the the lane control operation further comprises: message control unit from the receiving unit in the UFS generating and sending the first signal as a lane termination physical layer, and standby notice signal in the target mode in response to comparing the second signal and the first signal to test the lane realignment complete signal; and whether data provided by the host device is normally receiving the second signal as the lane termination standby 40 transmittable in the memory device. notice signal in the host mode to perform the lane ter 13. The method of claim 4, wherein the first signal sent mination, from the test unit is received by a UFS translator layer, which wherein the performance of the lane control operation is adds predetermined information relating to the first signal to determined to in accordance with UFS protocol when a header of the first signal. the generating of the first signal and the receiving of the 45 14. The method of claim 4, wherein predetermined infor second signal are sequentially performed. mation relating to the second signal, included in a header of 9. The method of claim 5, wherein testing performance of the second signal, is decoded by a UFS translator layer, the the reset operation comprises: method further comprising: generating and sending the first signal as a host reset signal receiving the decoded predetermined information at the to a device management entity (DME) of the UFS link 50 test unit from the UFS translator layer. layer in the host mode via an initialization control unit in 15. A memory device having self-test capability in a test response to a first control signal from the host control mode, the memory device comprising: unit, the DME sending host layer reset signals to a plu a flash memory; and rality of layers of the UFS link layer to perform the reset a memory controller configured to control the flash operation and receiving a host reset complete signal; 55 memory and including abus and a hostinterface coupled sending the host reset signal constituting the first signal to to the bus; the transmitting unit of the UFS physical layer to be wherein the host interface comprises: transmitted to the receiving unit in response to the host a universal flash storage (UFS) physical layer including a reset complete signal; and transmitting unit configured to output a first signal and a receiving the host reset signal as the second signal at the 60 receiving unit configured to receive the first signal via a initialization control unit from the receiving unit in the loop-back line (LBL) as a second signal, according to UFS physical layer. UFS protocol; 10. The method of claim 5, wherein testing performance of a UFS link layer configured to pass the first signal to the the reset operation comprises: transmitting unit and to pass the second signal from the generating and sending the first signal as a target reset 65 receiving unit, according to the UFS protocol; and signal to a device management entity (DME) of the UFS a test unit, operatively coupled between the bus and the link layer in the target mode via an initialization control UFS link layer, configured to test whether the UFS US 9,026,854 B2 23 24 physical layer and the UFS link layer normally operate accordance with the UFS protocol based on at least one according to the UFS protocol by generating and trans of the first signal and the second signal. mitting the first signal to the UFS link layer and receiv 22. The memory device of claim 17, wherein the test opera ing the second signal from the UFS link layer. tion unit further comprises: 16. The memory device of claim 15, wherein the test unit a message control unit for testing whether the UFS physi comprises: cal layer and the UFS link layer transmit and receive data a flow control unit configured to receive a test mode signal in accordance with UFS protocol by performing a mes indicating one of a host mode or a target mode, and to Sage transmission and reception operation. generate a first arbitration signal in the host mode and a 23. The memory device of claim 22, wherein the message second arbitration signal in the target mode in response 10 to the test mode signal; and control unit is configured to generate and send the first signal a test operation unit configured to receive the first and as a target data signal to the transmitting unit of the UFS second arbitration signals from the flow control unit, to physical layer, via the UFS link layer, to be transmitted to the at least one of generate the first signal and receive the receiving unit in response to a second control signal from the second signal in the host mode in response to the first 15 target control unit, to receive the target data signal as the arbitration signal, and to at least one of generate the first second signal from the receiving unit in the UFS physical signal and receive the second signal in the target mode in layer, and to compare the second signal and the first signal to response to the second arbitration signal. test whether data provided by the memory device is transmit 17. The memory device of claim 16, wherein the test opera table to the host device in accordance with UFS protocol. tion unit comprises: 24. The memory device of claim 22, wherein the message a host control unit activated in response to the first arbitra control unit is configured to generate and send the first signal tion signal, and configured to generate the first signal as as a host data signal to the transmitting unit of the UFS a host signal and to receive the second signal as the host physical layer, via the UFS link layer, to be transmitted to the signal in the host mode; and receiving unit in response to a first control signal from the a target control unit activated in response to the second 25 host control unit, to receive the host data signal as the second arbitration signal, and configured to generate the first signal from the receiving unit in the UFS physical layer, and signal as a target signal and to receive the second signal to compare the second signal and the first signal to test as the target signal in the target mode. whether data provided by the host device is normally trans 18. The memory device of claim 16, wherein the flow mittable in the memory device in accordance with the UFS control unit comprises a state machine. 30 protocol. 19. The memory device of claim 17, wherein the test opera 25. The memory device of claim 17, wherein the memory tion unit further comprises: device further comprises: an initialization control unit for testing whether the UFS a UFS translator layer configured to receive the first signal link layer operates in accordance with UFS protocol from the target control unit, to add predetermined infor during a reset operation. 35 mation relating to the first signal to a header of the first 20. The memory device of claim 19, wherein the initializa signal, and to transmit the first signal to the UFS link tion control unit is configured to generate and send the first layer. signal as a host reset signal to a device management entity 26. The memory device of claim 25, wherein the UFS (DME) of the UFS link layer in the host mode in response to translator layer is further configured to receive the second a first control signal from the host control unit, 40 signal from the UFS link layer, to decode predetermined wherein the DME is configured to send host layer reset information relating to the second signal included in a header signals to a plurality of layers of the UFS link layer to of the second signal, and to transmitat least one of the second perform the reset operation and to receive a host reset signal and the decoded predetermined information to the complete signal, and further to send the host reset signal target control unit. constituting the first signal to the transmitting unit of the 45 27. A memory device having self-test capability, the UFS physical layer to be transmitted to the receiving unit memory device comprising a flash memory and a memory in response to the host reset complete signal, and controller controlling the flash memory, the memory control wherein the initialization control unit is further configured ler including a bus and a host interface coupled to the bus, the to receive the host reset signal as the second signal from host interface comprising: the receiving unit in the UFS physical layer. 50 a universal flash storage (UFS) physical layer including a 21. The memory device of claim 20, wherein the initializa transmitting unit configured to output a first signal and a tion control unit is further configured to generate and send the receiving unit configured to receive the first signal via a first signal as a target reset signal to the DME in the target loop-back line (LBL) as a second signal; mode in response to a second control signal from the target a UFS translator layer for at least one of adding predeter control unit, 55 mined information relating to the first signal to a header wherein the DME is configured to send target layer reset of the first signal, and detecting predetermined informa signals to the plurality of layers of the UFS link layer to tion relating to the second signal in a header of the perform the reset operation and to receive a target reset Second signal; complete signal, and further to send the target reset a UFS link layer configured to pass the first signal from the signal constituting the first signal to the transmitting unit 60 UFS translator layer to the transmitting unit in the UFS of the UFS physical layer to be transmitted to the receiv physical layer and to pass the second signal from the ing unit in response to the target reset complete signal, receiving unit in the UFS physical layer to the UFS and translator layer, and wherein the initialization control unit is further configured a test unit configured to test whether the UFS physical layer to receive the target reset signal as the second signal 65 and the UFS link layer normally operate according to from the receiving unit in the UFS physical layer, and to UFS protocol by generating and transmitting the first determine whether the reset operation is performed in signal to the UFS translator layer and receiving the sec US 9,026,854 B2 25 26 ond signal and the detected predetermined information a flow control unit configured to receive a test mode signal relating to the second signal from the UFS translator indicating one of a host mode or a target mode for a layer. testing an operation of the memory device, and to gen 28. The memory device of claim 27, wherein the test unit erate a first arbitration signal in the host mode and a further comprises: second arbitration signal in the target mode in response a message control unit for testing whether the UFS physi to the test mode signal, wherein the test unit operates as cal layer and the UFS link layer normally transmit and a host device external to the memory device in the host receive data by performing a message transmission and mode and operates as the memory device in the target reception operation, wherein the message control unit is mode; configured to compare the second signal and the first 10 a host control unit for at least one of generating the first signal to test at least one of whether data provided by the signal as a host signal and receiving the second signal as memory device is normally transmittable to a host the host signal in the host mode, in response to the first device or data provided by the host device is normally arbitration signal; and transmittable in the memory device. a target control unit for at least one of generating the first 29. The memory device of claim 28, wherein the test unit 15 signal as a target signal and receiving the second signal further comprises: as the target signal in the target mode, in response to the an initialization control unit for testing whether the UFS second arbitration signal. link layer normally operates during a reset operation, wherein the test unit is configured to transmit the first wherein the initialization control unit is configured to signal to the UFS link layer in one of the host mode and generate and send the first signal as one of a host reset the target mode, and to receive the second signal from signal or a target reset signal to a device management the UFS link layer in one of the host mode and the target entity (DME) of the UFS link layer, wherein the DME is mode, the UFS link layer passing the first and second configured to perform the reset operation in response signals between the test unit and the UFS physical layer, and to send the one of the host reset signal and the target to test whether the UFS link layer and the UFS physical reset signal constituting the first signal to the transmit 25 layer normally operate according to UFS protocol based ting unit of the UFS physical layer to be transmitted to on the first and second signals. the receiving unit, and 31. The test unit of claim 30, wherein the tested operation wherein the initialization control unit is further configured comprises at least one of a reset operation for initializing the to receive the one of the host reset signal and the target UFS link layer and the UFS physical layer, a lane control reset signal as the second signal from the receiving unit 30 operation for providing a lane between the UFS physical layer in the UFS physical layer. and the host device, or a message transmission and reception 30. A test unit included in a host interface of a memory operation for transmitting and receiving data by the UFS link controller coupled to a flash memory, the test unit coupled a layer and the UFS physical layer. bus of the memory controller and to a universal flash storage 32. The test unit of claim 30, wherein the flow control unit (UFS) link layer and a UFS physical layer of the host inter 35 is further configured to generate a test result signal based on face, the UFS physical layer including a transmitting unit whether the generating of the first signal and the receiving of configured to output a first signal and a receiving unit config the second signal by at least one of the host control unit and ured to receive the first signal via a loop-back line (LBL) as a the target control unit are performed. Second signal, the test unit comprising: