UFS Tutorial

UFS Tutorial Presented by Scott Jacobson Harish Verma Flash Memory Summit 2013 Santa Clara, CA 1 UFS – Universal Flash Storage Overview . JEDEC UFS Roadmap . What are the drivers? . What is UFS? . Why is UFS important? . What are the details? UFS Jedec Roadmap The Mobile Revolution – A Golden Age for Consumers Cell Phones Used By Smartphones Used By 1 of 1,000 Business People 600 Million People Worldwide 1984 2012 Mobile Mobile Telephone Computer smaller, simpler, cheaper mightier But the Golden Age has Rocked the Ecosystem 1984 http://dealbook.nytimes.com/2011/08/15/google-to-buy-motorola-mobility/ http://money.cnn.com/2012/04/24/technology/apple-earnings/index.htm http://www.splatf.com/2011/12/rim-charts/ What’s Enabled the Mobile Revolution? Many New Mobile Protocols New protocols enable advancement and drive need for advanced verification IP Memory card < 3 years old FM NAND CSI2 Camera > 3 years old DRAM NAND receiver LPDDR Flash CSI3 interface FLASH UFS SD 3.0 SD 4.0 SD GPS 4.5 Touch screen receiver I2C UFS controller LPDDR 2 LPDDR 3 RFFE eMMC Display Multimedia Cellular Applications driver modem DigRF processor processor DSI ® ™ AMBA 4 ACE OCP 2.0 ™ ™ LLI AMBA AXI , AHB OCP 3.0 SSIC WiFi Audio SDIO3 interface SLIMbus SLIMbus Bluetooth Motion GBT sensors cJTAG SPMI USB 3.0 OTG Power USB 2.0 HDMI 1.4 control Full Product Verification Each development stage has unique VIP requirements System Level (HW+SW) SoC Level ARM CPU Subsystem Customer’s Application Specific Components A15 A15 A7 A7 AES 3D DSP L2 cache L2 cache Graphics Application A/V Accelerators … Core IP Level … Cache Coherent Fabric LPDDR3 Controller Fully pipelined SoC Interconnect Fabric AHB Command BIST Low Power Queue UAR OCP GPIO Ethe HDMI T 2-Stage PCIe LPDDR 3Transaction USB3.0 r Display INTC Ordering Gen 2,3 SATA DEN Engine Processing net MIPI PMU I2C 3 2 Arbitration P P MIPI SPI Write Queue PHY PHY PHY WLAN AXI4 LookH-aheadH Low-speed peripheral JTAG Timer Priority optimizationY Y LTE subsystem Engine Read Queue AXI High speed, wired interface peripherals Other peripherals Low speed peripherals ECC DIMM “Our SATA controller has to talk IP Verificationwith my competitor's Challenges chip. They Customer feedbackdeviate from the spec but I still “My 3rd party SLIMbus IP have to make it work. I need to make sure my chip will handle was shipping in silicon, but non-compliance gracefully.” it still had bugs. My application was different - Leading Hard Drive Company than the others. I wish I had done my own “The UFS spec is compliance checking.” IP Component not fully baked, but if we delay development we’ll - Cellular SoC Provider Fully pipelined be late to market. AHB I need early Command BIST Low Power access to OCP Queue memory models “Moving from SATA 3G 2-Stage and rapid to SATA 6G cost me 2 Ordering Transaction incorporation of Engine Processing spec updates.” engineers for 6 months DEN to develop the VIP. Arbitration - Mobile Device Write Queue Protocol expertise is an AXI4 Look-ahead OEM expensive commodity.” Priority optimization Engine Read Queue AXI - Storage Chipset Leader ECC DIMM “I’m developing a USB3 device. We know there “Our IP blocks connect via an OCP fabric. The verification will be a number of team is short handed so the designers need to catch bugs. I need stable VIP some of their own bugs. The assertion-based VIP we use that works. I can’t really helps with that. The designers run a quick formal afford to debug that analysis to verify compliance. That speeds up our overall too.” verification.” - Mobile SoC leader - Leading DSP Company “The protocol interfaces are only half SoC Verification theChallenges problem. My memory interfaces are just as complex. I need to make Customer feedback sure they will work, regardless of the “My chip is big. Simulation is orders of memory vendor my customer uses.” magnitude too slow for functional coverage collection. The best I can do is run toggle tests.” - Major Server Developer - Network SoC Leader “The IP blocks are “My SoC has a multi- ARM CPU Subsystem Customer’s Application Specific Components all tested. I need to core CPU, but so does A15 A15 A7 A7 verify the my competitor’s. We AES interactions between 3D can’t beat their DSP L2 cache L2 cache Graphics Application bocks. There are 8 performance with SW- A/V Accelerators … Core major interfaces that based cache … need to be tested coherency. We need to Cache Coherent Fabric manage coherency in together. If I’m HW. We need VIP that missing VIP for any understands this.” 1 of those, I’m toast.” SoC Interconnect Fabric - Mobile Chipset - Networking Leader supplier UAR GPIO Ethe HDMI T PCIe LPDDR3 USB3.0 r Display INTC Gen 2,3 SATA net “The SoC verification MIPI PMU I2C“We use a mix of 3 2 simulators, partly for P P MIPI SPI environment is built byPHY PHY PHY WLAN H H Low-speed peripheralhistorical reasons an contributions from our JTAG Timer worldwide teams and Y Y LTE subsystem partly to optimize our sometimes from partner expenditures. We need to High speed, wired interface peripherals“Believe me,Other I’d peripheralslove to use VIPLow speed peripheralsbe able to utilize all our companies. As a result, the for all my interfaces, but the cost testbench often employs a simulation resources.” is way too high. Get real! I need mix of verification languages licensing that matches the needs and methodologies. That’s - Communications Chipset of SoC verification.” Company just reality.” - Server SoC Start-up - Global Semi Provider The System Verification Problem Customer feedback “The hardware in my product is state of the art, but the software is what the customer sees. If it “We do it all the analysis we doesn't work flawlessly with the can - system modeling, RTL hardware, we’ll drop market simulation, simulation share – fast.” acceleration, emulation, and prototyping. Each fills a need, but each is incomplete by - Mobile Device Company itself.” - Global Telecomm Co. “The hardest bugs to find are the HW/SW corner cases. We spent “Early HW/SW integration 3 months in the lab to is a must. In the past it get rid of 2 bugs on one was a serial process that baseband processor. cost us 2 quarters in time During that time we lost to market.” the customer.” - Baseband SoC - Applications Processor Provider Leader UFS overview • What is UFS? – Next generation flash storage that provides the low power of eMMC with the high performance of SCSI SSD – JEDEC Standard JEDS220 UFS overview • What is UFS? – Built on MIPI interface standards, M-PHY and UniPro, for interconnect layer – For UFS, UniPro stack treated as a black box to maximum extent UFS overview • What is UFS? – Two form factors – Embedded SSD – SD Card UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements – Higher computing demands – Dual Core – Multi Core UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements – Higher Storage Capacity UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements – Higher Storage Capacity UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements – Lower Latency and High IOPS UFS overview • Why Is UFS Important? – Mobile Device demands are driving new requirements – Higher Bandwidth & High IOPS UFS overview • What are the details? UFS overview • What are the details? UFS overview • What are the details? – Specified as Application layer on Unipro Protocol Stack – Multiple Layers – UCS layer – Uses SBC and SPC commands – UTP layer based on SCSI Architecture Model (SAM-5). – Command queuing – Multi-thread operations – UIC layer based on MIPI standard protocols – Interface and DME layers using MIPI Unipro protocol – Physical layer based on MIPI M-PHY .

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