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United States Patent ( 10 ) Patent No.: US 10,629,695 B2 Tsai Et Al

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United States Patent ( 10 ) Patent No.: US 10,629,695 B2 Tsai Et Al US010629695B2 United States Patent ( 10 ) Patent No.: US 10,629,695 B2 Tsai et al. (45 ) Date of Patent : Apr. 21 , 2020 (54 ) SEMICONDUCTOR DEVICE AND METHOD (52 ) U.S. CI. FOR FABRICATING THE SAME CPC HOIL 29/516 (2013.01 ) ; HOLL 21/02181 ( 2013.01 ) ; HOIL 21/02189 ( 2013.01 ) ; ( 71) Applicant: UNITED MICROELECTRONICS (Continued ) CORP . , Hsin - Chu ( TW ) ( 58 ) Field of Classification Search CPC HO1L 29/516 ; HO1L 21/02189 ; HOIL ( 72 ) Inventors: Shih -Hung Tsai, Tainan ( TW ) ; 21/02181; HO1L 29/4966 ; HOLL Po -Kuang Hsieh , Kaohsiung ( TW ) ; 21/28167 ; Yu - Ting Tseng , Tainan ( TW ) ; Cheng - Ping Kuo , Pingtung County (Continued ) ( TW ) ; Kuan -Hao Tseng , Kaohsiung (56 ) References Cited (TW ) U.S. PATENT DOCUMENTS (73 ) Assignee : UNITED MICROELECTRONICS 8,785,995 B2 7/2014 Dubourdieu et al . CORP ., Hsin - Chu ( TW ) 9,196,696 B2 11/2015 Xie ( * ) Notice : Subject to any disclaimer, the term of this (Continued ) patent is extended or adjusted under 35 U.S.C. 154 ( b ) by 0 days . FOREIGN PATENT DOCUMENTS ( 21) Appl. No .: 16 /239,541 CN 100550391 C 10/2009 (22 ) Filed : Jan. 4 , 2019 OTHER PUBLICATIONS Li, Title : Sub -60mV - Swing Negative -Capacitance FinFET without (65 ) Prior Publication Data Hysteresis , IEEE 2015 . US 2019/0140068 A1 May 9 , 2019 (Continued ) Primary Examiner — Victor A Mandala Related U.S. Application Data (74 ) Attorney, Agent, or Firm Winston Hsu (63 ) Continuation of application No. 15 /678,125 , filed on Aug. 16 , 2017 , now Pat . No. 10,211,313 . (57 ) ABSTRACT A semiconductor device includes a metal gate on a substrate , (30 ) Foreign Application Priority Data a polysilicon layer on the metal gate , a hard mask on the polysilicon layer , and a source /drain region adjacent to two Jul. 17 , 2017 ( TW ) 106123732 A sides of the metal gate . Preferably , the metal gate includes a ferroelectric (FE ) layer on the substrate, a work function (51 ) Int. Ci. metal layer on the FE layer , and a low resistance metal layer HOIL 29/51 (2006.01 ) HOIL 21/28 (2006.01 ) on the work function metal layer . (Continued ) 9 Claims, 6 Drawing Sheets 56 38 42 52 26 22 32 28 46 32 44 30 24 14 24 12 36 US 10,629,695 B2 Page 2 (51 ) Int. Ci. 9,779,997 B2 10/2017 Li HOIL 21/02 ( 2006.01 ) 9,793,397 B1 10/2017 Ando HOIL 29/40 9,831,244 B2 11/2017 Kim ( 2006.01 ) 2008/0085591 A1 * 4/2008 Gomez HOIL 29/1066 HOIL 29/66 ( 2006.01 ) 438/585 HOIL 29/49 ( 2006.01 ) 2008/0128796 A1 * 6/2008 Zhu HOIL 21/845 HOIL 29/78 ( 2006.01 ) 257/328 (52 ) U.S. CI. 2013/0270619 A1 * 10/2013 Schloesser HO1L 29/516 CPC .. HOIL 21/02194 (2013.01 ) ; HOIL 21/02356 257/295 (2013.01 ) ; HOIL 21/28167 ( 2013.01 ) ; HOIL 2013/0330899 Al 12/2013 Bu 21/28255 ( 2013.01 ) ; HOIL 29/408 ( 2013.01) ; 2015/0214322 A1 7/2015 Mueller 2016/0111549 A1 * 4/2016 Baars HO1L 29/78391 HOIL 29/4966 ( 2013.01 ) ; HOIL 29/66545 257/295 ( 2013.01 ) ; HOIL 29/66795 ( 2013.01) ; HOIL 2016/0155748 A1 * 6/2016 Li HOIL 29/66545 29/785 (2013.01 ) 257/295 ( 58 ) Field of Classification Search 2016/0163808 Al 6/2016 Cheng CPC HOLL 21/02356 ; HO1L 29/66545 ; HOIL 29/66795 ; HO1L 29/408 ; HO1L 21/02194 ; HO1L 21/28255 ; HO1L 29/785 OTHER PUBLICATIONS See application file for complete search history . Shih -Cheng Chen , Title of Invention : Semiconductor Device, U.S. Appl. No. 15 /206,319 , filed Jul. 11 , 2016 . (56 ) References Cited Kung- Hong Lee, Title of Invention : Multi- Threshold Voltage Semi U.S. PATENT DOCUMENTS conductor Device , U.S. Appl. No. 15/ 391,822 , filed Dec. 27 , 2016 . 9,362,283 B2 6/2016 Hong 9,379,242 B1 6/2016 Lin et al. * cited by examiner U.S. Patent Apr. 21, 2020 Sheet 1 of 6 US 10,629,695 B2 16 26 22 28 20 24 14 24 12 18 FIG . 1 34 26 22 32 28 32 -30 24 14 24 12 FIG . 2. U.S. Patent Apr. 21 , 2020 Sheet 2 of 6 US 10,629,695 B2 -40 7 38 | 26 22 32 28 32 -3 ) 24 14 24 12 36 FIG . 3 42 38 [26 22 32 | 28 32 -3 ) 24 14 24 12 36 FIG . 4 U.S. Patent Apr. 21 , 2020 Sheet 3 of 6 US 10,629,695 B2 48 42 4644 38 26 22 32 28 32 3 ) 24 14 24 12 36 FIG . 5 5 ) 4446 42 38 26 22 32 28 32 30 24 14 24 12 36 FIG . 6 U.S. Patent Apr. 21 , 2020 Sheet 4 of 6 US 10,629,695 B2 52 44 46 42 38 26 223 32 28 32 3 ) 24 14 24 12 36 FIG . 7 54 38 4252 4644 26 22 32 28 32 3 ) 24 14 24 12 36 FIG . 8 U.S. Patent Apr. 21 , 2020 Sheet 5 of 6 US 10,629,695 2 56 38 42 52 26 22 32 28 46 32 44 -3 ) 24 14 24 12 36 FIG . 9 48 42 58 60 46 44 38 26 22 32 28 32 30 24 14 24 12 36 FIG. 10 U.S. Patent Apr. 21 , 2020 Sheet 6 of 6 US 10,629,695 B2 56 38 58 6 ) 52 42 26 223 32 28, 46 32 44 -30 24 14 24 12 36 FIG. 11 US 10,629,695 B2 1 2 SEMICONDUCTOR DEVICE AND METHOD SUMMARY OF THE INVENTION FOR FABRICATING THE SAME According to an embodiment of the present invention , a CROSS REFERENCE TO RELATED method for fabricating semiconductor device includes the APPLICATIONS 5 steps of: forming a gate structure on a substrate ; forming an interlayer dielectric ( ILD ) layer around the gate structure ; This is a continuation application of U.S. patent applica removing the gate structure to form a first recess; forming tion Ser . No. 15 /678,125 , filed on Aug. 16 , 2017 , and all ferroelectric (FE ) layer in the first recess ; forming a com benefits of such earlier application are hereby claimed for pressive layer on the FE layer ; performing a thermal treat this new continuation application . 10 ment process ; removing the compressive layer ; and forming a work function metal layer in the recess. BACKGROUND OF THE INVENTION According to another aspect of the present invention , a semiconductor device includes : a metal gate on a substrate ; 1. Field of the Invention a polysilicon layer on the metal gate ; a hard mask on the 15 polysilicon layer; and a source/ drain region adjacent to two The invention relates to a semiconductor device , and sides of the metal gate . more particularly , to a semiconductor device containing These and other objectives of the present invention will ferroelectric (FE ) material. no doubt become obvious to those of ordinary skill in the art 20 after reading the following detailed description of the pre 2. Description of the Prior Art ferred embodiment that is illustrated in the various figures and drawings . A semiconductor device means any device which can function by utilizing semiconductor characteristics , such as BRIEF DESCRIPTION OF THE DRAWINGS an electro -optical device , a semiconductor circuit, and an 25 electronic device . Accordingly , semiconductor devices are FIGS. 1-9 illustrate a method for fabricating a semicon used in a variety of electronic applications, such as personal ductor device according to an embodiment of the present computers , cell phones , digital cameras, and other electronic invention . equipment, as example . FIG . 10 illustrates a structural view of a semiconductor Semiconductor devices are typically fabricated by 30 device according to an embodiment of the present invention . sequentially depositing insulating or dielectric layer , con FIG . 11 illustrates a structural view of a semiconductor ductive layers , and semiconductor layers over a semicon device according to an embodiment of the present invention . ductor substrate , and patterning the various material layers using lithography to form circuit components and elements DETAILED DESCRIPTION thereon . Since the semiconductor integrated circuit industry 35 has experienced rapid growth and improvement, technologi Referring to FIGS . 1-9 , FIGS. 1-9 illustrate a method for cal advances in semiconductor materials and design have fabricating a semiconductor device according to an embodi produced increasingly smaller and more complex circuits . ment of the present invention . As shown in FIGS. 1-2 , a Consequently , the number of interconnected devices per unit substrate 12 , such as a silicon substrate or silicon - on of area has increased as the size of the smallest components 40 insulator ( SOI) substrate is first provided , and at least a that can be reliably created has decreased . However , as the transistor region such as a NMOS region and a PMOS region size of the smallest components has decreased , numerous are defined on the substrate 12. Next , at least a fin -shaped challenges have risen . As features become closer, current structure 14 is formed on the substrate 12 , in which the leakage can become more noticeable , signals can crossover bottom of the fin - shaped structure 14 is surrounded by an more easily , and power usage has become a significant 45 insulating layer or shallow trench isolation (STI ) 22 made of concern . material including but not limited to for example silicon Typically , when a gate bias of a metal -oxide - semiconduc oxide . It should be noted that even though this embodiment tor field effect transistor (hereinafter abbreviated as MOS pertains to the fabrication of a non - planar FET device such FET) device is below the threshold voltage Vth , the current as FinFET device , it would also be desirable to apply the flow between the source and the drain , which is defined as 50 following processes to a planar FET device , which is also the subthreshold current, is supposed to be zero .
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