Machine to Machine – ENSEIRB 2014-2015

Machine to Machine

1) Introduction

This document describes communication buses between units and other devices (extensions, sensors, actuators, display...). These buses use . Serial transmission of digital information (bits) through a single wire (or other medium) is less costly than parallel transmission through multiple wires (number of pins, chip size, PCB size, routing time...). State of the art technology also provides more flexibility on serial transmission for equivalent throughput.

2) Definitions

a) Duplex

A duplex communication is a point-to-point system composed of two connected parties or devices that can communicate with one another in both directions. Systems that do not need the duplex capability use instead simplex communication in which one device transmits and the others can only "listen" and can not be heard (one transmits/talks and the other can only receive/listen at a time). A half-duplex (HDX) system provides communication in both directions, but only one direction at a time (not simultaneously). Typically, once a party begins receiving a signal, it must wait for the transmitter to stop transmitting, before replying. In automatically run communications systems, such as two-way data-links, the time allocations for communications in a half-duplex system can be firmly controlled by the hardware. Thus, there is no waste of the channel for switching A full-duplex (FDX) system, or sometimes called double-duplex, allows communication in both directions, and, unlike half-duplex, allows this to happen simultaneously.

b) Synchronous/Asynchronous Communications

As we consider communications between clocked digital systems, all data exchanges are based on a clock (bits are sent on the wires at a periodic interval). Although clocking is involved in these communications, they may be referenced as synchronous or asynchronous communications.

The distinction between synchronous and asynchronous communications is related to the presence of a clock signal in the communication itself. A comunication is called synchronous each time it is possible to distinguish two following bits only by observing the signals.

For example, if one of the communication wires is dedicated to provide edges that will trigger a bit change, then the communication is synchronous. On the other end, if the commnication is only based on timing references and the receiver has to build its own time reference, then the Machine to Machine – ENSEIRB 2014-2015 comunication is asynchronous (it is not possible to make the difference between one bit at a low rate and several identical bits at a higher rate).

Some complex communication interfaces do not use specific clock wires but modulate clock and data on the same channel. These interfaces are synchronous since demodulation is possible to rebuild the original clock.

c) Transfer Rates

All communication means are associated with units to precise their transmission capabilities. Most of these units are roughly equivalent but it is safer to clearly precise the meaning of each of them. All values are theoric values, they describe a maximal instantaneaous transmission capacity regardless of some necessary additional control bit or silent phases. The actual transfer rate is the amount of data that can be transfered in a real situation. Such a transfer rate is physically possible but generally requires strict conditions.

Units : Hertz (kHz, MHz, …) : This unit is not precisely a transfer rate unit, but a clock frequency. It is generally understandable that each dataline transfers one bit per clock period (This is a general assumption with exceptions, like DDR lines, see part 7).

Baud (kbaud, Mbaud...) : This unit is more particularly used in academic contexts or in RF transmission. It represents the number of symbols sent in 1 second. For basic digital communication, a symbol correspond to one bit. For more complex communications, a symbol may represent several bits. This unit is deprecated because it requires knowledge about the communication itself to be usable.

Bit per second (bps, bit/s …) : This unit reflects the quantity of data sent for each unit of time. It is the unit which physically reflects a transfer rate. For commercial reasons, half duplex communications rates are sometimes described as the sum of the two communication ways. In such cases, a 2Mbps link actually provides 1Mbps communications in both ways.

3) UART (Universal Asynchronous Receive Transmit)

A universal asynchronous receiver/transmitter, (UART) is a component that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as RS-232, or RS-485. The name UART is abusively used to describe a serial communcation that follows these specifications. Many modern Integrated Circuits now come with a UART that can also communicate synchronously; these devices are called USARTs (universal synchronous/asynchronous receiver/transmitter).

The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signalling levels.For example, in RS-232, a '1' is coded by a voltage between -15V and -3V and a '0' is coded by a voltage between +3V and +15V. The link may also be 'non electrical' (Ir, …).

Comunications based on UART are Full duplex and symetrical, so when two components are connected using this link, none of them has more priority than the other). Machine to Machine – ENSEIRB 2014-2015

a) Interface :

UART comunication only requires 2 unidirectional lines : 1 line to transmit data (TX) and 1 line to receive data (RX). It is necessary to add a ground signal if transmitter and receiver do not use the same power supply. The transmit line of each device (TX) is an output and is connected to the receive line of the other device(RX) which is an input.

b) Operation :

The idle, no data state is high-voltage, or powered. Each character is sent as a logic low start bit, a configurable number of data bits (usually 8, but users can choose 5 to 8 or 9 bits depending on which UART is in use), an optional parity bit if the number of bits per character chosen is not 9 bits, and one or more logic high stop bits (see table below). The start bit signals the receiver that a new character is coming. The next five to nine bits, depending on the code set employed, represent the character. If a parity bit is used, it would be placed after all of the data bits. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters.

Bit number 1 2 3 4 5 6 7 8 9 10 11 Start bit 5–8 data bits Stop bit(s) Start (0) Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Stop (1)

c)Parity A parity bit, or check bit, is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd. Parity bits are used as the simplest form of error detecting code.

There are two variants of parity bits: even parity bit and odd parity bit. In case of even parity, the parity bit is set to 1 if the count of ones in a given set of bits (not including the parity bit) is odd, making the count of ones in the entire set of bits (including the parity bit) even. If the count of ones in a given set of bits is already even, it is set to a 0. When using odd parity, the parity bit is set to 1 if the count of ones in a given set of bits (not including the parity bit) is even, making the count of ones in the entire set of bits (including the parity bit) odd. When the count of set bits is odd, then the odd parity bit is set to 0.

d)Flow control

As any point of the UART link may send data whenever it needs, flow control considerations are necessary. Hardware : In older versions of the specification, RS-232's use of the RTS and CTS lines is asymmetric: The sender asserts RTS to indicate a desire to transmit to the receiver, and the receiver asserts CTS in response to grant permission. This scheme is deprecated in most modern systems that only use UART as a console interface.

Software : Software flow control uses special codes, transmitted in-band, over the primary communications channel. These codes are generally called XOFF and XON (from "transmit off" and "transmit on", respectively). Thus, "software flow control" is sometimes called "XON/XOFF Machine to Machine – ENSEIRB 2014-2015 flow control". For systems using the ASCII character code, XOFF is generally represented using a character or byte with value 19; XON with value 17. When one end of a data link is unable to accept any more data (or approaching that point), it sends XOFF to the other end. The other end receives the XOFF code, and suspends transmission. Once the first end is ready to accept data again, it sends XON, and the other end resumes transmission.

The principal advantage of software flow control is the reduction in the number of wires between sender and receiver. However, software flow control is not without its problems. Sending XOFF requires at least one character time to transmit, and may be queued behind already-transmitted data still in buffers. Hardware signals may be asserted almost instantaneously, and out-of-order. As the name "software flow control" implies, flow control using this method is usually implemented in software (or at least a higher level of firmware), which can cause further delays in XOFF response. Hardware flow control is typically under the direct control of the transmitting UART, which is able to cease transmission immediately, without the intervention of higher levels.

Finally, since the XOFF/XON codes are sent in-band, they cannot appear in the data being transmitted without being mistaken for flow control commands. Any data containing the XOFF/XON codes thus must be encoded in some manner for proper transmission, with corresponding overhead. This is frequently done with some kind of escape sequence.

Terminal emulator software generally implements XOFF/XON support as a basic function. This generally includes the system console on modern Unix and Linux machines, as well as GUI emulators such as xterm and the Win32 console.

None : In this mode, no flow control is implemented. This behavior demands both ends of the link to accept and process data at the rate of the connection. This is generally the case with standard baudrates and modern computers/microcontrolers. In other cases, this mode is used when the designer of the system is aware of data volumes and knows that internal FiFo memory is big enough to handle the amount of data.

e) standard baudrates

UART speed is generally referenced as a baudrate which, in this cas is equivalent to the theoretical bitrate of both communication ways. Standard speeds are (in Bauds) : 75, 110, 300, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200. Rates lower than 300 are less ans less supported whereas new spedd tend to appear : 230400, 460800 and 921600. For , the speed can be set to any value since hardware configuration of the baudrate generator is fully accessible.

f) configuration

A UART link is a point to point connection, meaning that data are sent to only one destination. Thus, there is no possibility to select a destination. As it is an asynchronous link, both ends have to use the same parameters in order to correctly deserialize the data. These parameters are : • Baudrate • number of data bits • presence and type of parity • number of stop bits • flow control type Machine to Machine – ENSEIRB 2014-2015

4) SPI (Serial Peripheral Interface)

The Serial Peripheral Interface or SPI is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode.

Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).

a) Interface :

The SPI bus specifies four logic signals:

• SCLK : Serial Clock (output from master). • MOSI : Master Output, Slave Input (output from master). • MISO : Master Input, Slave Output (output from slave). • SS : Slave Select (active low, output from master).

Alternative naming conventions are also widely used (from the 'master' point of view):

• SCLK : SCK, CLK. • MOSI : SIMO, SDO, DO, DOUT, SO. • MISO : SOMI, SDI, DI, DIN, SI. • SS : nCS, CS, CSB, CSN, nSS, STE, SYNC.

The MOSI/MISO convention requires that SDI on the master be connected to SDO on the slave, and vice versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSS or nCS) suggest otherwise.

b) Configuration

The SPI bus can operate with a single master device and with one or more slave devices. There are different slave configuration.

Independent slave SPI configuration : In the independent slave configuration, there is an independent chip select line for each slave. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or disconnected). Devices without tri-state outputs cannot share SPI bus segments with other devices; only one such Machine to Machine – ENSEIRB 2014-2015 slave could talk to the master in this configuration mode. For such devices Daisy chain is the only possibility to use several devices.

Daisy chain SPI configuration : Some products with SPI bus are designed to be capable of being connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of what it received during the first group of clock pulses. The whole chain acts as an SPI communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.

c) Operation

To begin a communication, the bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are typically up to few tens of MHz. Machine to Machine – ENSEIRB 2014-2015

The master then transmits the logic 0 for the desired chip over the chip select line. A logic 0 is transmitted because the chip select line is active low, meaning its off state is a logic 1; on is asserted with a logic 0. If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles.

During each SPI clock cycle, a full duplex data transmission occurs: • the master sends a bit on the MOSI line; the slave reads it from that same line • the slave sends a bit on the MISO line; the master reads it from that same line When the transfer is finished, the master transmits the logic 1 on the chip select to release the device. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave.

Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs. Depending on the device, it is possible/mandatory to send several data words before deselecting the slave.

Every slave on the bus that has not been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. The master must select only one slave at a time.

Clock polarity and phase

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device. – At CPOL=0 the base value of the clock is zero • For CPHA=0, data are captured on the clock's rising edge (low→high transition) and data is propagated on a falling edge (high→low clock transition). • For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge. – At CPOL=1 the base value of the clock is one (inversion of CPOL=0) • For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge. • For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge.

That is, CPHA=0 means sample on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle.

The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. This adds more flexibility to the communication channel between the master and slave.

Mode numbers The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the Machine to Machine – ENSEIRB 2014-2015 low order bit: Mode CPOL CPHA 0 0 0 1 0 1 2 1 0 3 1 1

d) Interrupts

SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard.

e) Standard limitations

The SPI bus is a de facto standard, it is actually a way to classify lots of already existing serial interfaces in a signal type of 'bus'. The lack of a formal standard is reflected in a wide variety of protocol options. Different word sizes are common. Every device defines its own protocol, including whether or not it supports commands at all. Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low. Some protocols send the least significant bit first.

Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device ( many of the read clocks run from the chip select line).

Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.) Many SPI chips only support messages that are multiples of 8 bits.

There are also hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called 'three-wire' signaling (in contrast to normal 'four-wire' SPI). Anyone needing an external connector for SPI defines their own. Signal levels depend entirely on the chips involved.

5 ) I 2 C

I²C (Inter-Integrated Circuit, referred to as I-squared-C, I-two-C, or IIC) is a multimaster serial single-ended computer bus used for attaching low-speed peripherals to a motherboard, embedded system, cellphone, or other digital electronic devices. SMBus, defined by Intel in 1995, is a subset of I²C that defines the protocols more strictly. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C systems Machine to Machine – ENSEIRB 2014-2015 incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus, requiring only minimal reconfiguration.

a) Interface

I²C uses two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted. This bus is half-duplex because of the bidirectional data line. Communication is address based (all devices on the bus are given an address). It also uses a Master/Slave scheme, but the bus can have several master devices.

The I²C reference design has a 7-bit address space. Common I²C bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but arbitrarily low clock frequencies are also allowed. Recent revisions of I²C can host more nodes and run at faster speeds (400 kbit/s Fast mode, above 1Mbit/s for more recent standard versions). These speeds are more widely used on embedded systems than on PCs.

The maximum number of nodes is limited by the address space, and also by the total bus capacitance of 400 pF, which restricts practical communication distances to a few meters.

b)Configuration

All devices are connected to the SDA and SCL line in parallel. In addition to the two communication lines, I²C devices provide two to four pins to configure their full address. The remaining of the 7 address bits are hard-coded. For some devices, manufacturers also provide different series of the same IC, providing different hard-coded address bits. Microcontrollers and other programable devices are particuliar cases that may receive their configuration by other means.

As it generates the SCL clock signal, the master has to use a clock frequency that suits all devices on the system. There is no relationship between the transmission speed and the ability of the devices to process the data sent (see clock stretching)

c)Operation

The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave.

If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively).

The address and the data bytes are sent most significant bit first. The start bit is indicated by a high- to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. All other transitions of SDA take place with SCL low. Machine to Machine – ENSEIRB 2014-2015

If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.) If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.)

The master then either ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message"). In a combined message, each read or write begins with a START and the slave address. After the first START in a combined message, the next STARTs are also called repeated START bits. Repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message.

Any given slave will only respond to particular messages, as defined by its product documentation.

Clock Stretching One of the more significant features of the I²C protocol is clock stretching. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave may not finish the transmission of the current bit, but must wait until the clock line actually goes high. If the slave is clock stretching, the clock line will still be low (because the connections are open-drain). The same is true if a second, slower, master tries to drive the clock at the same time. (If there is more than one master, all but one of them will normally lose arbitration.)

The master must wait until it observes the clock line going high, and an additional minimum time (4 μs for standard 100 kbit/s I²C) before pulling the clock low again.

Although the master may also hold the SCL line low for as long as it desires, the term "clock stretching" is normally used only when slaves do it. Although in theory any clock pulse may be stretched, generally it is the intervals before or after the acknowledgment bit which are used. For example, if the slave is a microcontroller, its I²C interface could stretch the clock after each byte, until the software decides whether to send a positive acknowledgment or a NACK.

Clock stretching is the only time in I²C where the slave drives SCL. Many slaves do not need to clock stretch and thus treat SCL as strictly an input with no circuitry to drive it. Some masters, such as those found inside custom ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not I²C.

Arbitration Every master monitors the bus for start and stop bits, and does not start a message while another master is keeping the bus busy. However, two masters may start transmission at about the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. In contrast to protocols (such as ) that Machine to Machine – ENSEIRB 2014-2015 use random back-off delays before issuing a retry, I²C has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares it with the levels it expects; if they do not match, that transmitter has lost arbitration, and drops out of this protocol interaction.

If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different from that expected, and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it's a master, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA, and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message.

If the two masters are sending a message to two different slaves, the one sending the lower slave address always "wins" arbitration in the address stage. Since the two masters may send messages to the same slave address—and addresses sometimes refer to multiple slaves—arbitration must continue into the data stages.

Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clock- stretching, not all devices support arbitration. Those that do generally label themselves as supporting "multi-master" communication.

In the extremely rare case that two masters simultaneously send identical messages, both will regard the communication as successful, but the slave will only see one message. For this reason, slaves that can be accessed by multiple masters must have non destructive commands (there should be no difference between executing this command once or twice).

d) Interrupts like for SPI devices, I²C devices may use another signal line to send an interrupt signal to a host CPU. Interrupts are not covered by the I²C; it is frequent that, if available, interrupt lines are also open-drain to keep consistency with the communication scheme. There is no problem to use such line as firm input from the master point of view since it never drive interupts lines.

e) limitations

The I²C bus is much better documented and described than the SPI bus, so restrictions are mainly technical.

I²C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare. Support for the 1 Mbit/s speed is more widespread, since its electronics are simple variants of what is used at lower speeds. Many devices do not support the 400 kbit/s speed. I²C nodes implemented in software (instead of dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in the specification is rarely usable. All devices must at least partially support the highest speed used or they may spuriously detect their device address.

Devices are allowed to stretch clock cycles to suit their particular needs, which can starve bandwidth needed by faster devices and increase latencies when talking to other device addresses. Bus capacitance also places a limit on the transfer speed, especially when current sources are not used to decrease signal rise times. Machine to Machine – ENSEIRB 2014-2015

Because I²C is a shared bus, there is the potential for any device to have a fault and hang the entire bus. For example if any device holds the SDA or SCL line low it prevents the master from sending START or STOP commands to reset the bus. Thus it is common for designs to include a reset signal that provides an external method of resetting the bus devices. However many devices do not have a dedicated reset pin forcing the designer to put in circuitry to allow devices to be power cycled if they need to be reset.

Because of these limits (address management, bus configuration, potential faults, speed), few I²C bus segments have even a dozen devices. It is common for systems to have several such segments. One might be dedicated to use with high speed devices, for low latency power management. Another might be used to control a few devices where latency and throughput are not important issues; yet another segment might be used only to read EEPROM chips describing add-on cards.

For all these reasons, care should be taken before considering using I²C communications wthin a real-time constrained system.

f) derivative technology/ extensions

Late versions of the I²C standard provide higher working frequencies and new features like 10-bit addressing. The presence of non-compatible devices on the bus make most of these improvement unusable in standard cases. However, the 10-bit addressing extension was defined to be backward compatible with older devices, pushing the limit of the address space issue.

I²C is the basis for the VESA Display Data Channel (DDC) interface (between computers and screens for plug'n'play features), the (SMBus) for computer motherboards managements, Power Management Bus (PMBus) and other dedicated buses. These variants have differences in voltage and clock frequency ranges, and may have interrupt lines.

TWI (Two Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus implemented on various system-on-chip processors from Atmel and other vendors.[9] Vendors use the name TWI, even though I²C is not a registered trademark. Trademark protection only exists for the respective logo (See upper right corner) and patents on I²C have now lapsed.

In some cases, use of the term "two-wire interface" indicates incomplete implementation of the I²C specification. Not supporting arbitration or clock stretching is one common limitation, that is still useful for a single master communicating with simple slaves that never stretch the clock.

5)CAN

CAN bus (for controller area network) is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer.

CAN bus is a message-based protocol, designed specifically for automotive applications but now also used in other areas such as aerospace, maritime, industrial automation and medical equipment. Its specifications target the security of the transfers, but they require more complex control that the previous buses. Therefore, it should be considered a network protocol rather than a mean to access devices. It is however presented here because of its frequent presence in embedded systems. Machine to Machine – ENSEIRB 2014-2015

CAN is a multi-master broadcast serial bus standard for connecting Embedded computing Units (ECUs). Each node is able to send and receive messages, but not simultaneously. A message consists primarily of an ID (identifier), which represents the priority of the message, and up to eight data bytes. It is transmitted serially onto the bus. This signal pattern is encoded in non-return-to- zero (NRZ) and is sensed by all nodes.

The devices that are connected by a CAN network are typically sensors, actuators, and other control devices. These devices are not connected directly to the bus, but through a host processor and a CAN controller.

If the bus is idle which is represented by recessive level (Logical 1), any node may begin to transmit. If two or more nodes begin sending messages at the same time, the message with the more dominant ID (which has more dominant bits, i.e., zeroes) will overwrite other nodes' less dominant IDs, so that eventually (after this arbitration on the ID.) only the dominant message remains and is received by all nodes. This mechanism is referred to as priority based bus arbitration. Messages with numerically smaller values of IDs have higher priority and are transmitted first.

Physical CAN links use Low Voltage Differential Signals (LVDS), so, for each logical level, one of the two signals of the differential pair is logic high and the other one is logic low. This is why, to avoid confusion, official documents mention recessive (1) and dominant (0) bits. The behavior of these bits is equivalent to open-drain connections (whoever writes a logical '0' gains priority on the other ones).

A CAN frame contains from 44 bits to 110 bits depending on the quantity of data transfered (from 0 to 64 bits). A message containing 0 bits of data may be the signaling of a single event. Extensions may provide identifiers (or addresses) of 29 bits instead of 11, frames then contains from 64 to 128 bits. Machine to Machine – ENSEIRB 2014-2015

6)Comparison

Bus type UART SPI I²C CAN Duplex Full Full Half Half Throughput (typical) ~10/20 kbps ~10Mbps ~100kbps ~ 250 kbps Throughput (standard max) 115kbps No limit 3Mbps 1Mbps Number of devices 2 ~10 ~50 hundreds Line number (excl. ground) 2 (4) 4 (+ n) 2 2 Line directions Unidir Unidir Bidir Bidir Addr space - - 7 or 10 bits 11 to 29 bits Flow control HW possible None Clk stretch. In message Number of masters 2 1 Any any Error checking Parity bit None None 15b CRC Acknowledgement No No Yes Yes Distance ~10m 10cm 1-2 m 40m to 500m Hot Plug No No Possible Possible Real-time Yes Mast. Dep. No No

7)Other buses

Many other communication buses are not presented here : USB, Ethernet, PCI-e and SATA (for example) are all based on one or several LVDS lines. Differences come from the structure of data packets and the software protocol.

Modern designs avoid parallel buses because of the complexity of PCBs for high performance (high number of lines, requirements to get similar impedance and propagation delays). When throughput needs are particularly high, several serial buses are prefered to a single high speed parallel bus. Data are then split among the different available buses.

8) References

– https://en.wikipedia.org : UART, SPI, I²C, CAN bus ... – I²C-bus specification and user manual v5 ( http://www.nxp.com/documents/user_manual/UM10204.pdf )