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Table of Contents v1.19 Table of Contents 1. Introduction 2. Warranty 3. Features 4. Technical Support 5. Hardware Information 1. Connector Pin-out 2. Building an External Display 6. Selected POST Codes 1. AMI BIOS 2. Quadtel BIOS / PhoenixBIOS Q3.07 3. PhoenixBIOS 4.0 Release 6.0 4. Award BIOS 4.51PG 5. MR BIOS 3.4x 7. Information Resources 1 1. Introduction: The PST44 is a P.O.S.T (Power On Self Test) diagnostics card for the ISA bus. It monitors port 80H and displays the data on two 7-segment LED displays. The PST44 is designed for use in computers with a 286 or later processor since these use port 80H as their POST port. The card also includes 4 LEDs to indicate if the power supplies are supplying current. These LEDs simply indicate the presence or absence of voltage; they do not actually indicate whether the voltage is within specifications. A DB-15 connector on the card's back-plane provides access to the 7-segment data pins if desired. Using this connector, it is possible to connect an external cable and display for easy viewing of the POST codes. When the computer's power is turned on, the BIOS performs a series of system tests before the operating system is loaded. This series of tests is referred to as the Power On Self Test, or POST. This series of tests typically checks the memory, disk controllers, keyboard, video card, and a number of other things. If all goes well, then the computer moves on to loading the operating system. If a major problem occurs and the computer hangs up, then we need some feedback to tell us where the problem occurred. The POST card provides this feedback. As the BIOS steps through each test it must perform, it writes a numeric code to port 80H. The POST card detects this code, latches it, and displays it. If the system passes the test, then the code will remain visible for only a short period of time before being replaced by the code for the next test. If the computer hangs up, then the code for the failed test is left on the display, indicating where the problem occurred. The computer technician must then consult a reference table for that particular brand of BIOS and see what area of hardware the POST code refers to. This manual includes POST code tables for American Megatrends, Quadtel, Phoenix, and MR BIOS. Other less popular codes can be obtained from Internet sites (see the Information Resources section of this manual). Package Contents The package you received should contain 2 items: 1. This manual 2. The PST44 P.O.S.T diagnostics card Disclaimer The PST44 is not intended or designed for use in military, medical, or other life- critical applications. Winford Engineering shall not be held responsible or liable for damages or injury that occur as a result of the use this product. 2 2. Warranty: Winford Engineering provides a 2-year warranty for the PST44 P.O.S.T. card. This warranty does not cover the misuse or abuse of this product. In the event of product failure, Winford Engineering should be contacted for information regarding the return and replacement of the product. 3 3. Features: Works with 8 or 16-bit ISA bus. Monitors port 80 hexadecimal (standard for AT machines). Has voltage-present indicators** on the +5, -5, +12, -12 supply lines. Has a DB-15 connector on the back which allows the connection of an external display. ** These LEDs simply indicate the presence of voltage on the supply lines. They do not verify that it is within the required specifications. For example, the LED on the +12 volt supply line will light up even if the supply is only 8 volts at the time. These indicators simply indicate that some voltage is present. 4 4. Technical Support: If you find yourself in need of technical assistance beyond what is covered in this manual, there are several ways to contact Winford Engineering. If your problem is not urgent, we would prefer that you use e-mail or fax. Please provide us with your preferred e-mail address, as well as phone/fax numbers where you wish to be reached. This will help us get back to you in a timely fashion. NOTE: We cannot provide information about obscure POST codes. We do provide the common BIOS code definitions in this manual. We also provide Internet links to POST code lists in the Information Resources section of this manual. Technical Support Contacts Phone: 1-989-671-2941 FAX: 1-989-671-2941 E-mail: [email protected] Winford Engineering Technical Support 4169 Four Mile Road Bay City, MI 48706 5 5. Hardware Information: 5.1 Connector Pin-out The outputs of the LED display driver chips are brought out via the DB-15 connector on the back of the card. This connector can be used to display the POST codes on an external display (not provided). This provides convenient access to the codes if the card itself is not in a position to be viewed. The outputs are active-low (meant for a common anode 7-segment display). The outputs are brought out before any current-limiting resistors, so these will need to be built into any external display. The outputs for the upper display digit (most significant) are denoted with a 'U' prefix in the table below. The lower digit is indicated with an 'L' prefix. Pin Function 1 U_a 2 U_b 3 U_c 4 U_d 5 U_e 6 U_f 7 U_g 8 GND 9 L_a 10 L_b 11 L_c 12 L_d 13 L_e 14 L_f 15 L_g 6 5.2 Building an External Display It is a simple task to build your own external display for the POST card. You need a battery (typically a 9-volt), two common-anode 7-segment displays, and some current-limiting resistors. A schematic is shown below. a f b g e c d 7 6. Selected POST Codes Each BIOS manufacturer defines their own POST codes. Therefore, you need a list of BIOS code definitions from your manufacturer. Each manufacturer also has more than one version of BIOS, so check that as well. POST codes for some common BIOS versions are listed below. If your BIOS is not listed, check the Information Resources section of the manual for links to more POST code lists. 6.1 AMI Code Definitions CODE AMI DESCRIPTION 00 System configuration is displayed. Going to give control to INT 19h boot loader. 01 Processor register test about to start, and NMI to be disabled. 02 NMI is DIsabled. Power on delay starting. 03 Power on delay complete. Any initialization before keyboard BAT is in progress. 04 Any initialization before keyboard BAT is complete. Reading keyboard SYS bit, to check soft reset/ power-on. 05 Soft reset/ power-on determined. Going to enable ROM. i.e. disable shadow RAM/Cache if any. 06 ROM is enabled. Calculating ROM BIOS checksum, and waiting for KB controller input buffer to be free. 07 ROM BIOS checksum passed, KB controller I/B free. Going to issue the BAT command to keyboard controller. 08 BAT command to keyboard controller is issued. Going to verify the BAT command. 09 Keyboard controller BAT result verified. Keyboard command byte to be written next. 0A Keyboard command byte code is issued. Going to write command byte data. 0B Keyboard controller command byte is written. Going to issue Pin-23,24 blocking/unblocking command. 0C Pin-23,24 of keyboard controller is blocked/ unblocked. NOP command of keyboard controller to be issued next. 8 CODE AMI DESCRIPTION 0D NOP command processing is done. CMOS shutdown register test to be done next. 0E CMOS shutdown register R/W test passed. Going to calculate CMOS checksum, and update DIAG byte. 0F CMOS checksum calculation is done, DIAG byte written. CMOS init. to begin (If "INIT CMOS IN EVERY BOOT IS SET"). 10 CMOS initialization done (if any). CMOS status register about to init for Date and Time. 11 CMOS Status register initialized. Going to disable DMA and Interrupt controllers. 12 DMA controller #1,#2, interrupt controller #1,#2 disabled. About to disable Video display and init port-B. 13 Video display is disabled and port-B is initialized. Chipset init/ auto memory detection about to begin. 14 Chipset initialization/ auto memory detection over. 8254 timer test about to start. 15 CH-2 timer test halfway. 8254 CH-2 timer test to be complete. 16 CH-2 timer test over. 8254 CH-1 timer test to be complete. 17 CH-1 timer test over. 8254 CH-0 timer test to be complete. 18 CH-0 timer test over. About to start memory refresh. 19 Memory Refresh started. Memory Refresh test to be done next. 1A Memory Refresh line is toggling. Going to check 15 micro second ON/OFF time. 1B Memory Refresh period 30 micro second test complete. Base 64K memory test about to start. 20 Base 64k memory test started. Address line test to be done next. 21 Address line test passed. Going to do toggle parity. 22 Toggle parity over. Going for sequential data R/W test. 23 Base 64k sequential data R/W test passed. Any setup before Interrupt vector init about to start. 24 Setup required before vector initialization complete. Interrupt vector initialization about to begin. 9 CODE AMI DESCRIPTION 25 Interrupt vector initialization done. Going to read I/O port of 8042 for turbo switch (if any). 26 I/O port of 8042 is read.
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