DATA CONVERTER APPLICATIONS
ANALOG-DIGITAL CONVERSION
1. Data Converter History 2. Fundamentals of Sampled Data Systems 3. Data Converter Architectures 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to Data Converters 7. Data Converter Support Circuits 8. Data Converter Applications 8.1 Precision Measurement and Sensor Conditioning 8.2 Multichannel Data Acquisition Systems 8.3 Digital Potentiometers 8.4 Digital Audio 8.5 Digital Video and Display Electronics 8.6 Software Radio and IF Sampling 8.7 Direct Digital Synthesis (DDS) 8.8 Precision Analog Microcontrollers 9. Hardware Design Techniques I. Index ANALOG-DIGITAL CONVERSION
DATA CONVERTER APPLICATIONS 8.1 PRECISION MEASUREMENT AND SENSOR CONDITIONING CHAPTER 8 DATA CONVERTER APPLICATIONS
SECTION 8.1: PRECISION MEASUREMENT AND SENSOR CONDITIONING
Introduction
The high resolution Σ-∆ measurement ADC has revolutionized the entire area of precision sensor signal conditioning and data acquisition. Modern Σ-∆ ADCs offer no- missing code resolutions to 24 bits, and greater than 19-bits of noise-free code resolution. The inclusion of on-chip PGAs coupled with the high resolution virtually eliminates the need for signal conditioning circuitry—the precision sensor can interface directly with the ADC in many cases.
As discussed in detail in Chapter 3 of this book, the Σ-∆ architecture is highly digitally intensive. It is therefore relatively easy to add programmable features and offer greater flexibility in their applications. Throughput rate, digital filter cutoff frequency, PGA gain, channel selection, chopping, and calibration modes are just a few of the possible features. One of the benefits of the on-chip digital filter is that its notches can be programmed to provide excellent 50-Hz/60-Hz power supply rejection. In addition, since the input to a Σ-∆ ADC is highly oversampled, the requirements on the antialiasing filter are not nearly as stringent as in the case of traditional Nyquist-type ADCs. Excellent common-mode rejection is also a result of the extensive utilization of differential analog and reference inputs. An important benefit of Σ-∆ ADCs is that they are typically designed on CMOS processes, therefore they are relatively low cost. High Resolution 24 bits no missing codes 22 bits effective resolution (RMS) 19 bits noise-free code resolution (peak-to-peak) On-Chip PGAs High Accuracy INL 2ppm of Fullscale ~ 1LSB in 19 bits Gain drift 0.5ppm/°C More Digital, Less Analog Programmable Balance between Speed × Resolution Oversampling & Digital Filtering 50 / 60Hz rejection High oversampling rate simplifies antialiasing filter Wide Dynamic Range Low Cost
Figure 8.1: Σ-∆ ADC Architecture Benefits
8.1 ANALOG-DIGITAL CONVERSION
In applying Σ-∆ ADCs, the user must accept the fact that because of the highly digital nature of the devices and the programmability offered, the digital interfaces tend to be more complex than with traditional ADC architectures such as successive approximation, for example. However, manufacturers' evaluation boards and associated development software along with complete data sheets can ease the overall design process considerably.
Some of the architectural benefits and features of the Σ-∆ measurement ADC are summarized in Figure 8.1 and 8.2.