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Chapter 8: Data Converter Applications DATA CONVERTER APPLICATIONS ANALOG-DIGITAL CONVERSION 1. Data Converter History 2. Fundamentals of Sampled Data Systems 3. Data Converter Architectures 4. Data Converter Process Technology 5. Testing Data Converters 6. Interfacing to Data Converters 7. Data Converter Support Circuits 8. Data Converter Applications 8.1 Precision Measurement and Sensor Conditioning 8.2 Multichannel Data Acquisition Systems 8.3 Digital Potentiometers 8.4 Digital Audio 8.5 Digital Video and Display Electronics 8.6 Software Radio and IF Sampling 8.7 Direct Digital Synthesis (DDS) 8.8 Precision Analog Microcontrollers 9. Hardware Design Techniques I. Index ANALOG-DIGITAL CONVERSION DATA CONVERTER APPLICATIONS 8.1 PRECISION MEASUREMENT AND SENSOR CONDITIONING CHAPTER 8 DATA CONVERTER APPLICATIONS SECTION 8.1: PRECISION MEASUREMENT AND SENSOR CONDITIONING Introduction The high resolution Σ-∆ measurement ADC has revolutionized the entire area of precision sensor signal conditioning and data acquisition. Modern Σ-∆ ADCs offer no- missing code resolutions to 24 bits, and greater than 19-bits of noise-free code resolution. The inclusion of on-chip PGAs coupled with the high resolution virtually eliminates the need for signal conditioning circuitry—the precision sensor can interface directly with the ADC in many cases. As discussed in detail in Chapter 3 of this book, the Σ-∆ architecture is highly digitally intensive. It is therefore relatively easy to add programmable features and offer greater flexibility in their applications. Throughput rate, digital filter cutoff frequency, PGA gain, channel selection, chopping, and calibration modes are just a few of the possible features. One of the benefits of the on-chip digital filter is that its notches can be programmed to provide excellent 50-Hz/60-Hz power supply rejection. In addition, since the input to a Σ-∆ ADC is highly oversampled, the requirements on the antialiasing filter are not nearly as stringent as in the case of traditional Nyquist-type ADCs. Excellent common-mode rejection is also a result of the extensive utilization of differential analog and reference inputs. An important benefit of Σ-∆ ADCs is that they are typically designed on CMOS processes, therefore they are relatively low cost. High Resolution 24 bits no missing codes 22 bits effective resolution (RMS) 19 bits noise-free code resolution (peak-to-peak) On-Chip PGAs High Accuracy INL 2ppm of Fullscale ~ 1LSB in 19 bits Gain drift 0.5ppm/°C More Digital, Less Analog Programmable Balance between Speed × Resolution Oversampling & Digital Filtering 50 / 60Hz rejection High oversampling rate simplifies antialiasing filter Wide Dynamic Range Low Cost Figure 8.1: Σ-∆ ADC Architecture Benefits 8.1 ANALOG-DIGITAL CONVERSION In applying Σ-∆ ADCs, the user must accept the fact that because of the highly digital nature of the devices and the programmability offered, the digital interfaces tend to be more complex than with traditional ADC architectures such as successive approximation, for example. However, manufacturers' evaluation boards and associated development software along with complete data sheets can ease the overall design process considerably. Some of the architectural benefits and features of the Σ-∆ measurement ADC are summarized in Figure 8.1 and 8.2. Analog Input Buffer Options Drives Σ−∆ Modulator, Reduces Dynamic Input Current Differential AIN, REFIN Ratiometric Configuration Eliminates Need for Accurate Reference Multiplexer PGA Calibrations Self Calibration, System Calibration, Auto Calibration Chopping Options No Offset and Offset Drifts Minimizes Effects of Parasitic Thermocouples Figure 8.2: Σ-∆ System on Chip Features Applications of Precision Measurement Σ-∆ ADCs High resolution measurement Σ-∆ ADCs find applications in many areas, including process control, sensor conditioning, instrumentation, etc. as shown in Figure 8.3. Because of the varied requirements, these ADCs are offered in a variety of configurations and options. For instance, Analog Devices currently (2004) has more than 24 different high resolution Σ-∆ ADC product offerings available. For this reason, it is impossible to cover all applications and products in a section of reasonable length, so we will focus on several representative sensor conditioning examples which will serve to illustrate most of the important application principles. Because many sensors such as strain gages, flow meters, pressure sensors, and load cells use resistor-based circuits, we will use the AD7730 ADC as an example in a weigh scale design. A block diagram of the AD7730 is shown in Figure 8.4. 8.2 DATA CONVERTER APPLICATIONS 8.1 PRECISION MEASUREMENT AND SENSOR CONDITIONING Process Control 4-20mA Sensors Weigh Scale Pressure Temperature Instrumentation Gas Monitoring Portable Instrumentation Medical Instrumentation WEIGH SCALE Figure 8.3: Typical Applications of High Resolution Σ-∆ ADCs AVDD DVDD REFIN(–) REFIN(+) VBIAS AD7730 REFERENCE DETECT 100nA AIN1(+) STANDBY SIGMA-DELTA ADC AIN1(–) BUFFER + SIGMA- PROGRAMMABLE + MUX ∑ PGA DELTA DIGITAL SYNC _ MODULATOR FILTER +/– AIN2(+)/D1 MCLK IN AIN2(–)/D0 100nA CLOCK SERIAL INTERFACE 6-BIT GENERATION AND CONTROL LOGIC MCLK OUT DAC REGISTER BANK SCLK VBIAS CS CALIBRATION MICROCONTROLLER DIN DOUT ACX AC EXCITATION ACX CLOCK AGND DGND POL RDY RESET Figure 8.4: AD7730 Single-Supply Bridge ADC The heart of the AD7730 is the 24-bit Σ-∆ core. The AD7730 is a complete analog front end for weigh-scale and pressure measurement applications. The device accepts low level signals directly from a transducer and outputs a serial digital word. The input signal is applied to a proprietary programmable gain front end based around an analog modulator. The modulator output is processed by a low pass programmable digital filter, allowing adjustment of filter cutoff, output rate and settling time. The response of the internal digital filter is shown in Figure 8.5. 8.3 ANALOG-DIGITAL CONVERSION 0 –10 –20 SINC3 + 22-TAP FIR FILTER, –30 CHOP MODE ENABLED GAIN –40 (dB) –50 –60 –70 –80 –90 –110 –120 –130 0 10 20 30 40 50 60 70 80 90 100 FREQUNCY (Hz) Figure 8.5: AD7730 Digital Filter Frequency Response The part features two buffered differential programmable gain analog inputs as well as a differential reference input. The part operates from a single +5-V supply. It accepts four unipolar analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and +80 mV and four bipolar ranges: ±10 mV, ±20 mV, ±40 mV and ±80 mV. The peak-to-peak noise-free code resolution achievable directly from the part is 1 in 230,000 counts. An on-chip 6-bit DAC allows the removal of TARE voltages. Clock signals for synchronizing ac excitation of the bridge are also provided. The serial interface on the part can be configured for three-wire operation and is compatible with microcontrollers and digital signal processors. The AD7730 contains self-calibration and system calibration options, and features an offset drift of less than 5 nV/°C and a gain drift of less than 2 ppm/°C. The AD7730 is available in a 24-pin plastic DIP, a 24-lead SOIC and 24-lead TSSOP package. The AD7730L is available in a 24-lead SOIC and 24-lead TSSOP package. Key specifications for the AD7730 are summarized in Figure 8.6. Further details on the operation of the AD7730 can be found in References 1 and 2. 8.4 DATA CONVERTER APPLICATIONS 8.1 PRECISION MEASUREMENT AND SENSOR CONDITIONING Resolution of 80,000 Counts Peak-to-Peak (16.5-Bits) for ± 10mV Fullscale Range Chop Mode for Low Offset and Drift Offset Drift: 5nV/°C (Chop Mode Enabled) Gain Drift: 2ppm/°C Line Frequency Common Mode Rejection: > 150dB Two-Channel Programmable Gain Front End On-Chip DAC for Offset/TARE Removal FASTStep Mode AC Excitation Output Drive Internal and System Calibration Options Single +5V Supply Power Dissipation: 65mW, (125mW for 10mV FS Range) 24-Lead SOIC and 24-Lead TSSOP Packages Figure 8.6: AD7730 Key Specifications A very powerful ratiometric technique which includes Kelvin sensing to minimize errors due to wiring resistance and also eliminates the need for an accurate excitation voltage is shown in Figure 8.7. The AD7730 measurement ADC can be driven from a single supply voltage which is also used to excite the remote bridge. Both the analog input and the reference input to the ADC are high impedance and fully differential. By using the + and – SENSE outputs from the bridge as the differential reference to the ADC, the reference voltage is proportional to the excitation voltage which is also proportional to the bridge output voltage. There is no loss in measurement accuracy if the actual bridge excitation voltage varies. +FORCE +5V +5V/+3V R LEAD AVDD DVDD 6-LEAD +SENSE BRIDGE + VREF AD7730 + A ADC V IN O –A IN 24 BITS – SENSE –VREF R AGND DGND –FORCE LEAD Figure 8.7: AD7730 Bridge Application Showing Ratiometric Operation and Kelvin Sensing 8.5 ANALOG-DIGITAL CONVERSION It should be noted that this ratiometric technique can be used in many applications where a sensor output is proportional to its excitation voltage or current, such as a thermistor or RTD. Weigh Scale Design Analysis Using the AD7730 ADC We will now proceed with a simple design analysis of a weigh scale based on the AD7730 ADC and a standard load cell. Figure 8.8 shows the overall design objectives for the weigh scale. The key specifications are the fullscale load (2 kg), and the resolution (0.1 g). These specifications primarily determine the basic load cell and ADC requirements. Capacity 2 kg Sensitivity 0.1 g Other Features Accuracy 0.1 % Linearity ±0.1 g Temp.Drift (±20ppm @ 10~30°C) Speed (Readings / second) Power (120V AC) Dimensions (7.5"× 8.6" × 2.6") Qualification ("Legal for Trade") Marketing Price ($400) Figure 8.8: Design Example—Weigh Scale The specifications of a load cell which matches the overall requirements are shown in Figure 8.9.
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