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FEATURES 6 Corsi e Ricorsi: The EDA Story A design pioneer reflects on the technical, economic, human, and philosophical history of his craft. By Alberto Sangiovanni-Vincentelli Grasping Systems Design By Albert Benveniste Getting Acquainted with Prof. Parsley By Piero Martinotti Head in the Clouds, Feet on the Ground By Massimo Vanzi Industrial Influence: Sangiovanni as Entrepreneur and Consigliere By Michael Borrus ABOUT THIS IMAGE: More information about this colorful object can be found in 26 Summer of ’81 the article by Gelsinger et al. At IBM, a group of industrial engineers and university researchers collaborated in the summer to develop the earliest successful method of logic synthesis for ICs. By Robert Brayton

32 Such a CAD! Coping with the complexity of microprocessor COLUMNS/ design at Intel. DEPARTMENTS By Patrick Gelsinger, Desmond Kirkpatrick, 3 CONTRIBUTORS Avinoam Kolodny, and Gadi Singer 4 EDITOR’S NOTE 44 Alberto Sangiovanni-Vincentelli 62 PEOPLE and STMicroelectronics 73 CHAPTERS The 30-years’ peace. 76 SOCIETY NEWS By Philippe Geyres, Pasquale Pistorio, and Aldo Romano 77 IEEE NEWS 48 81 CONFERENCE REPORTS Presentation of the 2001 Phil Kaufman Award 94 CALENDAR to Professor Alberto Sangiovanni-Vincentelli 96 FOOTER By A. Richard Newton

52 Remembering Richard By Alberto Sangiovanni-Vincentelli

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IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 1 Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:30:49 UTC from IEEE Xplore. Restrictions apply. Administrator, Katherine Olstein Terms to 31 Dec. 2012 IEEE SOLID-STATE IEEE SSCS, 445 Hoes Lane Kerry Bernstein, John J. Corcoran, CIRCUITS MAGAZINE Piscataway, NJ 08854 USA Hae-Sung (H.S.) Lee, Trudy Stetzler, Tel: +1 732 981 3410 William Redman-White EDITOR-IN-CHIEF Fax: +1 732 981 3401 Region 8 Representative Mary Y. Lanzerotti SSC ADMINISTRATIVE COMMITTEE Tohru Furuyama, fulfilling term [email protected] of Jan Sevenhans President, Bernhard Boser TECHNOLOGY EDITOR University of California, Berkeley, USA Region 10 Representatives Richard C. Jaeger C.K. Wang [email protected] Vice-President, Rakesh Kumar Technology Connexions, Poway, Chairs of Standing Committees TUTORIALS EDITOR California, USA Awards—John J. Corcoran Rakesh Kumar Secretary, Paul Hurst, University Chapters—Jan Van der Spiegel [email protected] of California, Davis, USA Education—C.K. Ken Yang Treasurer, H.S. Lee, MIT Meetings—Bill Bidermann ASSOCIATE EDITOR FOR Membership—Tzi-Dar Chiueh EUROPE/AFRICA Past President, Willy Sansen Nominations—Willy Sansen Tony Harker K.U. Leuven, Belgium Publications—Glenn Gulak [email protected] Other Representatives ASSOCIATE EDITOR FOR IEEE PERIODICALS/ THE FAR EAST Representative to Sensors Pengfei Zhang Council MAGAZINES DEPARTMENT Darrin Young [email protected] SENIOR MANAGING EDITOR Representative to CAS from SSCS Geraldine Krolin-Taylor CONTRIBUTING EDITOR Tony Chan Carusone Tom Lee SENIOR ART DIRECTOR Representative to SSCS from CAS [email protected] Janet Dudar Michael Flynn ASSISTANT ART DIRECTOR NEWS EDITOR Representatives to EDA Council Gail A. Schnitzer Katherine Olstein Bryan Ackland, Jan Rabaey [email protected] PRODUCTION COORDINATOR Representatives to ISSCC Theresa L. Smith Bryan Ackland, Jan Van der Spiegel MAGAZINE ADVISORY BOARD STAFF DIRECTOR, PUBLISHING OPERATIONS Chair: Richard Jaeger, Erik Heijne, Representatives to IEEE GOLD Fran Zappulla Rakesh Kumar, Mary Lanzerotti, Program Sean Nicolson, Emre Ayranci EDITORIAL DIRECTOR Tom Lee, Katherine Olstein, Anne O’Neill, Dawn M. Melley Willy Sansen, Lewis Terman, Alice Wang, Representatives to Nanotechnology PRODUCTION DIRECTOR Pengfei Zhang Council Elad Alon, Ian Young Peter M. Tuohy ADVERTISING PRODUCTION MANAGER Elected AdCom Members at Large Felicia Spagnoli IEEE SOLID-STATE CIRCUITS SOCIETY Terms to 31 Dec. 2010 BUSINESS DEVELOPMENT MANAGER Terri S. Fiez, Tohru Furuyama, Susan Schneiderman +1 732 562 3946 Fax: +1 732 981 1855 Executive Director, Anne O’Neill Tadahiro Kuroda, Bram Nauta, [email protected] IEEE SSCS-West Mehmet Soyuer www.ieee.org/ieeemedia 1500 SW 11th Avenue #1801 Portland, OR 97201 USA Terms to 31 Dec. 2011 IEEE prohibits discrimination, harassment, and Tel: +1 732 981 3400 Ali Hajimiri, Paul J. Hurst, bullying. For more information, visit http://www. Fax: +1 732 981 3401 Domine Leenaerts, Kenneth O, ieee.org/web/aboutus/whatis/policies/p9-26. [email protected] Ian Young html.

SCOPE: Each issue of IEEE Solid-State Circuits Magazine is envisioned as a self-contained resource for fundamental theories and practical advances within the field of integrated cir- cuits (ICs). Written at a tutorial level and in a narrative style, the magazine features articles by leaders from industry, academia and government explaining historical milestones, current trends and future developments. CONTACT INFORMATION: See the “Contact Us” page on SSCS Web site: http://ewh.ieee. org/soc/sscs/index.php? option=com_content&task=view&id= 10&Itemid=3. IEEE Solid-State Circuits Magazine (ISSN 1943-0582) is published quarterly by The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016-5997, USA +1 212 419 7900. Responsibility for the contents rests upon the authors and not upon the IEEE, the Society, or its members. The magazine is a membership benefit of the IEEE Solid-State Circuits Society, and subscriptions are included in Society fee. Replacement copies for members are available for $20 (one copy only). Nonmembers can pur- chase individual copies for $138.00. Nonmember subscription prices are available on request. Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Librar- ies are permitted to photocopy beyond the limits of the U.S. Copyright law for private use of patrons: 1) those post-1977 articles that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01970, USA; and 2) pre-1978 articles without fee. For other copying, reprint, or republication permission, write to: Copyrights and Permissions Depart- ment, IEEE Service Center, 445 Hoes Lane, Piscataway NJ 08854 USA Copyright © 2010 by The Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Periodicals postage paid at New York, NY, and at additional mailing offices. Postmaster: Send address changes to A. SANGIOVANNI-VINCENTELLI. IEEE Solid-Sate Circuits Magazine, IEEE, 445 Hoes Lane, Piscataway, NJ 08854 USA. Canadian ABOUT THE COVER: GST #125634188 PRINTED IN USA Alberto Sangiovanni-Vincentelli and the evolution of EDA. Digital Object Identifier 10.1109/MSSC.2010.937948

2 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:30:49 UTC from IEEE Xplore. Restrictions apply. CONTRIBUTORS

ALBERTO SANGIO- ROBERT BRAYTON, PHILIPPE GEYRES VANNI-VINCENTELLI retired from the began his profession- holds the Edgar L. University of Cali- al career with IBM at and Harold H. Butt- fornia, Berkeley, has Corbeil-Essonnes, ner Chair of Electri- authored more than France, before join- cal Engineering and 450 technical papers ing the Schlumberg- Computer Sciences at the University and ten books on the analysis of er Group in 1980, working fi rst in oil of California at Berkeley, of which nonlinear networks, simulation and services and then at Fairchild Semi- he has been on the faculty since optimization of electrical circuits, conductors. 1976. logic synthesis, and formal design verifi cation. PASQUALE PISTORIO ALBERT BENVENISTE joined Motorola in received the CNRS PATRICK GELSINGER Italy, in 1967 and rose Silver Medal in 1990, has had numerous through the ranks to was elected an IEEE roles at Intel in near- become director of Fellow in 1991, and ly 30 years with the international market- received the Grand company, including ing, based in Phoenix, Arizona. Prix France Telecom of the Académie fi rst-ever Intel CTO. des Sciences in 2008. ALDO ROMANO DESMOND KIRKPAT- joined SGS Micro- PIERO MARTINOTTI RICK was a member elettronica (a prede- is currently an inde- of the Pentium Pro cessor company to pendent technology and Pentium 4 mi- STMicroelectronics) business adviser. He croprocessor design as a designer of lin- began his career at teams, contributing ear integrated circuits (ICs) in 1965. SGS as an application to full-chip assembly and intercon- In 1970, Romano was appointed head and marketing engineer. nect performance management as of the Linear IC Design Department. well as to the specifi cation of Intel’s MASSIMO VANZI 130-nm process technology. has been an invited panelist or speaker AVINOAM KOLODNY, at several interna- in his 20 years at In- tional conferences and tel, pioneered static workshops including timing analysis of ICCAD, DATE, IPSoC, ESSDERC, and processors as the DAC. lead developer of the CLCD tool. MICHAEL BORRUS has focused much of GADI SINGER joined his academic and con- Intel in 1983 and has sulting work on how held a variety of se- business models can nior technical and adjust to success- management posi- fully commercialize new technologies, tions, including vice exploit new opportunities, or adapt to president and CTO of Intel Communi- new competitors. cations Group.

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Mary Lanzerotti

Welcome to the Summer 2010 Issue!

In the Summer 2010 and Fall 2010 is- ■ “Remembering Rich- The long-term goal sues, we are honored to feature the ard” by Alberto San- We are also delighted of this magazine is to I to present expert work of Alberto Sangiovanni-Vin- giovanni-Vincentelli. become a series of self- centelli, a technical and intellectual We remain thankful articles that describe contained re sources, pioneer at the University of Califor- for the support and the impact of each containing origi- nia at Berkeley. initiatives of Execu- Prof. Sangiovanni- nal sources and new In this issue (Part I), we are tive Director Anne Vincentelli’s work. contributions by experts delighted to present an original O’Neill, SSCS Tech- describing the current state article by Prof. Sangiovanni-Vincen- nology Editor Dick of aff airs and evolution of a telli titled “Corsi e Ricorsi: The EDA Jaeger, SSCS Treasurer Rakesh particular area of IC technology. Story.” We are also delighted to pres- Kumar, and News Editor Kather- We hope you enjoy IEEE Solid- ent expert articles that describe the ine Olstein and for the columns of State Circuits Magazine. Thank you impact of Prof. Sangiovanni-Vincen- PengFei Zhang, associate editor of for reading it. telli’s work. Asia and Africa, Tony Harker, asso- Please send comments and ■ “Grasping Systems Design,” by ciate editor of Europe, and Tom feedback to marylanzerotti@post. Albert Benveniste Lee, contributing editor. harvard.edu. ■ “Getting Acquainted with Prof. Parsley,” by Piero Martinotti ■ “Head in the Clouds, Feet on the Ground,” by Massimo Vanzi ■ “Industrial Infl uence: Sangio- vanni as Entrepreneur and Con- sigliere,” by Michael Borrus as well as a short remembrance about EDA pioneers Don Pederson and Richard Newton by Prof. Sangio- vanni-Vincentelli. Reminiscences in this issue about the work and life of Prof. Sangiovan- ni-Vincentelli are the following: ■ “Summer of ‘81,” by Robert Brayton ■ “Such a CAD!” by Patrick Gelsinger, Desmond Kirkpatrick, Avinoam Kolodny, and Gadi Singer ■ “Alberto Sangiovanni-Vincentelli and STMicroelectronics,” by Phil- lipe Geyres, Pasquale Pistorio, and Aldo Romano. We also have two reprint articles: ■ “Presentation of the 2001 Phil Kaufman Award to Professor Alberto Sangiovanni-Vincentelli” by A. Richard Newton

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A design pioneer reflects on the technical, economic, human, and philosophical history of his craft.

dedicate this article to the memory of electronic design automation (EDA) pioneers Don I Pederson and Richard Newton (see “Don Pederson and Richard Newton, EDA Pioneers”), who are no longer with us, and to the many friends, colleagues, and students with whom I had the great pleasure to work. The article is a reflection on the development of the EDA field, from its early days to its explo- sive growth and present maturity. It is based on “The Tides of EDA,” an article published in 2003 in IEEE Design and Test of Computers, after a key- note address I gave in 2003 on the occasion of the 40th anniversary of the Design Automation Conference (DAC). I have interspersed various personal comments and recollections in order to convey a more personal view of the evolution of the field. My personal history begins in Milan, Italy. My early days were characterized by a passion for books, art, philosophy, sports (I was at best a mediocre volleyball player, a decent long-dis- tance runner, a reasonable swimmer, and a very poor soccer player but a scholar of any sport known to man), and—quite a rarity among kids in that period—fashion and design. My high school was not focused on science and tech- nology: rather, I studied at a school concentrat- ing in the humanities, where I had eight years of Latin and five of ancient Greek, philosophy, and history of art. I believe these disciplines had a strong impact on what I accomplished in my career, especially when it came to selecting

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. research problems that carried with them a degree of intellectual aesthetics. After graduation from high school, my aspirations were to study phi- losophy. I was lucky, however, that among my family’s friends were Raf- faele Girotti, the CEO of ENI, the Ital- ian energy company, and Raffaele Mattioli, the president of Banca Com- merciale Italiana, the most important Italian bank, where my father worked. Mattioli was dubbed “the Renaissance banker” because of his activities in humanistic studies. Girotti told me Alberto Sangiovanni-Vincentelli and the Italian crowd of present and former students at the many wonderful stories about indus- 2001 Kaufman Award ceremony in San Jose. try and managing a large company. Mattioli convinced me to look into electronics as the way of the future one that I have tried to instill in deep meaning of interdisciplinarity: (it was 1965!) and to love economics all the students who have had the to be outspoken when it comes to for its intellectual challenges. Con- misfortune of crossing my path. In the search for the truth and to de- sequently, instead of following my the Anglo-Saxon and German tradi- spise bending in front of the pow- fantasies in the humanities, I ended tion, by contrast, engineering has erful for personal gains. With such up in engineering (at the Politec- not been considered socially or in- an education, I had little choice but nico di Milano, then considered the tellectually important (after all, the to pursue an academic career at the best school in Italy). My older son, people who fix your bathroom in a Politecnico, where I early on became Andrea, who is now teaching phi- hotel are called engineers). At the a professore incaricato (associate losophy at King’s College in London, Politecnico, I fell in love with re- professor). During this period, I had later vindicated me and fulfilled my search and education, inspired not the good fortune of being associ- early academic dreams. I finished only by my research advisor, Vito ated with my old friend Mauro San- high school in 1966, just when the Amoia, but also by others (Guido tomauro, with whom I shared years events that originated at the Univer- Guardabassi, Emanuele Biondi, Fran- of study and research work, as well sity of California, Berkeley, were tak- cesco Brioschi, Francesco Carassa, as an office at the Politecnico. ing Europe by storm. Berkeley was Luigi Dadda, and Emilio Gatti) who My research focused on the math- not only important to me for that gave me a taste for interdisciplinary ematical aspects of electrical circuit but also for a scientific reason: in 1959, Emilio Segre, an Italian physi- cist, won the Nobel Prize for his work While studying at the Politecnico, I met there. I was 12. I vividly remember my first scientific mentors, who inspired me my amazement when I read papers with their idea of engineering as a noble and by Giancarlo Masini, a science writer I would meet many years later after I intellectually rich endeavor. came to Berkeley. In these papers, I read about the mythical Berkeley, research touching many different analysis. During this early period, the view of the bay from its hills, its fields: from control theory to bio- I started reading papers on circuit eccentric students and faculty, the engineering, from optimization to simulation by Robert Brayton, which I earthquakes, the freedom and the communication, from computers to found most fascinating. Brayton influ- excitement you could sense every- electronics. In particular, Giuseppe enced my research in EDA more than where—things that I learned to love Grandori taught me about the ethi- anyone else in the field, and I learned and cherish (except the quakes). cal factors in civil engineering and about a computer program, SPICE, While studying at the Politecnico, about the trade-offs between design that was being developed at Berkeley. I met my first scientific mentors, efficiency, elegance, and robustness. My mentors at the Politecnico who inspired me with their idea of Mario Silvestri, who was an accom- encouraged me to go to the United engineering as a noble and intel- plished scientist in nuclear engi- States to improve my research skills. lectually rich endeavor. This is a neering but also a most respected In 1975, I chose Berkeley as the place tradition inherited from the French, and gifted historian, taught me the to be, given my interests. Little did I

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To begin, I must say that I have zero ties in the EDA community. This in develop a family of loosely time-triggered architectures. I was fortunate and of itself illustrates the fact that Alberto Sangiovanni-Vincentelli has to be part of this train, so I could see up close how quickly and deeply had an influence that extends far beyond his original community. His Alberto works. vision of system design triggered research on systems design in both But there is more. I remember several of Alberto’s keynote addresses, computer science and control science. in which he explained how advances and novel approaches to systems Alberto is well known for his invention and promotion to a very wide design could lead to a reorganization of the whole business of some audience of the concept of platform-based design (PBD). PBD allows industrial sectors. By supporting orthogonalization of concerns, PBD for a “uniform description of systems at any level of the design hierar- would allow for a drastically different approach in building a system chy (be it function or architecture)” and supports the “orthogonaliza- from subsystems: subsystems would not be constrained to be divided tion of concerns.” “spatially” or “horizontally” (as a car consists of an engine, a chassis, The consequences of the PBD concept indeed pushed far beyond the and so on), nor would they be divided “vertically” (into basic and appli- important drivers in systems design mentioned above. Since the impor- cation layers). Instead, they could be split in a much more flexible way. tance of model semantics when dealing with functions had been firmly Thus the topology and geography of supplier chains and OEM/supplier established in the computer science community for years, it became relations would become richer and more flexible but also more com- obvious that doing the same for architectures was equally important. plex to manage. How should system integration be controlled in such a Hermann Kopetz’s time-triggered architecture (TTA) idea is probably context? It turns out that a great deal of ongoing research by the embed- the major achievement in this direction for the embedded systems sec- ded systems community around interfaces and design by contracts was tor. TTA obeys the simple and elegant mathematical model of strict syn- motivated by Alberto’s vision of the future of systems design. chrony, where a global clock triggers the entire system. While acting as —Albert Benveniste an ideal logical clock throughout the system, this clock is built on top of physical time, thanks to adequate protocols. For a long period, there About the Author were not many architectures for real-time embedded control systems Albert Benveniste has a dual background in control science and com- in existence that relied on a precise model of computation and com- puter science. He has made important contributions on system identifi- munication. Alberto’s promotion of PBD suggested that there should be. cation in control science. He is a coinventor of the Signal synchronous This gap was first identified in the early 2000s by Paul Caspi, and Al- language in computer science. He also has research interests in telecom- berto and several of his colleagues then joined together to propose and munications. He received the CNRS Silver Medal in 1990, was elected an IEEE Fellow in 1991, and received the Grand Prix France Telecom of Digital Object Id entifier 10.1109/MSSC.2010.937694 the Académie des Sciences in 2008.

know that I was going to spend 35 faculty, even in Italy. Once more, I of my 35-year life in Berkeley. Rich- years there! Interactions with the had to take my family to Berkeley. ard initiated me into the world of systems faculty members—in par- The academic year 1976–1977 was computer-aided design (CAD) and ticular Charlie Desoer, Lucien Polak, the most challenging one in my computing in general. His influence Leon Chua, and Ernie Kuh—marked career, but I survived and, much to was crucial. I then collaborated with my early days in Berkeley. After six my surprise, my teaching evaluations the integrated circuit faculty on sev- eral projects and moved closer to this area, while maintaining my intel- My mentors at the Politecnico encouraged lectual ties to the systems domain. me to go to the United States to improve my By 1980, I was fully convinced that CAD was going to be my future. research skills. That year marked the beginning of a wonderful collaboration with Rob- months I returned to the Politecnico, were good. I ended up applying for ert Brayton and Gary Hachtel that but Leon Chua insisted I return for a position in the systems group, lasts to this day. It all started with another year to teach his classes (he encouraged by Chua, Desoer, and my one-year (1980–1981) visit to the won a Berkeley research fellowship Polak, and I was eventually hired as math department of IBM’s T.J. Watson and could not teach the following an assistant professor (dicey consid- Research Center. During this period, year). I resisted the idea very much, ering I already had tenure in Italy, the foundations of EDA had been set. given my lack of English proficiency but danger is my vocation). In the remainder of this article, I will and my ignorance about the U.S. When I joined the faculty, I started examine the evolution of the field teaching system, but I had under- interacting with Richard Newton. (as I see it) to the present day, along estimated the power of the Berkeley This became the most exciting aspect with some future projections.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. Corsi e Ricorsi Storici heroes is characterized by the use of associate these three periods with (Recurring Cycles in History) imagination, which lets us supersede the ages of gods, heroes, and men, Going through the proceedings of sensory information to arrive at our as outlined by Vico. the DAC and the International Con- first abstract interpretations of real- ference on Computer-Aided Design ity. It is the age of creativity, the foun- The Age of Gods (1964–1978) (ICCAD) as well as articles in journals dation of the great achievements of In this period, the foundations of such as IEEE Transactions on Circuits humankind. The period that follows, EDA were laid out. I was surprised and Systems and IEEE Design & Test the age of men, is characterized by while browsing among the early of Computers to hunt for relevant the use of reason, i.e., rational analy- EDA papers to find seminal work papers was indeed a formidable task. sis that dissects events. In this period, that still has a strong impact today. (To avoid consuming much of the novelty and creativity are feared as I classified the papers by relevant space allotted for this paper with a leaps made in the dark because analy- topic, and I clustered fundamental long list of references, I will quote sis cannot guarantee the success of contributions in six areas: circuit authors’ names and their basic con- the initiatives. Vico identified the age simulation, logic simulation and tributions. Readers can make use of men as the beginning of a societal testing, MOS timing simulation, of the wonderful work of the DAC decay and proposed that after the printed circuit board (PCB) layout organizing committee, which has decadence of this period, human- systems, wire routing, and regu- produced a disc containing all the kind would loop again through the lar arrays. papers published in the proceedings three stages, returning first to the of the DAC and in IEEE Transactions age of gods. Relevant Technologies on Computer-Aided Design of Inte- grated Circuits and Systems, IEEE The Ages of EDA Circuit Simulation Design & Test of Computers, and the Surprisingly, I found that I could Circuit simulation has always been proceedings of ICCAD, to identify the identify similar “ages” in the history an important topic for EDA, espe- precise contributions.) cially in the area of IC While doing this work, design. I would argue I looked for regular that the great success Design Automation Conference Attendance patterns that could be 25,000 of circuit simulation in used to understand the Total* Attendance important IC designs history of the field and 20,000 Conference Only was the dominant rea- its destiny. son for the birth of 15,000 Aided by my back- EDA as an industry. IBM ground in classics, 10,000 researchers were the I found unexpected most prominent force help in the work of a 5,000 in these years: Frank compatriot: Giovanni Branin was a pioneer 0 Battista Vico, the 17th- in determining the

century philosopher 1964 1966 1968 1970 1972 1974 1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 architecture of a circuit who analyzed history simulation. In my opin- and its patterns from FIGURE 1: DAC attendance, 1964–2009. ion, Brayton, Hachtel, a philosophical point and their colleagues at of view in his masterpiece Scienza of EDA. I would like to take you on IBM’s T. J. Watson Research Center Nuova (1725). Vico’s fundamental a fascinating voyage through them. in Yorktown Heights, New York, who contribution was that history repeats To determine a time span for each, I introduced all the algorithms that lie itself in a regular pattern; he called used DAC attendance data, as shown behind circuit simulation as we know these cycles corsi e ricorsi storici. in Figure 1. it today, from sparse matrices to Vico identified three phases in In the figure we see an initial backward differentiation formulae, the history of humankind: the age of period from 1964 to 1978 during made the fundamental, revolution- gods, the age of heroes, and the age which attendance was small, fol- ary contributions to this field. They of men. The age of gods is character- lowed by a period of great prosperity enabled the development of two ized by the knowledge that comes to from 1979 to 1992 with a very sharp important programs: ASTAP (at IBM) us from the use of our senses; in this increase in participation. Then comes and SPICE (at Berkeley). At Berkeley, respect, events and natural phenom- a period of relative stagnation, from the early contributions of Ron Rohrer ena are inexplicable for the most part 1993 to today, with the last couple and Don Pederson were essential in and are attributed to “external” enti- of years showing a marked decrease making SPICE the workhorse for cir- ties like the ancient gods. The age of in attendance. It seems natural to cuit simulation for many years.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. GETTING ACQUAINTED WITH PROF. PARSLEY

In life, one rarely plans on nurturing an acquaintanceship or a consultant in the design area. At that time, my contact with SDA had friendship. Generally, things start by themselves because of some more to do with J. Solomon, its CEO, who was a colleague of mine at event and then move forward because another sequence of events Motorola Semiconductors in the 1970s. occurs. Only after a while does one start to realize that a relation- I consider therefore that my real acquaintance with Alberto actually ship can also be planned, for instance by involving both people in began during one of the regular “market vision meetings” that P. Pistorio a common project. (the CEO of SGS and then of ST for 20 years), who knew Alberto long This is exactly what happened in the course of my relationship with before I did, used to organize for his entire staff. These occupied a full Alberto Sangiovanni-Vincentelli, which can now be called a professional day of each year, regardless of outside market conditions. Pistorio, a friendship—or more simply, a friendship. visionary leader, wanted his staff to step back from all daily problems for I am not an EDA expert, nor am I a fan of EDA; I did, however, rely heav- one day each year, and Alberto was regularly chosen to be a “resource ily on EDA systems from their inception so that my group could perform leader” and facilitator on those occasions. its development work using the best design methodologies available. It was there that I really started getting to know Alberto. I appreciated In the mid-1980s, while I was running a subsidiary of STMicroelec- his long-term view, which extended far beyond any time frame I was tronics (SGS Microelettronica at that time) named IST and searching for used to operating in and focusing on. This was and still is my perspec- the best automated design system available, I met Prof. Sangiovanni- tive in looking at Alberto. I am simply not equipped to take part with Vincentelli for the first time. We were evaluating an EDA system that him in a dialogue based on the mathematical equations underneath a had just been developed by a new U.S.-based start-up, SDA, the nucle- simulation program. us around which Cadence was eventually formed. This EDA evaluation I clearly remember, for instance, during one of these “vision meet- exercise ended with the execution of the first agreement signed with ings” in the late 1980s, that Alberto forcefully said, “The PC is dead.” SDA/Cadence by an affiliate of the SGS group. The agreement was then Whether these were his exact words I cannot recall, but this was exactly expanded to the full corporation and later further expanded to the new the concept he expressed. STMicroelectronics group formed by the merger of SGS with Thomson This was the beginning of the PC era, remember. So this statement Semiconducteurs, towards the end of 1987. was simply shocking, and it was obviously thrown on the table to pro- This first meeting with Alberto was rather casual. He was one of the voke us—in a positive way—to adopt a certain thinking pattern. Alberto founders of SDA and was already involved with SGS as a technical wanted to prepare us to think in terms of future evolutions accompanied by possibly dramatic changes, changes that are now actually happen- Digital Object Id entifier 10.1109/MSSC.2010.937695 ing, 20 years later.

Logic Simulation and Testing MOS Timing Simulation The infamous Lee maze router devel- Logic simulation had already been in The process of exploiting the quasi- oped in 1961, before the first DAC, is use for some time when DAC started. unidirectional characteristic of a still the basis for most of the routers Computer companies such as IBM and MOS transistor to speed up circuit in current use. The Hightower line CDC were relying on this technology simulation was first described in the extension algorithm dates back to to debug their logic design. The con- work of Hermann Gummel and his 1969, and the idea of channel rout- tributions to this field were countless. colleagues at Bell Labs in 1975. Gum- ing arrived in 1971 with the work of The founding fathers of the field also mel’s intuition was to approximate the Hashimoto and Stevens. played a fundamental role in devel- solution of the ordinary differential oping automatic test pattern genera- equations describing the circuit equa- Regular Arrays tion and fault simulation. The roles tions with a fast relaxation–based With the advent of large-scale ICs, the of Ulrich, Hayes (at the University of heuristic algorithm. The insight was appeal of regular layout patterns for Michigan, Ann Arbor), Breuer (at the to recognize that when analyzing the reducing design time was strong. Gate University of Southern California, Los timing of a digital circuit, it is not im- arrays (called “master slices” at IBM) Angeles), and Szygenda (at the Uni- portant to have accurate waveforms and standard cells (“master images” versity of Texas at Austin), to name a as long as the switching events can at IBM) were developed as alternatives few, were invaluable. The invention of be placed in time correctly. Fast cir- to custom layouts. At IBM and Bell the level-sensitive scan design (LSSD) cuit simulation is still based on this Labs, integrated tools for the auto- methodology by Tom Williams and idea today. matic layout of circuits using these colleagues and the consequent devel- design styles were extensively used opment of the D-algorithm by Paul Wire Routing in this period. I remember the begin- Roth of IBM changed the way in which Most of the techniques we use today ning of the idea, when a gate array IC computer hardware was designed and in our tools are based on the results had four gates and a researcher from test patterns generated. that were obtained in this period. Schlumberger discussed the use of

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. Since then, from time to time I began to call on Alberto, primarily more, as I have already hinted, a continuously growing acquaintance when I needed a “strategic sounding board” to refine my thinking pro- either leads to a very difficult relationship that is eventually broken off cess at a level above the running of daily operations. or to a friendship. There is nothing in between. Happily, Alberto and I Maintaining a good balance between a long-term view and short-term have ended up becoming friends, a status occasionally blessed by an concrete operational management is a crucial element of success. Alber- excellent bottle of wine. to has definitely been instrumental in helping those of us whose respon- These days we are directly or indirectly involved in several projects sibilities are primarily operational not to lose track of the big picture, together, and we must interact at least once a week—not very common especially in moments when operational issues seem most pressing. in our business. The only problem is that when I have to locate Alberto, My interaction with Alberto increased greatly beginning in the mid- I never know in which time zone I will reach him. He is ubiquitous! 1990s, when I was called on to run STMicroelectronics’s New Ventures Here in Italy, our grandparents used to say, “The parsley grows every- Group, whose mission was to “incubate” new businesses within the where.” It is true: just a bit of wind carrying some seed and then some company. Some were destined to be eliminated after an initial trial pe- rain, and you can see it growing. Alberto is “always everywhere,” ready riod; some were eventually consolidated with larger STMicroelectronics to stimulate visionary thinking in all corners of the world. It is truly so, product groups; some were proposed as spin-off projects, if doing so led Prof. Parsley! to a better structuring of the approach to that specific business. —Piero Martinotti Alberto has been very instrumental in helping me plan the spin-off of a fingerprint-based biometrics business from STM. It became Upek, About the Author a U.S.-based company that today is a leader in this rather specialized Piero Martinotti began his career at SGS as an application and market- niche. Following the creation of Upek in 2004, and as a closing of the ing engineer. In 1968, he moved to Motorola Semiconductors as direc- loop of our cooperation on the project, the two of us found ourselves tor of strategic marketing for Europe and later became marketing and sitting on the board of Upek, where we still serve. sales director for Europe. He left Motorola to become managing director There I discovered another Alberto: a director with great sensitivity to at Weber Carburatori, part of Fiat Group. In 1981, he returned to SGS and experience in modern governance matters. These qualities all relate to head its growing MOS division; he later became corporate director to Alberto’s long association with several other company boards, in both for technology and strategy. In 1986, he was appointed CEO of Innova- the United States and Europe. In my experience, I have rarely encountered tive Silicon Technology, part of the SGS Group. In 1990, he was asked sensitivity on critical governance matters at the level Alberto provides. to take charge of corporate strategic planning for SGS-THOMSON Mi- Alberto for me is not so much the EDA guru of Berkeley or the profes- croelectronics, which became STMicroelectronics in 1998. In 1994, he sor of electronics but one of the most stimulating thinkers and vision- was appointed general manager of STMicroelectronics’s New Ventures aries in the field where I have operated for the last 40 years. Further- Group. He is currently an independent technology business adviser.

automated tools to optimize the use During this period, the first-gener- limited sales volume available to of the circuit. Look at the distance we ation CAD companies were founded. support those investments. have covered: in 40 years, we have Applicon was established in 1969, ■ They developed only limited cus- gone from four to 400 million gates Calma in 1970, and Computer Vision tomer loyalty, due to the per- on a single chip. in 1972. They all supported pretty ceived small size of the value much the same design activity: art- added by their products. The Business Side work editing on customized work- ■ They had a limited understanding CAD was considered to be of strategic stations. Their business model was of market evolutions and custom- value to the systems industry, and in centered on the sale of the worksta- er needs. particular to the computer industry. tions; the software was considered These factors contributed to a IBM and the other large companies an add-on to the hardware. Of these complete lack of innovation capabil- dealing with computer design consid- first-generation CAD companies, ities and eventual obsolescence. ered it so important that it warranted none is alive today. We can identify a sizable investment in funding and several causes for their demise: The Age of Heroes (1979–1993) resources. Internal CAD groups were ■ Their products’ architecture con- It is surprising to see that between powerful organizations in engineer- sisted of customized hardware 1979 and 1993, the EDA field exp- ing. Looking at the DAC proceedings, with complex software written loded in all its aspects. To be at we can also see a strong presence on mostly in assembly code. It was DAC in this period was an incredible the part of the Japanese computer very difficult for them to keep experience. The vibrancy and enthu- and communication systems indus- abreast of technological advances siasm that permeated the presenta- try in papers describing unified because of the investment needed tion rooms and the exhibits were approaches to system design using to design novel workstations, giv- clear signs of the healthy growth tools, thus showing the strategic en the concomitant severe soft- of the community. So many essen- value of the technology worldwide. ware porting problems and the tial contributions were made in all

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 11

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. aspects of EDA, from physical veri- and investigated acceleration tech- early 1990s elevated formal verifica- fication to layout synthesis, from niques that made this approach one tion to higher levels of abstraction. logic synthesis to formal verifica- of the most studied, even in numeri- They tackled the problem of veri- tion, from system-level design to cal analysis circles. fying whether a sequential system hardware acceleration. The technical Simulation for digital circuits, represented by an FSM would satisfy community expanded its expertise with accuracy falling in between a property described with a logic to include nonlinear and combinato- what could be achieved with cir- proposition defined on the states rial optimization, control, artificial cuit and logic simulation but with and transitions. intelligence, and logic. In its quest two orders of magnitude or more In the testing area, the famous for new methods and tools, the com- of speedup versus SPICE, yielded PODEM-X program, based on the D-al- munity also explored some avenues the work on MOSSIM by Randy Bry- gorithm, saw the light of day at IBM that did not yield the promised ant in 1980. Interconnects started under the direction of Prabhu Goel results. There were years when showing their impact as geometries in 1981. papers using expert systems and scaled down. The interconnect delay neural networks were dominant in model introduced by Penfield and Layout the conference; panels of all kinds Rubinstein in 1981 was extensively At the representation and basic discussed the potential impacts of used. Interconnect simulation was manipulation level, artwork edit- these methods. I personally disliked tackled by Pileggi and Rohrer at ing saw a fundamental change. these approaches, as they were miss- Carnegie Mellon University in Pitts- In the previous period, designers ing a deep analysis of capabilities burgh, resulting in their findings used different data repositories for and limitations. Indeed, little is left on asymptotic waveform evaluation each of the design steps and went today to show their impact, and I am (AWE) in 1988. through a great deal of tedious glad to report that no papers in these Formal techniques first aimed to translation work from one data areas were presented since 2002. answer the question of whether two format to another. Newton’s work In these years, the most suc- at Berkeley in the early 1980s cessful EDA companies were with the Squid, Oct, and VEM founded. The most prominent tools and Ousterhout’s with research groups hired a num- the Magic systems revolution- ber of people who fo cused on ized the field by showing that EDA for their thesis work; there it was possible to have a uni- was strong pressure from stu- fied database and graphical dents to enter this area. user interface. The impact As with the age of gods, I of this work cannot be over- have classified the main con- emphasized. The SI2 Open tributions made during these Access initiative is based on years, clustering them by topic. Newton’s seminal work; some of the data representation for Relevant Contributions Alberto Sangiovanni-Vincentelli at the 2001 Kaufman advanced physical design is Award presentation. based on corner stitching as Verification and Testing introduced by Ousterhout. In this field, there were two main different networks of gates com- Another revolutionary idea was lines of work: one was focused on puted the same Boolean function. brought to the fore by the work on making circuit simulation orders of The first use of formal verification silicon compilation and layout lan- magnitude faster than with SPICE, was by Bahnsen at IBM, during the guages done at around the same the other on formal techniques to age of gods. The seminal work by time at MIT (by John Battali), CalTech prove that the circuit would per- Randy Bryant on binary decision (by Carver Mead’s group with the form the correct function. In the first diagrams (BDDs) in 1986 revolu- Bristle Block silicon compiler), and domain, the work done around 1980 tionized the field by introducing a Bell Labs (by Hermann Gummel and on relaxation-based techniques and canonical form for Boolean func- his colleagues and by Misha Buric mixed-mode simulation by (among tions and very fast manipulation and others with the L layout lan- others) Lelarasmee, Newton, Ruehli, algorithms. The work by Coudert guage). The idea was to inject some and me provided the basis for the and Madre on finite-state machine portion of computer science culture fast MOS simulators in use today. (FSM) equivalence using BDDs and into IC design. While the approach Following this period, Jacob White, a that of Ed Clarke, Joseph Sifakis, was intellectually elegant and pow- student of mine, fully characterized Ken McMillan, Dave Dill, and Bob erful, there is not much of it left in the waveform-relaxation algorithm Kurshan on model checking in the present-day tools.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. In 1980, Kirkpatrick and Ge- work and somewhat independently, I asserted that test pattern genera- latt, two physicists who used their another approach to Boolean opti- tion and logic synthesis were indeed knowledge of spin systems to de- mization was initiated at IBM in two faces of the same coin. The work velop this technique, introduced 1979 by Brayton and Hachtel, in col- by Keutzer, Devadas, Malik, McGeer, simulated annealing at IBM to solve laboration with Newton and me at and Saldanha in collaboration with a placement problem for gate array Berkeley. This method utilized the Brayton, Newton, and me produced a layout. Once the approach was made two-level logic optimizer ESPRESSO number of results in redundancy re- public, a great deal of research on and the multilevel logic optimizers moval and delay testing using logic- efficient implementation of the al- Yorktown Silicon Compiler and MIS. synthesis techniques. New testing gorithm and on its theoretical prop- The work, supported by the Defense algorithms came out from V. Agrawal, erties began. Customization of the Advanced Research Projects Agency Tim Cheng, and others that revealed algorithm took place for standard- (DARPA), spanned a period of more the cross-fertilization taking place cell and macro-cell layout, as well as than ten years. In the early stages between the two fields. for global routing. Most of the major of its development, MIS (adopted In the mature period of logic companies, from Intel to DEC to by all major companies, including synthesis, Coudert and Madre were Motorola to Texas Instruments (TI), DEC, Honeywell, Intel, Motorola, able to speed up logic synthesis used the TimberWolf system written Philips, STMicroelectronics, and TI) algorithms considerably by using by Sechen, then a student of mine at was technology-independent; Bool- BDDs based on CNF representa- Berkeley, for the layout of standard ean functions were manipulated and tions of Boolean function. cells; it was followed by a version optimized. Later, this was followed for macro-cell layout. In these years, by a technology-mapping step that Hardware Description Fabio Romeo, Debasis Mitra, I, and mapped the optimized Boolean func- Languages most notably Greg Sorkin with his tion to a library of gates. For this sec- The technical work that has been seminal thesis contributed to the ond phase, the common approach characterized as logic synthesis understanding of the mathematical was to use rule-based techniques, would have been better classified as properties of the simulated anneal- as in the SOCRATES system devel- logic optimization, since the algo- ing algorithm, going beyond the oped at GE by Aart DeGeus and his rithms were changing a Boolean rep- analogy to spin systems and laying colleagues. When I met Kurt Keutzer resentation of a digital circuit into an the foundations for statistical opti- mization techniques. In these years, we also saw a High-level or system-level design is a bridge great deal of interest from theo- retical computer scientists towards to the future. the combinatorial aspects of lay- out design. The work of Rivest and Pinter on routing at MIT and of Karp at a talk at Princeton in 1982, he optimized, equivalent one. Synthesis and his students on placement and showed me how the work of Aho and implies a bridge between two layers routing at Berkeley was an example Ullman on compilation could be used of abstractions. Hardware descrip- of this involvement, a clear sign of to obtain a very efficient technology tion languages (HDLs) were born to the success the EDA field was hav- mapping. The idea was to formulate represent digital systems more effi- ing in attracting contributions from the problem as a tree-covering prob- ciently and compactly than Boolean other communities. In these years, lem and use dynamic programming functions. The real synthesis job was the work of Kuh at Berkeley yielded to solve it, a great idea that survives then to map an HDL description into integrated layout systems for macro- in most of the logic-synthesis sys- a netlist of gates. Unfortunately, the cell design and point tools for place- tems in use today. The work in Japan development of HDLs at the begin- ment and routing that had a great at Fujitsu, NEC, and NTT was out- ning was independent from the work impact in the field. standing, producing working logic- on logic optimization. This implied synthesis systems that were mostly that not all constructs of HDLs, such Logic Synthesis based on the original work of Darrin- as Verilog, which was proposed by A seminal paper by Darringer, Joyner, ger at IBM. Moorby and colleagues, and VHDL and Trevillyan introduced logic syn- Logic synthesis was a great achieve- could be tackled by logic synthesis thesis into the EDA vocabulary in ment of our community. As such, it algorithms. We then had to restrict 1979. They used rule-based peep- gave rise to a large number of papers the use of these languages to what hole optimization to generate effi- and interests in related fields. I gave was called their synthesizable sub- cient gate-level representations of a a keynote address at the Internation- set. While HDLs were indeed a major design. Immediately following this al Test Conference in 1985 in which advance, greatly reducing design

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. DON PEDERSON AND RICHARD NEWTON, EDA PIONEERS

Don Pederson, who died in 2004, was a pio- neer in IC design and CAD. He graduated from Stanford University in Palo Alto, California in 1951 and after a period at Bell Laboratories, joined Berkeley in 1955, where he taught and carried out research until his retirement in 1991 (and even after). He developed the Berkeley IC manufacturing laboratory, one of the first in the country at a university. In 1971, with Ron Rohrer, he started developing what in 1975 became SPICE, a circuit simulator that ended up being for many years the most used IC CAD program. His philosophy was that CAD had to be driven by design: he always looked at software tools as a means of obtaining better designs, never an end in themselves. He insisted that all tools developed in his group be in the open domain. This view marked the development ship on the boards of several companies, and his tenures as chairman of of CAD research at Berkeley and ended up being the general policy of the the Department of Electrical Engineering and Computer Sciences first and Department of Electrical Engineering and Computer Science at Berkeley dean of the College of Engineering. Even those who did not know him for software developed by faculty and students. It was at the foundation well lost a friend on 2 January 2007, when he passed away at the age of of the open-source movement. He was instrumental in attracting Richard 55. Richard was not only a wonderful engineer and a superb professor but Newton from his native Australia and convincing me to focus on this also a great man. He would not rest on the laurels of his (many) industrial exciting field. Pederson was awarded the 1998 IEEE Medal of Honor in and academic successes; rather, he relentlessly pursued noble causes that addition to many other awards. He was a member of the National Acad- could (and did) have an impact on the human condition. Nothing was too emy of Sciences and the National Academy of Engineering. hard for him. He would complain at times and seem distressed, but he Richard Newton was a great person and a great friend. He came to would never abandon an idea he believed in. He was not detail-oriented. Berkeley as a graduate student to work in Don Pederson’s group in 1975 Richard liked big, audacious ideas, and as soon as he saw a way of mak- when I arrived from Italy as a visitor to the department. From that time ing them become a reality he would move on to something bigger and on, we worked together, forming a strong personal bond that let us share better, letting others to work out the details. I wrote a paper shortly after many exciting adventures, including founding Cadence and Synopsys. his death [“Remembering Richard,” IEEE Trans. Computer-Aided Design, Richard had a unique gift: he could “sense” the future and act to direct vol. 26, pp. 1357–1366, Aug. 2007] that I hope can serve to give an un- it. His accomplishments are many, including his VC activity, his member- derstanding of a little of what he accomplished.

time by introducing verification that the adoption of two standards and his colleagues. The great advan- early in the design cycle, the need for a single task is in general a bad tages it provided in performance for subsetting showed they had idea: “Adoption of VHDL was one of gave rise to strong activity in the in- problems on the semantic side. the biggest mistakes in the history dustrial domain, where a number of The HDL battle was a very inter- of design automation, causing users new companies were formed to serve esting one during these years. Ver- and EDA vendors to waste hundreds this market. ilog was a proprietary language of millions of dollars.” The idea of hardware acceleration (Gateway Design was selling a Ver- was extended to other EDA fields, for ilog simulator and licensed the lan- Hardware Acceleration example, wire routing (by Ravi Nair guage), while VHDL was born as an All EDA approaches require a massive and his colleagues at IBM), but due open standard supported by DARPA amount of computing time to execute to the limitations of the algorithms within the VHSIC program. We had complex algorithms on very large implemented it did not have enough countless debates about the superi- sets of data. During a great expansion appeal to duplicate the interest gen- ority of one language over the other period for the technology, the appeal erated by the YSE. at DAC. When Verilog was made pub- of customized hardware to speed up In parallel with this work, an al- lic, there were only cosmetic differ- the execution of EDA algorithms was ternative idea was pursued: using ences between the two, even though huge. As usual, IBM—which I believe general-purpose parallel computers you would find people strongly is the single institution that had the to achieve similar performance ad- attached to one or the other, accord- most impact on the field—proposed vantages but with a lower develop- ing to their personal tastes. Joe Cos- a special-purpose architecture for ment cost. In the late 1980s, there tello, in his keynote talk at DAC in logic simulation, the Yorktown Simu- was a great deal of interest in parallel 1993, was very eloquent in arguing lation Engine (YSE), devised by Pfister architectures in the computer design

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. community. The Thinking Machine, tapped source of important results produced results that had some a massively parallel architecture de- for EDA and other engineering ap- degree of success in the industrial signed by Danny Hillis at MIT, gener- plications, but the fundamental domain. These include the work ated excitement in the research and problem of software support for at IMEC by DeMan and Rabaey on industrial communities, including parallel computing must be solved the Cathedral system and the hard- our own. A company (Thinking Ma- before this technology can be of ware-software codesign approach- chine Inc.) was created, tasked with widespread use. In particular, the es embedded in systems such as disseminating this approach to com- advent of multicore microproces- Flex, developed by Paulin; Cosy- puting, and it attracted some of the sors is opening up a wealth of great ma at Braunschweig University of very best minds in the field. I was opportunities for EDA algorithms. Technology in Germany; and POLIS fortunate to be called on to partici- A flurry of early announcements of at Berkeley. pate in the company at its inception existing tools converted to multi- During this period, Edward Lee as a fellow, during my sabbatical core architectures has hit the press developed Ptolemy, and Harel devel- year in 1987, spent at MIT. release treadmill. oped state-charts for design capture This was another defining mo - and verification at the algorithmic ment of my career. The atmosphere High-Level Design level. Both represent work that is of the company had some of the High-level or system-level design is affecting current approaches to em- characteristics of the Renaissance a bridge to the future. We all agree bedded system design. In software period in the arts and literature. that raising the level of abstraction is design, Berry at École des Mines in For example, the routing algorithms essential in order to increase design Paris, Benveniste and Le Guernic at for the communication among pro- productivity by orders of magnitude. INRIA, and Caspi and Halbwachs cessors were designed and imple- I am indeed very passionate about at Verimag proposed synchronous mented by Dick Feynman, a Nobel this field, and I believe our future languages (Esterel, Signal, and Lus- laureate in physics, who spent a is pinned to the success of design tre, respectively). great deal of time on Thinking Machines’s premises. Impromptu debates about algorithms and appli- The vibrancy and enthusiasm that permeated cations were common; seminars by the presentation rooms and the exhibits the most prominent scientists of were clear signs of the healthy growth the time were organized every day. My students and coworkers (Andrea of the community. Casotto, Roberto Guerrieri—one of the most creative people I have ever methodologies and tools in this area. Relevance of EDA Research met—and Don Webber) developed The foundational work began in the in the Scientific Community algorithms for circuit and logic sim- 1980s with high-level synthesis (e.g., During this period, EDA research ulation, as well as for placement and the work of Thomas, Parker, and was in the spotlight and was equally routing, that were customized for Gajski). Though this work started pursued in electrical engineering and the Thinking Machine. The lack of up almost in parallel with logic syn- computer science. The relevance of understanding that complete solu- thesis and several commercial tools the work is reflected by the number tions rather than hardware were were developed, there has not been of awards that EDA researchers col- what mattered to final users, how- a wide acceptance in the design com- lected and by an astonishing statis- ever, limited the industrial use of munity for this approach. Much still tic: in the early 2000s, “Optimization the Thinking Machine to research needs to be done. by Simulated Annealing” (Kirkpatrick laboratories and eventually led to its The basic questions to ask are, et al., 1983), “Graph-Based Manipula- death, much to my chagrin. It was a What made logic synthesis success- tion of Boolean Functions” (Bryant, wonderful attempt at marrying sci- ful, and what made the adoption of 1986), and “State-Charts: A Visual entific excellence to business. high-level synthesis so difficult? I Formalism for Complex Systems” Other parallel architectures such believe that the original work on (Harel, 1987) were the three most as the N-cube, the Sequent, and the high-level synthesis was too gener- cited papers in computer science. Intel hypercube, were actively pur- al: too many alternatives had to be (See the NEC CiteSeer database.) One sued and used in EDA during this explored, and tools had a difficult could argue that these data do not period. There has been no commer- time beating humans at this game. show scientific excellence but rather cial tool sold on these machines, When system-level design was fo- that our community is more gener- however. I believe that parallel cused on constrained architectures ous in quoting other people’s work computing with various degrees of such as DSPs and microprocessor- than more traditional computer sci- heterogeneity is still a partially un- based architectures, however, it ence areas, but this still reflects very

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. positively on the EDA studies of several companies, including National tributed US$1 million each) while these years. Semiconductor, became dependent several venture capitalists (VCs) led on software that was created at Berke- by Don Lucas contributed another The Business Side ley. Don Pederson’s policy was to US$1 million. The company endured The second- and third-generation leave all the results and all the soft- a difficult period until 1986 due to EDA companies were formed during ware that was developed at Berkeley product delays and other difficul- this period. The second-generation in the open domain. Indeed, the birth ties, but in the end, with the help companies, Daisy, Mentor Graphics, of the open-source movement can be of a particular partnership model and Valid, were created in the 1980– traced back to this decision. This idea (again, a new business idea), SDA 1981 time frame to serve the digital made it easy to disseminate research was finally profitable. Joe Costello design market with schematic data results and favored the adoption of was behind the push towards this capture and simulation on worksta- the tools. On the other hand, it cre- business model. I helped form part- tions. Daisy and Valid built their ated serious support problems, since nerships with STMicroelectronics own workstations, in line with the several engineers were needed to cus- and Kawasaki Steel’s LSI Division. traditional approach of the first- tomize and improve the code inside The role of Jon Cornell, general generation companies, while Men- the companies. manager of Harris Semiconductors, tor sold Apollo workstations with an Jim Solomon was among the in the early days of SDA cannot be OEM agreement. For all three, hard- most vocal people to suggest that overemphasized as he sustained the ware sales were a very substantial Richard Newton and I should start company at many junctures, includ- part of revenues. a new company so that the cost ing a substantial new round when In 1982, ECAD and Solomon De- of support for the Berkeley tool the company was in distress. Jon sign Automation (SDA) were founded could be abated for the users of was also the first high-level execu- (their merger in 1987 created Ca- the technology. Both of us, how- tive to believe in my research and dence). These companies were the ever, loved research and Berkeley to support my activities with sub- first examples of “software-only” too much to contemplate the idea stantial grants. He also invited me to spend a quarter at Harris in Mel- bourne, Florida, where I learned It is surprising to see that between 1979 and how to interact with designers and convince them (or not!) to try new 1993, the EDA field exploded in all its aspects. methods and tools. James Spoto, who was in charge of EDA, became my partner in crime on many Har- companies that did not base their of leaving our academic careers for ris and industry-wide initiatives. He business models on hardware. Since the new enterprise. After a couple later joined Cadence when the Ana- I was involved in the creation of SDA, of years of searching unsuccess- log Division was formed, heading its I would like to share a tidbit that may fully for a person to lead the new engineering group. not be widely known: ECAD and SDA company, Jim Solomon volunteered Another company had a strong were actually supposed to be one to leave National Semiconductor to influence on my understanding of company from the very beginning. start ISIS (the name originally pro- semiconductor design problems Paul Huang, however, had already posed, which unfortunately was after 1978: SGS, which later became completed Dracula and wanted to already taken). We could not find a STMicroelectronics after the fusion go to market quickly, while the SDA name that was liked by all and that with Thomson. STMicroelectronics side of the equation was not quite was still available. Thus we used had participated in our endeavors ready. They merged because of the Solomon Design Automation as a in design technology at Berkeley be- decision of SDA to go public in 1987, placeholder; this name was never ginning in the early 1980s, when a on the day that is still remembered actually replaced until Cadence was stream of visitors spent time in our as Black Monday. Stock market con- formed. Richard and I helped to CAD center and participated in the ditions prevented any IPO for a few write the business plan, a team of early development of analog circuit quarters after Black Monday, how- former Berkeley students and Bell design optimization and simulation ever; Joe Costello, Jim Solomon, Labs researchers was assembled, and logic synthesis. In particular, the Paul Huang, and Glen Antle felt and the adventure began. first application of our tools was prob- that the best strategy was to merge The funding mechanism was ably a pacemaker chip developed in with ECAD. novel, as the majority of the money the early 1980s in Agrate. I was very The creation of Cadence was an came from large companies (Erics- fortunate to be able to associate with exciting period for Richard Newton son, GE, Harris Semiconductors, and leaders such as Pasquale Pistorio, Rai- and me. At the beginning of the 1980s, National Semiconductor, which con- mondo Paletto, Philippe Geyres, Piero

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. Martinotti, Aldo Romano, and Mas- 1990, however, Tom Bruggere, then In 1991, I had to make one of simo Vanzi, who were my partners chairman of Mentor Graphics, com- the most difficult decisions of in crime for more than 25 years. mented negatively on the business my career. Cadence and Synopsys During this period, Silicon Com- model of software-only companies, started competing when it became pilers and Silicon Design Labs were saying that he knew of no long-term clear that the IC design ecosys- founded around the concepts of successful EDA company that did not tem needed global players to sup- silicon compilation and symbolic sell workstation hardware. Special- port an ever increasing complexity layout. View Logic was pursuing the ized hardware-acceleration companies fueled by Moore’s law. I was then EDA market from the PC angle, aim- were also founded during that pe- faced with a heart-breaking choice: ing at low-cost solutions for digital riod, including IKOS, PiE Design, and I could not continue working with design. Gateway was formed to com- Quickturn. Mergers and acquisitions both. Aart de Geus, who was tran- mercialize Verilog and its associated have left no independent hardware- sitioning to become the CEO of the simulator. In 1987, Optimal Solutions acceleration company today. company after Harvey Jones’s ten- Inc. (OSI) was incorporated in North Even though there was a strong ure, offered me greater involvement Carolina. (I believe not many people incentive to adopt commercial solu- with Synopsys and a board position. know that this was the original name tions for IC and system companies, Incredibly, on the very same day Joe of Synopsys.) OSI was born out of the the strategic value of EDA kept Costello offered me the same posi- activities of Aart de Geus at GE with internal investment high. In particu- tion at Cadence. After two and half Socrates and out of a conviction I lar, Bell Labs and IBM were pulling very long months of agony, I ended shared with Richard Newton that ahead of the competition in tools up accepting Costello’s offer, in part logic synthesis was indeed the next and environments. because the company was forming a big step in EDA. The funding model The second-generation business new division dedicated to system- for OSI was the same as for SDA: sub- model (hardware plus software) level design, a theme I had begun to stantial support from GE and appreciate three years earlier. Harris Semiconductors (I con- I did really feel awful about vinced Jon Cornell to invest in ending the exciting work I was this enterprise as well), accom- doing at Synopsys with some panied by VC funding secured of my brightest friends and by Richard Newton, who was former students, however. starting to work in the VC com- munity as an associate partner The Age of Men (1993–2008) at Mayfield. Richard joined the In my opinion, 1993 was the be- new company’s board of direc- ginning of a new phase in our tors, and I became the chair of community. Technical innova- its Technology Advisory Board. tion started slowing down, and The original offering, based the vendor community became on an engineered version of Alberto catching up on his reading. mature from Wall Street’s point Socrates, was then enriched of view and was much less in- and substantially changed by Rick was proven unsustainable due to clined to take risks. Vico would have Rudell and Albert Wang; they were the dominance of general-purpose identified this as the passage of the both students of mine, cosupervised workstations in the years that fol- EDA community to the age of men. by Robert Brayton, who introduced lowed. Daisy and Valid died slow To quote the keynote address of my the algorithms used in MIS to yield deaths through acquisitions, while dear friend Richard Newton at the the design compiler. OSI offered Mentor reinvented itself in order to 1995 DAC: “If there is a single point the same partnership model used withstand competition and be eco- I wish to make here today, it is that with SDA to a number of companies; nomically viable. Silicon Compilers as a discipline, both in industry and this created a very strong commer- and Silicon Design Labs also disap- in academia, we are just not taking cial foundation for the company. By peared through a series of mergers enough risks.” 1990, the company had changed its and acquisitions. Silicon compilation This period coincides with the ex- name to Synopsys and had moved to in its basic form did not pay enough plosion of the Web and its applica- California; shortly thereafter, it went attention to performance and the tions. We may draw the conclusion public in one of the most successful area of the final result; layout lan- that the best energies and minds IPOs of the time. guages and symbolic layout systems in electrical engineering and com- By then it was clear that selling were not accepted by a community puter science were attracted by this workstation hardware was not an ap- used to using images and geome- emerging field and that VC fund- pealing business model. As late as tries to represent its designs. ing was therefore targeting Internet

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. HEAD IN THE CLOUDS, FEET ON THE GROUND

I met Alberto for the first time in 1978 when I was at Stanford University, ASIC project (STPC) and the Transputer core that was ported to STMi- in Palo Alto, California, for my master’s in EE and Alberto was just be- croelectronics’s technologies after the INMOS acquisition. In the same ginning his research and teaching career at the University of California, period (1985–1990), I will never forget Alberto’s strategic support during Berkeley. Those were the golden years for EDA, and lots of great ideas the finalization of STM’s EDA partnerships with SDA and with Synopsys; were under development: at Stanford under Robert Dutton (at my lab, there were very tough negotiations for several weeks with Joe Costello AEL) and of course at Berkeley by the wonderful team made up of Peder- in the first case and with Aart De Geus in the second, and Alberto’s son, Newton, Sangiovanni-Vincentelli, and those they worked with. participation behind the scenes was key. At that time, my research activity was mostly concerned with technolo- The second 15 years of our relationship focused on the development gy CAD (TCAD), while Alberto was focusing instead on circuit simulation of Accent, the fabless ASIC STMicroelectronics spin-off that Alberto and algorithms. These two topics overlapped at the transistor-modeling sponsored from the beginning. He helped me craft the strategy and level, and that was an important matter of discussion between us. What I mission of the start-up. Initially, the company was a joint venture be- appreciated most in Alberto was his great enthusiasm for what he was do- tween STMicroelectronics and Cadence; thanks to Alberto‘s support ing and planning; he was always looking ahead to the next step, bringing and ideas, within about ten years it became the number-one custom IC to bear the lofty view of a real technology visionary. When I returned to design service company in Europe and one of the top ten worldwide. Italy in 1980 to join STMicroelectronics (SGS at that time), our relation- In that period Alberto grew much closer to me and to the team because ship became still more productive. I was asked to create a new EDA team of his role as director. We all enormously appreciated his enthusiasm within SGS‘s central R&D group, and Alberto started to play the role of and technological guidance. scientific and technology adviser to the company in general and to my What I can say in conclusion is that as a man, Alberto is a wonderful team specifically for EDA. This wonderful relationship lasted for 30 years; person with strong ethical principles who brings great care to all the for half of that time he was our scientific adviser, and subsequently he human aspects of any relationship and places human values ahead of helped me create an STM/Cadence joint venture called Accent. I man- all other business or economic considerations. From a scientific and aged Accent, and Alberto became director of its board. technological viewpoint, Alberto offers a unique and perfectly balanced Besides providing constant scientific and technological support, Al- amalgam of science and business. You may see him arguing about algo- berto organized an annual one-day workshop during which we inves- rithms with a Nobel laureate one moment and hammering out business tigated new R&D topics in electronics and EDA. My team consisted of strategy with the CEO of a large corporation the next. This is a mix of about a hundred research engineers, and they always anticipated these capabilities I have found in no other prominent member of the aca- workshops with great eagerness. We continued talking about what Al- demic community. berto presented to us for several months afterwards, and for months in —Massimo Vanzi advance of the next workshop we all tried to guess what would be on the agenda. He always managed to surprise us with new topics, new About the Author ideas, and new results, however. The day of the workshop was without Massimo Vanzi is currently a technology adviser to Montalbano Tech- any doubt the most exciting moment of the year from a scientific and nology SpA and to a few more high tech start-up companies in Italy and strategic point of view. France. He is also CEO of Inocs Sarl. He serves as the adviser on tech- In addition, Alberto supported us in certain specific projects identified nology transfer to both the Ecole Polytechnique Fédérale de Lausanne in by management as the most strategically significant, such as the CP100 Switzerland and the University of Bologna in Italy. He a member of the scientific Committee of the Centre Suisse d’Electronique et de Microtech- Digital Object Id entifier 10.1109/MSSC.2010.937696 nique in Neuchâtel.

enterprises. This resulted in a lower that used a very large number of ization in Vico’s terms, I do not wish rate of innovation in EDA. At the transistors qualified as an SOC. In to take risks by assigning to research same time, the semiconductor sector my opinion (now shared by most positive or negative comments. I will continued to drive technology along companies), SOC is about integrating simply discuss some important top- the lines of Moore’s law, increasing different design styles in a coherent ics. I will leave the task of definitive the technical challenges for EDA. whole. Interdisciplinary approaches judgment to a keynote address ten System-on-chip (SOC) design started are necessary to solve the problem years from now. attracting notice, and by 2007 it had of designing complex systems posed Physical verification attracted a become the center of attention. by the advances in electronics. great deal of attention as the geom- SOC means many different things etries marched down towards the to different people. I found that in Relevant Contributions submicron range. Self-test emerged Japan and Korea, SOC meant the inte- The jury is still out as to what were as the only solution for the rising gration of memory and microproces- the fundamental contributions of cost and requirements of test equip- sors, while in other places anything this period; in line with its character- ment. Asynchronous design methods

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. and the associated synthesis prob- here. I talk about synthesis when I years, however, we see a different lem had been studied as potential use a mathematical representation of landscape: very few IPOs, if any, and solutions to performance problems the original design that is not biased acquisitions as the only exit strategy. due to the unpredictability of wire towards a particular implementation This period had been a roller delays and to power consumption. style. Compilation implies the trans- coaster, with adjustments in busi- Designers interested in pushing the lation from a programming language ness models going to increasingly envelope are still grappling with to assembly or machine code. In this higher ratable revenues. This was this paradigm change to see what case, the mathematical abstraction designed to make EDA more stable the limits that can be achieved are is the same. Opening a parenthesis, and predictable, but it also created and whether the gains of such an I was surprised to see that as early steep transients. During this period, approach are worth the risks. As as 1967 papers on software design Joe Costello left Cadence, heading chips incorporate an increasing were presented at DAC. (Back to the to the education domain. After his number of functionalities, analog future?) The basic difference is in the tenure as a gifted business leader design became the bottleneck. In type of software that was of interest. and innovative thinker, I learned to SOCs, the name of the game is to At the beginning of DAC, the papers appreciate the financial side of busi- find the best match between analog presented at the conference spanned ness from Ray Bingham, who became and digital components not to “opti- all activities: from buildings to struc- CEO of Cadence and with whom I had mize to death” the performance of tures and from electronic circuits to some of the most exciting periods of the analog portion. Because of the “standard” software, i.e., database my “industrial” life. Ray has been a dependency of analog circuits on all and airline reservation software. great friend and mentor in business kinds of second-order effects, analog issues for years. design activity has been more a craft The Business Side than a science. I believe we need to I have already alluded to the stress The Future of EDA: Age of bring science into the picture so as on the EDA industry created by the the Gods or Age of the Heroes? to make this activity repeatable and Internet and the accompanying high- According to Vico, following the age much faster than it is today. tech financial frenzy. I remember that of men, there is a traumatic rebirth When wiring delays became rel- evant in chip design, the separation If we look at the history of design methods, of concerns that originated from the layering of logic synthesis and lay- we see that the changes in design productivity out started producing problems for were always associated with a rise in the level achieving “design closure,” i.e., mak- ing sure that circuits designed at of abstraction of design capture. the logic layer to satisfy timing con- straints still satisfy them after final I used to receive two calls a day from of society with a new age of the gods. layout. Obviously, not achieving de - recruiters, asking desperately if I had Indeed, the period 2008–2010 (par- sign closure generates unacceptable some students who would be inter- ticularly the year 2009) has been very time-to-market delays and costs. The ested in working at one of the estab- difficult for high-tech industry at proposal put forward in this period lished EDA companies because there large. Staying alive has been a major was to merge layout and logic synthe- were not enough people to keep EDA challenge. At the same time, we must sis in a giant optimization loop. going in the vendor space. Established innovate and invest in new technol- As embedded system design vendors had unwanted terminations ogy. EDA must adapt to changed busi- moved towards increasingly soft- in the range of 20% of their work- ness conditions and structures. We ware-rich solutions, the issue of forces; the employees were being lost are witnessing a substantial change in achieving the same design pro- to start-ups in the Internet domain the client-vendor relationship. Part- ductivity gains that logic synthe- and in EDA. In 1999, there were on nerships are increasingly important sis brought to hardware created a the order of 80 start-ups in EDA. Dur- as semiconductor and systems com- strong interest in “hardware-soft- ing this period, companies such as panies rationalize their investments ware codesign,” where from a high- Ambit, Avanti, Get-to-Chip, Magma, in EDA technology, and all of this is level functional model of the design, Monterey, Verisity, and Verplex were happening in light of a fundamental the detailed and optimized software started with the idea of challenging technology change in the semicon- and hardware implementation could the dominant players. All these com- ductor industry that requires invest- be derived. In this perspective, the panies except Magma, which is still ments of a size never before seen issue of software synthesis became a stand-alone company, were later and that exposes the limitations of relevant. Note the difference be- acquired by Cadence and Synopsys. the present design methodology and tween synthesis and compilation If we look at the post–Internet bubble tools. No wonder the introduction

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 19

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. Berkeley, a wireless communication sensor and information elaboration node of a very rich network. It is in this domain that I started Education forming an increasingly deep re- search partnership and friendship Emergency Preparedness and Defense Against Terror with Jan Rabaey, who contributed in a substantial way to directing my re- Energy Efficiency search towards a better understand- ing of the communication is sues in Environmental Monitoring wireless devices and of low-power design methods. His leadership in Healthcare research programs such as the Berke- Transportation ley Wireless Research Center, the Gi- gascale System Research Center, and Service to the Third World the Multiscale System Research Cen- Using IT ter (as well as in producing excellent wines!) cannot be overemphasized.

IC Design Styles FIGURE 2: Applications in the interest of society. Taking for granted that these appli- cations are going to dominate the of the 32-nm technology node has five years as the design problems future landscape of electronics, what been delayed in many companies. faced by the system industry grow do we need to do to support them? The cost of ownership of ASIC design in complexity while time-to-market As already mentioned, the design is increasing rapidly due to nonre- requirements become ever tougher style of choice should favor reuse in curring engineering (NRE) and mask in the face of declining prices. all its forms and, given the constant costs. The cost of designing a new There have been interesting de- increase in NRE and mask costs, chip has reached the US$100 million velopments in the system design make software even more pervasive mark, thus restricting the number of area, however, that may prove Vico than it is today. Ad hoc communica- companies that can afford such an wrong: we may short-circuit the tion protocols will play a substantial endeavor. Consequently, there is a sequence and move directly to a new role in the design process. If we look constant reduction of design starts age of the heroes. at the history of design methods, in favor of standard solutions and of we see that the changes in design customization by software. The Move to System Design: productivity were always associated If we extrapolate the data, there Emerging Applications with a rise in the level of abstraction is only one message: the traditional Given my affiliation with a univer- of design capture. In 1971, the year EDA market centered on ASICs has sity known for its involvement with of my graduation, the highest level largely evaporated. There is no other social issues, I firmly believe that of abstraction for ICs was the sche- choice for the EDA community than the next drivers for the high-tech in- matic of a transistor; ten years later, looking at other application areas. dustry will refer to the global inter- it was the “gate”; by 1990, the use of While the semiconductor industry, ests of society. There is a consensus HDL was pervasive, and design cap- the main customer of EDA, is looking forming that electronics still has a ture was done at the register trans- for the next killer applications for its long way to go to penetrate applica- fer level (see Figure 3). products after PCs and cell phones, tion domains of great interest. Po- We need to work with blocks of the neighboring areas for EDA— tential applications are pursued in much coarser granularity than we mechanical CAD, computer-aided the Center for Information Technolo- used to in order to cope with the engineering (CAE), and embedded gy Research in the Interest of Society productivity increase we are being software design—have grown at a at Berkeley, a very broad program asked to provide. We must bring much faster rate. It makes sense for sponsored by the state of California system-level issues into chip design. the EDA industry to look at oppor- along with industry and created by The recent emphasis on SOC is a wit- tunities in these areas by leveraging Richard Newton (see Figure 2). ness to this trend. All companies the algorithmic and methodologi- The center role in this research involved in IC design are looking at cal knowledge accumulated over its is going to be played by devices this approach in order to shorten history. Mergers and acquisitions in such as the “smart dust” developed design time and decrease design this area are very likely in the next by Kris Pister and his colleagues at cost. The issue here concerns the

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. integration of intellectual property blocks (IPs). It is essential that the The Quest for the Next Level of Abstraction blocks be designed so that their Transistor Model Gate-Level Model SDF IP Block Performance properties are maintained when Inter-IP Communication Capacity Load Capacity Load Wire Load Performance Models connected together (this is called IP Blocks compositionality) in order to allow reuse without the need for extensive Abstract checking. In the past few months, there have been several acquisitions Abstract that are shaping the battle for the RTL Cluster RTL SW SOC market and the virtual proto- Abstract Clusters Models typing market (Co-ware and Vast Cluster have been acquired by Synopsys). The role of interconnect cannot Cluster be overemphasized in this con- text. Indeed, the characteristics of Abstract the communication infrastructure 34 determine the amount of verifica- 1970s 1980s 1990s 2000+ tion that must be carried out. Stan- dard interconnects, such as the FIGURE 3: Raising the level of abstraction. ones proposed by ARM, Arteris, and Sonics, aim to reduce the cost of assembly of IPs in an SOC design between performance and robust- started, this effort was extended and methodology. The standards, which ness. In particular, Carloni developed strengthened to include micropro- dictate rigorous rules about the a family of latency-insensitive proto- cessor design. I gave my full support coordination and separation of con- cols that could reduce the overhead to this initiative when Pat Gelsinger cerns, are offering a shortened path of using the synchronous paradigm asked me to review Intel’s micropro- to correct implementation at the in chips where the relative lengths cessor design approaches in 2007. potential cost of reduced perfor- of the interconnects were making Recently, I have provided support to mance. In particular, time-triggered the reduction in clock speed unac- Gadi and his team in conceptualizing architectures, as proposed by Her- ceptable. The synthesis procedures the principles of reuse, communica- man Kopetz at the Vienna Univer- implemented in COSI by Pinto aimed tion scheme selection, and protocol sity of Technology in Austria (which at providing a rigorous and unbiased and IP design for the next generation spawned the FlexRay standard in approach to selecting a bus archi- of chips, with particular emphasis the automotive domain), have defi- tecture versus an NOC or a mixed on embedded systems. nite advantages with respect to architecture, thus avoiding a sterile event-driven architectures in terms debate among camps divided on the The System Industry and of predictability, orthogonalization principles of the best interconnect to the Design Chain of timing and functionality, and use for moving towards the 45-nano- The trend has been rather clear over fault isolation, while sacrificing meter node and beyond. this period: the electronic industrial some performance. My personal efforts had been driv- sector has been segmenting at a The concept of network-on-chip ing for years towards this ap proach rapid pace. System companies have (NOC) architecture was introduced in to IC design. In 2005, I was asked retrenched in their core competence the late 1990s to offer an alternative by Sean Maloney of Intel to review of product specification and market to buses and point-to-point inter- its approach to communication analysis while shifting the task of connections that were running out products, and among other recom- delivering the engineering and the of steam in high-performance, com- mendations I presented the idea of components of the system to oth- plex SOCs. The seminal papers by De using SOC design in a pervasive way, ers. For example, companies such Micheli and his students analyzed with the aim of substantially reduc- as Ericsson and Nokia are doing the advantages of these interconnect ing development time and effort. At increasingly less in the chip design architectures. My re search group that time Gadi Singer was heading an area. Semiconductor companies are and (most notably) Luca Carloni and internal effort, called 6+6, along the being asked to do more for their Alessandro Pinto looked at automatic same lines: trying to reduce design strategic customers. Some of the synthesis procedures for the selec- cycles to six months for design engineering responsibilities have tion of protocols and topologies that and six months to productization. been transferred over. At the same could provide optimal trade-offs After the Atom design process time, semiconductor companies

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 21

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. have been increasingly relying on Platform-Based Design (PBD) needed to support it. It became the IPs provided by specialized compa- In 1988, in the middle of the age of basis for a method I later proposed nies, for example, ARM for proces- heroes period, I started looking at under the name of platform-based sor cores and Artist for libraries. system design problems, when the design. Some of these principles For some of the semiconductor CEO of Magneti Marelli’s electronic made it into the AUTOSAR standard companies, manufacturing has been division, Daniele Pecchini, showed embraced by the worldwide auto- successfully transferred to the likes me some very interesting products motive industry. of Global Foundries, IBM, SMIC, it was making for Formula 1 racing At that time, I also became inter- TSMC, and UMC, which are now at cars. These included a semiauto- ested in a novel branch of system the leading edge (if we exclude Intel) matic gear switch. This was a revo- and control called hybrid systems, with respect to bringing new tech- lutionary concept: the gearbox was where continuous and discrete time nology to the marketplace. In the essentially the same as in a manual subsystems are tied together. This area of PCBs, specialized compa- transmission, but the synchroniza- class of systems was an important nies such as Flextronics and Solec- tion of the speeds of the engine and model for engine control problems, tron are taking the lion’s share of transmission were automatically where I joined forces with a most manufacturing. performed by means of an embed- important collaborator: Marika Di Supporting this movement re- ded processor. The main issue was Benedetto, a control theory expert quires a view of design as a highly how to verify the system without who also happens to be my wife. She integrated activity taking place running extensive tests on the car, had a tremendous impact on clean- across company boundaries, a task given the short time allowed for ing up my mathematical approach- that is far from easy. Competen- deployment and the number of tests es and instilling further rigor in my cies in engineering disciplines as needed. I then noticed that there work, in addition to supporting me diverse as mechanical engineering was no documentation about the in a difficult time of my career when and electronics, RF, and MEMS have control algorithm used and that the I moved part-time to Europe. We are still working together in the house, furiously discussing research, and In 1988, in the middle of the age of heroes we have managed not to divorce yet—quite an accomplishment! period, I started looking at system design The concept of platform as an problems. “opaque” layer of abstraction that exposes the critical parameters of the layers below to the layer above to become part of an integrated code was entirely written in assem- is, in my opinion, an essential part of environment. Economic analysis of bly. The idea of starting the design a design methodology for design- alternative solutions has to be pro- by capturing the structure of the chain support and for effective vided, together with a set of tools algorithm and, only after this step, requirement and component char- capable of exposing the trade-offs of developing code by using higher- acterization management. I like to of available designs. Design repre- level languages such as C came to think of PBD as a sequence of steps sentations with rigorous semantics mind, and a novel adventure in my taken from the conception of the sys- have to be supported for clean han- research began. I became enamored tem to its realization. I came to the doffs between design teams and to of the automotive design problems realization that logic synthesis can favor more robust design verifica- and helped Dr. Pecchini to reno- be considered as an example of the tion methods. Databases capable vate the design methods and tools PBD paradigm applied from RTL to of handling design data together used in his division. Later on, I fol- the logic gates layer of abstraction. with manufacturing data and lowed Dr. Pecchini when he moved In this view, the library of gates we company databases will have to to become the CEO of the company’s limit ourselves to for implementation emerge. We call this emerging field powertrain division, where we devel- is the lower-level platform, while the design-chain support, which I be- oped a new design method based on RTL description is the top-level plat- lieve is a great opportunity for EDA functional decomposition, orthogo- form. When we select the best imple- at large to increase its relevance nalization of concerns, abstraction mentation platform, we try to “cover” both in terms of value added and layers, architectural reusable com- with the gates we have in the library of economic opportunities. To be ponents, and design-space explora- the logic function that is described able to respond to this challenge, tion. This approach was noted by by the RTL. In fact, when we have a we really need to think about de- BMW, which supported my research common semantic domain that can sign as a science instead of as a set and entered into a partnership be used to represent both the top of technicalities. with Cadence to develop the tools and the bottom layer of abstraction

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. INDUSTRIAL INFLUENCE: SANGIOVANNI AS ENTREPRENEUR AND CONSIGLIERE

Picture an elaborate formal dinner on the top floor of a private club in IC Industry Early in the Next Century” [IEEE Proceedings, 1998]. I can at- Tokyo in the mid-1980s, hosted by the CEO of a major Japanese compa- test that essentially all of the insights into the likely commercial evolution ny. Japan’s electronics giants had become the world’s top memory chip of the industry came from Sangiovanni-san. Even back then, he insisted producers and were threatening to eclipse U.S. producers in global semi- on the evolution toward SOC to lower costs and speed up design. Even conductor market share. Several of us had flown overnight to attend the then, he foresaw how the core methods and mathematics of EDA for chips dinner. Only one hadn’t slept a wink. With the endless enthusiasm and would begin to penetrate into systems design to help manage increas- boundless energy that has always marked him, that same sleepless soul ing complexity economically. He foresaw the increasing fragmentation held nonstop court throughout the long evening, enthralling his Japanese of the electronics industry through specialization. He knew that themes hosts and American colleagues with an account of how design know- like reuse, protocol design, and on-chip communications schemes would how would revitalize the U.S. industry. Alberto was “in the house.” become critical to continued progress in microelectronics design. In those days, I had just begun to know Prof. Sangiovanni-san, as our As his essay in this issue amply demonstrates, that vision into the future Japanese friends invariably called him. It was the start of a long and re- remains clear today. His ongoing commercial collaborations in industries as warding friendship, one in which Alberto’s remarkably prescient insights far afield as automobiles, avionics, and energy demonstrate as much. His have deeply influenced my own views and actions, just as they altered passion and concern for fostering continuing innovation finds expression in the evolution of the semiconductor and electronics industries on three his ongoing work with start-ups, his help in pioneering new industry-uni- continents. It is a characteristic mark of the man and his commitment to versity collaborations, and his involvement in resuscitating the Italian VC teaching excellence that he has made the effort to educate so many of us, industry. In that context, we should heed his admonition “to think of new unschooled in any technical discipline, to the point of competence in the ways to foster large-scale innovation in order to cope with the challenges complex technical wonders of microelectronics. None of us who have the electronic industry faces.” He is correct that there is “less money” to been the recipients of Alberto’s professorial largesse is surprised that his support venture-backed innovation in EDA and microelectronics. Even as work continues to be pathbreaking, his future vision compelling. it has put more capital under management, the traditional venture industry While justly known for his technical contributions, Alberto has had has largely moved away from these more traditional industrial sectors be- enormous influence in the business and VC communities while pur- cause they are seen as mature, as incapable of supporting venture returns. suing multiple roles, from entrepreneur to adviser. The University of Only fundamental innovation will change the settled wisdom. California, Berkeley, unlike its rival down the peninsula in Palo Alto, After such a long and distinguished career, I might advise Alberto to was not especially hospitable to the idea of spinning out start-ups in take a rest. But that’s like advising an eagle not to soar. For as long as the early 1980s when he and Richard Newton conspired to cofound I have known him, Alberto has been in perpetual motion—as he was SDA (the precursor to Cadence) by legally working around a recal- that night in Tokyo close to three decades ago. Relentless professional- citrant licensing office. (I’m happy to report that Berkeley’s licensing ism and the courage to follow his own work to commercial realization practices have improved immeasurably since those days.) Of course, have kept him mighty busy. I’ve never known his enthusiasm (or his self- cofounding one seminal, VC-backed, Silicon Valley EDA company confidence) to flag. From numerous overseas trips together to early (very wasn’t enough: he cofounded a second, Synopsis. Perhaps less well early!) mornings in his kitchen in Berkeley, I can attest that it isn’t just the known is the fact that Albert has fathered many additional VC-backed multiple, hand-cranked espressos that keep him going strong (though start-up progeny in EDA, software, and services through the genealogi- they help). Nor is it just the restless intellect, the never-ending search for cal line of his students. a purer and better algorithmic expression of the complex tasks of EDA, He has been principally responsible for the entry strategy of several or the energy of a visionary. It’s something much deeper: Alberto with- larger, established firms into microelectronics. His contributions to de- out motion is like the earth without rotation. Neither entity will cease sign progress at giants like IBM and Intel are recounted elsewhere in this doing what it does, not in our lifetimes. special issue. He has advised (and made money for) legendary silicon —Michael Borrus investors like Don Lucas and, as a member of various boards of directors About the Author and technical advisory boards, has helped guide many venture start-ups Michael Borrus is the founding general partner of X/Seed Capital, an toward commercial success. To this day, he remains a key adviser to early stage venture fund focused on breakthrough innovation. Prior to several VC firms, including my own. His penetrating insights, insistence founding X/Seed, he was an executive at Mohr Davidow Ventures and on detailed analysis in the face of entrepreneurial salesmanship, and managing director at The Petkevich Group (TPG), a merchant bank pro- willingness to speak the hard truth, have more than once saved me and viding financial advisory services to life sciences and technology com- my team from making a poor investment. It turns out that his advice is to panies. Before joining TPG, he was an adjunct professor in the College be treasured, even in technical fields seemingly far from EDA. of Engineering at the University of California, Berkeley, and a partner For the IEEE’s special publication on the 50th anniversary of the inven- at Industry and Trade Strategies, a business consultancy. Much of his tion of the transistor, Alberto and I coauthored a piece on the future of the academic and consulting work has focused on how business models semiconductor industry, “System ASICs and Continuous Innovation: The can adjust to successfully commercialize new technologies, exploit new Digital Object Id entifier 10.1109/MSSC.2010.937697 opportunities, or adapt to new competitors.

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 23

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. in the stack, then we can always ity measures are related to the num- in Rome, Italy, among automotive, formulate the selection of the best ber of software lines written per day tool, and IC companies (Magneti lower-level platform as a covering by an embedded software engineer Marelli, Cadence, and STMicroelec- problem. If we use my view of PBD, from the start of the project to the tronics) to advance the state of the then we see that our focus as a com- end of the testing phase.) Even after art in embedded system design. This munity has been for years the “inter- doing extensive testing, however, adventure continues today under a mediate” level, corresponding to the the software has an average of 3,000 new form (called ALES), under the ASIC design methodology. This real- errors per million lines of code. direction of my colleague and friend ization made me think that the PBD After visiting several companies Alberto Ferrari, who has developed approach could indeed be applied in different industrial sectors, I can many of the techniques that made to all design problems: not only in claim that this situation is com- PBD relevant. IC and electronic system design but mon to all. We need to elevate the In this area, I have embarked on also in energy-efficient buildings, design methodology for embedded a journey with large companies that face enormous engineering problems as they enter a new era of complexity I believe the EDA industry needs to dedicate the and customer demand. I have worked right amount of attention to enlarging business with General Motors for eight years, boundaries where it operates in these spaces. trying to make the design process for a car faster by leveraging virtual models and software tools. I have also avionics systems, and even synthetic software, introducing more science entered into new fields for me, such biology, as Jan Rabaey’s article elo- and treating software as an imple- as energy efficiency and avionics, quently illustrates. In the most recent mentation choice related to needed with the help of United Technology years of my research career, I have functionality, not in isolation. Since Corporation, which has supported finally been able to place what I have embedded software correctness is my work in many ways and where I accomplished thus far in a holistic often related to its timing behavior, found applications to PBD principles framework, to distill what I learned we need to somehow link behavior in air-conditioning systems as well as about design, and to put to work the with implementation platforms, a large avionics systems and elevators. teachings that my school mentors different paradigm from the classical Last but not least, the European imparted to me so many years ago. one in which the computing engine Community has funded a large details are carefully hidden. We need effort in embedded systems, cul- Embedded System Design to think of embedded system design minating in the formation of a joint At the system level, we need to take in a holistic fashion, rather than technology initiative called Artemis, a closer look at embedded software focusing only on embedded soft- which I helped start in 2005. design as a great opportunity to ware design to solve the problem. innovate. For the past ten years, key- To do so, we need to change the edu- The Business Side note addresses at DAC have pointed cation provided in our schools by We have outlined the grand chal- out the great importance of software broadening the background of engi- lenges for EDA. I believe the EDA for electronics, even for the semicon- neering students so as to make them industry needs to dedicate the ductor industry. There is a wide con- able to consider embedded systems right amount of attention to enlarg- sensus about the need to change the as a whole. We must develop ways ing business boundaries where it way we design software in general to design hardware and software operates in these spaces. It needs and embedded software in particu- concurrently but not independently. to do so, however, when the over- lar. There are several horror stories Soft ware developers will have to deal all business situation is difficult. about the failure of very expensive with parameters that characterize Innovation is an expensive and risky systems, such as the Mars Polar the behavior of the hardware in order proposition that sometimes clashes Lander and the Arianne vector, that to be able to predict physical quanti- with the status of a public com- can be traced to software bugs. In ties associated with the execution of pany of medium size. We have seen addition, Fabio Romeo presented an the software on the implementation over the years a wave of mergers interesting statistic about embedded platform, such as timing, memory and acquisitions carried out by the software for the automotive industry occupation, and power consump- major EDA companies. While “buy- as a member of a 2001 DAC keynote tion. Hardware designers will have to ing companies is a legitimate way of panel. In his data, the productivity for know what is important for the appli- doing research and development in embedded software ranged from six cation software to work correctly. In this industry,” as Robert Stern, then to ten lines per day depending on the this domain, we formed a research a Smith Barney analyst, said a few specific application. (The productiv- partnership called PARADES in 1996 years ago, I believe it is important

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. to find additional mechanisms with I came to the realization that logic synthesis which to innovate. The innovation from start-ups in EDA has been can be considered as an example of the PBD incremental except in a few, albeit paradigm applied from RTL to the logic gates important, cases (i.e., finding better ways to do things we already knew layer of abstraction. how to do). In addition, in the cur- rent economic climate—which of we need to dramatically enlarge us. I am calling for a deeper sense of course we hope will soon improve— the scope of the business if we are urgency and for a stronger partner- larger companies tend to outperform to expand and thrive. To do so, we ship among EDA vendors, includ- the market in terms of both earnings must look carefully at education as a ing electronics, mechanical, and and capitalization. If one looks at VC way of preparing the next generation software tool makers; system and investment, it is in decline. The IPO of engineers and scientists. semiconductor companies; and aca- window closed at the end of 2001. Extrapolating from the fields I demic institutions. Since then, not a single EDA com- have been discussing, I have con- I would like to end my recollec- pany has gone public. cluded that 1) teaching must be tions first with a heartfelt thank- Thus, while the start-up concept about concepts and must be inter- you to my family and to the many is still a valid one and is needed disciplinary and 2) we must be able friends, students, and colleagues to foster an important part of the to shape engineers who can face who have made my life and career innovation landscape, we need to problems that range from mechani- exciting adventures. Finally, I believe think of new ways to foster large- cal to electrical, from civil to nucle- that another quote (liberally trans- scale innovation in order to cope ar, from biological to medical. To do lated using all that remains of my with the challenges the electronic so, we have to provide a general sci- ability in Latin) from Vico will be a industry faces. Just at the moment entific foundation on the one hand. source of inspiration to us all. The when we need such innovation most, On the other, we must give students defining characteristic of the age of there is less money to spend. the tools they need to probe deep- heroes, he says, is “the holy furor for er when necessary to advance the truth that lives in the eternal attempt Partnering and Education state of the art. And it is not only to go beyond the limit, in the infinite Partnering between vendors and cus- about science. I am convinced that possibility of self-realization and of tomers is one way to solve the inno- economics, law, and—why not?— overtaking ourselves to discover the vation problem. It was very effective philosophy (especially ethics) can power of the spirit and give a new during the age of heroes. I cannot all provide even deeper insights into push towards knowledge.” Let us overemphasize the effect of partner- what we will be called on to build in make an effort to live these words. ships on the success of Cadence and the coming years. Synopsys for example. Partnering About the Author for innovation should include aca- Conclusions Alberto Sangiovanni-Vincentelli, demia, forming the virtuous triangle Design science as embodied in EDA a professor at the University of Cali- that was touted for years. We have (in the future, I am sure exten- fornia at Berkeley, has won numer- not seen many system engineers at sions in fields such as biology and ous awards, including: the IEEE/RSE the EDA conferences from the appli- medicine will be very relevant) is a Wolfson James Clerk Maxwell Award; cation domains, however. Nor have unique, wonderful field, in which the Kaufman Award of the Electronic I seen process engineers. We need a research, innovation, and business Design Automation Council for “pio- concerted effort to bring these com- have come together in a long and neering contributions to EDA”; the munities together and create a forum successful synergy, as demonstrated ACM/IEEE A. Richard Newton Tech- for the new age of EDA. But this will by the history of the past 47 years. nical Impact Award in Electronic clearly not be enough. Initiatives Can the EDA community continue Design Automation to honor persons such as the MARCO Focus Research its quest for better ways of doing for an outstanding technical contri- Centers, among which are the Gigas- design, increasing the productiv- bution; the Distinguished Teaching cale System Research Center and the ity of electronic system designers Award of the University of Califor- MUlti-scale System Center (MUSYC), by orders of magnitude while also nia; the Graduate Teaching Award bring these three constituencies to- increasing quality? Can we prove of the IEEE (a Technical Field award gether to find new ways of doing Vico wrong and return to the age of for “inspirational teaching of gradu- design. I believe we need to go a heroes without paying the price of ate students”); the Aristotle Award of step further, however, and that bold the age of gods? It is not going to be the Semiconductor Research Corpo- new initiatives are needed. Indeed, easy. Many difficulty lie in front of ration. And the list goes on.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:35:13 UTC from IEEE Xplore. Restrictions apply. Robert Brayton

At IBM, a group of industrial engineers and university researchers collaborated in the summer to develop the earliest successful method of logic synthesis for ICs.

COURTESY OF A. SANGIOVANNI-VINCENTELLI

n 1981, the idea that one could synthe- no attempt to optimize the network, possibly because size logic automatically from an RTL it was thought to be too hard to compete with manual description into an implementation of implementations. This program was mainly used to cre- I gates and flip-flops was not new. At IBM, ate a golden model for comparison with handcrafted there were already several efforts under logic, which was the mode of implementation at the time. way at that time, and there had been earlier efforts in There was a companion program, called SAS at IBM [8], the same direction by Se June Hong, John Paul Roth, and which was used to do the checking. It was a fairly uni- others. Roth had written a program that was used to cre- versal rule at IBM that before any logic was released in ate a logic network from an RTL description. There was a product, one should “SAS” it. This program was basi- cally an early version of a SAT solver and was remarkably

Digital Object Id entifier 10.1109/MSSC.2010.937690 capable for the time. It was finally published in the IBM

26 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/10/$26.00©2010IEEE

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. Journal of Research and Development than IBM’s MINI program [16] and led us to try to understand how MINI [24], but for a long time this program gave relatively good results. We and PRESTO worked. I had already was not documented except in the decided to study why this could done some experimentation with IBM Technical Disclosure Bulletin (see be so. This process led us to think multilevel logic, so I got that area. [23]). In 1974, Hong and Ostapko [16] further about logic in general, so We decided that there was a lot had created an early programmable we decided to devote the summer in common that could be shared logic array (PLA) minimization pro- of 1981 to logic synthesis, working between two-level and multilevel gram, MINI, which used some very together but dividing up the effort logic, even though the algorithms up innovative ideas and was the lead- into four areas; basic algorithms to then had little in common. So we ing PLA minimization program. Of (Hachtel), two-level minimization gave this area to Gary, with the idea course, in the early 1960s, Quine (Alberto), Ashenhurst-Curtis decom- that his work would feed into the and McCluskey had the first ideas position for delay (Bob Risch), and other two projects. Finally Bob Risch on minimization of sum-of-product multilevel synthesis (my area). In had some independent ideas on how expressions (SOPs). addition, each of us would employ to decompose logic so that it could In the late 1970s, John Darringer a student summer intern to help be made faster. Curt McMullen had led a group working on logic synthe- implement the ideas. We decided already worked several summers at sis at IBM [11]. They pioneered an to use the programming language IBM, and the previous summer he effort to create an industrial-strength APL as the implementation medium, had worked for Gary on numerical logic synthesis tool, LSS, and to mainly because we had been using methods for solving partial differen- apply logic synthesis throughout it in my group and it gave us a good tial equations (PDEs). IBM. LSS and its successor programs ultimately became very successful within IBM. Alberto was at IBM Research on a one-year Gary Hachtel, Alberto Sangiovan- sabbatical from Berkeley . . . He had been ni-Vincentelli and I were really nov- ices in the logic area at that time, told in a conversation with Richard with most of our experience coming Newton that a certain PLA minimization from working on problems posed program developed at Textronix was much in the continuous-variable domain. We had worked on solving sparse faster than IBM’s MINI program and gave algebraic differential equations relatively good results. with applications to circuit simula- tion; SPICE was the prime example in this area. At IBM, we had a simi- way to try out any idea quickly. Basic Algorithms lar program, ASTAP, which Gary and The student who worked with me One of the algorithms we decided to I had worked on in the preceding was Curt McMullen, who later was a look at was tautology, which is the decade [17]. In the late 1970s, I had coauthor of our book on ESPRESSO question of whether a set of prod- a colleague, Bob Risch, in my group [14] and who went on to be a noted uct terms (cubes) always evaluates who was developing an algorithm to mathematician, winning the Fields to 1. I had been using this algorithm test whether a given logic function Medal in 1998. For many years, earlier and had an APL program as could be implemented in a rather my group had had the tradition of part of an implementation of Risch’s exotic logic gate, a cascade emitter- bringing in talented graduate stu- algorithm for detecting if a given coupled logic (CECL) element [9]. dents and faculty for the summer logic function could be implemented He had outlined an algorithm, but and working with them on various into a single CECL circuit [9]. We also it needed to be programmed. This research projects. made a list of functions that seemed I did. It got me thinking about syn- In the rest of this article, I will to be basic and would be needed in thesizing logic, so that by 1981, I describe in more or less chronologi- the other projects. Besides tautol- had already done some early work cal order (at least as I remember it) ogy, these included complementa- in logic synthesis. what I have begun to call the “sum- tion, ANDing, ORing, simplification, Alberto was at IBM Research on mer of logic” and how things devel- generation of primes, and detecting a one-year sabbatical from Berkeley oped afterward. essential primes. One of the key at that time. He had been told in a discoveries in this effort, which conversation with Richard Newton Dividing Up the Work basically changed the way all the that a certain PLA minimization Two-level minimization was assigned algorithms of two-level minimiza- program developed at Textronix, to Alberto, probably because it was tion were done, was the unate recur- called PRESTO [2], was much faster his conversation with Newton that sive paradigm (URP). I will return to

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. URP after two-level minimization is in different directions to help cover they never wanted to do that again. further explained. other shrunken cubes, thereby cre- In their first implementations, clever ating a smaller cover. Reshape was tricks were often used to make the Two-Level Logic a technique that took two neigh- result more efficient. They were and PLA Minimization boring cubes and reshaped them more than willing to give up many We decided to build one program into an equivalent set of two cubes of these in order to make automatic (later called ESPRESSO, because it but with some of the points of one synthesis easier, however. was “fast, hot, and strong”) to do cube now part of the other cube. It PLA minimization, with a switch was basically a way of perturbing Common Algorithms to toggle between using the algo- the set of cubes without increasing As we got into the summer, our imple- rithms of MINI and those of PRESTO. their number. mentation of ESPRESSO revealed that There was a fundamental differ- certain algorithms could be sped up ence between the methods used in Multilevel Synthesis considerably. A few of them, such as the two programs. MINI relied on Part of my earlier effort with Risch tautology, seemed to have a common first computing the offset and then was to put together a small “logic theme, which we later called the using it to aid the other operations. editor” that took up to eight variables unate recursive paradigm (URP). There was thus an up-front cost. In and several logic functions given by The idea was that if a function was contrast, PRESTO used only the ini- logic expressions. These were tested unate, then certain operations could tial cover of the onset and possibly to see if all of them could be imple- be done on it much faster than for a a “don’t care” set. It took a greedy mented in a single CECL circuit. If general function. A sum-of-products approach, by selecting a cube and not, then the expressions were bro- (SOP) expression is unate if for all a literal in it and testing to see if ken down into smaller pieces and of its cubes, there appears only one that literal could be removed. Both tested again. This effort was origi- polarity of a variable. Thus, there programs started from the initial nally motivated by a group working should not be a cube with a positive polarity of a variable and another cube with a negative polarity of the One of the key discoveries, which basically same variable. A prime example changed the way all the algorithms of two- of an algorithm that is trivial for a unate function is tautology. In fact, level minimization were done, was the unate a theorem states that if a function recursive paradigm. has a unate SOP cover, then the func- tion is the tautology if and only if the cover already contains the uni- sets of cubes for the onset and the at IBM’s lab in Los Gatos, California, versal cube. “don’t care” set. MINI’s algorithms that Risch had made contact with The URP operated as follows: if a were more sophisticated. After earlier. They had implemented a cover of a function was not unate, complementation, the cubes were small microprocessor using CECL then one would choose a variable made prime by expanding each circuits because of their speed and (the most binate one) and split the cube using the offset to see if the the fact that a lot of logic could be cubes into two groups, one with expansion was possible. There was packed into one circuit. I remem- the variable set to 1 and the other an algorithm for detecting if a given ber using eight variables because I with the variable set to 0 (these prime was essential. Such essential thought that we would never need are called the two cofactors of the cubes could be taken out of the to work with more than that. By function with respect to the vari- onset cover and put temporarily the summer of 1981, I was up to 26 able). The variable would then be into the “don’t care” set. After this, variables, because I wanted to name removed from the sets. By doing the irredundant process was called, each one using a single letter (it was this recursively, one could arrive which takes the set of primes and convenient in APL). By then we also at a cofactoring tree in which the selects a subset that is irredundant. had requests from other groups with set of cubes at each leaf was unate. Although at this point one had a their own exotic circuits, such as the At the leaves, the appropriate set of irredundant primes, it only differential cascade voltage switch operation was performed (comple- represented a local minimum. The (DCVS), touted by several groups ment, tautology test, and so forth) way out of this local minimum was at IBM sites in Boca Raton, Florida, on the unate cover there (because to use two algorithms: reduce and and Burlington, Vermont. These it was easy), and the result was reshape. The first shrunk the cubes, groups all had the same motivation: pushed back up the tree. At each making them nonprimes, with the after implementing some circuits or internal node the result from the hope they could be expanded later designs by hand for a given project, two cofactors was merged in the

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. appropriate way according to the do remember having a longer initial into a technology-independent part operation being performed, and proof, but I was talked into shorten- and a technology-dependent part. this result was returned to the ing it for the book. The proof in the This was in contrast with other parent. Thus at the top node of the book was correct for single-output efforts that operated on logic that tree, the result of the operation or functions but not for multiple-output was always represented in terms test appeared. functions. I believe the longer proof of the gates to be used in the final As we explored the algorithms was correct, but I don’t really have implementation. These methods used in MINI and PRESTO, we got to a evidence for this any more. I recall were rule-based, using peephole point where we would always ask how that the shorter proof was Alberto’s. optimization as in LSS. If in a local we might implement any new algo- Another important point about area of the circuit a particular rithm using the URP. I remember that this research is that when Rick structure was seen, a rule might in 1981, Gary, Alberto, and I were at Rudell, a graduate student of Alberto’s, be fired to transform this into an the DAC, sitting at a lounge in a Las Vegas, Nevada, hotel and discussing how to do this on a particular algo- We deemed our summer of logic to be very rithm (I think it was the irredundant successful. We had a prototype of ESPRESSO as process, which seeks to find an irre- dundant subset of cubes). I remember well as a prototype of what became MIS at the the scene to this day: in a eureka mo- end of the summer. ment, we suddenly saw how it could be done. Such moments are few and far between, so when they happen, implemented ESPRESSO-II in C, he improved structure in terms of the they are usually remembered forever. put in a checker that at the end of logic gates allowed. Optimization In the end, the first implementa- the code would prove the equiva- was performed by moving the peep- tion of ESPRESSO used the URP in all lence between the original input hole over the circuit and firing rules of its principal subalgorithms. These and the final result, as an aid to until no more improvement could included the complement, expand, debugging the program. It was quite be obtained. irredundant, essential, and reduce fast, and nobody noticed it was Motivated by working on fun- processes. These were MINI’s origi- there. For many years, this checker damental algorithms for logic nal, basic algorithms but had been worked away quietly on many exam- manipulation and the algorithms completely redone using the URP. ples, since by then ESPRESSO was of ESPRESSO, our aim was to get the MINI’s reshape algorithm was omit- widely used in industry. Then one logic simplified as much as pos- ted, since from our experiments we day we got a note from a user asking sible before the mapping process. did not see any need for it. From about a strange message that had This way, we could use the results comparing PRESTO with these modi- appeared. There was indeed a bug for both the CECL [9] and DCVS fied algorithms, it appeared that in ESPRESSO, which we immediately [10] circuits we were investigat- ESPRESSO would be just as fast in fixed. The moral is that however ing. In addition, an algorithmic most cases but almost always pro- sure you are about a program, you approach appealed more to our vided superior results. We decided to still need to verify. sense of aesthetics. Starting with write up our results completely and After the summer, we quickly small examples, we saw the need found a publisher, Kluwer Academic wrote up some results and submitted to represent a circuit as a network Press, through Carl Harris. The book, them to the first International Con- of general logic functions, called a Logic Minimization Algorithms for ference of Computer Design (ICCD), Boolean or logic network. Of course, VHDL Synthesis, came out in 1984 held just down the road, at the Rye each logic function was to be rep- and became known as the “ESPRESSO Hilton in Westchester County, New resented as an SOP, since then we book.” It was perhaps one of the first York. I always tell the story that the could call ESPRESSO to simplify it. in the EDA field that proved in detail first ESPRESSO paper was rejected, We also had a very fast URP version every algorithm discussed. I believe neglecting to mention that the rea- of a simplify function, which used it set a tone for much of the later son was that there was nothing the fact that a unate cover was min- research and publications in the EDA really new in this first write-up with imum if and only if there was no field. Today it has more than 1,200 respect to MINI and PRESTO. It’s cube contained in any other cube. citations in the literature. more fun to leave that part out! There was a need for a method A few interesting anecdotes about for decomposing a node if its logic ESPRESSO: it was pointed out sev- Multilevel Logic Research function was too large. Boolean net- eral years after the book appeared We decided early on that multilevel works needed to both grow and that one of the proofs was wrong. I logic synthesis should be divided shrink as the optimization proceeded.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. This was done by merging several each type of circuit could imple- existed, but they were not as well nodes as well as decomposing large ment a rather complicated logic known as they are today, so we had nodes. Another apparent need was function, it was not obvious when never heard of them. For a DCVS to identify commonalities between a given function could be imple- gate, even though the ordering of nodes. This led to one of our most mented in it. CECL was complicated the variables need not be the same important ideas, that of kerneling further by the fact that it could for all paths, we quickly discovered [7]. You can think of a kernel as a have several outputs, as long as that ordered BDDs worked best. We basic divisor. These could be com- they were compatible in a particu- had also implemented a method puted for an SOP expression quite lar way. For CECL, we used Risch’s for finding a variable ordering by rapidly and could be shared in a method of testing. quickly determining if swapping table of kernels for all nodes in the For DCVS, we had to invent a adjacent pairs in the order would network. Then, common kernels new method. A DCVS circuit can be improve things. In the final imple- could be identified across different described as a set of muxes in which mentation, we used this “sifting” to nodes in the network. Kerneling is each mux is controlled by an input reduce the number of muxlike struc- also used in factoring and decompo- variable. There were three termi- tures in the DCVS circuit, since this sition algorithms. nal nodes: the top node connected translated into smaller areas. Although this was early work related to BDDs, we never wrote it The work we did in logic synthesis has served up since we failed to see its poten- as a foundation for much of the research tial for large functions. This was done since then. Programs such as ESPRESSO-II, only brought to light by Bryant’s pioneering work in 1986 [12]. One ESPRESSO-MV, ESPRESSSO-exact, MIS, SIS, moral here is that efficient imple- VIS, MVSIS, and ABC are descendants of these mentation can be key to recognizing the potential of a method. All our early efforts. initial implementations at the time were in APL, which did give us the

This work led to the notion of to VDD, representing the function advantage of being able to try out manipulating logic functions as if itself, and two leaf nodes, repre- ideas quickly, albeit with a signifi- they were algebraic expressions senting 0 and 1. A DCVS circuit rep- cant performance penalty. rather than Boolean expressions. resented the logic function, where The advantage was that this could those paths going to 1 comprised Aftermath be a much faster process, since some the onset of the function and those We deemed our summer of logic to be of the laws of Boolean logic could be going to 0 were the offset. The muxes very successful. We had a prototype ignored. The heuristic that worked controlled which path was taken: if of ESPRESSO as well as a prototype well was to first simplify the logic the controlling variable was 0, the of what became MIS at the end of the of a node using ESPRESSO, bringing path to the left was enabled, and if summer. We took on the task of rigor- it into a more “canonical” form from it was 1, the path to the right was ously writing up the results. Several which common expressions could enabled. So a DCVS circuit was just papers were written and submitted be more easily identified. Of course, like a small binary decision diagram to the 1982 International Circuit and this approach was not perfect, but it (BDD). The constraint on the circuit Systems conference in Rome, Italy worked quite well anyway. ESPRESSO was that there should not exist any [18], [7], [6]. The conference recep- represented a Boolean way of doing path passing through more than tion was in the beautiful Campidoglio things, and kerneling represented five muxes. Of course, a DCVS cir- there. Alberto chose a memorable an algebraic way. cuit could represent any function restaurant one night to introduce us In the end, the logic network with no more than five inputs, but to fine Italian dining. The dollar was had to be implemented by nodes in there are many functions of more quite strong at the time, and we told which the logic at each node could than five variables that can be the waiter to keep bringing dishes of be fit into a single logic gate. Our implemented by a single DCVS cir- his choice until our money ran out two technologies during the sum- cuit. I recall seeing some functions (our goal was probably US$20 per mer were CECL and DCVS. We had with perhaps nine or ten variables person). The food kept coming and an APL function for each, called that were so implemented. coming, and most of the dishes were ENUFOR, which when given a logic The ENUFOR code for DCVS cir- things I had never tasted before. All function would answer the question cuits would build a structure like a were delicious. of whether the gate (CECL or DCVS) BDD and look at the maximum path The papers stemming from was enough for the function. Since length. At the time, BDDs already the summer’s efforts included an

30 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. ESPRESSO paper [13], a short paper on [3] R. Brayton, R. Rudell, A. Sangiovanni-Vin- gram package for partitioned logic mini- centelli, and A. Wang, “MIS: A multiple-lev- mization,” in Proc. Int. Symp. Circuits and kerneling [7] that became quite well el logic optimization system,” IEEE Trans. Systems, Rome, Italy, Apr. 1982, pp. 42–48. known, and Risch’s paper on using Computer-Aided Design, vol. CAD-6, no. 6, [19] R. Rudell and A. Sangiovanni-Vincentelli, pp. 1062–1082, Nov. 1987. Ashenhurst-like decomposition to “Espresso-MV: Algorithms for multiple-val- [4] E. M. Sentovich, J. K. Singh, L. Lavagno, ued logic minimization,” in Proc. IEEE Cus- speed up a design [6]. The next sum- C. Moon, R. Murgai, A. Saldanha, H. Savoj, tom Integrated Circuits Conf., May 1985. mer Alberto again came to IBM and P. R. Stephan, R. K. Brayton, and A. San- [20] R. Rudell and A. Sangiovanni-Vincentelli, giovanni-Vincentelli, “SIS: A system for brought along several of his graduate “Multiple-valued minimization for PLA op- sequential circuit synthesis,” Tech. Rep. timization,” IEEE Trans. Computer-Aided De- students. For several years after, we UCB/ERL M92/41, May 1992. sign, vol. 6, no. 5, pp. 727–750, Sept. 1987. organized a few mini IBM/Berkeley [5] R. K. Brayton, G. D. Hachtel, A. Sangio- [21] M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, S. Sinha, vanni-Vincentelli, F. Somenzi, A. Aziz, and R. Brayton, “MVSIS,” in Proc. Int. Work- symposia, and Alberto visited IBM a S.-T. Cheng, S. Edwards, S. Khatri, Y. Ku- shop Logic Synthesis, Tahoe City, June 2001. number of times. I recall that once kimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. [22] MVSIS [Online]. Available: http://embed- we were expecting him at my house, Villa, “VIS: A system for verification and ded.eecs.berkeley.edu/mvsis/ but his flight was delayed. As punish- synthesis,” UC Berkeley Electron. Res. [23] R. E. Bryant and J. H. Kukula, “Formal meth- Lab., Tech. Rep. UCB/ERL M95/104, Dec. ods for functional verification,” in Best of ment, we made him cook dinner. One 1995. ICCAD: 20 Years of Excellence in Computer- night it was spaghetti carbonara and [6] R. Risch, in Proc. Int. Symp. Circuits and Aided Design. New York: ACM, 2002. the next, spaghetti salmonara. Systems, Rome, Italy, Apr. 1982, pp. 42–48. [24] G. L. Smith, R. J. Bahnsen, and H. Halli- [7] R. K. Brayton and C. McMullen, “The de- well, “Boolean comparison of hardware In 1985, I took a sabbatical at composition and factorization of Boolean and flowcharts,” IBM J. Res. Develop., vol. Berkeley. There I worked with Al- expressions,” in Proc. Int. Symp. Circuits 26, no. 1, pp. 106–116, Jan. 1982. and Systems, Apr. 1982. berto, and we first implemented MIS [8] G. Smith, R. Bahnsen, and H. Halliwell, with two very talented students, Rick “Boolean comparison of hardware and About the Author Rudell and Albert Wang. After return- flowcharts,” IBM J. Res. Develop., vol. 26, Robert Brayton received a B.S.E.E. no. 1, pp. 106–116, 1982. ing to IBM in 1986, my group worked from Iowa State University, in Ames, [9] A. A. Sharatt and S. Ward, “Comparison on the Yorktown Silicon Compiler of current-switched logic gates for high- in 1956 and a Ph.D. in mathemat- [15], which incorporated a lot of speed communications applications,” ics from Massachusetts Institute of IEEE J. Solid-State Circuits, vol. 25, no. 1, our early multilevel logic synthesis pp. 307-309, Feb. 1990. Technology, in Cambridge, in 1961. research into the Yorktown Logic [10] L. G. Heller and W. R. Griffin, “Cascode He was a member of the Mathemati- voltage switch logic: A differential CMOS Editor (YLE). The entire compiler was logic family,” in ISSCC Dig. Tech. Papers, cal Sciences Department of the IBM written in APL. In 1987, I took early 1984, pp. 16–17. T. J. Watson Research Center until he retirement from IBM and left perma- [11] J. A. Darringer, W. H. Joyner, Jr., C. L. Ber- joined the Electrical Engineering and man, and L. Trevillyan, “Logic synthesis nently for Berkeley. In fact, during through local transformations,” IBM J. Computer Sciences Department at those years when Alberto was com- Res. Develop., vol. 25, no. 4, pp. 272–280, the University of California, Berke- July 1981. ing to IBM, we tried to hire him a ley, in 1987. He held the Edgar L. and [12] R. E. Bryant, “Graph-based algorithms for number of times. It is ironic that, in Boolean function manipulation,” IEEE Trans. Harold H. Buttner Endowed Chair and the end, he hired me. Comput., vol. C-35, no. 8, pp. 677–691, 1986. retired as the Cadence Distinguished The work we did in logic synthesis [13] R. Brayton, G. Hachtel, C. McMullen, and Professor of Electrical Engineering at A. Sangiovanni-Vincentelli, “ESPRESSO-II: has served as a foundation for much A new logic minimizer for programmable Berkeley. He is a member of the U.S. of the research done since then. logic arrays,” in Proc. 1984 Custom Inte- National Academy of Engineering and grated Circuits Conf., May 1984. Programs such as ESPRESSO-II [13], [14] R. Brayton, G. Hachtel, C. McMullen, and has received the following awards: ESPRESSO-MV [19], [20], ESPRESSSO- A. Sangiovanni-Vincentelli, Logic Minimi- IEEE Emanuel R. Piore (2006), ACM zation Algorithms for VLSI Synthesis. Nor- exact [20], MIS [3], SIS [4], VIS [5], well, MA: Kluwer, 1984. Kanallakis (2006), European DAA MVSIS [21], [22], and the latest, ABC [15] R. K. Brayton, R. Camposano, G. DeMi- Lifetime Achievement (2006), EDAC/ [1], are descendants of these early cheli, R. H. J. M. Otten, and J. van Eind- CEDA Phil Kaufman (2007), D.O. hoven, “The Yorktown silicon compiler,” efforts. Elements of MIS and SIS can IBM Res. Rep. RC-12500, 1986 (in Silicon Pederson best paper in Trans. CAD be found in most commercial logic Compilation, D. D. Gajski, Ed. Reading, (2008), ACM/IEEE A. Richard Newton MA: Addison-Wesley, 1988. synthesis software offerings. Technical Impact in EDA (2009), and [16] S. J. Hong, R. G. Cain, and D. L. Ostapko, “MINI: A heuristic approach for logic mini- Iowa State University Distinguished mization,” IBM J. Res. Develop., pp. 443– Alumnus (2010). He has authored References 458, Sept. 1974. more than 450 technical papers and [1] Berkeley Logic Synthesis and Verifica- [17] G. D. Hachtel, R. K. Brayton, and F. G. tion Group. ABC: A system for sequen- Gustavson, “The sparse tableau approach ten books in the areas of the analy- tial synthesis and verification [Online]. to network analysis and design,” IEEE sis of nonlinear networks, simula- Available: http://www-cad.eecs.berkeley. Trans. Circuit Theory, vol. CT-18, pp. 111– edu/~alanmi/abc 113, Jan. 1971. tion and optimization of electrical [2] D. Brown and A. Svoboda, “Fast multiple [18] R. K. Brayton, G. D. Hachtel, L. Hemanchan- circuits, logic synthesis, and formal output logic circuit minimization,” Pre- dra, R. Newton, and A. Sangiovanni-Vincen- design verification. liminary version report on PRESTO, Tech- telli, “A comparison of logic minimization tronix, Inc., 1979–1980. strategies using ESPRESSO: An APL pro-

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:37:48 UTC from IEEE Xplore. Restrictions apply. Patrick Gelsinger, Desmond Kirkpatrick, Avinoam Kolodny, and Gadi Singer

Coping with the complexity of microprocessor design at Intel.

PICTURED, FROM LEFT, ARE PATRICK GELSINGER, GENE HILL, AND ALBERTO SANGIOVANNI-VINCEN- TELLI. PHOTO COURTESY OF INTEL

uring the 1980s, Intel Corporation fully exploit technology scaling. The number of available transformed itself from a semicon- transistors doubled with each new generation of pro- ductor company producing memory cess technology, which came on line roughly every two D chips into a computer company [1]. years. As shown in Table 1, major architecture changes Intel’s transformation was actually in microprocessors were brought about by an approxi- part of a revolution in the entire electronics industry: mately fourfold increase in available transistor counts In the beginning of the decade, microprocessors were every second generation. Intel’s microprocessor design considered to be toys, and the computer industry was teams had to come up with ways to keep pace with the dominated by mainframes and minicomputers made size and scope of every new project. by vertically integrated companies. By the end of that This incredible growth rate could not be achieved by decade, microprocessors became the standard engines hiring an exponentially growing number of design engi- for computing platforms, and the whole industry was neers. It was fulfilled by adopting new design method- restructured. Many more vendors entered the industry, ologies and by introducing innovative design automation each specializing in different areas. software at every processor generation. These method- These changes were fueled by the continuous scaling ologies and tools always applied principles that raised of MOS technology, following Moore’s law. Interestingly, design abstraction, becoming increasingly precise in in his original 1965 paper (reprinted in 1998 [2]), Gordon terms of circuit and parasitic modeling while simultane- Moore expressed a concern that the growth rate he pre- ously using ever increasing levels of hierarchy, regular- dicted would not be sustainable because the process of ity, and automatic synthesis. As a rule, whenever a task defining and designing products in the context of such became too painful to perform using the old methods, rapidly growing complexity would not be able to keep a new method and associated tool were conceived for up with his predicted growth rate. The highly competi- solving the problem. This way, tools and design prac- tive business environment, however, drove companies to tices were constantly evolving, always addressing the most labor-intensive task at hand. Naturally, the evolu- Digital Object Id entifier 10.1109/MSSC.2010.937691 tion of tools occurred bottom-up, from layout tools to

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. circuit, logic, and architecture. At TABLE 1. INTEL PROCESSORS, 1971–1993. each abstraction level, the verifica- PROCESSOR INTRO DATE PROCESS TRANSISTORS FREQUENCY tion problem was typically the most m painful; hence it was addressed first. 4004 1971 10 m 2,300 108 KHz The synthesis problem at that level 8080 1974 6 mm 6,000 2 MHz was addressed much later. 8086 1978 3 mm 29,000 10 MHz This article is the story of the 80286 1982 1.5 mm 134,000 12 MHz coevolution of design methodolo- m gies, practices, and CAD tools in 80386 1985 1.5 m 275,000 16 MHz Intel’s design environment as it Intel 486 DX 1989 1 mm 1.2 M 33 MHz coped with increasing complexity in Pentium 1993 0.8 mm 3.1 M 60 MHz the turbulent 1980s and up through recent years. It is interesting to note their way into the EDA industry as originated in Don Pederson’s group that at the beginning of this process key enablers of many EDA tools and at Berkeley and later on was refined the engineering culture was advo- today’s fabless ASIC/SOC semicon- by Richard Newton, Alberto, and cating a tall, thin design. Nowadays, ductor industry. their students (Intel’s version was very large scale integration (VLSI) known as ISPEC). It was possible to engineers are highly specialized in Design Environment for simulate and check logic behavior different areas of the design disci- the Early X86 Processors and timing waveforms for small cir- pline, where specialized tools are cuits that incorporated up to a few used in each area. This is analogous Inherited Tools from Memory Chips hundred transistors. to the restructuring of the whole Intel’s initial design environment As Intel started designing logic computer industry from vertical to was formed to serve the needs of products, including the first micro- horizontal. memory chips. During the 1970s, processors (the Intel 4004, 8008, In the 1980s, the CAD industry the primary CAD tools were layout and 8080), design engineers inher- itself was nascent at best. While capture and verification tools, used ited all of those tools and methods, some areas like schematic or layout by draftsmen to generate and check which had initially been conceived entry had solid commercial offer- mask layouts. These tools were put for memory chip design. Some engi- ings, the rapidly evolving complex- in place because the layouts were neers preferred to perform logic ity of this young industry meant already too complicated to develop design using gate-level schemat- there could be little hope from and maintain solely on paper or ics, but this generated some resis- commercial tool offerings. There- Mylar. Polygon-based layout repre- tance from the layout designers. fore most tools emerged from inter- sentations therefore had to be stored They were familiar with transistor nal development, external university research, or often a coevolving blend of internal work with external tools This article is the story of the coevolution of and research. While there were a design methodologies, practices, and CAD tools number of corporate-university in Intel’s design environment as it coped with relationships at that time, none was as prolific as that of Intel with the increasing complexity in the turbulent 1980s University of California, Berkeley. and up through recent years. In particular, Alberto Sangiovanni- Vincentelli and his collaborative research team, which consisted of and handled by computerized tools, representations, which directly Robert Brayton, Richard Newton, and initially on dedicated systems such matched the layout. Translating logic many graduate students, had devel- as the Calma or Applicon. gate symbols into transistor struc- oped a strong partnership with Intel Engineers were doing circuit and tures was not a trivial task because and its microprocessor teams. This logic designs at the transistor level, the early microprocessors and long partnership with Intel stands usually by hand, producing hand- numeric coprocessors (8087, 80387) as one of the most fruitful relation- drawn schematics at the transistor were designed in NMOS technology. ships in EDA, bringing fundamental level for the layout designers. The Circuit operation relied on device breakthroughs in multiple elements engineers did most of their design strength ratios, so each gate symbol of microprocessor logic, synthesis, work using pencil and paper, but had to be accompanied by specific and layout. Many of these early suc- they also had circuit simulation transistor sizes. In addition, the pre- cesses resulted in enormous ben- tools derived from the industry- vailing design style supported many efits to Intel and eventually made standard SPICE [3] program. SPICE complex gate pull-down devices,

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 33

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. pass transistors for clocking struc- After this experience, engineers Conway’s famous book [5]. Today, tures, dynamic circuits, and numer- turned to building functional mod- this approach seems trivially obvi- ous other clever and often “tricky” els with general-purpose program- ous. In that era, however, logic structures that could not be cleanly ming languages. One of the first design was typically done in the represented by a simple logic gate register-transfer level (RTL) models context of detailed timing-depen- abstraction. Consequently, even at Intel was developed for the 8087 dent behavior, where both timing logic design was actually performed numeric coprocessor in 1978. It was and logical function were verified by engineers at the transistor level a FORTRAN program that described simultaneously. With the synchro- (also called the switch level), such the logic behavior of circuits, as nous methodology, separation of that even well-known techniques extracted by human interpretation the functional simulation from such as logic minimization by Kar- of the transistor-level schematics. the timing issues enabled success- naugh maps, which were taught It was used for verifying and debug- ful large-scale design and created at engineering schools, were not ging the microcode programs stored two kinds of engineers, who could widely used by VLSI engineers in on the chip. worry about two separate prob- those NMOS days. The clever NMOS In the design of the 80286 pro- lems: the logic designers, focused design tricks typically resulted in cessor, the starting point was on the functional correctness superior densities, albeit with com- already a functional RTL model. problem, and the circuit designers, mensurate complexities. This model was manually translated focused on transistor sizes, volt- into schematics in a top-down age levels, parasitic capacitances, Evolution of Intel’s Logic fashion, rather than the other way and gate delays. The separation of Design and RTL Modeling around. The model was written in concerns like this continues to be As it became too error-prone to MAINSAIL [4], an Algol-like gener- a powerful mechanism in design debug logic behavior of processor al-purpose programming language automation. circuits by hand and too time-con- derived from the Stanford Artifi- Taking advantage of MAINSAIL’s suming to verify the logic behavior cial Intelligence Language (SAIL). support for the dynamic linking of separately compiled modules, RTL models of large circuit blocks were Intel’s transformation was actually part of a coded as program modules, and a simulator, µSIM [6], was developed revolution in the entire electronics industry. to control and monitor their execu- tion. The first Intel design to use such a scheme was the iAPX 432 by circuit simulation using con- RTL modeling and simulation by chip set, developed in Oregon and tinuous waveforms, people at Intel a compiled program in a standard released in 1981. were looking for an executable language (where logic propagation In the 80286 design, the blocks of functional model. At that time, the between gates is actually assumed RTL were manually translated into mainframe computer industry was to occur without any delay) was the schematic design of gates and already using gate-level logic simu- made possible because of a strictly transistors, which were manually lators, which used variable-delay synchronous design methodology, entered in the schematic capture models for TTL gates (made with with two nonoverlapping clock sig- system, which generated netlists of bipolar junction transistors). An nals Phi1, Phi2. During each phase the design. The schematics would be attempt to adopt logic simulation of the clocks, new signal values simulated via the switch-level simu- at Intel resulted in failure: Intel had can propagate in the logic network, lator MOSSIM [7] and compared with developed a gate-level logic simula- and the logic designer only cared the RTL design on a per clock, per tor called LOCIS in the mid-1970s, about the final, steady-state val- signal basis. This was a laborious and the 8086 design engineers ues that were latched at the end procedure but verified the logical converted their transistor-level of the clock phase. As a separate integrity of the RTL with that of the schematics into an equivalent logic task, someone (a circuit designer) entered schematic design. Design model using LOCIS gate models. The had to ensure that the cycle time changes were always challenging, as generic gate models of the simulator was long enough for the circuit to they required the synchronization did not match the tricky MOS logic reach a steady state in each phase. of the changes into RTL and sche- structures of the 8086 schematics, The RTL program simulated the matic databases. however, and its gate-delay models circuit behavior at a cycle-by-cycle There was a separate path for burdened users with too many irrel- timing resolution by invoking code the handful of programmable logic evant timing-related messages and for each clock phase in turn. This arrays (PLAs). In this case, the PLA glitch warnings. approach was inspired by Mead and functions were optimized using

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. the internal LOGMIN tool, which This crisis triggered the intro- of the chip. In particular, we were automated the logic minimization duction of static timing analysis into looking to accelerate the design process. The same resulting PLA Intel and development of the Coarse- process, minimize manual trans- codes were loaded into the RTL as Level Circuit Debugger (CLCD) tool lation errors, and handle the rap- a macro function and into the sche- [10]. It was a schematic-level analy- idly increasing design complexity. matic system; they were then used sis tool for electrical rule checking Given these goals, the relationship to program the PLA arrays into and critical path finding that could with Berkeley—and especially with the layout. Much of the early auto- discover circuit-level bugs and Alberto—quickly became central mation in PLA synthesis at Intel resolve device-sizing issues. It could to our efforts. Albert Yu (manager was enabled by Alberto’s Berkeley also extract the logic functionality of the Microprocessor Division) research in two-level logic minimi- of transistor-level circuit structures and Pat Gelsinger (then in charge zation by Espresso [8] and physical and represent them using logical of new design methods in the cor- automation (e.g., PLA folding [9]) to expressions. The new capabilities porate CAD group) visited Berke- make large control circuit synthesis were applied in the next-generation ley to explore some of Alberto’s using PLAs practical. microprocessor, the 386, which was research work and its potential no longer built in NMOS but rather application to our problems as well Performance Verification in CMOS. as the possibility of partnering on The RTL-based functional design these challenges. methodology separated the issue of The 386 Design Environment The meeting focused on topics timing from the issue of functional In moving to the 386 during 1982, such as the regularization of lay- correctness, assuming that synchro- the design team quickly ported out, the potential use of YACR (yet nous methodology was enforced and the 286 design modules to the 386 another channel router) [11], Tim- that the clock was slow enough for design environment as a starting berWolf [12], logic synthesis, and all logic paths to settle to a steady point. In particular, for the complex the potential for multilevel logic logic state within each clock phase. During this time, however, critical paths were only modestly consid- It is important to note that in the 1990s, ered during the design phase. This was largely due to a lack of tools and a very significant productivity gain was the engineer’s limited knowledge achieved by increasing the computational of the design and the likely critical areas. Most of the critical paths were power available to design teams. not resolved until they were discov- ered on silicon. The clock could be slowed down until no critical path memory protection model of the synthesis, where the path between failure existed. Then the clock fre- 286, some of these blocks would input and output could propagate quency was sped up, but specific make it to the final 386 with mini- through several logic gates rather clock pulses were extended to help mal changes. Most of the remain- than only two as in a PLA. Albert isolate the failing circuit. For exam- der of the design, however, went Yu’s idea was that Intel needed to ple, the 49th clock pulse during the through radical changes with the keep a two-year beat to develop test program could be made longer move to a 32-bit data path width a new microprocessor, and he to allow completion of a slow logic and the introduction of the flat pag- thought that the only way to keep operation somewhere in the chip. ing model. The design work iter- to this timetable was to introduce This was done using special “clock ated rapidly, with the RTL being the new tools and methods. Albert and stretcher” debugging equipment. center of the logic design team’s Pat fully appreciated the potential However, the 286 design had many efforts. RTL simulation for the first of multilevel logic synthesis and second sources, and those manu- time dominated the overall comput- of regular layout. Albert proposed facturers very quickly found clever ing load of the design team as logi- supporting the research at Berkeley, ways to speed up their designs to cal correctness became the focus of introducing the use of multilevel rival Intel’s. This led to a minor crisis the team’s activity. logic synthesis and automatic lay- within Intel: the industry was rapidly With the team focused on RTL out for the control logic of the 386, exerting pressure on the company design and the substantial complex- and setting up an internal group to with respect to the very architecture ity increase from the 286, the ques- implement the plan, though Alberto and design it had created, and the tion was how to more effectively pointed out that multilevel syn- tools to dig into the problem were provide the translation to schemat- thesis had not been released even both weak and laborious. ics and the logical representation internally to other research groups

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 35

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. at Berkeley. The design manager of annealing proved to be the per- The 486 Design Environment the project, Gene Hill, put Alberto fect answer. Of course, with ample on a consulting contract: Alberto computing cycles made available The Challenge of Logic would facilitate progress on these on the IBM 3081, one could play Design in the 486 issues as well as review the 386’s with the parameters offered at While the 386 design heavily lev- floor plan to better understand the length to find ever better layout eraged the logic design of the 286, broader applicability of advanced results. After global placement by the 486 was a more radical depar- CAD methods to the design. TimberWolf, specific cell place- ture. It involved the move to a fully It is important to note that with ment occurred in standardized pipelined design, the integration the 386, the era of CMOS began at rows of standard cells and routing of a large floating-point unit, and Intel. While we were far from the channels using a tool called P3APR, the introduction of the first on- power wall of the early part of the developed by Manfred Wiesel, who chip cache: a whopping 8-kB write- decade from 2000–2009, NMOS came to Intel from the BellMac through cache used for both code power was increasing at a nearly project at AT&T. and data. Given that substantially exponential rate. CMOS brought with In fact, the results were good less of the design was leveraged it a reasonable P device and a strong enough that the design team elimi- from prior designs and the fourfold bias toward complementary logic nated all the small PLAs from the increase in transistor counts, there structures to eliminate steady-state 286 and simply converted them was enormous pressure for yet power dissipation, achieve sym- to interconnected logic gates (i.e., another leap in design productivity. metry between rise and fall times, random logic). This made the logic While we could have pursued simple and get full-swing logic voltage lev- blocks larger, with greater potential increases in manpower, there were els regardless of transistor sizes for further logic-design optimiza- questions regarding the company’s and transition speeds. With NMOS, tion. Only the I/O ring, the data and ability to afford the employees, find there was much to be gained from a address path, the microcode array, them, train them, and effectively cleverly ratioed design. While there and three large PLAs were not taken manage a team that would have needed to be much larger than the 100 people who eventually made up A key challenge of applying logic synthesis to the 486 design team. With this challenge in front of our industrial design was the clocking style. us then, several aggressive goals were proposed to enable our rela- tively small team to tackle the 486 were still arguments for complex through the synthesis tool chain design: domino-type design approaches, on the 386. While there were many ■ a fully automated translation from the inherent nature of CMOS design early skeptics, the results spoke for RTL to layout (we called it RLS, for created a strong move toward using themselves. RT-to-layout synthesis) a standard set of gates from a cell With layout of standard cell ■ no manual schematic design (dir- library rather than the individually blocks automatically generated, the ect synthesis of gate-level netlists sized and customized gate struc- layout and circuit designers could from RTL, without graphical sche- tures that were common in the days myopically focus on the highly opti- matics of the circuits) of NMOS. mized blocks like the data path and ■ multilevel logic synthesis for the Working with a cell library, we I/O ring, where their creativity could control functions were able to employ Berkeley tools have much greater impact. Further, ■ automated gate sizing and opti- like Espresso for logic minimiza- these few large blocks greatly sim- mization tion and TimberWolf for simulated plified the overall global chip floor- ■ inclusion of parasitic elements es- annealing of cell placement. We planning effort, allowing for a much timation were quickly demonstrating large more rapid final chip assembly with ■ full chip-layout and floor-plan- regular blocks of reasonably well far fewer errors. An in-house pro- ning tools. optimized logic designs. While the gram called CVS, written by Todd To execute this visionary design idea of simulated annealing seemed Wagner [13], performed verification flow, we needed to put together a rather chaotic at best, the results of final connectivity. While today CAD system that did not yet exist. were quite good. An oft-repeated the 386’s 275,000 transistors seem Once again, we traveled to our lesson in science and engineering trivial, at the time it was a monu- (now) good friend Alberto at Berke- is to apply proven techniques from mental feat, breaking ground in ley to extend our previous collabo- other fields to similar problems in performance, ISA compatibility, and ration with new tool development. your field. In this case, simulated design methodology. A liaison from Intel (Gary Gannot)

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. was stationed in Berkeley for two years as a participant in Alberto’s research team. While we were working on the 386, academic CAD research was going through a major renaissance at Berkeley. The original research in CAD there was being combined into the Berkeley Synthesis Project, with a focus on merging the efforts in logic synthesis and layout gen- eration. After collaborating with Alberto at IBM from 1980 to 1982 and a Berkeley sabbatical in 1985, Robert Brayton joined the Berkeley faculty full-time in 1987. The three main CAD professors, Alberto, Brayton, and Richard Newton, then joined forces to begin what became a highly prolific period in CAD. In a tour de force 2003 Design Automation Conference (DAC) keynote speech, Alberto termed this era “the age of heroes,” a “vibrant era of creativ- ity and expansion.” In hindsight, Alberto and his colleagues fostered strong industrial collaboration with their decision to make the results FIGURE 1: The Intel 80386 processor. Taking a clockwise path around the chip: The upper of the Berkeley research (including right was bus interface and instruction decode, the lower right was test and control logic software systems) freely available and the large microcode ROM, and the lower left was the data path for primary instruction executive. Moving up the data stack on the left of the chip was the segment and virtual ad- to everyone. Through this arrange- dress generation. Finally, paging and final physical address generation was in the top left. ment, the close technical collabora- Synthesized random logic blocks stand out clearly in the middle given their row of cells and tion between Intel and the Berkeley routing channel characteristics. (Photo courtesy of Intel Corporation.) CAD group was able to benefit both academia and industry, which in turn (who headed the corporate CAD link from RTL to logic synthesis was fueled further research advances. group) that a central methodology the input language for RTL model- As the 486 project was starting development group under Rafi Nave ing. Languages like MAINSAIL and C in 1986, Gene Hill (the director of should be formed, with Pat Gels- didn’t have the formalism required microprocessor development) was inger and Jim Nadir at the center to describe synthesizable hardware. deliberating whether to take the full of the group. Jim Nadir’s primary Languages like VHDL were in the risk of devising a new CAD system focus was on library and physical process of being invented at the or to work on a more conservative design; Pat Gelsinger was in charge time but were considered hopelessly plan in parallel as well. Gary Gannot of the methodology and the tools, complex, given the broad industry recalls: “He asked me if I felt com- working closely with the CAD teams process being used to define them. fortable that the code written by the in the United States and Israel and Thus, we launched the iHDL effort students at Berkeley would be reli- with Berkeley and Alberto. He did to devise a language defined specifi- able enough in a production-worthy not expect this at the time, but his cally by the formalism required for environment. Since I was proud to next assignment would be manag- synthesis, with clear semantics for be part of the MIS team, I immedi- ing the 486 design: he was shortly items like buses, native algebraic ately responded that I felt very com- to become the customer for the very and Boolean logic functions, and fortable.” Finally, Hill decided to go tool chain he was driving. the basic control flow mechanisms for it: he transferred “open requisi- a logic design requires. The iHDL tions” to hire 15 engineers from his Intel’s Hardware language defined by Tzvi Ben Tzur, budget for the corporate CAD group. Description Language Randy Steck, Gadi Singer, and Pat There was agreement among Gene A major technical challenge we had Gelsinger filled the bill. In a series of Hill, Albert Yu, and Mike Aymar to overcome for enabling a direct summits among the Israel, Oregon,

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. and Santa Clara teams in 1985 and more difficult and politically sensi- design was the clocking style: Intel 1986, we converged on a language tive assignments anywhere in the designs commonly used transpar- definition. Meanwhile, the CAD team company at the time, as each proj- ent latches to allow more flexibility in Israel was developing the language ect group in the company wanted in the number of logic levels between compiler. The result was a formal to have some unique cells. The state elements. Furthermore, skew language description for RTL devel- resistance to a standard cell library penalties apply only once to a loop opment and logic/layout synthesis sounds absurd today, when libraries of transparent latches, rather than from that description. Berkeley’s are offered to design houses as the to every sampling element (as with creation of a standard intermedi- basic access interface to semicon- flip-flops, where the “hold time” is ate format for logic representation ductor manufacturers. wasted in each flop). Finally, latches were smaller. Yet this introduced complexity for synthesis in coping Collaboration among Intel, Alberto Sangiovanni- with a two-phase clocking system, both at the logic level and dur- Vincentelli, and the University of California, ing place-and-route. Since design Berkeley, continues to this day in a broad range debates raged then (as they do now) of areas of computer architecture, particularly about whether to flop or to latch in any given design, our CAD programs platform-based design. had to cope with both. We also needed to address timing, parasitic estimation, and the automated siz- (BLIF) was a key enabler for Intel Intel’s Adaptation of ing of gates. To do this, we used the (and others) to develop higher-level Berkeley Logic Synthesis internally generated CLCD tool [10]. description languages. Amazingly, We decided that our RLS system In addition to CLCD, we also devel- Intel didn’t replace iHDL with Ver- would be based on a tool called Multi- oped a central timing tool called ilog until 2005, simply because of Level Logic Interactive Synthesis Sys- TISS, which managed the global tim- its expressive completeness and tem (MIS) [14], which was actually ing signal requirements. Some of effectiveness for synthesis. It had a an experimental workbench being these would be generated automati- 20-year life. developed by the graduate students cally from synthesis, some would at Berkeley for executing various be globally determined by external Intel’s First Standard Cell Library restructuring operations on combi- requirements, and some were highly The vision of automatic conversion of national logic blocks. Gary Gannot, optimized design signals, such as RTL to layout hinged also on the exis- our liaison, was regularly sending critical data path signals that were tence of a standard cell library. The software releases of MIS from Berke- tuned through manual circuit design library cells had to fit multiple tools: ley to the Intel CAD team in Haifa, and layout approaches. they had to have a standard “height” Israel. The team in Haifa wrote soft- Much of the RLS integration/ and ports to enable automatic place- ware programs to perform a series of development effort was done in ment and routing. Their delay char- tasks: compile iHDL models into inter- Israel due to the central role that the acteristics had to be modeled for mediate data structures; decompose CLCD tool played and the relative static timing analysis, and the whole the compiled blocks into separate stability of the other tools in the library had to serve as input to the combinational blocks and sequential flow. Pat Gelsinger recalls some of logic synthesis tools. Beyond this, a elements (latches or flip-flops); feed the sensitivity associated with work- decision was made to develop a sin- each combinational block into MIS for ing across a geographical and cul- gle library for use by multiple design logic minimization (the output was a tural barrier. He says, “I demanded teams across Intel and to increase network of generic NAND gates); con- the CLCD team work directly for me, productivity via large-scale reuse vert the generic form into a combina- as I knew how central it was to the and modularity. Given the long his- tion of actual gates from the library; overall flow. Mike Aymar, who ran tory of individual transistor optimi- and combine all the results, along corporate CAD at the time, refused, zation at Intel, obtaining agreement with the sequential elements, into claiming I needed to learn how to on standard cells was no small task. a final netlist that could be handed manage indirectly and through Jim Nadir in corporate CAD was over to the layout synthesis tools. influence. I wanted to kill him at given the assignment to create Berkeley developed the library-map- the time, knowing the Israelis were the common cell library, working ping step at our request [15], as it was tough and remote , and I didn’t have closely with people at Intel’s tech- essential for our program. time for such nonsense if we were nology development group in Ore- A key challenge of applying going to pull the overall RLS system gon. This turned out to be one of the logic synthesis to our industrial off in time for the 486 program to

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. start up on it. It was a valuable learn- fred Wiesel, produced a series of ■ synthesis (which provided the ing and development experience for tools. The DAPR standard-cell tool automatic conversion from RTL to me as a manager, even if I despised [17], [18] placed and routed blocks gates and layout). Aymar for at least a year for making of several thousand standard cells This was the “magic and powerful me live through such a challenging in double-back rows (shared power triumvirate.” Each one of these ele- management experience.” Aymar supply) with diffusion sharing, rout- ments alone could not revolutionize put a strong emphasis on continu- ing over the cell, and double-layer design productivity. A combination ally pulling the teams in Oregon, metal technology. For the 486, we of all three was necessary. These California, and Israel together. He had for the first time developed a three elements were later standard- recalls: “This placed significant full-chip floor-planning and assem- ized and integrated by the EDA indus- demands on people’s personal lives, bly tool called ChPPR, which used a try. This kind of system became the as they had to spend quite a bit of extended time in remote sites from their home site. It worked though, At the end of the design, Pat, Gene, and and overall pretty well. In those days Alberto were featured in a video that Intel I got hooked on e-mail. I remem- ber describing to Andy Grove how distributed worldwide to universities. amazing it worked in allowing folks to communicate between various 1/2 design rule boundary abstraction basis for the entire ASIC industry and sites and time zones. He didn’t buy to create correct-by-construction the common interface for the fabless it at the time. This was one of the abutting block placements, over-the- semiconductor industry. rare times—maybe the only time—I cell routing, and a hierarchical global At the end of the design, Pat, anticipated the importance of an abutment and connectivity check that Gene, and Alberto were featured in emerging trend before he did!” bypassed traditional connectivity a video that Intel distributed world- verification [13] and that was orders wide to universities [19]. The video Physical Design Automation in RLS of magnitude faster because it elimi- described how microprocessor de - With the advent of multilayer metal nated layout extraction. The ChPPR sign was done at Intel and how we process technologies, layout syn- hierarchical tool was actively used on had revolutionized CAD by working thesis became competitive with mainstream microprocessors at Intel with Alberto’s team to bring in new manual layout artwork. The com- for almost 20 years, until 2005. technology and deliver stunning plexity of creating dense designs acceleration in the 486 program. made automation more suitable for Complete RLS Flow for This touting of our academic col- and acceptable to engineers. At the Random Logic Synthesis laboration was widely recognized time, Intel still used manual effort The combination of all these tools in the industry as extremely effec- to generate structures that were was stitched together into a system tive. As part of that video, Pat joked more regular, such as memories called RLS, which was the first RTL- about that “small school in the bay.” and data paths, but control logic to-layout system ever employed in a For a Stanford graduate, a partner- was synthesized both at the logic major microprocessor development ship with Berkeley might be a bit and layout levels. Place-and-route program, although similar synthesis unexpected. But with our collabo- algorithms came from Alberto’s projects were implemented at sev- rations in Israel and with Berkeley, students at Berkeley; TimberWolf eral other companies in the 1980s. we had created an extraordinary used simulated annealing and was RLS was used only for control logic sense of teamwork, crossing numer- directly and heavily used to create in the 486 chip, covering the most ous unwritten barriers to diversity optimized placements. While routers complex and tedious logic design and creativity. were written for industrial use, the effort; the highly regular data path algorithms were heavily based on was done manually in order to Design Environment of technology from Alberto: the infa- achieve high density and speed. Pentium Processors mous YACR2 algorithm [11] and the RLS succeeded because it com- The 486 processor was followed Chameleon [16] multilayer approach bined the power of three essential by Pentium, Pentium Pro, and vari- by Doug Braun (who joined Intel in ingredients: ous more advanced generations, 1987 and wrote most of the routing ■ CMOS (which enabled the use of a which integrated numerous archi- compaction algorithms). cell library) tectural extensions and continu- The physical design automation ■ a hardware description language, ously in creased complexity. It is software was written in MAINSAIL, or HDL (which provided a conve- interesting to note that the same as were most CAD tools at Intel at nient input mechanism for cap- basic design methodology and the time, and the team, led by Man- turing design intent) design flow remained in effect

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. through all of those generations, replaced by a single clock and are used in defining and verifying while the initial set of tools was master-slave flip-flops, which were system architectures. replaced by more robust and bet- simpler to synthesize and check The first Pentium was a supersca- ter-integrated tool sets. As the and are easily supported by com- lar microprocessor design, and the EDA industry matured, some of mercial tools. RTL remains the pri- microarchitecture included new fea- the in-house tools were replaced mary entry point into the design tures like microcode-based instruc- by commercial tools. Starting with cycle. No higher-level synthesis has t ion s, a 6 4 - bit fa st e x ter n a l dat a bus, the Pentium generation, the two- emerged in the design of proces- and a completely revamped float- phase clocking scheme was largely sors, although higher-level models ing-point unit with unprecedented levels of performance (e.g., FMUL operations had 15 times greater throughput than in the 486). At 3.1 million transistors, the Pentium required stronger EDA capabilities. Gadi Singer, designated to be the next Intel liaison to Alberto’s group, relocated from Israel to California in the summer of 1990; Avtar Saini, the Pentium design manager, met Gadi at Intel’s Santa Clara cafete- ria the evening before Gadi drove to Berkeley, and he convinced him to retarget his stay and become the Pentium design automation (DA) manager. That shift did not end up as a total negative for the Intel- Berkeley interaction, as the Pentium DA team continued a very deep and effective interaction with Alberto, Richard Newton, and the rest of the Berkeley team. Logic and layout synthesis for the control circuits in the Pentium could be performed by the RLS flow and was no longer a problem. The productivity bottleneck for the Pentium design was mainly in the much more complex data path circuits, which were still designed at the schematic level by manual conversion of the RTL model. In particular, the translation of sche- matics to layout was too slow. The layout designers were using a new symbolic editor, but fol- lowing well-entrenched practice they continued to lay down wires and gates in a polygon-oriented manner. With a combination of basic training and a set of automa- tion tools to aid symbolic layout, productivity tripled in a matter FIGURE 2: The Intel 486 processor. Counter-clockwise from top left: memory interface, 8-kB unified cache, floating-point unit. At the bottom right is the decode logic; microcode ROM is of weeks. This was an important at bottom (mostly handcrafted); going up, there is a split into data path on left (handcrafted) lesson for the future: the human and control on right (all synthesis, with a small handcrafted section in middle of die); cross- factor is a major aspect in getting ing control signals are handled by full-chip assembly. (Photo courtesy of Intel Corporation.) value out of new capabilities.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. Manually designed data path cir- arithmetic logic as well as all asso- developed tools for combinational cuits had to be checked to verify that ciated microcode was function- and sequential equivalence checking, their behavior was identical to the ally correct. This spawned another respectively. Dynamic verification RTL model. This area required sub- phase of Intel’s close collaboration remains the main way to address the stantial investment in developing with academic researchers (though functional verification problem, how- test vectors that would be executed not with an emphasis on Berkeley) ever. Formal techniques were helpful on both the schematic and RTL and [21], which led to the creation of the for property checking by simulation would result in high coverage of all Intel Strategic CAD Labs. instrumentation (tracking violations functionality branches. Simulat- Formal verification looked like of formally specified properties). ing the schematics at the switch a promising approach. In principle, RTL simulations, carefully designed level was a major sink of computing this is a static method that exam- to “cover” the enormous space of resources, and incomplete coverage ines the design without simulating processor states and logical condi- left holes in verification that were its behavior over time and does not tions, remain the primary verifica- manifested as circuit bugs. Gadi require test inputs. But the promise tion vehicle, and they still consume developed a new technology to for- did not fully materialize. Functional more than 80% of the computing mally and completely validate the equivalence checking of RTL to gates resources for such projects. correlation between schematics and has been added to the design flow as Yet another area that became crit- RTL. It was a combination of two a static check. Widely used at Intel, ical in the Pentium era was full-chip existing capabilities in a brand-new SALT and PEPPER are two internally timing and modeling of interconnects context. First, the data path circuit schematics were automatically ana- lyzed for their logic expressions and translated into RTL representation [10], [20]. Then, the extracted logic models (in iHDL) were fed into the logic synthesis programs codevel- oped with Alberto’s group, which could take two logic descriptions, turn them into canonical form, and compare them mathematically. By using this new schematic formal verification (SFV) functionality, all circuits that resided between latch and memory elements could be fully verified against their original RTL descriptions without a single simu- lation cycle. This removed a whole domain of investment during the Pentium project, reducing test devel- opment for schematic verification to zero, reducing the run time to a frac- tion of the previous dynamic veri- fication, and improving the quality level significantly toward zero sche- matic mismatches. Still, the size of the functional verification task for the full-chip RTL model has grown nonlinearly with the size of the processor. The impor- tance of verification was exemplified FIGURE 3: The Intel Pentium processor. Counter-clockwise from top left: floating-point unit by the infamous “Pentium FDIV bug,” (handcrafted data path on the left and synthesized controls on the right). The middle of the where a rare and minute numerical die consists of the primary data path (handcraft on the right) with a control section on the left (all synthesis) with a channel for chip assembly. The top right consists of an 8-kB data inaccuracy in a mathematical calcu- cache. The bus interface logic resides below the data cache. The 8-kB instruction cache occu- lation created a business crisis. The pies the lower right of the die. The instruction fetch and the branch target buffer memory are technical challenge, then, was to on the lower left. The microcode ROM and logic were drawn below the floating-point unit. formally verify that floating-point (Photo courtesy of Intel Corporation.)

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. for static timing analysis. In previ- so on. The functional simulations details, and their creative “rights.” ous products, smaller circuits were could easily be partitioned into They did not want to accept the designed using accurate extractions, different jobs and run on different standards and restrictions of new but large static timing analysis was workstations. A major invention at methodologies (which were chosen based on a simplified lumped capac- Intel was called NetBatch. The idea in order to minimize verification itance extraction model. This was was to utilize all of the engineering and allow automation). This kind insufficient to support the aggres- workstations at Intel worldwide as of conservatism goes together with sive timing requirements and the a virtual pool for running verifica- risk avoidance, as people stick to new cross-unit interdependencies tion tasks in parallel, exploiting familiar methods and tools, trying that introduced many long-haul sig- time-zone differences among sites. to minimize risks from large-scale nals, however. Distributed RC extrac- This is conceptually similar to grid engineering programs. tion and modeling was introduced and cloud computing, which became It is also interesting that while for the Pentium along with power commercially available several manufacturing technology scal- grid analysis. years later. ing proceeded predictably via coor- It is important to note that in the dinated efforts, with Moore’s law 1990s, a very significant productiv- Discussion and Trends and Dennard’s theory as a top-down ity gain was achieved by increasing At each step of the CAD evolution, road map and a strategic guideline, the computational power available higher productivity was enabled the evolution of CAD and design to design teams. Interestingly, begin- by increased automation, which lev- methodology occurred from the bot- ning with the development of the eraged increasing computational tom up and through numerous con- 386, Intel began employing UNIX capacity, higher abstraction, higher troversies. as its primary engineering develop- regularity, more usage of hierarchy, Finally, many of the break- ment environment, given its more and a more disciplined and restric- throughs described in this article flexible and engineering-oriented tive methodology. were only accomplished by means nature. In fact, Pat’s entry to the In the evolution we have de - of significant cross-discipline coop- design team was because of Intel’s scribed, using RTL instead of sche- eration. The design teams took zeal for UNIX. The 386 design team matics was an example of higher significant risks in embracing new was fed up with the DEC 20 and IBM abstraction. Using a cell library was methods that had yet to be proven. CMS environments and was highly an example of higher regularity. Design tools were being invented attracted to the flexibility of UNIX. Hierarchical decomposition (“divide simultaneously with the design But the only machine then big and conquer”) was achieved when team’s requirements. enough (and available) was the IBM complex problems were divided Collaboration among Intel, Alberto 370/168, later replaced by the 3081. into independent pieces (e.g., the Sangiovanni-Vincentelli, and the Uni- Since Pat was a bit of a UNIX hacker separation of logic verification from versity of California, Berkeley, con- at the time, he set up the entire timing verification and the separa- tinues to this day in a broad range of design team inside his CMS account, tion of logic synthesis from library areas of computer architecture, par- which was running the UTS UNIX mapping). This decomposition led ticularly platform-based design. It environment from Amdahl. Thus, to increasing specialization of engi- is very likely that in order to achieve he was root on the UTS environ- neering expertise: for example, due the next step function in design pro- ment for the entire 386 design team. to RTL and synthesis, logic designers ductivity, people in the electronic Everyone was extremely motivated have become programmers. design community will have to take to get to UNIX and thus quickly Examples of a restrictive meth- such radical codevelopment risks overlooked Pat’s naiveté in logic odology are numerous: the synchro- again in large-scale engineering pro- design as a way to get away from nous design paradigm, the specific grams where failure is not an alter- the corporate IT environment. UNIX iHDL language design for synthesis, native. With such risky endeavors, license plates reading LIVE FREE OR DIE the cell library, and static CMOS all the “era of heroes” may be upon us commonly adorned the design team involve some self-imposed restric- once more. members’ offices. tions as part of the engineering Late in the 486 design process, discipline. Disciplined restrictions Acknowledgments Intel’s whole computing environ- are essential in every methodology. The authors wish to thank their many ment was moved to local UNIX The introduction of new methods collaborators on the design teams at workstations. In addition to the and tools did not proceed smoothly both Intel and Berkeley. Such friends interactive performance, the design but rather encountered skepti- and memories stand as some of the team was extremely motivated to cism and resistance from design- finest of our collective careers. Fur- develop the 486 on 386 machines, ers who did not want to give away ther, such an overview is prone to the Pentium on 486 machines, and their work habits, their control of errors of memory. While the authors

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. have attempted to be as accurate as Conf. Computer-Aided Design ICCAD-87, Research Center at Berkeley. In 1986, possible, we are certain that errors Nov. 1987, pp. 116–119. he joined Intel, where he contributed [16] D. Braun, J. Burns, S. Devadas, K. H. Ma, K. of recollection exist and there are Mayaram, F. Romeo, and A. L. Sangiovan- to hierarchical, full-chip timing anal- significant contributions that should ni-Vincentelli, “Chameleon: A new multi- ysis, floor planning, layout synthe- layer channel router,” in Proc. 23rd Design be recognized and chronicled to give Automation Conf., 1986, pp. 495–502. sis, and extraction, earning two Intel a fuller history of CAD and micro- [17] M. Rose, M. Wiesel, D. Kirkpatrick, and N. Achievement Awards. He received an processor development. Nettleton, “Dense, performance directed, S.B. degree in electrical engineering auto place and route,” in Proc. IEEE Cus- tom Integrated Circuits Conf., 1988, pp. from MIT in 1986 and a Ph.D. degree References 11.1.1–11.1.4. in electrical engineering and com- [18] M. Rose, N. Papakonstantinou, G. Welling- [1] A. S. Grove, Only the Paranoid Survive: puter sciences from Berkeley in 1997. How to Exploit the Crisis Points That Chal- ton, D. Kirkpatrick, and M. Wiesel, “Syn- lenge Every Company. New York: Double- thesis for high performance random lay- Avinoam Kolodny is an associate day, 1996. out,” in Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 885–889. professor of electrical engineering at [2] G. Moore, “Cramming more components onto integrated circuits,” Proc. IEEE, vol. [19] G. Hill, “Design and development of the Technion–Israel Institute of Technol- 86, no. 1, Jan. 1988, pp. 82–85. Intel 80386 microprocessor,” Video re- ogy. He joined Intel after completing cording, Univ. Video Commun., Stanford, [3] T. Quarles, A. R. Newton, D. O. Pederson, CA, 1988. his doctorate in microelectronics at and A. Sangiovanni-Vincentelli, SPICE 3BI User’s Guide. Berkeley, CA: Univ. of Cali- [20] D. Fischer, Y. Levhari, and G. Singer, the Technion in 1980. During 20 years fornia Press, Apr. 1987. “NETHDL: Abstraction of schematics to high-level HDL,” in Proc. Conf. European with the company, he was engaged [4] C. R. Wilcox, M. L. Dagcforde, and G. A. Design Automation, 1990, pp. 90–96. Jirak, “Mainsail implementation over- in diverse areas, including nonvola- view,” Stanford Comput. Syst. Lab., Rep. [21] Y. Chen, E. M. Clarke, P. Ho, Y. V. Hoskote, tile memory device physics, EDA, No. CSL TR-167, Leland Stanford Junior T. Kam, M. Khaira, J. W. O’Leary, and Univ., Palo Alto, CA, Mar. 1980. X. Zhao, “Verification of all circuits in and organizational development. He a floating-point unit using word-level served as Intel’s corporate CAD sys- [5] C. Mead and L. Conway. (1980). Introduc- model checking,” in Proc. Formal Meth- tion to VLSI Systems. Reading, MA: Addison- ods in Computer-Aided Design, 1996, pp. tem architect in California during the Wesley [Online]. Available: http://ai.eecs. 19–33. umich.edu/people/conway/VLSI/VL- codevelopment of the RLS system SIText/VLSIText.html and the 486 processor, and was man- [6] K. Tham, R. Willoner, and D. Wimp, “Func- About the Authors tional design verification by multi-level ager of Intel’s performance verifica- simulation,” in Proc. 21st Design Automa- Patrick Gelsinger has been president tion CAD group in Israel. He has been tion Conf., 1984, pp. 473–478. and COO for EMC Corporation’s infra- a member of the faculty of Electrical [7] R. E. Bryant, “MOSSIM: A switch-level sim- ulator for MOS LSI,” in Proc. 18th Design structure products since 2009. In his Engineering at the Technion since Automation Conf., 1981, pp. 786–790. 30 years with Intel, he has held numer- 2000. His current research is focused [8] R. K. Brayton, G. D. Hachtel, C. T. McMul- len, and A. L. Sangiovanni-Vincentelli, ous positions, including senior vice primarily on interconnect issues in Logic Minimization Algorithms for VLSI president and general manager of the VLSI systems, covering all levels from Synthesis (The Kluwer International Series in Engineering and Computer Science, vol. Digital Enterprise Group, first-ever physical design of wires to network- 2). Boston, MA: Kluwer, 1984. Intel CTO, CTO for Intel Architecture on-chip and multicore systems. [9] G. D. Hachtel, A. L. Sangiovanni-Vincen- Group, general manager of desktop Gadi Singer is vice president of telli, and A. R. Newton, “Some results in optimal PLA folding (invited paper),” in products, design manager for the the Intel Architecture Group and gen- Proc. IEEE Int. Conf. Circuits and Comput- Pentium Pro and 80486 processors, eral manager of Intel’s SoC Enabling ers (ICCC ’80). New York, NY: IEEE, 1980, vol. 2, pp. 1023–1027. architect of the 80486 processor, and Group. He joined Intel in 1983; [10] A. Kolodny, R. Friedman, and T. Ben-Tzur, CAD logic methodology manager and among other accomplishments, he “Rule-based static debugger and simulation compiler for VLSI schematics,” in Proc. IEEE designer for the 80386 processor. was appointed vice president and Int. Conf. Computer-Aided Design (ICCAD), He has a master’s degree in E.E.C.S. CTO of Intel Communications Group Santa Clara, CA, Nov. 1985, pp. 150–152. from Stanford, a bachelor’s degree in in 1999 and 2004, respectively. From [11] J. Reed, A. L. Sangiovanni-Vincentelli, and M. Santomauro, “A new symbolic channel E.E.C.S. from Santa Clara, and an hon- 2005 through 2007, Singer served as router: YACR2,” IEEE Trans. Computer-Aid- orary doctorate from William Jessup general manager of the Ultra Mobility ed Design Integr. Circuits Syst., vol. 4, no. 3, pp. 208–219, 1985. University. He has received a variety Group. Among his prior roles, Singer [12] C. Sechen and A. L. Sangiovanni-Vincen- of industry awards, published sev- was general manager of Intel’s Design telli. “TimberWolf 3.2: A new standard cell placement and global routing package,” in eral books and many papers, and is Technology Division, cogeneral man- Proc. 23rd Design Automation Conf., 1986, an IEEE Fellow. He is married with ager of the IA-64 Processor Division, pp. 432–439. four adult children. and general manager of the Enterprise [13] T. J. Wagner, “Hierarchical layout verifi- cation,” in Proc. 21st Design Automation Desmond Kirkpatrick is a prin- Processors Division. He has received Conf., 1985, pp. 484–489. cipal engineer responsible for Intel’s three Intel Achievement Awards [14] R. K. Brayton, R. Rudell, A. L. Sangiovan- ni-Vincentelli, and A. R. Wang, “MIS: A research road map in design effi- for his technical contributions. In multiple-level logic optimization system,” ciency. From 1991 to 1999, he was a 1983, Singer received his bachelor’s IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. CAD-6, no. 6, pp. 1062– member of the Pentium Pro and Pen- degree in electrical engineering from 1081, Nov. 1987. tium 4 microprocessor design teams. Technion–Israel Institute of Technol- [15] E. Detjens, G. Gannot, R. Rudell, A. San- In 1999, he became Intel’s first tech- ogy, where he also pursued graduate giovanni-Vincentelli, and A. Wang, “Tech- nology mapping in MIS,” in Proc. IEEE Int. nical liaison to the Gigascale Silicon studies from 1986 to 1988.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:38:32 UTC from IEEE Xplore. Restrictions apply. Philippe Geyres, Pasquale Pistorio, and Aldo Romano

The 30-years’ peace

his article is about the long and productive rela- tionship Alberto Sangiovanni-Vincentelli had with STMicroelectronics (STM) and T the many exciting moments we shared with him. Alberto started working with STM when it was called SGS-ATES back in 1978; he had joined the Berkeley faculty just a couple of years earlier. Two of us (Pasquale and Philippe) were not in the company yet. In fact, Pasquale used to joke that Alberto was older than he (meaning at STM). Pasquale was called in from Motorola, where he was general manager of the International Semiconductor Divi- sion, to lead SGS in 1980 and met Alberto shortly after during one of his visits to SGS. Until then, Alberto’s contact at our company was Raimondo Paletto, who ran R&D. Philippe joined the company after the merger with Thomson, a key step in making STM one of the largest semi- conductor companies in the world. Aldo and Philippe became the managers of the company’s two largest product groups: telecommunication, peripherals and automotive (TPA) and home, personal, and communication (HPC). Alberto provided us with outstanding guidance and consulting in the following three forms.

Advising in Specific Technology Matters Concerning Architecture, Software Development, and Complex Platforms In this respect, Alberto’s advice was specifically technical in nature and was focused in particular on the product groups’ general managers and the direction of R&D. Pasquale’s role as CEO was to be the catalyst for implementing Alberto’s advice. Alberto contributed in a substantial way in central R&D to structuring the design flows and tools used at STM. He accomplished this by introducing optimization in analog design and by using novel simu- lation tools and logic synthesis methods, as discussed in Massimo Vanzi’s sidebar in “Corsi e Ricorsi: The EDA Story.” In particular, he was instrumental in setting up the partnerships

Digital Object Id entifier 10.1109/MSSC.2010.937692

44 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/10/$26.00©2010IEEE

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:41:07 UTC from IEEE Xplore. Restrictions apply. with SDA, Cadence, Chrysler, Magneti Marelli, and STM and Synopsys that all described how they followed are still essential in a design methodology, platform- our design flows. based design, to design their prod- Alberto contributed in ucts. In particular, they explained a substantial way to the how Magneti Marelli, PARADES, and design methods and archi- STM collaborated using Cadence’s tecture definition for the two Virtual Component Composer tool product groups led by Aldo and to design engine controllers based Philippe. In the TPA group, he on the ST10 microprocessor and to helped guide the development of design a novel dual-core architec- microprocessors for automotive ture called Janus. Alberto’s con- applications and pushed the group tributions to automotive design to look into dual-core architectures influenced the formation of the in the years 1996–2000, before AUTOSAR standards.

Alberto helped guide the development of microprocessors for automotive applications and pushed the TPA group at STM to look into dual-core architectures before all IC companies, including Intel, began to design this kind of microprocessor.

all IC companies, including Intel, On the HPC front, Alberto helped became interested in and began to shape the concept for a platform design this kind of microproces- that was crucial in the develop- sor. In 1996, he formed an indus- ment of product offerings in the trial research group, the Project set-top box category, where STM on Advanced Research in Archi- went on to earn a dominant market tecture Design and Embedded position, especially in the satellite Systems (PARADES) in Rome domain. that was supported by STM, Cadence, and Magneti Advising with Regard to the Broad Marelli. The role of this orga- Technology Trends of the Industry nization was crucial in facilitating Pasquale used to have regular the creation of specific programs yearly events during which Alberto among the three companies and gave presentations to the senior in creating new ways of designing management team, dubbed “Pisto- semiconductor products to help rio’s staff,” and guided debates on manage the technical relationships industry trends. Those events were between Tier 1 suppliers and STM. always extremely provoking and In addition, he helped reinforce the stimulating for all of us and partic- relationships of Tier 1 suppliers ularly for Pasquale. Alberto pointed such as Magneti Marelli, STM and out the evolution of IC companies BMW. In 2000, he organized a semi- toward more regular designs, reuse, nal special session at Convergence and the system-on-chip concept. in Detroit, the most important con- The evolution of design methodolo- ference in automotive electronics. gies toward the system level and the There, BMW, Cadence, Daimler- challenges of increasing complexity

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 45

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:41:07 UTC from IEEE Xplore. Restrictions apply. and design costs made it essential and sent one or two STM engineers to ■ STM Berkeley Labs. Alan Kram- to gain efficiency in order to remain Berkeley to collaborate on advanced er, a doctoral student of Alberto’s, competitive. Alberto also pushed research. Then it participated in joined STM as a summer intern the company toward the adoption industrial consortia such as the in 1993 in central R&D. His work of an organizational structure that CAD/CAM Consortium, the Berkeley was so much appreciated that Joel would favor reuse. Pasquale issued Sensor and Actuator Center (BSAC), Monnier, head of R&D, offered him a directive in 1998 to create aware- the Berkeley Wireless Research Cen- a permanent position as director ness of the need to reuse designs ter, and the Center for Information of a new research group of more and to define a methodology in- Technology Research in the Inter- than 20 people. He started on this tended to be followed by the entire est of Society (CITRIS). Alberto’s following a research collaboration corporation. Roberto Fantechi was doctoral students, colleagues, and with Roberto Guerrieri in Berke- asked to drive this initiative, which visitors have collaborated in many ley on novel chip-sensing archi- yielded a set of design rules called ways with STM. To give two promi- tectures. They developed a new the Blue Book. nent examples: Roberto Guerrieri CMOS camera and a new CMOS capacitive fingerprint sensor that was the very first example of the use of ICs in fingerprint recogni- Among his many gifts, Alberto has always been tion. In 1996, following the forma- able to reduce complex technological matters tion of the Cadence Berkeley Labs, STM decided to follow Alan’s and to simple terms in order to make them easily my recommendation to form STM understood by managers without deep scientific Berkeley Labs. The Labs were in- backgrounds. deed established in 1996, under Alan’s leadership. There, the fin- gerprint idea was developed far enough that it became part of Alberto also spoke to us about headed the STM/University of Bolo- Piero Martinotti’s New Venture the need to invest in software and gna Research Center, and Rinaldo Group at STM, under the name of in system design in order to facili- Castello headed the STM/Univer- Touch Chip. tate the introduction of innova- sity of Pavia Research Center, where ■ UPEK. After a few years, it be- tive products. some of the most interesting analog came apparent that there was an Alberto’s direct interaction with design concepts were formed. Other interesting business behind this Pasquale as CEO related to the pro- initiatives he was involved with are product that could best be lever- ductivity and organizational struc- listed below: aged by spinning it off. Pasquale ture of R&D and the interaction of ■ Accent. In 1993, Alberto, Joe Cos- had a meeting with Alberto, Alan, central R&D with the various busi- tello, Pasquale Pistorio, and Rai- and Piero, and the spin-off was ness groups. Pasquale always appre- mondo Paletto met in Pasquale’s approved. It did take time to form ciated Alberto’s ability to bring both office in Agrate and launched a the company, which was head- his deep scientific knowledge and joint venture between Cadence quartered in Berkeley, but in the his understanding of entrepreneurial and STM on design technology, end VC funding was provided and and business topics to bear on strate- with Massimo Vanzi as the gen- the company started went into gic company issues. eral manager and Raimondo Pal- operation in 2005 with Alberto etto as CEO. Alberto and Aldo and Piero as board members. Helping in the Establishment of Romano were named to the board. Alberto helped STM in many dif- Research Labs, Joint Ventures, This joint venture had a Cadence ferent ways that had a strong impact and New Initiatives majority (51% Cadence, 49% STM) during the critical years of its growth. Alberto has always had a keen inter- that was later changed to 51% After we left the company, we all est in putting together companies STM, 49% Cadence to reflect the stayed in touch with Alberto, as a and groups to collaborate for the strategic value that Accent had for friend and as a business and technol- advancement of technology and Aldo’s TPA group. In 2005, Accent ogy adviser. Pasquale did so during business. During our tenure with became independent after an in- his tenure as president of Telecom the company, STM has always sup- fusion of VC funding; Alberto was Italia, where Alberto had advised the ported the research of Alberto and the only surviving director after previous president on technology his colleagues at Berkeley. First, it the transition. Piero Martinotti issues pertaining to the use of wire- directly funded his research activ- took the position of chairman of less sensor networks. Pasquale in- ity in design methodology and tools the board. vited Alberto to present his ideas to

46 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:41:07 UTC from IEEE Xplore. Restrictions apply. management and to various meetings he became corporate vice presi- and was subsequently appointed to of the Telecom Italia research staff. dent for strategic planning at SGS- the position of honorary chairman. Aldo is a partner in crime in a new Thomson. In 2005, he assumed Pistorio is also founder and presi- initiative on clean energy, sharing a responsibility for the company’s dent of the Pistorio Foundation, a position with Alberto on the board newly created home, personal, nonprofit organization that assists of advisers of HIQE, and Philippe has and communications group and underprivileged children. discussed innovation with Alberto became executive vice president Aldo Romano graduated in 1963 at Oberthur. following the formation of STMi- in electronic engineering from the Among his many gifts, Alberto has croelectronics’s Corporate Execu- University of Padova. Two years later, always been able to reduce complex tive Committee. In 2007, he was Romano joined SGS Microelettronica technological matters to simple terms appointed CEO of Oberthur Card (a predecessor company to STMicro- in order to make them easily under- Systems, a French smart card com- electronics) as a designer of linear stood by managers without deep sci- pany. Since 2009, he has consulted integrated circuits (ICs). In 1970, entific backgrounds. For this reason, for the electronics and smart card Romano was appointed head of the he has always been an invaluable resource for high-level management. It is rare to find a deep technologist who can also get to the point quickly Alberto helped shape the concept for a platform and underline the important aspects that was crucial in the development of product of an issue so as to help in making offerings in the set-top box category, where important decisions. One last consideration: we have STM went on to earn a dominant market rarely met a person who, in addition position, especially in the satellite domain. to his scientific and business com- petence, has such a strong drive and ability to deal with many different business, social, and scientific envi- industries. He is a member of the Linear IC Design Department. In ronments and subjects. Alberto can board of ADB, Arteris, ASK, and 1976, he was promoted to head of contribute effectively in an amazing Trident Microsystems. marketing and applications and be- variety of tasks and contexts, includ- Pasquale Pistorio graduated in came director of the Bipolar IC Divi- ing academic duties, research ac- 1963 in electrical engineering from sion in 1980. Following the merger tivities, start-up companies, the VC the Polytechnic of Turin with a de- of SGS Microelettronica with Thom- area, on the boards of several cor- gree in electronics. In 1967 he joined son Semiconducteurs in 1987, all porations, and, on top of all of this, Motorola in Italy, rising through the application-specific IC activities of pursuing all those activities in many ranks to become director of interna- the company were grouped into Ro- different parts of the world. Alberto tional marketing, based in Phoenix, mano’s organization, renamed the is a real Renaissance man. Arizona. He was also appointed vice Dedicated Products Group. In 1991, president of Motorola Corporation he was appointed CEO of STMicro- About the Authors and then became general manager electronics srI, the group’s Italian Philippe Geyres graduated as of Motorola’s International Semi- subsidiary, in addition to his role as an engineer from the École Poly- conductor Division, responsible for general manager of the Dedicated technique, near Paris, in 1973. He design, manufacturing, and market- Products Group. Following a reor- began his professional career that ing activities for all regions outside ganization in 1998, the Dedicated year with IBM at Corbeil-Essonnes, of the United States. In July 1980, Products Group became the Tele- France, before joining the Schlum- he returned to Italy as president communications, Peripherals, and berger Group in 1980, working first and CEO of SGS Group, the only Automotive (TPA) Groups, with head- in oil services and then at Fairchild Italian microelectronics company. quarters in Agrate Brianza (Italy) and Semiconductors. He worked for ST- In 1987, he oversaw the successful Grenoble (France), and he was pro- Microelectronics and its predeces- integration of SGS with the French moted to corporate vice president sor companies from 1983 to 2006. semiconductor firm Thomson Semi- and TPA’s general manager. Romano In 1983, he was appointed direc- conducteurs. He is a member of the retired from his position as head of tor of Thomson Semiconducteurs’s United Nations Information and the TPA Groups in 2005 while con- bipolar IC division. Following the Communications Task Force, dedi- tinuing to serve as CEO of ST Italy. merger of Thomson Semiconduc- cated to bridging the “digital di- Since 2006, he has also been presi- teurs and SGS Microelettronica, vide.” He retired from STM in 2005 dent of the Italian subsidiary.

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 47

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:41:07 UTC from IEEE Xplore. Restrictions apply. Presentation of the 2001 Phil Kaufman Award to Professor Alberto Sangiovanni-Vincentelli

8th November, 2001 By A. Richard Newton

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Reprinted with permission.

Digital Object Id entifier 10.1109/MSSC.2010.937689

48 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE

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IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 49

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50 SUMMER 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE

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7R$OEHUWR About the Author A. Richard Newton was the Roy W. Carl- etal and quality-of-life problems in areas that include son Professor of Engineering at the Univer- energy, the environment, transportation, health care, sity of California, Berkeley, a professor in disaster mitigation and response, and education. He was the department of Electrical Engineering the founding director of the MARCO/DARPA Gigascale and Computer Sciences, and the founding Silicon Research Center for silicon chip design and test, director of the MARCO/DARPA Gigascale a founding member of both the EDIF technical and steer- Silicon Research Center for Design and Test. ing committees, an advisor to the CAD Framework Initia- He received a number of awards and honors for his tive, and a founding member of EDAC. teaching and research, including the IEEE Golden Jubilee In addition to his academic role, Richard had helped to Award for his contributions to circuits and systems, a found a number of design technology companies, includ- Doctorate of Laws, honoris causa, from his alma mater ing SDA Systems (now Cadence Design Systems), PIE Design the University of Melbourne, Australia, and an honorary Systems (now a part of Cadence), Simplex Solutions, Cross- professorship in integrated circuit design at the National bow, and Synopsys. He was a member of the Board of Chiao Tung University, Hsinchu, Taiwan. In 2003, he Directors of Tensilica, Inc., a member of the technology received the 2003 EDAC Phil Kaufman Award. council of ST Microelectronics, and a long-time member His teaching and research interests included all of the Microsoft Research’s Technical Advisory Board. He aspects of the design of electronic systems, the appli- also was a venture partner with the Mayfield Fund, and cation of information and communication technolo- with Tallwood Venture Capital. In addition, he served gies (ICT) to the solution of societal problems (Center on the Board of Trustees for the Anita Borg Institute for for Information Technology Research in the Interest of Women and Technology. Society), and B-2-4B: the role of ICT in the creation of He was a Member of the ACM, Fellow of the IEEE, a an inclusive global society. In 1999, he founded CITRIS, member of the National Academy of Engineering, and a dedicated to the application of information and commu- member of the American Academy of Arts and Sciences. nication technologies to the solution of such tough soci- Dr. Newton died in 2007.

IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 51

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:42:27 UTC from IEEE Xplore. Restrictions apply. Remembering Richard

I. INTRODUCTION We had practice on Mondays and Wednesdays, and we played A. Richard Newton was larger than life in the eyes of the ones games on Saturdays. Most Sundays, I’d be flat on my back re- who had the fortune of meeting him. His outlook on life was covering because it’s a very violent game. I also played bas- so different, innovative, and refreshing that one could not avoid ketball for the University of Melbourne. I traveled around the being enthralled by his ideas long after parting ways. In this country playing for the University for two seasons. I was also paper, I remember him both as a wonderful human being and as active in athletics when I was younger. My preferred event was an old and dearest friend. It is not easy for me to do justice to the triple jump. One of my brothers told me last year—he’s a the great contributions that he made to the EDA community and school teacher back in Australia—that I still hold the Victoria to the world in general. I begin with my own rendition of his state triple-jump record for high school students under the age accomplishments and his biography decorated with comments of 17.” from students and colleagues. The body of the paper is about Aart de Geus in his presentation for Richard’s Kaufman his most significant speeches, which are the best witnesses of Award recalls how he became involved in electronics. “His his vision and legacy. His own words are so eloquent and con- passion for electrical engineering was awakened by his dad, vincing that any editing would dilute the message. I will first whose own dream was to be an engineer. As Rich’s brother quote excerpts from his DAC key note address of 1995 and con- Mike says: ‘If Dad were alive today, he would probably see clude with his unabridged presentation in Berkeley about “the in Rich everything that he himself always wanted to be.’ The future of the future.” projects that Rich took on were big ones, limited only by the amount of equipment and electric wire he could drum up. His entire family recalls vividly how he transformed the roof of II. RICHARD:THE MAN AND HIS HISTORY their house into an aerial antenna, which he used as a radio Richard was not only a wonderful engineer and a superb pro- telescope and to track satellites.” Richard deeply loved his fessor but also a great man. He would not rest on the laurels of family. He and his siblings had been always close even though his (many) industrial and academic successes like many of us they would see each other infrequently. are tempted to do; rather he pursued relentlessly noble causes He excelled in other “sports” as well. He told me several that could (and did) have an impact on the human condition. stories about the competitions among Australian students to Nothing was too hard for him. He would complain at times and see who was able to drink beer quickly and in gargantuan act distressed, but would never abandon an idea he believed in. proportions! Richard liked BIG, audacious ideas and as soon as he saw a His involvement with EDA started way back. A fortuitous way of making them a reality and in good hands, he would move meeting in the early 1970s with Donald Pederson, who died on to something bigger and better. in 2004, was the event to kick-start Newton’s lifelong interest In Chancellor Birgeneau’s words: “An inspired and dynamic in electronic design automation (EDA). In his own words “In leader, Richard understood the power of engineering and 1970, I had the good fortune to bump into Professor Donald technology in entirely new ways and he connected them to Pederson in the computer room of the University of Melbourne, addressing society’s toughest problems. He had an unrelenting Australia, and before I knew it, I was a SPICE-1 developer” commitment to engineering for the betterment of society. His [1]. He arrived in Berkeley to pursue his Doctorate in August passing is an enormous loss to us at UC Berkeley and for 1975; I arrived there July of the same year. We met at the end of engineering nationally and internationally.” Richard’s own August when he literally ran over me turning a corner at the words are perfect to define the kind of leadership he exercised: speed of light while I was running in the opposite direction. “A great leader is someone, first and foremost, who can build a From that collision, where it is easy to imagine who had the relationship of trust with the people that he or she works with. worst consequences (Richard was almost 2 meters tall and I am A leader needs to create a vision that’s compelling enough 1.68 meters short!), a close friendship sparked. We talked and that everyone who is part of that vision wants to contribute to talked and talked about everything in life. We were so different it personally, and also believes that they’re part of something in background and yet so close in our enthusiasm and passion for much greater than themselves.” He was all of this and more. the intellectual endeavors that a University career would offer As a perfect epitome of the Greek and Roman classical ideas us. of “mens sana in corpore sano” (a healthy mind resides in a While a student in Berkeley, he spent time in a village in healthy body), Richard was an accomplished athlete. In his own the inner part of India to do volunteer work. His passion for words in an interview with Peggy Aycinena [11]: “I played a third world countries and for disadvantaged populations origi- number of sports. Ultimately, I played Australian-rule football nated then. He described to me over and over again the extreme semi-professionally as a student. Eventually, however, I had to poverty he saw and his ideas on how to alleviate the suffering of make a tradeoff between my studies and my sports injuries. children and women in that part of the world. In 1978, Newton earned his Ph.D. degree under the guid- ance of Don Pederson and was appointed to the engineering Digital Object Identifier 10.1109/TCAD.2007.902701 faculty later that year after he received several important offers

Digital Object Id entifier 10.1109/MSSC.2010.937688

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. in industrial research Labs and other Universities. His choice unmatched talent in marrying technical insights with industrial for Berkeley is best described by his own words [11]: “I had a needs. In these years, he also predicted the great importance of girlfriend at the time, a student from Berkeley who was on an logic manipulation and optimization [6] that led to the forma- exchange program in India. I wrote her a letter there and ex- tion of Synopsys in 1987. There he served on the Board of Di- plained my choices, and asked her what she thought I should rectors from its inception and had a major role convincing Aart do. She wrote back and said all of the offers looked good, and de Geus, who later became one of his best friends, to try the that I should choose the one that I thought I liked best. I chose start-up adventure. He played an important role also in forming Berkeley because I knew she was familiar with the campus and other EDA companies such as Pie Design and Simplex Solu- thought that would be her first choice. When I wrote her and tions (both eventually acquired by Cadence). told her, she wrote back and said that Berkeley was the worst After the great technical and business success of these ini- possible choice. Unfortunately, she wasn’t my girlfriend much tiatives, Richard moved his interest to the process of enterprise longer after that.” We at Berkeley are so grateful to her for “in- formation. Beginning in 1988, he advised several venture cap- spiring” Richard’s choice of the “right” place to work! ital firms, including the Mayfield Fund, where he was a Ven- Richard quickly scaled the academic ladder, going from assis- ture Partner until 2002, and Tallwood Venture Capital, where tant professor in 1978 to associate professor in 1982 and to full he contributed both to the evaluation and early stage develop- professor in 1985. During that period, we traveled the world to- ment of more than two dozen new companies including Silicon gether giving lectures and courses on circuit simulation, layout, Light Machines (where he acted as president and CEO during and logic synthesis. I remember our plan of visiting China to- 1994 and 1995)—while still teaching digital logic design to an gether for the summer with our families. We were invited by undergraduate class of over 180 students. “Newton had an as- the Chinese government who would have allowed us to hike in tute business mind, something you wouldn’t necessarily expect Nepal that at that time was closed to tourism. The plan never ma- from an academic,” said Dado Banatao, managing partner of terialized because of the length of stay that the Chinese govern- Tallwood and chair of the Berkeley College of Engineering ad- ment required of us. We instead went to Japan and Hong Kong visory board. Few people know that he helped found Crossbow visiting companies and places where no English was spoken and with Mike Horton, one of his students, and in doing so, sparked we had to make do with the Italian universal gesture language. the research on the Berkeley motes, smart dust, and wireless In his Ph.D. thesis, Richard saw the possibility of developing sensor networks [9]! tools for mixed-mode design where analog and digital compo- In the late 1990s, Richard raised the industrial and academic nents could be developed together [2]. He also intuited that re- world to a new level of understanding [8]. He initiated a com- laxation-based techniques had great promise for MOS circuits plex process that led eventually to the formation in 1998 of the and developed what was then called Iterated Timing Analysis in MARCO/DARPA Gigascale Silicon Research Center (GSRC), collaboration with his students. This method is still the basis of a major private-public partnership with the U.S. government the fast circuit simulators being sold today by the EDA industry. and the semiconductor industry that funds and coordinates long- Together, we developed jointly a body of knowledge that went range research at a dozen major U.S. universities and involves under the name of “Relaxation-Based Simulation.” The paper many industrial collaborators [10]. He served from 1998 to 2002 that summarized our thoughts [4] was published simultaneously as the founding Director of the GSRC. As a consequence of by three journals, a unique case in our discipline. his new interests and acquired skills, Richard served as chair In parallel, his interests evolved to cover all branches of EDA of the Department of EECS from 1999 to 2000. In 2000, he was [3]. His main technical contributions in this period were in the elected Dean of the College of Engineering and became the Roy field of CAD frameworks where he spearheaded the develop- W. Carlson Professor of Engineering. He served in this capacity ment of unified databases and graphical user-interfaces for the until his death. design of electronic circuits. He was the technical force behind During his tenure as Dean, Richard was the driving force be- the Electronic Data Interchange Format (EDIF) standard [2]. hind the creation of the UC Berkeley-based Center for Informa- This work evolved into the OCT/Vem framework that served tion Technology Research in the Interest of Society (CITRIS), as the backbone for the Berkeley EDA team programs and one of four California Institutes for Science and Innovation. approaches [5], [7]. In 1983, he helped found SDA, the parent CITRIS was established in 2001 to develop the next generation company of Cadence Design Systems, Inc., a company that of technologies that will be critical to sustaining California’s made the ideas of a unified framework for design its flagship. economic growth and global competitiveness and to solving so- In this period, it was clear that he had a unique gift: he could ciety’s most critical needs. “sense” the future and act to direct it. He saw in the late 1970s In these last few years, Newton became a champion of with great clarity that the computing world was moving towards synthetic biology, seeing the emerging field as the application workstations from big mainframes and that Unix would have be- of engineering principles to the life sciences. He played a major come the operating system of choice for engineering worksta- role in the establishment of the Berkeley Center for Synthetic tions. He then put his reputation on the line at a very young age Biology, as well as of the Synthetic Biology Engineering and pushed companies and colleagues (including me!) to join Research Center, or SynBERC, launched last year with a $16 in developing tools and methods on a DEC VAX equipped with million grant from the National Science Foundation. “The Berkeley Unix. In doing so, he was creating the basis for a new center wouldn’t have happened without Rich,” said SynBERC industry and at the same time, he was providing a great test-bed director Jay Keasling, professor of chemical engineering and for our Berkeley colleagues in the Unix group. Richard had an bioengineering. “He was an incredible supporter and an

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. excellent spokesperson for the center. He could make beautiful to “go for it” and set their talent free!” His students perceived analogies between what has happened in high technology and how much Richard cared for them. Deirdre Ryan Hanford, what is now happening in synthetic biology.” Richard Blum, Senior Vice President, Global Technical Services, at Synopsys, San Francisco financier, philanthropist and vice chair of the said: “Richard was proud of me. I could feel it. This helped UC Regents, credits Richard for helping develop the concept propel me.” Resve Saleh, the founder of Simplex and now for the Richard C. Blum Center for Developing Economies, Professor at University of British Columbia: “He was a great a major multidisciplinary campus initiative launched in April role model. I hope to carry on his legacy through what I have 2006 with a $15 million gift from Blum. “It was his idea that learned from him and will pass this knowledge on to the next we should use UC’s innovative technologies to help developing generation of students in our field.” Mike Horton: “Indeed, countries,” said Blum. “Technology had mainly benefited Richard’s biggest gift to me is the strengthening of my inner developed countries.” person and the opening of my mind to a world which is much Richard was a strong advocate of promoting women in engi- bigger and brighter than I had realized on my own.” neering, and while he was dean, the number of women on the Richard and I built together a strong research team at faculty at the College of Engineering nearly doubled from 15 in Berkeley stressing the importance of disinterested collabora- 2000 to 27 today. Newton also served on the Board of Trustees tion and friendly competition. As Aart puts it: “The ‘Rich and for the Anita Borg Institute for Women and Technology, which Alberto’ combo, was an engine of formidable impact. Both are provides resources and programs to help industry, academia and very good friends, quick on their feet, deeply technical, and government recruit, retain, and develop women leaders in high totally competitive.” We used to play tennis tournaments (the technology careers. infamous CAD group double and single tournaments, domi- Richard earned numerous awards throughout his career, in- nated by Bob Brayton after he joined our group!) and to ski cluding the 2003 Phil Kaufman Award. In 2004, he was named in Lake Tahoe. Richard was not a great skier but he would try to the National Academy of Engineering, and in 2006, he was nevertheless even the most challenging slopes with big laughs named to the American Academy of Arts and Sciences. He was from all of us when he crashed! We even used to impersonate also a member of the Association for Computing Machinery and an Australian contest where two teams are competing on the a fellow of the Institute of Electrical and Electronics Engineers. speed with which beers could be drunk. My team always lost Outside of academia and research, Newton maintained a except once when we were clearly ahead but Srinivas De- strong interest in spirituality and Eastern philosophy, formed vadas—one of Richard’s students, now Professor at MIT, and during his years as a student at UC Berkeley. I vividly re- an enterprising member of Richard’s drinking team—who was member our endless discussions about the aspects of Eastern anchoring Richard’s team, decided to sacrifice for the common and Western culture and philosophy where I was playing the good by pouring a full pint of beer over his head (a legal move part of the Western rationalist and he would try to convince me according to Aussie rules!). We ended up losing again! I am about the intangible and the spiritual. He also enjoyed poetry sure Richard is still smiling about this event! (one of his favorite poets being Rilke), painting, and hiking. He was a dear friend to many people. Kurt Keutzer said: While he had numerous occasions to leave the University “Over the years, I’ve thought a lot about the qualities of friend- for a stellar career in industry or other private academic insti- ship: honesty but sensitivity; integrity but loyalty; and most tutions, his love was for UC Berkeley and its students. Orville of all, the irrational willingness to go the extra mile. Richard Schell, UC Berkeley dean of the Graduate School of Journalism demonstrates all of those. Every one of us has so many stories and a close family friend of Richard’s, said “Rich believed with about how Richard’s big heart reached out to make us happy. a passion that it was the responsibility, in fact the obligation, But the fact is that Richard wanted to make each one of you of a great research university to serve the public by applying happy, in a very personal way, and everything else he did arose its brain power to the problems of people around the world. out of that.” What he wanted was for all of us to find ways to harness our brains, brawn, money, entrepreneurial energy, research abilities, III. EXCERPT FROM RICHARD’S DAC KEYNOTE,JUNE 1995 and dedication to solving the problems of our besieged world. Richard devoted most of his career to develop the EDA Rich was an evangelist for academic relevance. He viewed uni- industry and research agenda. He was also instrumental in versities as one of the most important pieces of civil society bringing the Design Automation Conference to heights that real estate in our country and the logical locus of innovative made it one of the most successful conferences in engineering. problem solving. For him, there was no more appropriate task His keynote address in 1995 is a landmark of strategy blended for a “public” university, such as UC Berkeley, than to serve the with analysis of the past. In this talk, he outlined the history of public.” CAD and of the EDA industry and pointed to the challenges Richard always acknowledged the role of his students in that were looming in the dark. Twelve years later, most of his his career and never forgot to mention their contributionsin remarks are of surprising relevance. I selected from the text of accepting honors such as the Kaufmann Award and the DAC that presentation the parts that I felt were of most importance. keynote address. Aart de Geus in his presentation of the Kauf- “From FORTRAN, punched cards, line printer output, even mann Award to Richard wrote: “When asked, though, what he ‘computer rooms’ as we old fogies used to call them, to the is most proud of, the answer is: “my students.” The common interactive, multimedia world we live in today. Along the way, theme among all of them is that Rich was (and is) always there I have had the distinct privilege to observe, and participate in, a for them and fundamentally was the one that “catalyzed” them process of profound change and to work with many very talented

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. people, the people who have driven that change, over the past bigger risks-both from a technical as well as from a business quarter century. perspective, and both in industry as well as in academia. This In a keynote address, one is encouraged to deal only with the risk is a very personal one, it involves putting our reputations prime underlying elements or themes, to try to set a tone for the and our careers on the line at all levels of our organizations, days ahead. That is not easy in an industry that has proven time from student to CEO. and time again, at least to me, that the devil is almost always Those who fund research must return to the longer-term em- in the details! Predicting the future of an industry like ours is phases that actually led us to where we are today. Don’t ask always risky. for ‘deliverables in six months or a year,’ ask ‘what might we The point I make is that long-range predictions of the future in learn from this work.’ Don’t ask for software, but rather expect technology—in our field—tend almost always to be overly pes- a deeper understanding. Even in the question itself, one preju- simistic. The long-term future almost always outperforms the dices the process. Trust that the deliverables, the understanding, pundits, often in unpredicted directions. We are almost always and even perhaps the software will come, It’s more likely to be too conservative, even in an industry that has changed the world. what you really need if you don’t insist upon it. As you look When we think of the semiconductor industry today, we see around the Conference this week, and reflect back on the state plots on semi-log paper continuing upward and to the right. We of our industry a quarter century ago, I’m sure you will agree imagine lots more gates, mixed-signal design, more chips on a we have a lot to be very proud of indeed. The $100B semicon- board, and lots more hard work for us all. We imagine tough ductor industry simply would not exist in its present form if it problems just getting tougher, and they are important problems wasn’t for our meager $1.2B contribution. That’s right, we and they are getting tougher. But are big, complex, deep-submi- just don’t get the respect we deserve! cron chips the only path which leads to the future? Fortunately, So the EDA carousel may characterize a phenomenon many there is a small cadre of marginally crazy people out there trying of us have observed over the years. But what is its root cause? to change the problem rather than simply trying to solve it. And is it possible to defuse it? Try to imagine, for example, self-powered chips powered I believe the cause is most strongly related to a lack of con- only by incident radiation or some novel battery technology, sistent and sustained investment in the technical infrastructure communicating amongst each other using tiny semaphores, by of the industry and that it most certainly could be avoided. The waving tiny micromechanical mirrors, or by making noises like topic we refer to as Deep Sub-Micron is perhaps the most ob- crickets in the night. These unpackaged, tiny silicon die might vious approach to revolutionary change, certainly it was a hot float around us, perhaps sampling atmospheric conditions and topic at last year’s Conference and is the approach that has been signaling results back to some central site. They might be most discussed over the past year. The one caveat I will add dumped by the bucket-load from transcontinental jet aircraft, here is that this is as much about methodology as it is about working together as a team as they drift slowly to earth. Or tools—as much about the way the tools are organized and the perhaps they might be glued onto the leading edge of a jetliner, way they interact as it is about the specific capabilities or par- steering the plane using thousands of 100-micron long micro ticular emphasis of the tools themselves. The real winners here fingers. Or perhaps, a slurry of such chips might be painted will be those who re-think the entire back-end IC design flow, onto the surface of a bridge, or the walls of a house, sampling not those who simply improve or augment existing offerings, ex- temperatures and stresses. Fortunately, there are people con- isting methodology. With one hundred million devices and eight sidering such things, even developing them. And I’m sure, in layers of relatively poor interconnect, we are wiring-driven-the the future, such developments will come to pass. In this light, problem becomes routing and placement, rather than placement if there is a single point I wish to make here today, it is that and routing. Even logic synthesis must change, with a return to as a discipline, both in industry and in academia, we are just a switch-level emphasis and library generation on-the-fly. not taking enough risks today, and most certainly not from a At the other end of the electronic design spectrum, we have technical perspective. heard a lot about HLDA and ESDA. System-on-a-chip and hard- We still have just as many bright, creative people as we have ware-software co-design. We are told of the advantages of cycle- always had, most of whom stand ready to change the world in based simulation and the promise of formal verification. There very dramatic ways. Many of whom continue to be frustrated is a revolution coming here, and all of the aforementioned will as they share their vision in a hiring process which often seems doubtless be a part of it. However, once more, this is not a tool to consider Windows 95 programming experience as its most issue per se but it is rather largely a methodology issue. It has to important strategic hiring criterion. It is perhaps no wonder then do with how best to represent the design at higher levels of ab- that the business community believes that “Buying companies straction first, what are the right primitives to use in our models. is a legitimate way of doing research and development in this Right from both the user’s point of view as well as the design industry,” as Robert Stern, an analyst with Smith-Barney put it. technologist. Acceptable ways to represent the passage of time, Taking technical or business risk is not new to us. Virtually to represent the protocols between elements of the design and, every successful start-up in our industry owes its early advan- of at least equal importance, the best ways for the user to interact tage to such risks. And the larger companies in our industry are with the design. In my view, a key insight here is the realization often forced to take on substantial business risk, as they struggle that in today’s world, with its complex and ever-changing in- to feed the ever-demanding Wall Street inferno. teractions among the components of an electronic system, mod- However, if we are to continue the revolution, if we are to eling and animating the environment in which a design is ex- exceed our own expectations, we must be prepared to take even pected to operate is as important as modeling the design itself.

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. reminded of Bob Lucky’s comment at this very meeting some years ago: “I feel like I’m driving a car into an impenetrable fog and I can’t see even a foot in front of me, while when I look into the rear vision mirror everything is crystal clear!” It seems to me that the Future of the Future is far more about how we are headed today than trying to guess where we are headed. With that in mind, I have organized my remarks into three parts, as follows: 1. The Century of the Engineer, and the critical role of the Research University campus; 2. The Bay Area is the Corporation; 3. The Reformulation of Everything.

A. The Century of the Engineer Sun Microsystems CTO Greg Papadopoulos once told me, and I quote: “If the 20th century was the century of big sci- ence—particle accelerators and uncovering the secrets of the To me, this means a lot more than simply a ‘pins-out’ perspec- atom; discovering the secrets of the cosmos—then the 21st Cen- tive. If one starts by building a system that can represent and tury has to be [emphasis added by editor] the Century of the En- animate the rest of the world, then animating and evaluating the gineer—the global challenges we all face simply demands it.” design itself becomes straight forward. In summary, we have I certainly agree with Greg, as I’m sure many of you do as come a long way over the past quarter century and it should be well. Beyond the borders of our own college and of Berkeley clear to us all that we have an exciting future ahead of us. per se, what looms first and foremost on my mind today are I would like to take this opportunity to thank all of those who the many great challenges our global society faces, and what I have had the distinct privilege to work with over the years, in science and engineering might be able to do to help us address all aspects of our field, and most especially I thank my many them. Of course, I have certainly been inspired in my own students. It is through their eyes that I continue to see the world thinking about these problems by our CITRIS institute and in a new light almost every day. by the many faculty, students, and industrial and Government We are, once again, on the verge of a revolution, a revolution partners at our four CITRIS campuses who share these con- which has a number of important dimensions, each of which will cerns. These challenges are certainly not small ones. For me, change our world and will benefit our users in profound ways. any list of global priorities must include the Three E’s,asI Success in any one of these areas involves taking risks, big risks, refer to them—developing a sustainable and affordable supply in both research and in development. As a discipline, I hope we of environmentally-friendly Energy; curing Epidemics, and find a way to undertake these challenges and opportunities but, particularly the neglected diseases of the developing regions no matter what happens, the times are certainly bound to remain of the world; and Education—especially educating women ‘interesting.’ ” throughout the world. These are my top three—of course there are many more and even these can be broken down into IV. THE FUTURE OF THE FUTURE:RICHARD’S ADDRESS some fairly sizeable sub-challenges themselves. If we faculty, TO THE BERKELEY EECS ANNUAL RESEARCH students, and our partners on the great research university SYMPOSIUM,FEBRUARY 23, 2006 campuses of our world—and I include everyone here today—if After his visionary role as a founder of the EDA industry and we don’t step up to these challenges, then who else will? Who as a founder of the MARCO GSRC center, Richard responded else can? And that is the first point I would like to leave you to higher calls of duty when he took on the responsibility of the with today. College of Engineering at Berkeley. His tenure was memorable: Over the past two decades we have witnessed the demise of he founded CITRIS and started many important programs that the great corporate research institutions of the 20th Century: set the stage to make Berkeley a guiding light in fields such as Bell Labs, Xerox PARC, and it seems to me that even IBM Re- synthetic biology. The text in this section is the best I have ever search is under attack. I used to say HP was a significant holdout seen for global vision, passion and ideals. I believe there is no until they recently cut their research labs in half. My friend better way of remembering him than trying to fulfill his vision! Ulrich Ramacher, here today from Infineon, called me from Ger- “When Kurt Keutzer first asked me to speak with you today many last year to say that his Corporate Central Research Labs about the Future of the Future, I think he and I both had in mind a were being largely disbanded. With the exception of Microsoft talk about technologies and their implications beyond the end of Research—for now—none of the modern ICT companies have any known ‘roadmaps’—a kind of updated Buck Rogers of the made any significant investments in internal, medium to long 25th Century talk. But the more I thought about it, the more I range research. came to the conclusion that The Future of the Future—where we With every passing day and the death of every corporate re- are headed—depends far more on how we approach the journey search laboratory, and as the complex, societal-scale problems itself than on any particular outcome. In these times of rapid we choose to tackle truly demand the “horizontal collabora- change and global restructuring of just about everything, I am tions” Carly Fiorina often referred to, the research university

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. campus is evolving to become a critically important resource the world—is that never before has actually where you are on for government as well as industry, playing the role of a kind the world been more important! of open “demilitarized zone of research,” where companies can How many of you remember UN advisor Rene Dubos’ collaborate with faculty and with many of the brightest young 1972 adage, “Think globally, act locally?” Dubos believed minds in the world—as well as among themselves, which is that we should create a World Order in which “natural and another important role whose value should not be underesti- social units maintain or recapture their identity, yet interplay mated—on medium and long-range research partnerships. with each other through a rich system of communications.” Well, here we are. Tom Friedman says, “ so the current B. The Bay Area Is the Corporation keep-you-awake-at-night issue for nation states and their As companies continue to reduce their internal investments citizens is how to deal with corporations that are no longer in long-range research and development, the financial and bounded by a thing called the nation-state. To whom are they intellectual leverage and the opportunities for pre-competitive loyal?” Clearly, an important question. But for me, one that is collaboration provided by university campuses and associated rhetorically subsumed by another: in Friedman’s Flat World, government-subsidized research laboratories like UC Berkeley, the corporation itself is ultimately hostage to its employees and our Lawrence Berkeley National Laboratory (LBNL), Stan- to the relationships it must forge with third parties—an area ford, SLAC, and UC San Francisco here in the Bay Area, is where an attentive nation-state can create a real advantage. I becoming a truly critical resource to industry, to its workforce, often find myself reflecting upon Silicon Valley and the San and to the creation and sustaining of an effective “bump” on Francisco Bay Area in this regard it its continuing role as a Tom Friedman’s Flat World. cradle of innovation and economic strength; as a friend and Now I’m sure most of you have either read Tom Friedman’s colleague at HP Dr. Patrick Scaglia recently commented, “Rich, latest best-selling book entitled “The World Is Flat: A Brief the Bay Area itself is the corporation. We are all employees of History of the Twenty-first Century” or you have had a friend the Bay Area Corporation.” So this is my second point: “The summarize it enthusiastically for you. What Friedman means Bay Area is the Corporation.” Patrick is absolutely right! In by “flat” is a direct consequence of “connected”: the lowering fact, I’m actually looking for a student to do the analysis of of trade and political barriers and that the exponential technical the Bay Area Corporation for me—what is our retention rate, advances of our digital revolution that have made it possible to our revenues and our expenses? How much are we spending on do business, or almost anything else, instantaneously with bil- R&D, marketing and sales, G&A and advanced research? With lions of other people across the planet. As one reviewer put it, Berkeley, LBNL, UCSF, Stanford, and SLAC as Advanced “He wants to tell you how exciting this new world is, but he Research, what percentage of our revenues are we spending on also wants you to know you’re going to be trampled if you don’t advanced research in our Bay Area Corporation and how is that keep up with it.” Personally, reading it from an American per- trending? As employees move among companies here in the spective, at first I found Friedman’s vision quite pessimistic! Bay Area, they are really moving among divisions of this Bay As another U.S. reviewer wrote, “Clearly the mathematics is Area Corporation. Never before has it been more important against us and the inevitable result is that our standard of living to us to invest regionally in our strengths—to differentiate is headed for a substantial fall—unless some other solution is ourselves, and so create a real and meaningful “bump” on found. Friedman summarized the factors eroding America’s Tom Friedman’s flat world. This is what Berkeley SIMS Dean competitiveness—unfortunately, he failed to look clearly into Annalee Saxenian refers to as a regional advantage—not a the future or to find a solution.” But Tom didn’t talk to me be- state advantage or a national advantage. I argue that what the fore he wrote the book! Nor did he talk to faculty at MIT, or profound corporate, global flattening actually does is it makes Stanford, or IIT, or ETH, any other leading research university the local region—the Bay Area in this case—even more impor- or research laboratory for that matter. He didn’t seem to talk to tant than the State in this regard, and the State more important any science or engineering educator or administrator who has than the nation. Our well-being, here in the Bay Area—the spent time thinking about the consequences of a flat world and quality of our schools, our infrastructure, our ability to create what they need to do to keep their heads above water. and attract new industries, and so high-paying jobs and tax As Dean of one of the most distinguished Colleges of En- dollars; the quality of our own lives—is highly dependent upon gineering in the world; Dean of a college whose graduates, how we respond first at the regional level, then the State level, faculty, and students have created over $250B of economic and then as a nation. value, and whose research innovations have saved hundreds It follows then that never before has it been more important of thousands—if not millions—of lives, Dean at the U.S. for us to truly facilitate real collaboration and effective exchange University that the National Science Foundation says produces between and among our universities, government laboratories, more Ph.D.s in science and engineering annually than any and our industrial partners, particularly those prepared to in- other university in America, you might just think that this is a vest substantially in our local region. Never before has it been phenomenon I should care about—and, believe me, I do! And more important to facilitate the sharing of IP, sharing of under- what I’m about to say in this regard is as relevant to Tsing standing, and the creation of a local advantage for those working Hua, Beijing, and China, for example, as it is to Berkeley, the with us—here in the Bay Area, or California. To be very clear, Bay Area, California, and the United States. I posit that the I’m in no way excluding so-called international partners here ei- real irony of Friedman’s Flat World—where his flatness should ther—in fact, exactly the opposite. Personally, I really think we really be considered largely a corporate and business view of should strongly consider dropping the idea of “flag-of-origin”

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. as a symbol of corporate identity. In this new and flat corpo- search and teaching laboratory at MIT if he would like to set rate world, companies should be judged far more on where they up shop here in Berkeley as well. He replied, “No thanks, but choose to invest and partner, where they pay taxes and create how about Berkeley Engineering sets up a satellite campus here jobs in a sustained way over a number of years, rather than in Cambridge, Massachusetts?” Rodney gets it! I call this what particular national flag-of origin they happen to carry. I strategy “intellectual insourcing,” by the way. It is our attempt know it may be painful for many of us to even contemplate, but at Berkeley to create a sizeable bump—ideally a mountain—on we really should ask the question as to whether an Intel or HP Tom Friedman’s otherwise flat world. Right there in Berkeley. are actually U.S. companies any longer under this definition, While many of my competitors are setting up satellite campuses while perhaps some foreign companies like a Toyota actually in Singapore, or England, or Qatar, or setting up laboratories want to be! So from my own selfish perspective then, how do and encouraging their faculty to spend time in India or Dubai, we keep our local Berkeley/Bay Area Corporation vibrant and I say bring those super people to Berkeley—bring them physi- alive? How do we keep it up to date and able to evolve with the cally to Berkeley and to the San Francisco Bay Area. As without challenges of this global business transition? It’s simple—like doubt the most distinguished public teaching and research in- any great corporation, we need to recruit, attract, and retain stitution in this nation, we also have another unfair advantage the very best knowledge workers in the world. Just as we have in this regard. More than one third of our students at Berkeley been doing for decades now. We need to bring these great minds are U.S. Federal Pell-Grant-eligible. That means they are stu- first to Berkeley, then to the Bay Area, to California, and to the dents coming from families earning less than $35 000 per year. United States. Just as any of you visiting Berkeley from other As our Chancellor Bob Birgeneau likes to point out, we have parts of the United States or the world need to bring as many more of those economically disadvantaged American students of those same people as you can to your local, geographical at Berkeley than all of the Ivy League schools combined! Many region. When you think about it, it is really the only feasible of us at Berkeley believe that this is our secret weapon, by the response! In fact, it could be argued that at a great public uni- way—our public mission and State “subsidy” of California res- versity like Berkeley it is our responsibility to our community idents’ supports access to the University of California for a very and to our respective states and nations. Just to be really clear, important pool of local American talent that our private com- I’m not presenting a xenophobic perspective here; exactly the petitors have not tapped into yet. Bring the very best students we opposite—for those of you visiting the Bay Area, I believe this can find to Berkeley: first and foremost from the Bay Area and goal is equally as important for you in your region, and I truly California, then from the United States, and then from around hope you succeed in such a venture, just as well as we suc- the world. Like many of the great institutions of this or any other ceed—well, perhaps not quite as well as we succeed! A strategy time Berkeley is far more about a culture than it is about the con- like this actually requires us to engage far more aggressively tent it produces. It’s the Berkeley graduates that are special, not with the rest of the world and to develop very strong and fo- just the pedagogy we produce. Berkeley is about rubbing shoul- cused relationships with the very best sources of talent, wher- ders in the hallways and the cafeterias with students, faculty, and ever they are to be found. After all, these people used to come visitors from around the world, people who share a mission and here almost automatically because of the opportunities we rep- a vision although their fields may differ significantly. You who resented here in the United States. But now, in a flat world have spent time on the campus of a world-class research univer- and where national as well as international competitors are ex- sity know precisely what I mean. These are people who truly ploiting their relative strengths and are investing very aggres- want to make a difference in the world through their teaching, sively for a local advantage, we must change our strategy to that their research, and their service. You simply can’t achieve that of an aggressive acquirer of talent. Bring the very best people culture at a distance; in this flat world I don’t believe you can to Berkeley—undergraduates, graduate students, post docs, fac- even sustain such a culture unless you double-down the bet and ulty, staff, executives, SME’s, outposts of corporate research work aggressively to seek out, attract, and retain the very best labs, and yes, even campuses of other universities—but only of the best, wherever they may be. The Bay Area is the Corpo- the very best ones in the world! As it said in the New York ration, and we must all do everything in our power to make it Times last week, I have already surprised a university presi- the most effective corporation in the world. dent and a dean of engineering or two by inviting them to set But at the same time that the earth is tending rapidly to- up shop adjacent to our Berkeley campus—most recently, the wards flatness, we do have another absolute disaster to deal with Vice President of Research for Tsing Hua University in Beijing, here in the United States. We simply aren’t preparing our citi- China. While he was interested in having our students and fac- zens and our society adequately for this radical transition. And ulty visit his university for extended periods, I replied: “Actu- this is a much bigger disaster than many of us seem to realize. ally, I have a proposal for you. How about if you set up a Tsing Most of you have probably read or heard about the recent re- Hua campus right here in Berkeley? Just up the road—we have port from the National Academies, “Rising Above The Gath- 90 acres of beautiful University-owned land we call the Bay- ering Storm: Energizing and Employing America for a Brighter side Research Park. Let’s identify a group of donors who want Economic Future.” That report points out clearly and unambigu- to help Tsing Hua and ask them to fund an outpost of your uni- ously that without an immediate wide-ranging effort, the United versity right here.” Then let’s do the same with IIT, with Cam- States “could soon lose its privileged position” as the world’s bridge, and ETH. So far, I haven’t had any takers though! Bring leader in science and engineering. “Decisive action is needed the very best here to Berkeley and to the U.S. About a year ago now,” the report warns, adding that the nation’s old advantages I even asked Professor Rodney Brooks, the head of a major re- “are eroding at a time when many other nations are gathering

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. strength.” The proposed actions include creating scholarships no enemy save the ignorant, and for a friend the people of Cali- to attract 10 000 top students a year to careers in teaching math fornia.” Words spoken at the building’s inauguration just about and science, and 30 000 scholarships for college-level study of a hundred years ago. As Jack London wrote in his November science, math and engineering; expanding the nation’s invest- 19, 1902 column in the San Francisco Examiner, commenting ment in basic research by 10 percent a year for seven years; on this grand building’s groundbreaking ceremony, “In number and making broadband access available nationwide at low cost. of students it [UC Berkeley] has the largest roll, and with the The Academies panel estimated that the cost of implementing best equipment in the world it is inevitable that it shall take first these and all of their other wide-ranging and substantial recom- rank among the colleges of mining. From all the world students mendations is $10 billion a year. As Intel Chairman and NAE of mining will flock to it; and to all the world it will send forth Chair Craig Barrett points out, even today the U.S. government its engineers to the conquest of force and mastery of matter.” spends $25 billion on farm subsidies—five times as much as Friends and colleagues, I don’t think I could have summa- it does for all of its investments in advanced research and de- rized our aspirations for today any more lucidly; perhaps Tom velopment! I was in Washington last week with a group of engi- Friedman’s challenging ideas and wake-up call come as close neering deans from many of our top U.S. universities, helping to as we have today to Jack London and his ideal for the future reinforce these points with our respective representatives. It was Berkeley. Back to multidisciplinary research and the reformu- clear from our discussions with them that Craig, along with the lation of everything. Since we have heard a lot about software CEO’s and senior executives of many of the companies repre- and electronics this morning, I’m going to draw upon an ex- sented here today, have played an absolutely key role in pressing ample sourced in biology to illustrate my point. An example, the importance of these issues and having a number of them by the way, that ultimately depends upon more electrical engi- actually presented in President Bush’s State of the Union ad- neering and computer science than even our EECS department dress late last month. But that said, can we do it? Will we do does. it? These are major challenges that we must all work to im- It is not often one has the chance to be present at the birth plement, and with every bone in our bodies. And we must do of an entirely new industry, let alone one that has the potential so now. I have absolutely no doubt that the economic future of to address, if not solve, many of our most pressing global the United States depends on us changing the course of this Ti- problems—and at least two of my Three E’s mentioned above. tanic before it is too late. As Berkeley alumnus, former faculty More years ago now than I care to remember, I began my member, and now President of the University of Maryland Dan career in the microelectronics industry as we contributed to Mote puts it, we have heard about Rising Above the Gathering the relentless evolution of Gordon Moore’s famous law of Storm; now it is time to Gather Above the Rising Storm! The exponential growth in chip complexity. My industry started Future of the Future. So far, I have spoken about Papadopolous’ with physics—the physics of materials called semiconduc- Century of the Engineer and the essential role of our research tors. Physicists at Bell Laboratories in New Jersey struggled universities to that future, and I have hopefully convinced you of for years to understand the detailed physics of materials like the perhaps ironic, but increasing importance of “place” in this germanium, gallium arsenide, and silicon. They studied sur- flat world and what we need to do about it—Scaglia’s The Bay faces, properties like resistance and thermal conductivity under Area is the Corporation. My third and final point today is a con- various conditions, and many other physical and electronic sequence of a recent conversation with Tom Kalil, Berkeley’s properties of semiconductors, until in 1947 the physicists John Special Assistant to the Chancellor for Science and Technology. Bardeen, William Shockley, and Walter Brattain were credited “Rich,” he said, “In any talk about the Future of the Future with inventing the semiconductor transistor. And it was then you really must talk about the importance of multidisciplinary that the engineers took over! They understood that the basic research.” Of course, multidisciplinary research—both use-in- physics of materials was far too complicated and that if they spired research as well as pure curiosity-driven research—is were to make anything practical out of this new science they what we are all struggling to come to grips with. Of course, would have to work with a limited subset of physics. This new multidisciplinary research is a critically important first step. But breed, called electronics engineers, defined their own library I truly believe it is simply that—a first step on our way to what of components and the “recipes” they needed to build them will, perhaps a quarter century from now, actually seem like a in a semiconductor—components like resistors, capacitors, complete reformulation of everything we do. In 50 years, those transistors and wires. They defined standard voltage levels and of you still here will chuckle “Remember the good old days standard formats for binary computation. It was more than a when we used to talk about electrical engineering and computer decade later that Robert Noyce at Fairchild and Jack Kilby at science as a field of its own?” Texas Instruments almost simultaneously combined a number As a reminder, remember the good old days when Phoebe Ap- of these components together on a single chunk of semicon- person Hearst sponsored Berkeley’s Hearst Memorial Mining ductor and the integrated circuit was born. Today, almost a half Building? Today, that building houses much of our most ad- century later, we can reliably manufacture over a billion of vanced research on nano-sciences and nano-engineering. A kind these components, invented by engineers, on a single sliver of of “mining,” I suppose, but certainly not what Phoebe had in silicon and, as we all know so well, microelectronics has truly mind or what her very successful husband George used to do for revolutionized our world. a living. “May this building be consecrated to the service of effi- Today, when I hear Berkeley professors Jay Keasling, Adam cient citizenship and to the industrial development of the Pacific Arkin, Carlos Bustamente, or Dan Fletcher talk about the coast, of America, of the world. May this School of Mines have nascent field of Synthetic Biology, I really have the sense that I

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. am back with Shockley and his team as history is about to repeat companies represented here today—from National Instruments itself, but this time with biology at its core rather than physics. and Sun Microsystems, to HP and IBM—have the potential to For many years now, molecular and cell biologists have worked play a central role in this new industrial ecosystem as well. I hard to uncover the secrets of how living systems work. First joked last week with Nick Donofrio of IBM that perhaps IBM we understood the genome, and proteins and enzymes, and will redefine its name one day to International Biological Ma- eventually how specific pathways operate in living systems like chines! As Ed Penhoet, Chiron co-founder and former CEO, the E-coli bacterium or a yeast microbe. More recently we have former Dean of Public Health here and Berkeley and now presi- discovered how to assemble genetic material and introduce it dent of the Gordon and Betty Moore Foundation, said at a lunch into simple living systems to modify their properties. As the back in 2001, “The biotechnology revolution is not as much scientists continue to understand more and more about living about biology as it is about information technology.” systems, and as we develop the instruments we need to observe their behavior in the finest, atomic-level detail, once again the C. The Reformulation of Everything engineers have arrived on the scene! Not satisfied with simply So in conclusion, the 21st Century clearly must be the Cen- understanding living systems, our engineers want to harness tury of the Engineer—and the century of the information and that knowledge and apply it for a useful purpose. communications technology worker as well. For the Future of This time, however, it is not a germanium, gallium arsenide the Future, the role of the world’s great research universities is or silicon substrate. This time the substrate for their work is even more critical than it has ever been before—not only for actually a bacterium like E-coli, yeast, or bacillus. This time teaching and research, but as a kind of science and technology these chemical and bioengineers aren’t working with transis- nexus, where the great thinkers and great doers from academia, tors, resistors, and capacitors as their components, but rather industry, and government alike can come together in a kind of they are using pathways, enzymes and sequences of base-pairs “DMZ of research.” They must come together to contemplate to construct their new “bio-chips.” But the basic principle is the not only the technical challenges we face, but also do so in a same—don’t try to use all of biology but rather define, char- broad, societal context that truly implements those “horizontal acterize and re-use a restricted and well-understood library of collaborations” Carly Fiorina refers to, and in a way that far “biocomponents”—“bio-bricks” as this new generation of stu- more carefully considers the societal consequences of our ac- dents refer to them—derived from a wide variety of different tions as well. Our responsibility at Berkeley is not to accom- living systems and used to build entirely new living cells that modate ourselves to this Flat World—far from it! Our responsi- have a specific purpose. Just like a silicon chip is an assembly bility as nation states and their employees is to use every bone in of components designed to perform a specific function, such as our bodies to counter flatness, to redirect its energy in our own to implement an iPod, a cell phone, or a personal computer, favor; to take full advantage of it, to “Aikido” it. To do that, these new living systems are assembled on a biological sub- we simply must double-down on what we have been doing in- strate to perform a specific function as well. This time, how- formally for years—we must invest heavily in people. We must ever, that function might be the conversion of corn syrup to a invest in ways of identifying the very best talent, ways of cre- drug that cures malaria or certain types of cancer, or it might ating the incentives to bring them here—from California and even be a bacterium that photosynthesizes carbon dioxide in the from around the world—and we must do our best to inspire and air directly into diesel fuel! In the mean time, inspired by the support them as they invent the kind of future that our global potential impact of their fundamental work, the basic science society demands. Leadership in all aspects of science and en- is accelerating forward and providing the engineers with ever gineering remains an element of ever increasing importance in more interesting and important understanding and capability. creating the unfair advantage for so many other important and It is truly an image of the virtuous cycle we have all benefited emerging disciplines—in establishing a very sizeable bump. On from in the age of the semiconductor. These new challenges and behalf of our College, I thank you all for your support of our opportunities presented by Synthetic Biology are what our fac- students and our faculty, as we all look forward to continuing to ulty and students are working on, along with a handful of col- work with you to keep Berkeley, the Bay Area, California, and leagues throughout the world today, in this new and exciting the United States, the most important ecosystems in the world field. They are working to understand a small number of mi- for innovation and collaboration in science and engineering.” crobes very, very well (their “substrates”) and they are com- piling a catalog of well-understood, useful components that they V. C ONCLUSION can “assemble” on their new substrates for a purpose. Over the I would like to conclude with two quotes: the thoughts of next quarter century, I have absolutely no doubt that this new fellow countryman Giovambattista Vico (1668–1744) which are field of Synthetic Biology has the potential to revolutionize our a perfect rendition of what moved Richard: “The holy furor for world just as microelectronics has done in my own professional truth lives in the eternal attempt to go beyond the limit, in the in- lifetime. This new revolution has the potential to bring with it finite possibility of self-realization and of overtaking ourselves tremendous progress for humanity, as well as any number of to discover the power of the spirit and give a new push towards attendant challenges—as with any new technology. This revo- knowledge.” And the wonderful words by Tibetan Lama So- lution also brings with it a need for many high-technology sup- gyal Rimpoche, chosen by Dick Blum, San Francisco financier, porting industries and, if we can develop these industries here philanthropist and vice chair of the UC Regents, for all of us: in the Bay Area, we will certainly return a new generation of “One way of comforting the bereaved is to encourage them to high-paying, high technology careers to California. Many of the do something for their loved ones who have died, by living even

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Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on August 15,2010 at 19:43:12 UTC from IEEE Xplore. Restrictions apply. [4] A. R. Newton and A. Sangiovanni-Vincentelli, “Relaxation-based elec- trical simulation,” IEEE Trans. Electron. Devices, vol. ED-30, no. 9, pp. 1184–1207, Sep. 1983, SIAM J. Sci. Stat. Comput., vol. 4, no. 3, Sep. 1983, IEEE Trans. Comput-Aided Des. Integ. Circuits Syst, vol. CAD-3, no. 4, pp. 308–331, Oct. 1984. [5] A. Sangiovanni-Vincentelli and A. R. Newton, “CAD tools for ASIC design,” Proc. IEEE, vol. 75, no. 6, pp. 765–776, Jun. 1987. [6] A. R. Newton, Ed., Logic Synthesis for Integrated Circuit Design. Piscataway, NJ: IEEE Press, 1987. [7] D. Harrison, R. Newton, R. Spickelmier, and T. Barnes, “Electronic CAD frameworks,” Proc. IEEE, vol. 78, no. 2, pp. 393–417, Feb. 1990. [8] A. R. Newton, “Has CAD for VLSI reached a dead end?,” in Proc. VLSI 91 IFIP TC10/WG 10.5 Int. Conf., Edinburgh, U.K., Aug. 1991, pp. 187–192. [9] M. A. Horton and A. R. Newton, “Method and Apparatus for De- termining Position and Orientation of a Moveable Object Using Ac- celerometers,” U.S. Patent 5 615 132, Mar. 25, 1997. [10] R. E. Bryant, C. Kwang-Ting, A. B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. M. Rabaey, and A. Sangiovanni-Vincentelli, “Limitations and challenges of computer-aided design technology for CMOS VLSI,” Proc. IEEE, vol. 89, no. 3, pp. 341–365, Mar. 2001. [11] P. Aycinena, “Dr. Richard Newton, taking his place among the best and the brightest,” EDA Cafe (Oct. 27, 2003) [Online]. Available: www. edacafe.com more intensely on their behalf after they have gone, by prac- ticing for them, and so giving their death a deeper meaning. Don’t let us half die with our loved ones, then; let us try to live, after they are gone, with greater fervor.” I certainly will do so, to Alberto Sangiovanni-Vincentelli (M’76–SM’81–F’82) received the electrical carry your flag until I reach you! Goodbye Richard, my friend. engineering and computer science degree (“Dottore in Ingegneria”) summa cum laude from the Politecnico di Milano, Milan, Italy in 1971. He holds the Edgar L. and Harold H. Buttner Chair of Electrical Engineering CKNOWLEDGMENT A and Computer Sciences at the University of California at Berkeley, where he I wish to acknowledge the contributions of the people who has been on the Faculty since 1976. In 1980–1981, he spent a year as a Visiting Scientist in the Mathematical Sciences Department of the IBM T. J. Watson provided the quotes that I inserted throughout the paper. I Research Center, Yorktown Heights, NY. In 1987, he was Visiting Professor at would like to thank Ellen Sentovich, Andreas Kuehlman, An- Massachusetts Institute of Technology, Cambridge, MA. He was a co-founder drea Sangiovanni-Vincentelli, and Clas Jacobson who provided of Cadence and Synopsys. He is an author of over 800 papers and 15 books in the area of design tools and methodologies, large-scale systems, embedded support and editing. The UC Berkeley Chancellor’s office pro- controllers, hybrid systems, and innovation. vided additional material that helped in assembling the paper. Prof. Sangiovanni-Vincentelli is a member of the Board of Directors of Ca- This paper is dedicated to Petra, Neris, and Amrita who made dence, Sonics Inc., Gradient Design Automation, UPEK, Value Partners, and Accent. He was a member of the HP Strategic Technology Advisory Board Richard’s life rich and emotionally exciting. and is a member of the GM Science and Technology Advisory Board and of Fondazione Tronchetti Provera Advisory Board, and the founder and Scien- ALBERTO SANGIOVANNI-VINCENTELLI tific Director of the Project on Advanced Research on Architectures and De- Department of EECS sign of Electronic Systems (PARADES), a European Group of Economic In- terest supported by Cadence, United Technologies Corporation, and ST Micro- University of California at Berkeley electronics. He is on the Technology Advisory Board of the VC funds Walden Berkeley, CA International, Sofinnova, and Xseed Venture Capital Group. He is the Special [email protected] Advisor for Technology and Innovation of the Governor of Abruzzo. He is a member of the High-Level Group and of the Steering Committee of the EU Artemis Technology Platform. In 1981, he received the Distinguished Teaching EFERENCES R Award of the University of California. He received the worldwide 1995 Grad- [1] A. R. Newton and D. O. Pederson, “Analysis time, accuracy and uate Teaching Award of the IEEE (a Technical Field award for “inspirational memory requirement tradeoffs in SPICE2,” in Proc. 11th Annu. Conf. teaching of graduate students”). He has received numerous best paper awards Circuits Syst. Comput., Pacific Grove, CA, Nov. 1977, pp. 6–9. including the Guillemin-Cauer Award (1982–1983) and the Darlington Award [2] A. R. Newton, “Techniques for the simulation of large-scale integrated (1987–1988), and five best paper awards from the Design Automation Confer- circuits,” IEEE Trans. Circuits Syst., vol. 26, no. 9, pp. 741–749, Sep. ence. In 2002, he was the recipient of the Aristotle Award of the Semiconductor 1979. Research Corporation. In 2001, he was given the Kaufman Award of the Elec- [3] A. R. Newton, “Computer-aided design for VLSI circuits,” Proc. IEEE, tronic Design Automation Council for pioneering contributions to EDA. He was vol. 69, no. 10, pp. 1189–1199, Oct. 1981. elected to the National Academy of Engineering in 1998.

This article was reprinted from IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 8, pp. 1357–1366, Aug. 2007.

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