Data Transfer System for Host Computer and Fpga Communication
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DATA TRANSFER SYSTEM FOR HOST COMPUTER AND FPGA COMMUNICATION Thesis Submitted to The School of Engineering of the UNIVERSITY OF DAYTON In Partial Fulfillment of the Requirements for The Degree of Master of Science in Electrical Engineering By Michael T. Barnard UNIVERSITY OF DAYTON Dayton, Ohio December, 2015 DATA TRANSFER SYSTEM FOR HOST COMPUTER AND FPGA COMMUNICATION Name: Barnard, Michael T. APPROVED BY: Eric Balster, Ph.D. John G. Weber, Ph.D. Advisor Committee Chairman Committee Member Associate Professor, Department of Professor, Department of Electrical and Electrical and Computer Engineering Computer Engineering Tarek M. Taha, Ph.D. Committee Member Associate Professor, Department of Electrical and Computer Engineering John G. Weber, Ph.D. Eddy M. Rojas, Ph.D., M.A., P.E. Associate Dean Dean, School of Engineering School of Engineering ii c Copyright by Michael T. Barnard All rights reserved 2015 ABSTRACT DATA TRANSFER SYSTEM FOR HOST COMPUTER AND FPGA COMMUNICATION Name: Barnard, Michael T. University of Dayton Advisor: Dr. Eric Balster This Thesis describes a communication system to allow for the transmission of data between a host computer and a DE2-115 FPGA board over an Ethernet connection. This is achieved by using a socket between the host computer and a NIOS II embedded processor that accepts the data from the host computer and transfers it to the FPGA fabric. The host computer uses a C++ program to open a file and send the data over the socket to the NIOS II processor. The NIOS II acts as memory controller for the Synchronous Dynamic Random Access Memory (SDRAM) on the board with separate input and output data sections for the Hardware Description Language (HDL) processing module. A HDL module then processes the data and sends it back to the NIOS II to be returned to the host computer over the socket. The data transfer system is tested with three basic image processing functions performed on three sample images to verify its functionality. This data transfer system allows for easier testing of digital designs on the DE2-115 board by providing test data to the digital design in an efficient manner. iii To Myself... ...for all of your hard work. iv ACKNOWLEDGMENTS I would like to thank everyone in my life during the completion of both the design and docu- mentation; you all helped in your own way. I would like to especially thank the following people for their contributions. • Dr. Eric Balster, PhD: I would like to thank your for all of your advice and guidance throughout my time at UD both undergrad and graduate. I can confidently say that you are the reason that I both attempted and completed a Masters Degree. • Dr. John Weber, PhD and Dr. Tarek Taha, PhD: Thank you to Dr. Weber and Dr. Taha for your advice and input on the writing of my thesis and for being on my thesis committee. I know you have busy schedules, so thank you for allowing me to take up some of your valuable time. • David and Judy Barnard: I would like to thank you both for allowing me to pursue a Masters degree without balancing a budget on top of course work. Thank you again for all of the love and support you have given me all of my life. v TABLE OF CONTENTS ABSTRACT . iii DEDICATION . iv ACKNOWLEDGMENTS . v LIST OF FIGURES . viii LIST OF TABLES . x I. INTRODUCTION . 1 II. FPGA COST . 3 III. BACKGROUND TECHNOLOGIES . 6 3.1 Sockets and Socket Communication . 6 3.2 NIOS II Embedded Processor . 7 3.2.1 NIOS II/f Features . 8 3.2.2 NIOS II/s Features . 8 3.2.3 NIOS II/e Features . 8 IV. SYSTEM DESIGN AND IMPLEMENTATION . 10 4.1 Socket Client Program . 11 4.2 Communications Management Module . 13 4.3 Hardware Description Language Modules . 15 V. RESULTS . 20 5.1 Image Inverter . 21 5.2 Image Flipper and Inverter . 23 vi 5.3 Moving Average Filter . 24 5.4 Logic Utilization . 26 VI. CONCLUSION AND FUTURE WORK . 34 BIBLIOGRAPHY . 36 vii LIST OF FIGURES 2.1 DE2-115 Board . 4 4.1 Transfer System Data Flow . 11 4.2 Example of Console Output With Multiple Files Processed . 12 4.3 Map of Hardware and Important Connections . 16 4.4 Logic Diagram of Positive Edge Detector . 17 4.5 Positive Edge Detector Signals . 18 4.6 The Processing Module State Machine . 19 5.1 512x512 Grayscale Input Image . 21 5.2 1024x1024 Grayscale Input Image . 22 5.3 560x420 Color Input Image . 23 5.4 Console Output of Image Inverter With All Three Input Files . 24 5.5 512x512 Grayscale Inverted Output Image . 25 5.6 1024x1024 Grayscale Inverted Output Image . 26 5.7 560x420 Color Inverted Output Image . 27 5.8 Console Output of Image Inverter and Flipper With All Three Input Files . 28 5.9 512x512 Grayscale Inverted and Flipped Output Image . 28 viii 5.10 1024x1024 Grayscale Inverted and Flipped Output Image . 29 5.11 560x420 Color Inverted and Flipped Output Image . 29 5.12 Console Output of Moving Average Filter With All Three Input Files . 30 5.13 512x512 Grayscale Moving Average Output Image . 30 5.14 1024x1024 Grayscale Moving Average Output Image . 31 5.15 560x420 Color Moving Average Output Image . 31 5.16 Compilation Report for the Communication System . 32 5.17 Compilation Report for the Image Inverter . 32 5.18 Compilation Report for the Image Inverter and Flipper . 33 5.19 Compilation Report for the Moving Average Filter . 33 ix LIST OF TABLES 2.1 FPGA Boards Owned and Cost . 5 x CHAPTER I INTRODUCTION The flexibility of Field Programmable Gate Arrays (FPGAs) has allowed them to become preva- lent in many fields including digital design and control systems. These devices can be programmed with a wide range of digital logic designs leading to large amounts of possible research topics and design projects utilizing FPGAs [1]. An FPGA is a chip that contains hundreds of thousands of digital logic elements that can be connected in numerous ways to create any digital logic structure. FPGAs can be programmed as many times as needed, so improvements can be made to a design and the design can be updated without replacing any hardware. Designs may be prototyped on one chip and then programmed on to other FPGAs once the design is ready for production; one chip can also be used to prototype many designs one after the other. The main restriction to widespread FPGA prototyping is cost: the cost of the board hosting the FPGA, the cost of the software licenses required to program the board, and the cost of software development kits (SDKs) used for data trans- fer to and from the board. To be able to transfer data to the board most of the more expensive FPGA models have a dedicated SDK that takes care of connecting with the board and transferring the data while the less expensive models do not. These SDKs allow designers to focus on their specific en- gineering problem without having to worry about the complexities of data transfer. Less expensive FPGA models typically lack SDKs making them less capable and flexible in solving engineering 1 problems. This Thesis describes a communication system which allows designers to communicate data to the DE2-115 FPGA development board with ease. Chapter II discusses the impact that this data transfer design will have on the campus research community. Next, Chapter III is a discussion on the backgrounds of a few technologies significant to the design in addition to FPGAs and HDLs. How the design is created and implemented is explained in Chapter IV; covering all three sections of the design: the host PC program, the NIOS II program, and the HDL modules. Chapter V follows with a section on the results of three test functions on three test images and the data transfer system’s overall performance during these tests. Chapter VII concludes by summarizing this paper and discussing future work based on this research. 2 CHAPTER II FPGA COST Widespread FPGA prototyping would be more prevalent if the costs could be reduced: cost of the board hosting the FPGA, cost of software licenses required to program the board, and cost of software development kits (SDKs) for data transfer to and from the board. Most of the more expen- sive FPGA models have a dedicated SDK to transfer data to the FPGA board while less expensive models do not. These SDKs allow designers to focus on their specific engineering problem without having to worry about the complexities of data transfer. The SDKs for data transfer can cost up- wards of $4,000 per year alone, and Altera’s Quartus II software can also cost $2,000 per year [2]. That $6,000 a year allows for the use of the FPGA but does not include the cost of the FPGA itself. The FPGAs with this type of support software can cost up to $50,000 per board. Alternatively, there are inexpensive boards, like the DE2-115 shown in Figure 2.1, that can be programmed with license free software but do not have any SDKs to transfer data [3]. These inexpensive boards are limited to switches and buttons for data input which are not realistic input methods for large scale data transfer. The development of this data transfer system allows for communications between the inexpensive board and a host PC. The development of such a system allows for the possible $56,000 investment to be replaced with a $300 investment for prototyping purposes. 3 Figure 2.1: DE2-115 Board 4 FPGA Board NAME Number Owned Unit Cost Total Cost Gidel Proce V [5] 57 $12,450 $709,650 Gidel PROCStar III 110 [6] 3 $7,500 $22,500 Gidel PROCStar III 150 [6] 32 $14,150 $452,800 Total 92 $1,184,950 Table 2.1: FPGA Boards Owned and Cost This data transfer design will serve as the basis for other research projects.