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Glossary and Symbols GLOSSARY AND SYMBOLS The ISHM Glossary of Hybrid-Circuit Terms (Updated edition­ Summer 1987) by G.S. Szekely provided the foundation for this glossary. Definitions have in some cases been modified to fit this work. Other terms used by the authors and the packaging profession have been added and some terms in the original work have not been deleted. Material chemical symbols are found at the end of this glossary. A ACCELERATED STRESS TEST. A test conducted at a stress, e.g., chemical or physical, higher than that encountered in normal operation, for the purpose of producing a measurable effect, such as a fatigue failure, in a shorter time than experienced at operating stresses. ACCELERATOR. An organic compound which is added to an epoxy resin to shorten the cure time. ACTIVE COMPONENTS. Electronic components, such as transistors, diodes, electron tubes, thyristors, etc., which can operate on an applied electrical signal so as to change its basic characteristics, i.e., rectification, amplification, switch­ ing, etc. ADDITIVE PLATING. Processing a hybrid circuit substrate by sequentially plating conductive, resistive, and insulative materials, each through a mask, thus defining the areas of traces, pads, and elements. ADVANCED STATISTICAL ANALYSIS PROGRAM (ASTAP). The "Ad­ vanced Statistical Analysis Program" is the mM circuit analysis simulation program. It performs DC, time domain, and frequency domain simulations. Statis­ tics can be applied to all simulations to predict operating tolerances. Among its many features is a transmission line analysis program. Also see SPICE. 11-932 GLOSSARY AND SYMBOLS ALLOY. A solid-state solution or compound formation of two or more metals. Alternatively, a combination of metals resulting in a phase or phases containing some of each constituent. ALPHA PARTICLE. Decay product of some radioactive isotopes. It is a high­ energy (mv range) helium nucleus capable of generating electronlhole pairs in microelectronic devices and switching cells, causing soft errors in some devices. APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC). Applica­ tion Specific Integrated Circuit is an integrated circuit chip with personalization customized for a specific product. Personalization refers to wiring on the inte­ grated circuit chip. AREA ARRAY TAB. Tape automated bonding where edge-located pads and additional pads on the inner surface area of a chip are addressed in the bonding scheme. This is practiced with extremely complex dice, VLSI etc. Also for use with ICs where peripheral pad pitch cannot be further reduced and all 1I0s must be accommodated. ARRAY. A group of elements (pads, pins) or circuits arranged in rows and columns on one substrate. ASPECT RATIO. The ratio of the length of hole to the diameter of hole in a board. ASSEMBLY. A hybrid circuit which includes discrete or integrated compo­ nents that have been attached to the next level of package, usually a card. ASSEMBLYIREWORK. Terms denoting joining and replacement processes of microelectronic components. Assembly refers to the initial attachment of device and interconnections to the package. Rework refers to the removal of a device including interconnections, preparation of the joining site for a new device, and rejoining of the new device. Rework is necessary for either repair or engineer­ ing change. B BACKBONDING. Bonding active chips to the substrate using the back of the chip, leaving the face, with its circuitry face up. The opposite of backbonding is face down bonding. BACK-END-OF-THE-LINE (BEOL). That portion of the integrated circuit fabrication where the active components (transistors, resistors, etc.) are intercon- GLOSSARY AND SYMBOLS 11-933 nected with wiring on the wafer. It includes contacts, insulator, metal levels, and bonding sites for chip-to-package connections. Dicing the wafer into individual integrated circuit chips is also a BEOL process. The front-end-of-the-line (FEOL) denotes the first portion ofthe fabrication where the individual devices (transistors, resistors, etc.) are patterned in the semiconductor. BACK PANEL. A planar package component holding plugged-in lower-level package components (e.g., cards) as well as discrete wires and cables interconnect­ ing these components. BACKSIDE METALLURGY (BSM). A metallization pad electrically con­ nected to internal conductors within a multilayered ceramic package, to which pins are brazed. BALL GRID ARRAY (BGA). A Ball Grid Array is an area array of solder balls joined to a SCM or MCM and used to electrically and physically connect the package to the next level of package, usually a printed circuit board. BALL LIMITING METALLURGY (BLM). The solder wettable terminal metallurgy which defines the size and area of a soldered connection, such as C4 and a chip. The BLM limits the flow of the solder ball to the desired area, and provides adhesion and contact to the chip wiring. BANDWIDTH. The maximum pulse rate or frequency that can reliably propa­ gate through a transmission line. For a data bus, bandwidth is commonly used to describe the maximum data rate which is the single line pulse rate multiplied by the number of parallel bus bit lines. BIFET. The combination of bipolar and PET transistors integrated together on the same piece of silicon for enhanced performance and cost. BINDER. Materials (organic or inorganic) added to thick-film compositions and to unfired substrate materials to give sufficient strength temporarily for prefire handling. BIPOLAR TRANSISTOR. Original transistor design in which two semicon­ ductor junctions (regions of opposite polarity doping) are separated by a narrow region, called the base. Minority carriers are injected in the base from the emitter across the base-emitter junction, travel through the base, and are attracted to the collector through the base-collector junction. These transistors consume more power than Field-Effect Transistors (PET), but also achieve higher performance. BLOCK COPOLYMER. A copolymer compound resulting from the chemical reaction between n number of molecules, which are a block of one monomer, 11-934 GLOSSARY AND SYMBOLS and .on" number of molecules, which are a block of another monomer. Example: stearine (rigid) with silicone (elastic). BOARD. This package element can best be defined as an organic printed­ circuit card or board on which smaller cards or modules can be mounted. Its connections to the next higher level involve discrete wire or cables. BOILING. Phase change and formation of bubbles in a superheated liquid. BONDABILITY. Those surface characteristics and conditions of cleanliness of a bonding area which must exist in order to provide a capability for successfully bonding an interconnection material by one of several methods, such as ultrasonic or thermocompression wire bonding. BRAZE. A joint formed between two different materials by formation of liquid at the interface. BRAZING. Joining of metals by melting a non-ferrous, filler brazing metal, such as eutectic gold-tin alloy, having a melting point lower than that of the base metals. Also known as hard soldering. BTAB. The acronym for tape automated bonding when the raised bump for each bond site is prepared on the tape material as opposed to the bump being on the chip. BUMPED TAPE. A tape for the TAB process where the inner-lead bond sites have been formed into raised metal bumps on the tape rather than on the chip. This ensures mechanical and electrical separation between inner lead bonds and the non-pad areas of the chip (die) being bonded. BURN·IN. The process of electrically stressing a device (usually at an elevated temperature and voltage environment) for an adequate period of time to cause failure of marginal devices. BURN·OFF. Removal of unwanted materials-typically organics from green­ sheets or organic contamination from substrates. C CAMBER. A term that describes the amount of overall warpage present in a substrate. GLOSSARY AND SYMBOLS 11-935 CAPACITANCE. The electrostatic element that stores charge. In packaging systems, it is used in lumped equivalent circuits to represent part of a line discontinuity. It is also used in a distributed system to represent the electrostatic storage property of a transmission line. Because it delivers current in response to a change in voltage, another use is to filter powering systems. CARD. A printed-circuit panel (usually multilayer) that provides the intercon­ nection and power distribution to the electronics on the panel, and provides interconnect capability to the next level package. It is also known as a daughter board. It plugs into a mother printed-circuit board. CARD·ON·BOARD. Packaging technology in which multiple printed-circuit panels (cards) are connected to printed-circuit panel (board) at 90° angles. CELL DESIGN, STANDARD. A semicustom product implemented from a fully diffused or ion implanted semiconductor wafer carrying horizontal rows of primary cells, interlaced with wiring channels (bays). Vertical wiring is supplied by additional processed layers which may use the cell areas or lie in channels on an overhead layer. Channel widths may vary to suit particular chip logic, so that chip sizes are not fixed for all products of a family. CENTRAL PROCESSOR (CP). Computer processor responsible for fetching, interpreting, and executing program instructions. Also called Processor Unit (PU) and Central Processing Unit (CPU). CERAMIC. Inorganic, nonmetallic material, such as alumina, beryllia, or glass-ceramic, whose final characteristics are produced by subjection to high temperatures. Often used in forming ceramic-substrates for packaging semicon­ ductor chips. CERAMIC BALL GRID ARRAY (CBGA). A ceramic package using ball grid array technology. See ball gird array technology. CERAMIC COLUMN GRID ARRAY (CCGA). A ceramic package using ball grid array technology. See ceramic gird array technology. CERAMIC DUAL·IN·LINE PACKAGE (DIP), Dual-in-line package in ce­ ramic. See Dual-in-line Package. CERAMIC QUAD FLAT PACK (CQFP). Quad Flat Pack in ceramic. See Quad Flat Pack. 11-936 GLOSSARY AND SYMBOLS CERMET. A solid homogeneous material usually consisting of a finely divided admixture of a metal and ceramic in intimate contact.
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