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Parallella Reference Manual 13.11.25 (PRELIMINARY, for REVIEW PURPOSES ONLY!)

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Parallella Reference Manual 13.11.25 (PRELIMINARY, for REVIEW PURPOSES ONLY!) Parallella Reference Manual 13.11.25 (PRELIMINARY, FOR REVIEW PURPOSES ONLY!) PRELIMINARY INFORMATION (REV 13.11.25) 1 Revision History Version Comments 0.13.2.13 Initial release 1.13.6.24 Updated PEC_POWER Pin outs Part Numbers Added + Document Links Changed flash to 128Mb Replaced 5V DC/USB power mux with pin header Changed power sub-system Epiphany now uses 1.8V IO voltage Added UART 2-pin header Changed license to creative common 1.13.7.27 Added UART interface back to PEC_POWER Added test points for SYS_5V and 1P0V Added 2-pin header for 5V mounting hole 1.13.11.25 Added UART interface back to PEC_POWER Added test points for SYS_5V and 1P0V Added 2-pin header for 5V mounting hole PRELIMINARY INFORMATION (REV 13.11.25) 2 Related Documents: Epiphany Architecture Reference Manual: http://www.adapteva.com/support/docs/e3-reference-manual Epiphany SDK Reference Manual: http://www.adapteva.com/support/docs/esdk3-manual Epiphany-III Datasheet: http://www.adapteva.com/products/silicon-devices/e16g301/ Epiphany-IV Datasheet: http://www.adapteva.com/products/silicon-devices/e16g401/ Software Repositories: Parallella Hardware and Software Repository https://github.com/parallella/ Epiphany SDK Software Repository https://github.com/adapteva SD Card Images: ftp://ftp.parallella.org PRELIMINARY INFORMATION (REV 13.11.25) 3 Table of Contents 1Overview.................................................................................................................. 6 2Parallella Features.................................................................................................... 8 2.1Introduction........................................................................................................8 2.2CPU..................................................................................................................... 9 2.3Epiphany Coprocessor......................................................................................11 2.4SDRAM.............................................................................................................. 12 2.5Flash................................................................................................................. 12 2.6Gigabit Ethernet...............................................................................................12 2.7USB 2.0 (0) PC Connection...............................................................................12 2.8USB 2.0 (1) OTG connection.............................................................................12 2.9Micro SD...........................................................................................................12 2.10HDMI Port....................................................................................................... 12 2.11LED Indicators................................................................................................12 2.12Reset Button...................................................................................................12 2.13Serial Port.......................................................................................................12 2.14JTAG Debugging..............................................................................................13 2.15Parallella Power Sub-System..........................................................................14 2.16Parallella Expansion Connectors.....................................................................15 2.17Mounting Holes...............................................................................................15 3Parallella System Architecture................................................................................16 3.1Zynq Memory Map............................................................................................16 3.2Epiphany Memory Map.....................................................................................17 3.3Parallella FPGA Design......................................................................................17 3.4Epiphany Specific FPGA Resources...................................................................18 4Parallella Expansion Connector Details...................................................................19 4.1PEC_POWER......................................................................................................19 4.2PEC_FPGA......................................................................................................... 25 4.3PEC_NORTH/PEC_SOUTH...................................................................................30 5Parallella Specifications..........................................................................................38 5.1Dimensions and Weight....................................................................................38 5.2Power Consumption..........................................................................................39 5.3Performance Metrics.........................................................................................40 PRELIMINARY INFORMATION (REV 13.11.25) 4 6Parallella Quick Start Guides (TBD).........................................................................41 6.1Desktop Evaluation System..............................................................................41 6.2Embedded Platform..........................................................................................41 6.3Wireless Computer...........................................................................................41 6.4Stacked clusters...............................................................................................41 7About the Parallella Board......................................................................................42 7.1Design Information...........................................................................................42 7.2Build Options....................................................................................................43 7.3Contributors.....................................................................................................44 7.4Attributions....................................................................................................... 45 7.5Licensing..........................................................................................................46 7.6Disclaimers....................................................................................................... 46 7.7Warranty........................................................................................................... 48 PRELIMINARY INFORMATION (REV 13.11.25) 5 List of Figures Figure 1: The Parallella Board.....................................................................................6 Figure 2: Zynq Connectivity Diagram.........................................................................7 Figure 3: Parallella High Level Architecture.................................................................7 Figure 4: Power Sub-System.....................................................................................14 Figure 5: PEC Placement...........................................................................................15 Figure 6: Expansion Card Configuration....................................................................15 List of Table Table 1: Parallella Feature Summary...........................................................................6 Table 2: Parallella Component Summary....................................................................8 Table 3: Parallella Zynq Versions...............................................................................10 Table 4: Parallella Expansion Connectors (PEC)........................................................15 Table 5: Zynq Memory Map.......................................................................................16 Table 6: Epiphany System Registers.........................................................................17 Table 7: Epiphany System Registers.........................................................................18 Table 8: PEC_POWER Signal Summary......................................................................20 Table 9: PEC_POWER Pin Mapping.............................................................................25 Table 10: PEC_FPGA Signal Summary.......................................................................25 Table 11: PEC_FPGA Pin Mapping..............................................................................30 Table 12: PEC_NORTH/PEC_SOUTH Signal Summary.................................................30 Table 13: PEC_NORTH Pin Mapping for Parallella-16.................................................35 Table 14: PEC_NORTH Pin Mapping for Parallella-64.................................................36 Table 15: PEC_SOUTH Pin Mapping for Parallella-16.................................................37 Table 16: PEC_SOUTH Pin Mapping for Parallella-64.................................................38 Table 17: Dimension and Weight..............................................................................38 PRELIMINARY INFORMATION (REV 13.11.25) 6 Table 18: Power Consumption...................................................................................39 Table 19: Parallella Performance Goals.....................................................................40 PRELIMINARY INFORMATION (REV 13.11.25) 7 1 Overview The Parallella board is a high performance computing platform based on a dual-core ARM-A9 Zynq System-On-Chip
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