Nmi Yearbook 2014
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A 1024-Core 70GFLOPS/W Floating Point Manycore Microprocessor
A 1024-core 70GFLOPS/W Floating Point Manycore Microprocessor Andreas Olofsson, Roman Trogan, Oleg Raikhman Adapteva, Lexington, MA The Past, Present, & Future of Computing SIMD MIMD PE PE PE PE MINI MINI MINI CPU CPU CPU PE PE PE PE MINI MINI MINI CPU CPU CPU PE PE PE PE MINI MINI MINI CPU CPU CPU MINI MINI MINI BIG BIG CPU CPU CPU CPU CPU BIG BIG BIG BIG CPU CPU CPU CPU PAST PRESENT FUTURE 2 Adapteva’s Manycore Architecture C/C++ Programmable Incredibly Scalable 70 GFLOPS/W 3 Routing Architecture 4 E64G400 Specifications (Jan-2012) • 64-Core Microprocessor • 100 GFLOPS performance • 800 MHz Operation • 8GB/sec IO bandwidth • 1.6 TB/sec on chip memory BW • 0.8 TB/sec network on chip BW • 64 Billion Messages/sec IO Pads Core • 2 Watt total chip power • 2MB on chip memory Link Logic • 10 mm2 total silicon area • 324 ball 15x15mm plastic BGA 5 Lab Measurements 80 Energy Efficiency 70 60 50 GFLOPS/W 40 30 20 10 0 0 200 400 600 800 1000 1200 MHz ENERGY EFFICIENCY ENERGY EFFICIENCY (28nm) 6 Epiphany Performance Scaling 16,384 G 4,096 F 1,024 L 256 O 64 4096 P 1024 S 16 256 64 4 16 1 # Cores On‐demand scaling from 0.25W to 64 Watt 7 Hold on...the title said 1024 cores! • We can build it any time! • Waiting for customer • LEGO approach to design • No global timinga paths • Guaranteed by design • Generate any array in 1 day • ~130 mm2 silicon area 1024 Cores 1Core 8 What about 64-bit Floating Point? Single Precision Double Precision 2 FLOPS/CYCLE 2 FLOPS/CYCLE 64KB SRAM 64KB SRAM 0.215mm^2 0.237mm^2 700MHz 600MHz 9 Epiphany Latency Specifications -
Comparison of 116 Open Spec, Hacker Friendly Single Board Computers -- June 2018
Comparison of 116 Open Spec, Hacker Friendly Single Board Computers -- June 2018 Click on the product names to get more product information. In most cases these links go to LinuxGizmos.com articles with detailed product descriptions plus market analysis. HDMI or DP- USB Product Price ($) Vendor Processor Cores 3D GPU MCU RAM Storage LAN Wireless out ports Expansion OSes 86Duino Zero / Zero Plus 39, 54 DMP Vortex86EX 1x x86 @ 300MHz no no2 128MB no3 Fast no4 no5 1 headers Linux Opt. 4GB eMMC; A20-OLinuXino-Lime2 53 or 65 Olimex Allwinner A20 2x A7 @ 1GHz Mali-400 no 1GB Fast no yes 3 other Linux, Android SATA A20-OLinuXino-Micro 65 or 77 Olimex Allwinner A20 2x A7 @ 1GHz Mali-400 no 1GB opt. 4GB NAND Fast no yes 3 other Linux, Android Debian Linux A33-OLinuXino 42 or 52 Olimex Allwinner A33 4x A7 @ 1.2GHz Mali-400 no 1GB opt. 4GB NAND no no no 1 dual 40-pin 3.4.39, Android 4.4 4GB (opt. 16GB A64-OLinuXino 47 to 88 Olimex Allwinner A64 4x A53 @ 1.2GHz Mali-400 MP2 no 1GB GbE WiFi, BT yes 1 40-pin custom Linux eMMC) Banana Pi BPI-M2 Berry 36 SinoVoip Allwinner V40 4x A7 Mali-400 MP2 no 1GB SATA GbE WiFi, BT yes 4 Pi 40 Linux, Android 8GB eMMC (opt. up Banana Pi BPI-M2 Magic 21 SinoVoip Allwinner A33 4x A7 Mali-400 MP2 no 512MB no Wifi, BT no 2 Pi 40 Linux, Android to 64GB) 8GB to 64GB eMMC; Banana Pi BPI-M2 Ultra 56 SinoVoip Allwinner R40 4x A7 Mali-400 MP2 no 2GB GbE WiFi, BT yes 4 Pi 40 Linux, Android SATA Banana Pi BPI-M2 Zero 21 SinoVoip Allwinner H2+ 4x A7 @ 1.2GHz Mali-400 MP2 no 512MB no no WiFi, BT yes 1 Pi 40 Linux, Android Banana -
STAC Summits
TM STAC Summit October 16, 2012 Doors open: 9:30am Meeting starts: 10:00am Grand Hyatt New York Manhattan Ballroom Park Avenue at Grand Central Station New York, NY Register at http://www.STACresearch.com/fall2012NYC Platinum Sponsors: Gold Sponsors: Copyright © 2012 STAC. STAC and all STAC names are trademarks or registered trademarks of the Securities Technology Analysis Center, LLC. All other marks are the property of their respective owners. AGENDA Note: Times are approximate. BIG WORKLOADS 10:00am STAC Update – Big Workloads Peter Lankford, Founder & Director, STAC Peter will provide a brief update on the Council's activities related to big-data and big-compute workloads, including benchmarking. 10:10am Parallel Programming Case Study Robert Geva, Parallel Programming Model Architect, Intel An efficient parallel program utilizes all hardware parallel resources. Robert will compare and contrast capabilities of task-parallel technologies and demonstrate the vectorization programming models across both the Intel Xeon (Sandy Bridge) and Intel Xeon Phi (MIC) product lines. Using a case-study approach, he will demonstrate the consistency of parallel programming in these environments. 10:30am Data Management Frontiers A variety of new technologies have emerged to address new challenges in data management, enabling firms to do things they thought unthinkable not long ago. Through a series of short presentations, experts will discuss specific data management challenges and what they view as solutions. Scaling Graph Analytics Venkat Krishnamurthy, Lead Solution Architect, YarcData Graphs have been in the news with increasing frequency, thanks to a realization that a number of interesting problems in specific industries--including trading and investment--are best represented and analyzed as graphs. -
Survey and Benchmarking of Machine Learning Accelerators
1 Survey and Benchmarking of Machine Learning Accelerators Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, and Jeremy Kepner MIT Lincoln Laboratory Supercomputing Center Lexington, MA, USA freuther,pmichaleas,michael.jones,vijayg,sid,[email protected] Abstract—Advances in multicore processors and accelerators components play a major role in the success or failure of an have opened the flood gates to greater exploration and application AI system. of machine learning techniques to a variety of applications. These advances, along with breakdowns of several trends including Moore’s Law, have prompted an explosion of processors and accelerators that promise even greater computational and ma- chine learning capabilities. These processors and accelerators are coming in many forms, from CPUs and GPUs to ASICs, FPGAs, and dataflow accelerators. This paper surveys the current state of these processors and accelerators that have been publicly announced with performance and power consumption numbers. The performance and power values are plotted on a scatter graph and a number of dimensions and observations from the trends on this plot are discussed and analyzed. For instance, there are interesting trends in the plot regarding power consumption, numerical precision, and inference versus training. We then select and benchmark two commercially- available low size, weight, and power (SWaP) accelerators as these processors are the most interesting for embedded and Fig. 1. Canonical AI architecture consists of sensors, data conditioning, mobile machine learning inference applications that are most algorithms, modern computing, robust AI, human-machine teaming, and users (missions). Each step is critical in developing end-to-end AI applications and applicable to the DoD and other SWaP constrained users. -
SPORK: a Summarization Pipeline for Online Repositories of Knowledge
SPORK: A SUMMARIZATION PIPELINE FOR ONLINE REPOSITORIES OF KNOWLEDGE A Thesis presented to the Faculty of California Polytechnic State University San Luis Obispo In Partial Fulfillment of the Requirements for the Degree Master of Science in Computer Science by Steffen Lyngbaek June 2013 c 2013 Steffen Lyngbaek ALL RIGHTS RESERVED ii COMMITTEE MEMBERSHIP TITLE: SPORK: A Summarization Pipeline for Online Repositories of Knowledge AUTHOR: Steffen Lyngbaek DATE SUBMITTED: June 2013 COMMITTEE CHAIR: Professor Alexander Dekhtyar, Ph.D., De- parment of Computer Science COMMITTEE MEMBER: Professor Franz Kurfess, Ph.D., Depar- ment of Computer Science COMMITTEE MEMBER: Professor Foaad Khosmood, Ph.D., Depar- ment of Computer Science iii Abstract SPORK: A Summarization Pipeline for Online Repositories of Knowledge Steffen Lyngbaek The web 2.0 era has ushered an unprecedented amount of interactivity on the Internet resulting in a flood of user-generated content. This content is of- ten unstructured and comes in the form of blog posts and comment discussions. Users can no longer keep up with the amount of content available, which causes developers to start relying on natural language techniques to help mitigate the problem. Although many natural language processing techniques have been em- ployed for years, automatic text summarization, in particular, has recently gained traction. This research proposes a graph-based, extractive text summarization system called SPORK (Summarization Pipeline for Online Repositories of Knowl- edge). The goal of SPORK is to be able to identify important key topics presented in multi-document texts, such as online comment threads. While most other automatic summarization systems simply focus on finding the top sentences rep- resented in the text, SPORK separates the text into clusters, and identifies dif- ferent topics and opinions presented in the text. -
Master's Thesis: Adaptive Core Assignment for Adapteva Epiphany
Adaptive core assignment for Adapteva Epiphany Master of Science Thesis in Embedded Electronic System Design Erik Alveflo Chalmers University of Technology Department of Computer Science and Engineering G¨oteborg, Sweden 2015 The Author grants to Chalmers University of Technology and University of Gothenburg the non-exclusive right to publish the Work electronically and in a non-commercial pur- pose make it accessible on the Internet. The Author warrants that he/she is the author to the Work, and warrants that the Work does not contain text, pictures or other mate- rial that violates copyright law. The Author shall, when transferring the rights of the Work to a third party (for example a publisher or a company), acknowledge the third party about this agreement. If the Author has signed a copyright agreement with a third party regarding the Work, the Author warrants hereby that he/she has obtained any necessary permission from this third party to let Chalmers University of Technology and University of Gothenburg store the Work electronically and make it accessible on the Internet. Adaptive core assignment for Adapteva Epiphany Erik Alveflo, c Erik Alveflo, 2015. Examiner: Per Larsson-Edefors Chalmers University of Technology Department of Computer Science and Engineering SE-412 96 G¨oteborg Sweden Telephone + 46 (0)31-772 1000 Department of Computer Science and Engineering G¨oteborg, Sweden 2015 Adaptive core assignment for Adapteva Epiphany Erik Alveflo Department of Computer Science and Engineering Chalmers University of Technology Abstract The number of cores in many-core processors is ever increasing, and so is the number of defects due to manufacturing variations and wear-out mechanisms. -
Program & Exhibits Guide
FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW CONFERENCE PROGRAM & EXHIBITS GUIDE JUNE 24-28, 2018 | SAN FRANCISCO, CA | MOSCONE CENTER WEST Mark You Calendar! DAC IS IN LAS VEGAS IN 2019! MACHINE IP LEARNING ESS & AUTO DESIGN SECURITY EDA IoT FROM CHIPS TO SYSTEMS – LEARN TODAY, CREATE TOMORROW JUNE 2-6, 2019 LAS VEGAS CONVENTION CENTER LAS VEGAS, NV DAC.COM DAC.COM #55DAC GET THE DAC APP! Fusion Technology Transforms DOWNLOAD FOR FREE! the RTL-to-GDSII Flow GET THE LATEST INFORMATION • Fusion of Best-in-Class Optimization and Industry-golden Signoff Tools RIGHT WHEN YOU NEED IT. • Unique Fusion Data Model for Both Logical and Physical Representation DAC.COM • Best Full-flow Quality-of-Results and Fastest Time-to-Results MONDAY SPECIAL EVENT: RTL-to-GDSII Fusion Technology • Search the Lunch at the Marriott Technical Program • Find Exhibitors www.synopsys.com/fusion • Create Your Personalized Schedule Visit DAC.com for more details and to download the FREE app! GENERAL CHAIR’S WELCOME Dear Colleagues, be able to visit over 175 exhibitors and our popular DAC Welcome to the 55th Design Automation Pavilion. #55DAC’s exhibition halls bring attendees several Conference! new areas/activities: It is great to have you join us in San • Design Infrastructure Alley is for professionals Francisco, one of the most beautiful who manage the HW and SW products and services cities in the world and now an information required by design teams. It houses a dedicated technology capital (it’s also the city that Design-on-Cloud Pavilion featuring presentations my son is named after). -
Proyecto Fin De Grado
ESCUELA TÉCNICA SUPERIOR DE INGENIERÍA Y SISTEMAS DE TELECOMUNICACIÓN PROYECTO FIN DE GRADO TÍTULO: Despliegue de Liota (Little IoT Agent) en Raspberry Pi AUTOR: Ricardo Amador Pérez TITULACIÓN: Ingeniería Telemática TUTOR (o Director en su caso): Antonio da Silva Fariña DEPARTAMENTO: Departamento de Ingeniería Telemática y Electrónica VºBº Miembros del Tribunal Calificador: PRESIDENTE: David Luengo García VOCAL: Antonio da Silva Fariña SECRETARIO: Ana Belén García Hernando Fecha de lectura: Calificación: El Secretario, Despliegue de Liota (Little IoT Agent) en Raspberry Pi Quizás de todas las líneas que he escrito para este proyecto, estas sean a la vez las más fáciles y las más difíciles de todas. Fáciles porque podría doblar la longitud de este proyecto solo agradeciendo a mis padres la infinita paciencia que han tenido conmigo, el apoyo que me han dado siempre, y el esfuerzo que han hecho para que estas líneas se hagan realidad. Por todo ello y mil cosas más, gracias. Mamá, papá, lo he conseguido. Fáciles porque sin mi tutor Antonio, este proyecto tampoco sería una realidad, no solo por su propia labor de tutor, si no porque literalmente sin su ayuda no se hubiera entregado a tiempo y funcionando. Después de esto Antonio, voy a tener que dejarme ganar algún combate en kenpo como agradecimiento. Fáciles porque, sí melones os toca a vosotros, Alex, Alfonso, Manu, Sama, habéis sido mi apoyo más grande en los momentos más difíciles y oscuros, y mis mejores compañeros en los momentos de felicidad. Amigos de Kulturales, los hermanos Baños por empujarme a mejorar, Pablo por ser un ejemplo a seguir, Chou, por ser de los mejores profesores y amigos que he tenido jamás. -
Experiences Using Tegra K1 and X1 for Highly Energy Efficient Computing
Experiences Using Tegra K1 and X1 for Highly Energy Efficient Computing Gaurav Mitra Andrew Haigh Luke Angove Anish Varghese Eric McCreath Alistair P. Rendell Research School of Computer Science Australian National University Canberra, Australia April 07, 2016 Introduction & Background Overview 1 Introduction & Background 2 Power Measurement Environment 3 Experimental Platforms 4 Approach 5 Results & Analysis 6 Conclusion Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 2 / 20 Introduction & Background Use of low-powered SoCs for HPC Nvidia Jetson TK1: ARM + GPU SoC Nvidia Jetson TX1: ARM + GPU SoC TI Keystone II: ARM + DSP SoC Adapteva Parallella: ARM + 64-core NoC TI BeagleBoard: ARM + DSP SoC Terasic DE1: ARM + FPGA SoC Rockchip Firefly: ARM + GPU SoC Freescale Wandboard: ARM + GPU SoC Cubieboard4: ARM + GPU SoC http://cs.anu.edu.au/systems Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 3 / 20 Introduction & Background Use of low-powered SoCs for HPC In order for SoC processors to be considered viable exascale building blocks, important factors to explore include: Absolute performance Balancing use of different on-chip devices Understanding the performance-energy trade-off Mitra et. al. (ANU) GTC 2016, San Francisco April 07, 2016 4 / 20 Introduction & Background Contributions Environment for monitoring and collecting high resolution power measurements for SoC systems Understanding the benefits of exploiting both the host CPU and accelerator GPU cores simultaneously for critical HPC kernels Performance and energy comparisons -
AI-Optimized Chipsets
AI-Optimized Chipsets Part III: Key Opportunities & Trends Aug 2018 An Introduction Previously in Part I, we reviewed the ADAC loop and key factors driving innovation for AI- optimized chipsets. In Part II, we review the shift in performance focus computing from general application neural nets and how this is driving demand for high performance computing. To this end, some startups are adopting alternative, novel approaches and this is expected to pave the way for other AI-optimized chipsets. In this instalment, we review the training and inference chipset markets, assess the dominance of tech giants, as well as the startups adopting cloud-first or edge-first approaches to AI-optimized chipsets. The training chipset market is dominated by 5 firms, while the inference chipset market is more diverse with >40 players Training Chipsets Inference Chipsets No. of Companies • 5 (i.e. Nvidia, Intel, Xilinx, AMD, Google) • > 40 Differentiators • Computation Performance • Power Efficiency • Usability • System Latency • Innovation Road Map • Cost • Computation Performance Barriers to Entry • R&D Intensity • Manufacturing Scale Economies • Developer Support • High Switching Costs (End User) • Size of End Markets • Regulatory Requirements • Distribution ASP • USD 2,000 - USD 20,000 • USD 80 - USD 10,000 Source: UBS • The training chipset market is dominated by 5 firms which have developed massively parallel architectures, well-suited for deep learning algorithms. NVIDIA is the most prominent with its GPU technology stack. • The early leaders in this market are likely to maintain their lead, but the inference market is large and easily accessible to all, including tech giants and startups. Given the significant market for inference chipsets, many defensible market niches based on high-system speed, low power and/or low Total Cost of Ownership (TCO) products are likely to emerge. -
Mac Prefix 00:05:56 00:11:B2 70:02:58 C4:93:13 08:00:24 00:0B
mac_prefix 00:05:56 00:11:B2 70:02:58 C4:93:13 08:00:24 00:0B:10 00:50:29 00:A0:2D 00:30:70 44:37:19 60:FE:20 EC:96:81 6A:73:7D 00:13:87 28:F3:58 00:16:A9 B8:B7:D7 00:1B:8A 00:19:29 7C:1E:B3 00:11:99 00:0D:72 00:12:88 00:14:95 00:18:3F 00:19:E4 00:1A:C4 00:1B:5B 00:1D:5A 00:1E:C7 00:1F:B3 00:21:7C 00:22:A4 00:23:51 00:24:56 00:25:3C 00:26:50 00:D0:9E 28:16:2E 34:EF:44 38:3B:C8 3C:EA:4F 60:C3:97 64:0F:28 74:9D:DC 94:C1:50 98:2C:BE B0:E7:54 B8:E6:25 C0:83:0A 00:0F:A2 00:04:75 00:04:76 00:22:F0 00:18:40 E4:BA:D9 00:0E:60 B0:6C:BF 00:0F:05 1C:7E:51 00:01:02 00:01:03 00:02:9C 00:06:8C 00:0A:04 00:0A:5E 00:0B:AC 00:0D:54 00:0E:6A 00:0F:CB 00:10:4B 00:10:5A 00:12:A9 00:14:7C 00:16:E0 00:18:6E 00:1A:C1 00:1C:C5 00:20:AF 00:26:54 00:50:04 00:50:DA 00:60:08 00:60:8C 00:60:97 00:A0:24 00:D0:D8 02:60:8C 02:C0:8C 00:04:0B 00:05:1A 00:1E:C1 00:22:57 00:24:73 00:30:1E 00:50:99 00:90:04 00:D0:96 08:00:4E 20:FD:F1 40:01:C6 00:60:3D C0:A3:64 BC:25:F0 8C:4B:59 00:21:C5 00:07:D5 00:A0:B5 CC:F5:38 00:09:B5 00:16:A1 08:00:21 00:06:49 00:15:C2 38:63:F6 00:22:6F 00:02:AC 5C:56:ED 00:17:A1 00:08:DE 70:E1:39 00:05:0E 00:1A:8E 00:13:CF 00:0E:56 00:1F:D4 00:18:7B 00:11:C1 00:22:B2 00:11:4E AC:EE:3B 00:09:C0 00:14:2E 04:84:8A B8:99:19 00:18:4F 00:11:ED 00:1B:E5 00:22:82 18:2B:05 C4:93:00 7C:1A:03 00:90:A0 B8:E7:79 00:1B:7C 00:15:34 00:05:39 EC:FC:55 00:08:75 00:40:08 08:18:4C 00:15:6E 00:1F:A0 00:10:43 00:22:80 00:12:41 FC:E1:86 00:21:FA 00:06:B9 00:24:AB 00:E0:E6 00:0E:E7 00:30:D4 00:07:32 00:17:D9 00:26:72 00:90:57 E4:77:6B 00:08:5D 00:10:BC 00:02:0F 70:2F:97 00:30:97 -
STAC Benchmark Council: Recap of 2012
STAC Benchmark Council: Recap of 2012 22 January 2013 2012 was another productive year for the STAC Benchmark™ Council. STAC® has highlighted some of the main achievements in this document, with links to further information for members. Note that some of the links may require you to be logged in (individuals without a login can create one for free). In addition, access to some content may depend on the membership level of your firm. To have information about your firm's membership level sent to your email address, along with contact details for the individuals who manage the Council relationship for your firm, click here (your email address must be identifiable as a domain belonging to a Council member firm). If you have confirmed your firm's membership level and are denied access to materials to which you believe your firm is entitled, please submit a permissions request here. If you would like to discuss your firm’s membership level or have any other questions, please contact [email protected]. STAC Benchmark Council: Recap of 2012 Page 2 of 12 EXECUTIVE SUMMARY In 2012, membership in the STAC Benchmark Council grew to 249 organizations. 80% of these were trading organizations, with the balance being the vendors who serve them. Click here to see the list. The Council held six STAC Summits across New York, London, and Chicago, with the New York and London Summits being expanded, full-day events. Research in 2012 covered both Fast Workloads (low-latency trading, real-time messaging) and Big Workloads (big data and big compute, such as risk management, tick databases, and unstructured data tasks).