DOCSLIB.ORG

Towards Oxide Electronics: a Roadmap M

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Towards Oxide Electronics: a Roadmap M Towards Oxide Electronics: a Roadmap M. Coll, J. Fontcuberta, M. Althammer, M. Bibes, H. Boschker, A. Calleja, G. Cheng, M. Cuoco, R. Dittmann, B. Dkhil, et al. To cite this version: M. Coll, J. Fontcuberta, M. Althammer, M. Bibes, H. Boschker, et al.. Towards Oxide Electronics: a Roadmap. Applied Surface Science, Elsevier, 2019, 482, pp.1-93. 10.1016/j.apsusc.2019.03.312. hal-02122830 HAL Id: hal-02122830 https://hal-centralesupelec.archives-ouvertes.fr/hal-02122830 Submitted on 24 Aug 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Distributed under a Creative Commons Attribution - NonCommercial - NoDerivatives| 4.0 International License Applied Surface Science 482 (2019) 1–93 Contents lists available at ScienceDirect Applied Surface Science journal homepage: www.elsevier.com/locate/apsusc Towards Oxide Electronics: a Roadmap T M. Colla, J. Fontcubertaa, M. Althammerb,c, M. Bibesd, H. Boschkere, A. Callejaf, G. Chengg,h,i, M. Cuocoj, R. Dittmannk, B. Dkhill, I. El Baggarim, M. Fanciullin, I. Finaa, E. Fortunatop,q, C. Fronteraa, S. Fujitar, V. Garciad, S.T.B. Goennenweins,t, C.-G. Granqvistu, J. Grollierd, R. Grossb,c,v, A. Hagfeldtw, G. Herranza, K. Honox, E. Houwmany, M. Huijbeny, A. Kalaboukhovz, D.J. Keebleaa, G. Kostery, L.F. Kourkoutisab,ac, J. Levyh,i, M. Lira-Cantuad, J.L. MacManus-Driscollae, Jochen Mannharte, R. Martinsn,o, S. Menzeli, T. Mikolajickaf,ag, M. Napariae, M.D. Nguyeny, G. Niklassonu, C. Paillardah, S. Panigrahip,q, G. Rijndersy, F. Sáncheza, P. Sanchisai, S. Sannaaj, D.G. Schlomak,al, U. Schroederaf, K.M. Shenab,ak, A. Siemonam, ⁎ M. Spreitzeran, H. Sukegawax, R. Tamayof, J. van den Brinkao, N. Prydsaj, F. Miletto Granozioap, a Institut de Ciència de Materials de Barcelona (ICMAB-CSIC), Campus of UAB, 08193 Cerdanyola del Vallès, Catalonia, Spain b Walther-Meißner-Institut, Bayerische Akademie der Wissenschaften, 85748 Garching, Germany c Physik-Department, Technische Universität München, 85748 Garching, Germany d Unité Mixte de Physique, CNRS, Thales, Univ. Paris-Sud, Université Paris-Saclay, 91767 Palaiseau, France e Max Planck Institute for Solid State Research, Heisenbergstr. 1, 70569 Stuttgart, Germany f OXOLUTIA S.L, Avda. Castell de Barberà, 26, Tallers 13, Nau 1, 08210 Barberà del Vallès, Barcelona, Spain g CAS Key Laboratory of Microscale Magnetic Resonance and Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China h Department of Physics and Astronomy, University of Pittsburgh, Pittsburgh, PA 15260, USA i Pittsburgh Quantum Institute, Pittsburgh, PA 15260, USA j CNR-SPIN and Dipartimento di Fisica ''E. R. Caianiello", Università di Salerno, IT-84084 Fisciano (SA), Italy k Peter Grünberg Institut (PGI-7), Forschungszentrum Jülich GmbH, 52425 Jülich, Germany l Laboratoire Structures, Propriétés et Modélisation des Solides, CentraleSupélec,CNRS-UMR 8580, Université Paris-Saclay, 91190 Gif-sur-Yvette, France m Department of Physics, Cornell University, Ithaca, NY 14853, USA n Department of Materials Science, University of Milano Bicocca, Milano, Italy o MDM Laboratory, IMM-CNR, Agrate Brianza, Italy p CENIMAT/i3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia (FCT), Universidade NOVA de Lisboa (UNL), Portugal q CEMOP/UNINOVA, 2829-516 Caparica, Portugal r Kyoto University, Katsura, Kyoto 615-8520, Japan s Institut für Festkörperphysik, Technische Universität Dresden, 01062 Dresden, Germany t Center for Transport and Devices of Emergent Materials, Technische Universität Dresden, 01062 Dresden, Germany u Department of Engineering Sciences, The Ångström Laboratory, Upp sala University, P.O. Box 534, SE 75121 Uppsala, Sweden v Nanosystems Initiative Munich (NIM), 80799 München, Germany w Laboratory of Photomolecular Science, Institute of Chemical Sciencesand Engineering, Ecole Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland x Research Center for Magnetic and Spintronic Materials, National Institute for Materials Science (NIMS), 1-2-1 Sengen, Tsukuba 3050047, Japan y MESA+ Institute for Nanotechnology, University of Twente, 7500 AE Enschede, Netherlands z Department of Microtechnology and Nanoscience - MC2, Chalmers University ofTechnology, Göteborg, Sweden aa Carnegie Laboratory of Physics, SUPA, School of Science and Engineering, University of Dundee, Dundee DD1 4HN, UK ab Kavli Institute at Cornell for Nanoscale Science, Ithaca, NY 14853, USA ac School of Applied and Engineering Physics, Cornell University, Ithaca, NY 14853, USA ad Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and The Barcelona Institute of Science and Technology (BIST), Campus UAB, Bellaterra, E-08193 Barcelona, Spain ae Department of Materials Science and Metallurgy, University of Cambridge, 27 Charles Babbage Road, Cambridge CB3 0FS, UK af NaMLab gGmbH, Noethnitzer Straße 64, 01187 Dresden, Germany ag Chair of Nanoelectronic Materials, TU Dresden, 01062 Dresden, Germany ah Physics Department, University of Arkansas, Fayetteville, AR 72701, USA ai Nanophotonics TechnologyCenter, Universitat Politècnica de València, Camino de Vera s/n, 46022 Valencia, Spain aj Department of Energy Storage and Conversion, Technical University of Denmark, DK-4000 Roskilde, Denmark ak Laboratory of Atomic and Solid State Physics, Department of Physics, Cornell University, Ithaca, NY 14853, USA al Department of Material Science and Engineering, Cornell University, Ithaca, NY 14853, USA am Institut für Werkstoffe der Elektrotechnik (IWE 2), RWTH Aachen University, 52066 Aachen, Germany ⁎ Corresponding author. E-mail address: [email protected] (F. Miletto Granozio). https://doi.org/10.1016/j.apsusc.2019.03.312 0169-4332/ © 2019 The Author(s). Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/BY-NC-ND/4.0/). M. Coll, et al. Applied Surface Science 482 (2019) 1–93 an Advanced Materials Department, Jožef Stefan Institute, Jamova cesta 39, 1000 Ljubljana, Slovenia ao Institute for Theoretical Solid State Physics, IFW-Dresden, Helm- holtzstr. 20, D-01069 Dresden, Germany ap CNR-SPIN, Naples Unit, Complesso Universitario di Monte Sant’An -gelo, Via Cinthia, IT-80126 Napoli, Italy Abstract At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore’s law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this classofcom- pounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin filmsand heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics. Index 12. Oxides for data storage and processing: Ferroelectric tunnel Preface junctions M. Coll, J. Fontcuberta, N. Pryds and F. Miletto Granozio V. Garcia and M. Bibes 13. Oxides for data storage: Ferroelectric RAMs Introduction U. Schröeder and T. Mikolajick 14. Alternative logic concepts using oxide-based electronic 1. A Unique Exploration devices J. Mannhart and H. Boschker S. Menzel and A. Siemon 15. High-k dielectrics for CMOS and emerging logic devices Methods M. Fanciulli 16. Oxide nano-electronics for neuromorphic computing 2. What theoretical approaches can provide: a perspective on J. Grollier oxide electronics 17. Possible future quantum technologies based
Load more

Recommended publications
  • Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
    electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder.
    [Show full text]
  • CSE Yet, Please Do Well! Logical Connectives
    administrivia Course web: http://www.cs.washington.edu/311 Office hours: 12 office hours each week Me/James: MW 10:30-11:30/2:30-3:30pm or by appointment TA Section: Start next week Call me: Shayan Don’t: Actually call me. Homework #1: Will be posted today, due next Friday by midnight (Oct 9th) Gradescope! (stay tuned) Extra credit: Not required to get a 4.0. Counts separately. In total, may raise grade by ~0.1 Don’t be shy (raise your hand in the back)! Do space out your participation. If you are not CSE yet, please do well! logical connectives p q p q p p T T T T F T F F F T F T F NOT F F F AND p q p q p q p q T T T T T F T F T T F T F T T F T T F F F F F F OR XOR 푝 → 푞 • “If p, then q” is a promise: p q p q F F T • Whenever p is true, then q is true F T T • Ask “has the promise been broken” T F F T T T If it’s raining, then I have my umbrella. related implications • Implication: p q • Converse: q p • Contrapositive: q p • Inverse: p q How do these relate to each other? How to see this? 푝 ↔ 푞 • p iff q • p is equivalent to q • p implies q and q implies p p q p q Let’s think about fruits A fruit is an apple only if it is either red or green and a fruit is not red and green.
    [Show full text]
  • New Approaches for Memristive Logic Computations
    Portland State University PDXScholar Dissertations and Theses Dissertations and Theses 6-6-2018 New Approaches for Memristive Logic Computations Muayad Jaafar Aljafar Portland State University Let us know how access to this document benefits ouy . Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons Recommended Citation Aljafar, Muayad Jaafar, "New Approaches for Memristive Logic Computations" (2018). Dissertations and Theses. Paper 4372. 10.15760/etd.6256 This Dissertation is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. For more information, please contact [email protected]. New Approaches for Memristive Logic Computations by Muayad Jaafar Aljafar A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Dissertation Committee: Marek A. Perkowski, Chair John M. Acken Xiaoyu Song Steven Bleiler Portland State University 2018 © 2018 Muayad Jaafar Aljafar Abstract Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore’s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors.
    [Show full text]
  • Logic Functions Realized Using Clockless Gates for Rapid Single-Flux-Quantum Circuits
    R2-4 SASIMI 2021 Proceedings Logic Functions Realized Using Clockless Gates for Rapid Single-Flux-Quantum Circuits Takahiro Kawaguchi Kazuyoshi Takagi Naofumi Takagi Graduate School of Informatics Graduate School of Engineering Graduate School of Informatics Kyoto University Mie University Kyoto University Kyoto, 606-8501, Japan Mie, 514-8507, Japan Kyoto, 606-8501, Japan [email protected] [email protected] [email protected] Abstract— Superconducting rapid single-flux- and the area occupied by a clock distribution network are quantum (RSFQ) circuit is a promising candidate reduced. The reduction of the pipeline depth leads to a for circuit technology in the post-Moore era. RSFQ fewer DFFs for path-balancing and a smaller circuit area. digital circuits operate with pulse logic and are A clockless AND gate and a clockless NIMPLY gate was usually composed of clocked gates. We have proposed proposed in [10]. A NIMPLY (not-imply) gate is an AND clockless gates, which can reduce the hardware gate with one inverted input, which implements x∧¬y.A amount of a circuit drastically. In this paper, we confluence buffer [1], which merges a pulse from its inputs first discuss logic functions realizable using clockless to its output, can be used as a clockless OR gate. gates. We show that all the 0-preserving functions A clockless gate realizes only a 0-preserving logic func- can be realized using the existing clockless gates, tion, which outputs 0 from the input value of all 0s, be- i.e., AND, OR, and NIMPLY (not-imply) gates.
    [Show full text]
  • Automated Synthesis of Unconventional Computing Systems
    University of Central Florida STARS Electronic Theses and Dissertations, 2004-2019 2019 Automated Synthesis of Unconventional Computing Systems Amad Ul Hassen University of Central Florida Part of the Computer Engineering Commons Find similar works at: https://stars.library.ucf.edu/etd University of Central Florida Libraries http://library.ucf.edu This Doctoral Dissertation (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Electronic Theses and Dissertations, 2004-2019 by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation Ul Hassen, Amad, "Automated Synthesis of Unconventional Computing Systems" (2019). Electronic Theses and Dissertations, 2004-2019. 6500. https://stars.library.ucf.edu/etd/6500 AUTOMATED SYNTHESIS OF UNCONVENTIONAL COMPUTING SYSTEMS by AMAD UL HASSEN MSc Computer Science, University of Central Florida, 2016 MSc Electrical Engineering, University of Engineering & Technology Lahore, 2013 BSc Electrical Engineering, University of Engineering & Technology, Lahore, 2008 A Dissertation submitted in partial fulfilment of the requirements for the degree of Doctor of Philosophy in the Department of Electrical and Computer Engineering in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Summer Term 2019 Major Professor: Sumit Kumar Jha c 2019 Amad Ul Hassen ii ABSTRACT Despite decades of advancements, modern computing systems which are based on the von Neu- mann architecture still carry its shortcomings. Moore’s law, which had substantially masked the effects of the inherent memory-processor bottleneck of the von Neumann architecture, has slowed down due to transistor dimensions nearing atomic sizes.
    [Show full text]
  • Imply Logic Implementation of Logic Gates Using Memristors
    A.Lavanya Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 5, Issue 5, ( Part -5) May 2015, pp.105-109 RESEARCH ARTICLE OPEN ACCESS Imply Logic Implementation of Carry Save Adder Using Memristors *1A.Lavanya, 2BG.Gopal, 1PG Scholar, 2, Associate Professor, Vel Tech Multi Tech Dr. Rangarajan Dr. SakunthalaEngineering College, Avadi, Chennai, India Abstract- Memristor is a two terminal fundamental passive element that provides arelation between electric charge„q‟ and magnetic flux „Φ‟. It is a type of resistor with some memory property. Implication logic can be easily developed using memristors. Implication logic can be implemented with less number of memristors in comparison with silicon transistors. It has been proved that any Boolean expressions can be implemented with this logic [3]and[4]. Carry save adder (CSA) circuits is built up with IMPLY logic with the basic gates obtained with memristors and their working are briefly explained. The total number of memristors required iscompared with the number of transistors required in constructing the same circuit with CMOS logic. Keywords-- Memristor, flux, charge, memory, IMPLY logic, nonlinear dopant drift, logic gates. positivepoleand negative pole respectively. I. INTRODUCTION Depending on the time for which the type of charge Memristor is a two terminal fundamental passive passing through the device, the lengths of the doped element that line up with basic electrical and and undoped area varies from „w‟. The movement of electronic elements. It is passive because it just drops oxygen atoms follows the mechanism of dopant drift. the inputs applied and not goingtoimprove [6] i.e., Oxygen vacancies in the TiO2 prefer to move thesignalit.
    [Show full text]
  • Optical and Electronic Logic Gate with Orthogonal Inputs
    This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Optical and electronic logic gate with orthogonal inputs Xu, Cai 2018 Xu, C. (2018). Optical and electronic logic gate with orthogonal inputs. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/89677 https://doi.org/10.32657/10220/46334 Downloaded on 07 Oct 2021 17:59:43 SGT OPTICAL AND ELECTRONIC LOGIC GATE WITH ORTHOGONAL INPUTS XU CAI SCHOOL OF MATERIALS SCIENCE AND ENGINEERING 2018 OPTICAL AND ELECTRONIC LOGIC GATE WITH ORTHOGONAL INPUTS XU CAI SCHOOL OF MATERIALS SCIENCE AND ENGINEERING A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Doctor of Philosophy 2018 Statement of Originality I hereby certify that the work embodied in this thesis is the result of original research and has not been submitted for a higher degree to any other University or Institution. 17/01/2018 . Date Xu Cai Supervisor Declaration Statement I have reviewed the content and presentation style of this thesis and declare it is free of plagiarism and of sufficient grammatical clarity to be examined. To the best of my knowledge, the research and writing are those of the candidate except as acknowledged in the Author Attribution Statement. I confirm that the investigations were conducted in accord with the ethics policies and integrity standards of Nanyang Technological University and that the research data are presented honestly and without prejudice. 17/01/2018 . Date Chen Xiaodong Authorship Attribution Statement This thesis contains material from a paper (plan to be) published in the following peer- reviewed journal where I was the first and/or corresponding author.
    [Show full text]
  • New Design Approaches for Flexible Architectures and In-Memory Computing Based on Memristor Technologies
    THESE DE DOCTORAT DE L’ÉCOLE NATIONALE SUPERIEURE MINES-TELECOM ATLANTIQUE BRETAGNE PAYS DE LA LOIRE - IMT ATLANTIQUE ECOLE DOCTORALE N° 601 Mathématiques et Sciences et Technologies de l'Information et de la Communication Spécialité : Electronique Par Khaled ALHAJ ALI New design approaches for flexible architectures and in-memory computing based on memristor technologies Thèse présentée et soutenue à Brest, le 13 juillet 2020 Unité de recherche : Lab-STICC, UMR CNRS 6285 Thèse N° : 2020IMTA0197 Rapporteurs avant soutenance : Ian O'Connor Professeur, Ecole Centrale de Lyon Lorena Anghel Professeur, Grenoble INP Composition du Jury : Président : Adnan Harb Professeur, Lebanese International University Rapporteurs : Ian O'Connor Professeur, Ecole Centrale de Lyon Lorena Anghel Professeur, Grenoble INP Examinateurs : Rouwaida Kanj Associate Professor, American University of Beirut Encadrants : Mostafa Rizk Assistant Professor, Lebanese International University Jean-Philippe Diguet Directeur de recherche CNRS, Lab-STICC Dir. de thèse : Amer Baghdadi Professeur, IMT Atlantique Co-dir. de thèse : Jalal Jomaah Professeur, Lebanese University Invité(s) Grégory Di Pendina Ingénieur de recherche, SPINTEC Contents Contents I List of Figures IV List of Tables VII Résumé long IX Introduction 1 1 Memristor: Principals and Applications 7 1.1 Memristor fundamentals . .7 1.1.1 Basic operation . .8 1.1.2 Memristor device modeling . .9 1.2 Memristor as a memory element . 11 1.2.1 Emerging non-volatile memories . 11 1.2.2 Crossbar arrays . 13 1.3 Memristors for reconfigurable interconnects . 16 1.4 Memristors for logic design . 18 1.4.1 Memristor-based logic design styles . 19 1.4.1.1 IMPLY – Material Implication . 20 1.4.1.2 MAGIC – Memristor Aided Logic .
    [Show full text]
  • Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture
    Portland State University PDXScholar Dissertations and Theses Dissertations and Theses Spring 6-6-2016 Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture Kamela Choudhury Rahman Portland State University Follow this and additional works at: https://pdxscholar.library.pdx.edu/open_access_etds Part of the Electrical and Computer Engineering Commons, and the Nanoscience and Nanotechnology Commons Let us know how access to this document benefits ou.y Recommended Citation Rahman, Kamela Choudhury, "Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture" (2016). Dissertations and Theses. Paper 2956. https://doi.org/10.15760/etd.2952 This Dissertation is brought to you for free and open access. It has been accepted for inclusion in Dissertations and Theses by an authorized administrator of PDXScholar. Please contact us if we can make this document more accessible: [email protected]. Complete Design Methodology of a Massively Parallel and Pipelined Memristive Stateful IMPLY Logic Based Reconfigurable Architecture by Kamela Choudhury Rahman A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering Dissertation Committee: Marek A Perkowski, Chair Dan Hammerstrom Xiaoyu Song Rolf Koenenkamp Portland State University 2016 © 2016 Kamela Choudhury Rahman Abstract Continued dimensional scaling of CMOS processes is approaching fundamental limits and therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks that can be easily reconfigured.
    [Show full text]
  • Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. XXX, NO. XXX, XXX 1 201X Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies Shahar Kvatinsky, Student Member, IEEE, Guy Satat, Nimrod Wald, Eby G. Friedman, Fellow, IEEE, Avinoam Kolodny, Senior Member, IEEE, and Uri C. Weiser, Fellow, IEEE represented by voltage levels. In [3], memristors are used as a Abstract— Memristors are novel devices, useful as memory at reconfigurable switch. In [4], a hybrid memristor-CMOS all hierarchies. These devices can also behave as logic circuits. logic family is proposed - MRL (Memristor Ratioed Logic). In this paper, the IMPLY logic gate, a memristor-based logic In MRL, the memristors act as computational elements, circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic performing OR and AND Boolean functions, while the element, and latch in different stages of the computing process. CMOS transistors perform logical inversion and The logical state is determined by the resistance of the amplification of the logical voltage signals. A similar memristor. This logic family can be integrated within a approach is proposed in [5]. memristor-based crossbar, commonly used for memory. In this Another approach for logic with memristors is to treat paper, a methodology for designing this logic family is proposed. resistance as the logical state, where the high and low The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and resistance are considered, respectively, as logical zero and includes some additional design constraints to support the one.
    [Show full text]
  • MAGIC—Memristor-Aided Logic Shahar Kvatinsky, Student Member, IEEE, Dmitry Belousov, Slavik Liman, Guy Satat, Student Member, IEEE, Nimrod Wald, Eby G
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 61, NO. 11, NOVEMBER 2014 895 MAGIC—Memristor-Aided Logic Shahar Kvatinsky, Student Member, IEEE, Dmitry Belousov, Slavik Liman, Guy Satat, Student Member, IEEE, Nimrod Wald, Eby G. Friedman, Fellow, IEEE, Avinoam Kolodny, Senior Member, IEEE, and Uri C. Weiser, Fellow, IEEE Abstract—Memristors are passive components with a varying resistance that depends on the previous voltage applied across the device. While memristors are naturally used as memory, mem- ristors can also be used for other applications, including logic circuits. In this brief, a memristor-only logic family, i.e., memristor- aided logic (MAGIC), is presented. In each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional memristor serves as an output. The topology of a MAGIC NOR gate is similar to the structure of a common memristor-based Fig. 1. Memristor symbol. The polarity of the memristor is represented by crossbar memory array. A MAGIC NOR gate can therefore be a thick black line. When current flows into the device (the upper arrow), the placed within memory, providing opportunities for novel non-von resistance of the device increases. When current flows out of the device (the Neumann computer architectures. Other MAGIC gates also exist lower arrow), the resistance of the device decreases. (e.g., AND, OR, NOT,andNAND) and are described in this brief. Index Terms—IMPLY, in-memory computing, memristive sys- tions of memristors have been presented. Nonvolatile emerging tems, memristor, memristor-aided logic (MAGIC), stateful logic. memory technologies, including resistive RAM (RRAM) and spin–transfer torque magnetoresistive RAM, can be considered I.
    [Show full text]
  • Synthesizing Biomolecule-Based Boolean Logic Gates Takafumi Miyamoto,† Shiva Razavi,†,‡ Robert Derose,† and Takanari Inoue*,†,§
    Review pubs.acs.org/synthbio Synthesizing Biomolecule-Based Boolean Logic Gates Takafumi Miyamoto,† Shiva Razavi,†,‡ Robert DeRose,† and Takanari Inoue*,†,§ † ‡ Department of Cell Biology, Center for Cell Dynamics and Department of Biomedical Engineering, School of Medicine, Johns Hopkins University, Baltimore, Maryland 21205, United States § PRESTO, JST, 4-1-8 Honcho Kawaguchi, Saitama 332-0012, Japan ABSTRACT: One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. KEYWORDS: synthetic biology, Boolean logic gate, biomolecular devices, chemically inducible dimerization, biocomputers, circuit design cell is a sophisticated device that performs three elaborate the circuit is defined as either “0” or “1”, respectively. Digital A functions: sensing inputs, processing the input informa- circuits make extensive use of logic elements that are tion for decision-making, and executing the outputs.
    [Show full text]