International Journal of Pure and Applied Mathematics Volume 118 No. 18 2018, 4373-4392 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu

Survey based on Comparison of different CMOS logic styles with Hybrid CMOS Memristor Logic Style with issues and parameters 1Keerthy Rai V, 2Sakthivel R 1,2School of Electronics Engineering,VIT University,Vellore,INDIA.

ABSTRACT

A trait of the nanometer scale device conceives contemporary circumstances for innovative logic elements to realize the advanced circuits. CMOS dimensional scaling is continuous process imminent to fundamental limits. Hence new device Memristor is a promising nonvolatile memory besides resistor came into the picture. On the account of its Small size and low power consumption, it is anticipated to restore CMOS technology in several application areas.

Implementation of Hybrid CMOS with Memristor logic is proficient. In this paper, the conventional CMOS logic style with different designs was discussed. The paper presents the comparison of the CMOS logic, complementary pass transistor logic, transmission gate logic, hybrid CMOS logic and Memristor CMOS hybrid logic style with parameters of power, delay, Area and transistor count. 1.INTRODUCTION

The previous quite a few decades encompass perceive enormous development in semiconductor technology to facilitate to perpetual development ensuing in minor feature dimension in fabrication and also consumption of low energy [1].The explosive augmentation of battery operated portable appliance such as cellular phones, smart cards, PDAs Laptops and the progression of the contraction of the technology necessitate lesser silicon area, high throughput circuitry and most importantly low power[2,3]. By scaling the operating voltage and supply voltage any system‟s power consumption be able to reduce. However, it enlarges the system propagation delay and disgraces the design driving capability [3].

The Memristor is a two-terminal device for summit integration density is encouraging digital memory[4]. Chua in 1971 predicts the Memristor.The earliest Memristor device is fabricated by Hewlett-Packard labs in 2008.In view of the fact that interests in the locale of Memristor base design have withdrawn out and a numeral of works be there supported[1]. Amalgamation of expansively dissimilar technologies, for instance, Spintronics, optical circuits based on carbon nanotube field effect transistor, Meta nanomaterial and further in recent times the Memristor hold secure consideration, in consequence, create pristinely probable for designing inventive circuits and systems[5].

Extensively put side by side to CMOS Memristor retain lesser energy consumption and scalability beneath 10nm.The digital Memristors be able to construct by means of a MIM(metal insulator metal)structure by way of conduction of two electrodes squash in the midpoint of a thin insulator. The conducting filament created when the voltage is put into operation between two terminals outcome the rapid switching characteristics. While the gap is linked by the filament, the Memristor retains a resistance of low value. At what time the voltage is employed in reverse direction the filament will shrivel and ultimately break, place the Memristor in high-level resistance state[4].The beneficial features of Memristor are nonvolatile, linearity, dense, fast, low power consumption, scalability[6].

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Neural network implementation, physically unclonable functions, and Content address memory are the Memristor applications. These memory devices of nonvolatile nature and CMOS transistors are in amalgamation, proffer frequent recompenses within the design and implementation of subsequently formation high-performance systems[6].

Different logic styles using CMOS described in Section II. Detailed Memristor discussed in Section III. Hybrid CMOS logic with Memristor discussed in Section IV. In Section V comparison of different logic styles discussed. Finally, section VI has been given by conclusion. 2.DIFFERENT LOGIC STYLES BASED ON CMOS

The logic designs in the conventional domain are Standard Static Complementary Metal Oxide Semiconductor(C-CMOS), Dynamic CMOS logic, Complementary Pass-Transistor logic (CPL) and Transmission Gate (TG). Compared to dynamic equivalent, Static CMOS generally reliable, simpler and low power constraint but in the domain of on-chip area constraint is usually higher[2].Quite a few logic styles have been used in the part to implement the logic design cell. Every logic style has its individual merits and shortcomings [3]. The Different logic styles of Conventional CMOS and Memristor as shown in Fig. 1.

Logic styles

Conventional Memristor CMOS

Standard IMPLY(Material Hybrid CMOS Hybrid logic Static CMOS implication) with Memristor

Complementary Pass Transmission Gate Diffusion MAGIC(Memristor MRL(Memristor transistor (CPL) gate input(GDI) Aided Logic) ratioed logic)

Fig. 1. Different logic styles of Conventional CMOS and Memristor

The use of Pull-Up and Pull-Down transistors for CMOS structure formed with gives Standard Static CMOS design(C-CMOS) which is brought into play to offer full output voltage swing alongside voltage and size of the transistor. The Static CMOS has its larger area and limiting speed due to the availability of the P-MOS devices, most number of buffers required and high input capacitance is the detriments [2].The full adder circuit using Standard Static CMOS Design as shown in Fig. 2.

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Fig. 2. Circuit of Full adder using Standard Static CMOS Design [7]

Another logic design is complementary pass transistor logic (CPL) which has been provided the output voltage of full swing and becomes fast design. But the drawbacks are high switching activity, more transistor count, overloading of its inputs. The main disadvantage of this design is voltage degradation. Due to the reason for presenting static inverters and lot of internal nodes, it has more consumption power [2,3]. The full adder circuit using complementary pass transistor logic Design as shown in Fig. 3.

Fig. 3. Full adder using Complementary pass-transistor logic[7]

On the other hand, Hybrid pass logic with static CMOS (HPSC) introduced by Zhang provides full swing of the output voltage and presents fine driving capability. But the demerits of this design are larger propagation delay, transistor count is more, less speed [3].

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Further introduced hybrid logic design be composed of a combination of more than one logic styles to make progress the overall system concert. The major intention of this hybrid logic design is to shrink transistor count and the nodes of the design having power dissipation [2].Beyond this, limitation of this design is poor driving capability. In addition to their performance degrades massively while operates in cascade mode when suitably designed buffers are not replaced.

A new attitude eradicates the necessity of XOR/XNOR gates for full adder cell has to be designed. Gate Diffusion Input (GDI) technique is used to provide ultra-low power and high-speed digital components as well as full voltage swing, but it has high propagation delay[8]. The MUX full adder using GDI logic as shown in Fig. 4. Another design using Hybrid CMOS with Transmission gate design as shown in Fig. 5.

A

B Cin

Cin Cout Sum

B Cin

A

Fig. 4.MUX full adder using GDI logic[8]

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Vdd

Mp6

Vdd

Mn7

Mp3 Mn6 Cin Mp1 Mp2 Mp7

Cout B A Mn8 Mn2 Mn3 Mn1

Mp8

Mp4 Mp5

SUM

Mn4 Mn5

Fig. 5. Hybrid CMOS with Transmission gate design[2] 3.MEMRISTOR

A two-terminal Memristor device is electrical circuit element which changes the value of resistance by applying suitable voltages across it. In binary logic circuit applications, Memristors can be used to represent the two logic states by switching between two resistance values: Low resistance RON, and high resistance ROFF[1]. The I-V Characteristics of fundamental Elements as shown Fig. 6.

Resistor capacitor

t dv= R.di n e

r dq=C.dv r u c

Inductor Memristor

dϕ=L.di dϕ=M.dq

Voltage Fig. 6. I-V Characteristics of fundamental Elements[18]

In other words, a Memristor can act like a two-state switch which be capable of being opened or closed by a voltage application of different polarities.

A Memristor device can be fabricated by having a large of titanium dioxide (TiO2) sandwiched between two point electrodes.

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One part of the TiO2 layer has oxygen vacancies (through doping) that act as a source of positive ions and can liberate electrons when the suitable voltage is employed across it. The position of the boundary amid the doped and the undoped regions can be moved by the voltage applying on the cross of the device which can result in a change in resistance. A simple structure of Memristor with the doped region and equivalent circuit as shown in Fig. 7. Memristor‟s symbolic representation as shown in Fig. 8 .

The two ways that resistance can be varied.

(a) A forward bias voltage will expand the doped region thereby releasing electrons, which will affect larger current flow and consequently smaller resistance value. (b) A reverse bias voltage will decrease the width of the doped region, which will shrink the current flow and consequently larger the resistance value.

D W

ROFF (1-W/D) Doped Undoped RON(W/D)

Fig. 7. A simple structure of Memristor with doped region and equivalent circuit

Low current High Current

+ - - +

Fig. 8.Memristor‟s symbolic representation

The fourth basic element is the Memristor in the circuit theory to facilitate utilization of the operation[5].The electric charge is related to flux is given by the Memristor and is represented as

Dϕ=M*dq (1)

where M represents Memristance or Memristor value(Ω),Φ stands for flux throughout the field of magnet and q denotes electric charge i.e., current is proportional to magnetic field‟s flux which is flown through the Memristor material.

The doped and undoped regions are two regions that are presented in Memristor. The direction of the flow of the current or voltage changes the doped region width (w) and width of the undoped region (L-w).The doped region of the Memristor denotes RON resistance and un doped Memristor stands ROFF resistance completely: the Memristor voltage-current relationship is followed by [9].

v(t)={R 푤(푡) +R (1-푤(푡))}i(t) (2) ON 퐿 OFF 퐿

where, w(t) stands for doped region width ,and TiO2 thickness is represented by L. The doped region width is given as function of time which is given as

w(t)=µ 푅푂푁q(t) (3) v 퐿

-10 2 where µv is the average dopant mobility (~10 cm /s/v). The w(t) is differentiated with respect to time, the rate of change for the doped region width is specified by

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dw (t)= µ 푅푂푁i(t) (4) 푑푡 v 퐿 The hysteretic characteristics of digital Memristor with in dynamic range consisting voltage and current as shown in Fig.9.

60

40 ) A µ ( t n

e 20 r u C 0

-20

-2 -1 0 1 2 3

Voltage(v) Fig. 9. Hysteretic characteristics of digital Memristor within dynamic range consisting voltage and current [4].

III A. Memristor based Implementations:

Memory parallel processing system by the Crossbar have the heterogeneity of the crosspoint switches consisting resistance achieves processing of local information in a state of art Resistive RAM crossbar architecture among cross point selector devices like vertical group accessed transistors[10]

Complementary resistive switches are extremely desirable crosspoint junction elements owing to their innate prevention of sneak path. The complementary resistive switches are having implemented reconfigurable associative capacitive networks in the application of nondestructive capacitive readout procedure[11].

More than ever material implication is used by complementary resistive switching based stateful logic operation to afford the basic logic functionalities are needed to realize logic circuit[14]. Conversely, Passive crossbar arrays are affected by sneak path currents. The two anti-serial Memristive elements which are formed as complementary resistive switches with the state of high resistance and state of low resistance prevents the current of the sneak path [12].

Another implementation of Memristor memory is used to reinstate the current storage technology elements, because of its extreme density, ON /OFF ratio and retainability. The gated or gateless memories are used to built Memristor memory array. Gateless memory cells affected by the sneak path current due to that fabrication of sole Memristor like thin film positioned at every two bars intersection. This influences readout operation. Alternatively, gated array imitate the DRAM architecture. At the larger array density, the current of the sneak path is carried out by the gated devices [13].

The implication gate realization with two Memristors implied to be bi-stable linear devices oblige which facilitate stateful logics Ron and Roff. The series resistance RG is preferred as Ron Vcond).This IMPLY gate

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obliges distinct voltage levels within the circuit and additional circuit components dissipate more power and large computational complexity and need complicated circuitry[14]. The IMPLY logic design as shown in Fig. 10. The design truth table is shown in the table. 1.

Vcond Vset Case M1 M2 M2+ 1 0 0 1 2 0 1 1 3 1 1 1 4 1 0 0

M1 M2 Table.1. Truth table of IMPLY logic[14] RG

Fig. 10. IMPLY logic[14]

Another one is Memristor aided logic(MAGIC) which triumph over the limitations of IMPLY logic as shown in Fig. 11. Stable evaluation is enabled by MAGIC which does not require complicated structure. The stable state is evaluated when the single voltage pulse is applied to the circuit gateway. MAGIC needs Memristors only within the logic gates. The resistance is represented by a logic state in a MAGIC. The gate input and gate output are represented by logic states which necessitate separate Memristors. The initial logic state and final logic state represents the input and output of the Memristor[15].

On the other hand, the programmable resistance of the Memristor is being used to compute Boolean AND/OR functions in Memristor ratioed logic(MRL) as shown in Fig.12.The Memristors utterly used computational elements and not as memory elements. The logical value is represented by a voltage dependable with CMOS ensuring hybrid logic family[16].

in1 in1 in1

in2 in2 out out in2 out

in n in n vo in n (a)n-input OR gate (b)n-input AND gate

Fig. 11. Memristor Aided logic(MAGIC) [15] Fig. 12. Memristor ratioed logic(MRL)[16]

The Applications of Memistors as shown in Fig. 13.

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Memristor based applications

Cross bar array Discrete

Analog Discrete Analog Discrete Chaos circuits Logic operations Neuromorphic Content Addressable Networks Memory Schmitt trigger Digital Gates

Field programmable Non volatile memory Variable gain Reconfigurable analog arrays amplifier Logic circuits

Logic circuits

FIR filters Difference Pattern Physically Unclonable Comparator Recogniser Memories

Cellular neural Image Speech networks

Memristor based sinusoidal Oscillators

Fig. 13.A nomenclature of Applications of Memistors[22], FIR filters, Physically Unclonable memories and Oscillators in [23,24,25].

4.ANALYSIS OF THE HYBRID CMOS LOGIC STYLE WITH MEMRISTOR

The inquiry of Memristor basis design has turned out to be even more significant with the initiation of innovative hybrid CMOS molecular (CMOL) technologies[6].In the midst of the appearance of Memristor-CMOS (MCM) process to facilitate the merging of processing of CMOS amid nanoscale devices with Memristive nature, it turned out to be possible to condense make use of Silicon area. This provided that a promising alternative in the design of MCM fend for circuits[17].This Memristor fend for circuit structures is able to used to put into practice logic functions. The mechanism that had been description can be generally categorized into two class [1].

To begin with, Memristor is capable of extremely easily worn to comprehend the imply function (a≡a+b). A few arbitrary function be able to be uttered as series of imply operations and be capable of put into practice using Memristors. Secondly, Memristors be able to wear in the hybrid mode wherever the Memristors polarities are prearranged such that current moreover flows or not flows all the way through them[1].

Such implementations are able to used to put into practice arbitrary logic functions with the added advantage so as to they can be fabricated at the side of CMOS on top of the same wafer[1]. This major attribute of the CMOS logic style with Memristor is to facilitate it hold the potential of storing a

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considerable amount of chip area made by the silicon to the same extent of the numeral of raise of the inputs [1, 17].

Novel memories basis on distinct technologies, all contribute to devices of variable-resistance which are forced by resistance value same as the storing information is basic principle[6].A numeral of designs based on the hybrid Memristor CMOS circuits had been explored, such as an oscillator, programmable logic, chaotic circuit, crossbar memory etc[1].

The improvement of high dense Memristor devices shared with the suppleness of CMOS in construction complex systems, and the diligence of such 3D structures in designing memory systems, logic circuits and artificial neuromorphic networks[1].

The potential of architecture used to handle the emanate similar to the problem of data-intensive, leakages due to the current, and communication bottleneck. The system is able to offer area enhancement of 2-3 times and reduce the consumption of power. An additional benefit of the hybrid approach with CMOS Memristor is its fabrication compatibility and excessive density[18].

In exacting, the material implication maneuver is able to implement very effortlessly by means of two Memristors and one resistor. A chief drawback of the logic of Memristive implication is the requirement to carry out long-lasting series of operations of stateful logic which in turn to make a specified Boolean function[3,6].A variety of implementation substitutes for Memristors subsist that is to say IMPLY,HYBRID,MAGIC,CROSSBAR,RATIOED LOGIC[20,1,17,18].

IV.A.Comparison of Conventional CMOS circuit design with CMOS like nanoscale design concept:

Replacing existing FETs by polarized Memristors keep up maintain the well-defined CMOS design methodology[19]. It presents the same functionality of circuit which deliberates complementary digital logic encompasses the devices of switching two-state condition. The comparison of CMOS with Memristor as shown in Fig. 14.

The logic function F(x) implementation of circuit

Memristor based CMOS Circuit circuit design Sum of the products in Design vertical chains Vdd

Reversely biased P-MOS Devices Memristors implementing implementingF(x’) F(x’)

F(x) F(x)

N-MOS Devices Forward biased implementingF(x) Memristors implementing F(x) Gnd

Fig. 14. Comparison of CMOS with Memristor[16]

Each function of the logic F(x) implementation in CMOS VLSI circuit design has a precise formation intended for the Field Effect Transistors employed in the circuit.

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Using the same kind of devices with opposite polarization is defined by complementation. The pair of complementary and symmetrical p-types and n-types FETs are used by digital design for logic design implementation in Conventional CMOS and likewise in Memristor-based design uses the complementary and symmetrical pair of Memristor. The overall performance of two state switching Memristor is similar to that of Conventional CMOS[19].

The N-MOS area is used as Forwarding polarized Memristors (FPM) and the P-MOS area is used as Reversely polarized Memristors (RPM). RPMs related to P-type FETs are originally present in ROFF state. The state of ROFF to RON changed by applying negative voltage referred as the closed switch. Similarly, the state of RON to ROFF changed by applying positive voltage referred as an open switch[19].

The pertinent select lines drive the circuits to be contained both Memristors and auxiliary FETs. The CMOS switches remove the current sneak path, in addition, to aid to rectify retrieve operation to various Memristors which are received the identical input bias. The three-terminal device implementation in which the third terminal is the gate terminal of an access transistor used to form the Memristor transistor pair. The selection line drives Memristor transistor pair as shown in Fig. 15.

T1 T1

Sel

Sel

T2 T2 Fig. 15. Three-terminal device implementation in which the third terminal is the gate terminal of an access transistor used to form the Memristor transistor pair. The selection line drives Memristor transistor pair[19].

IV.B.The basic gates that are implemented by Memristors are :

AND gate: Two-input AND gate implementation is shown in the Fig. 16. . When both the inputs are applied by the identical voltages, Memristors does not have voltage and output voltage is same as the input voltage. On the other hand, among the inputs, if one is high and the further one is low, then the memristance of the Memristor having high input voltage i.e., ROFF becomes high and the other one i.e., RON is low gives nearer zero output voltage. By voltage divider rule

푅표푛 ∗푉푕푖푔푕 V = ≈0 out 푅표푛 +푅표푓푓

1 A R

F 2 B

Fig. 16.2-input AND gate

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OR gate: Implementation of two input OR gate is shown in Fig. 17.. When both inputs are the same, similar to AND gate, Memristors have no voltage and the output is equal to input. When one of the inputs is low and other one is high then the memristance of the Memristor having high input voltage i.e., RON becomes low and the other one i.e., ROFF is high gives nearer zero output voltage. By voltage divider rule

푅표푓푓 ∗푉푕푖푔푕 V = ≈1 out 푅표푛 +푅표푓푓

1 A

F 2 B

Fig. 17.2-input OR gate

NAND gate and NOR gate: Cascading the AND gate by Memristors and CMOS inverter forms NAND gate. Similarly, NOR gate is formed by cascading OR gate by Memristors and CMOS inverter. These designs are shown in Fig.18. and Fig.19.

VDD VDD 1 1 R A A F F 2 2 B B

VSS VSS Fig. 18. 2-input AND gate Fig. 19. 2-input OR gate

IV.C.2-to-1 MUX using Memristor and transistor hybrid approach:

INPUT1

MEMRISTOR

OUTPT

MOSFET

MEMRISTOR

SELECT

MOSFET

INPUT2 Fig. 20. 2-to-1 Multiplexer using hybrid CMOS Memristor logic[18]

A 2-to-1 Multiplexer consists of four transistors and NOT gate. So, totally six transistors are used to make 2-to-1 Multiplexer. Although in Memristor transistor hybrid approach, two transistors are used instead of six transistors as shown in Fig. 20. Hence the number of transistors is reduced in this approach. Two transistors, two Memristors, and one diode have incorporated by this design. The

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input 1 and input 2 are the two inputs of the Multiplexer and selection line can be either „0‟ or „1‟. The output gets the value of the input 1 if the selection line is zero and output get the value of the input 2 that one is the value of the selection line. The input 1 and input 2 is separated by the use of a diode in this Multiplexer design[18].

IV.D. Memristor Hybrid logic 4x1 Multiplexer:

S0 S1

I0 I1 I2 I3

F Fig. 21. Memristor Hybrid logic 4x1 Multiplexer[1]

Hybrid Memristor Structures are used to design the 4-to-1 Multiplexer in PLA like structure as shown in Fig. 21. The selection lines S0 and S1 have the four combinations related to four rows in the design. Based on the values of S0 and S1, the eight Memristors in the first four columns are used to set one of the four rows to „1‟. Consider for example, if S0=S1=0, then first and third columns obtains logic value „1‟ which forward biases the two Memristors in the first row ensuing the first row being set to „1‟.Remaining becomes „0‟.The next four columns are used to select one of the four inputs on the consequent line. Here in, the first row will be set to the value of I0, whereas remaining rows will be idle. The last column selects the active low character I0 on the first row and sends it to output F[1].

IV.E. Memory cell design using Ambipolar transistor and Memristor

The applications of the Multiplexer are using in logic designs, bus arbitration, switching networks, etc.

D ` G D G PG=0 S

G D S D G PG S PG PG=1 S

Fig. 22. Ambipolar Transistor symbol[5] Fig. 23. Ambipolar transistor characteristic[5]

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GATE

PG PG

DRAIN

SOURCE Fig. 24. Model of an Ambipolar Transistor[5]

The Ambipolar transistors are also exploited by the hybrid cell. The Ambipolar transistor symbol and characteristics are as shown in Fig. 22. and Fig. 23. The Memristance control and the restriction of the variations for the period of operation of READ and control of bidirectional in the WRITE operation are also done by the Ambipolarity. As a result of altering the gate bias, devices of the ambipolarity be capable of function in the mode of the switch. The Ambipolar transistor consists of four terminals that is gate, source, drain and power gate(PG).When PG is zero, the Ambipolar transistor becomes N- MOS transistor and When PG is one, it becomes P-MOS transistor. The model of an Ambipolar transistor as shown in Fig. 24.

BL BL’

WL

L1

NT1 NT2 OFF ON AMP1 AMP2 A B L2

Fig. 25. Memory cell design using Ambipolar transistor and Memristor[5]

The memory cell designed by the Hybrid Ambipolarity and Memristor approach as shown in Fig. 25.The bit line(BL) and the inverse bit line(BLꞌ) has to be used for sending the data. Despite the fact that the selection of line has been done by the use of word line. The selected memory cell makes the transistors NT1 and NT2 turn ON because of the voltage VDD at the word line(WL). BL and BLꞌ are used to send the data. The transistor NT2 connects BLꞌ and L2. Ambipolar transistor PG is linked to line L2. For that reason, BLꞌ is used for polarity selection. The Ambipolar transistor acts as N-MOS that BLꞌ is „0‟ and current flows from node A to node B. The Ambipolar transistors acts as P-MOS that BLꞌ is „1‟ and flow of the current take place from point B to point A. Thus Memristor writes in both the directions hence WRITE operation is bidirectional because of Ambipolar transistor trait is present[5].

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5.MEMRISTOR MODELS

TABLE-II

Memristor models from Literature survey[21]

Model State Variable(x(t),w(t)) Evolution i(t)-v(t) Relationship Linear ion 푑푤 푅푂푁 푤(푡) 푤(푡) =µv i(t) v(t)={RON +ROFF(1- )}i(t) drift 푑푡 퐷 퐷 퐷

Non linear 푑푤 푅푂푁 푤(푡) 푤(푡) =µv i(t)f(w) v(t)={RON +ROFF(1- )}i(t) ion drift 푑푡 퐷 퐷 퐷 Where f(w)=1-(2푤-1)2p 퐷 f(w)= 1-[푤-stp(-i)]2p 퐷 f(w)=j(1-(w-0.5)2+0.75)p)

Simmons 푑푤 |푖| 푤−푎표푓푓 |푖| 푤 Large system according =fOFF sinh exp(-exp(-( - )- ),i>0 tunneling 푑푡 푖표푓푓 푤푐 푏 푤푐 푖 푎표푛 −푤 |푖| 푤 f sinh( )exp(-exp(-( - )- ),i<0 Barrier ON 푖표푛 푤푐 푏 푤푐

푑푥 Yakopcic =g(v(t))f(x(t)) where a1x(t)sinh(bv(t)), if v(t)>0 푑푡 v(t) p i(t)= a2x(t)sinh(b(v(t)),else Ap(e -e ),if v(t)>vp -v(t) vp A (e -e ),if v(t)

f(x)= exp(-a (x-x )(푥푝 −푧+1),ifx>x p p 1−푧푝 p exp(a (x+x -1)( 푥 ),ifx<1-x n n 1−푥푛 n 1 ,otherwise

TEAM 푑푥 푖(푡) aoff 푥−푎표푓푓 λ=log(R /R ) =koff( -1) exp(-exp( )),if i>ioff off on 푑푡 푖표푓푓 푤푐 휆 푖(푡) 푎푛 −푥 v(t)=R (exp(( )(w-w )))i(t) aon on 푤표푓푓 −푤표푛 on Kon( -1) exp(exp( )),if i

Simplified 푑푤 |푖| 푤−푎표푓푓 |푖| 푤 λ=log(R /R ) =fOFF sinh exp(-exp(-( - )- ),i>0 off on Simmons 푑푡 푖표푓푓 푤푐 푏 푤푐 휆 푖 푎표푛 −푤 |푖| 푤 v(t)=R (exp(( )(w-w )))i(t) on 푤표푓푓 −푤표푛 on Barrier fON sinh( )exp(-exp(-( - )- ),i<0 푖표푛 푤푐 푏 푤푐

2p n b2v(t) Eshraghian f(w)=sf0+sfm(1-(2w-1) ) i(t)=a1w sinh(b1v(t))+a2(e -1) MIM with 푑푤 푣 푣 =f (1- )exp(f(w)Φ (1- 1 − )), threshold 푑푡 on 2훷0 0 2훷0

if v>0, w

if v<0, w>wmax

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6.COMPARISON OF DIFFERENT TECHNOLOGIES

TABLE-III

Comparison of different technologies at 180 nm technology[2,17]

Design Average Delay(ps) PDP(fJ) Transistor count power(µW) C-CMOS Medium Very high Medium High CPL Very high Very low Low Very high TGA Very high Medium High Medium HPSC Medium Medium Low Medium Hybrid Medium Medium Low High GDI Low High Very high Medium Hybrid Medium Low Low Low CMOS/Transmission Hybrid Very low Low Very low Very low CMOS/Memristor

TABLE-IV

Different technologies with area consideration[8,17]

Design Area(µm)2 C-CMOS High CPL Very high Hybrid Medium GDI Medium Hybrid CMOS/Transmission gate Low Hybrid CMOS/Memristor Very low

TABLE-V

Results Summary of simulation for Full Adder in180nm Technology with 1.8V supply in Literature

Design Average Delay(Ps) PDP(fs) Transistor Reference power(µW) count C-CMOS 6.2199 292.1 1.816832 28 [2] CPL 7.71985 183.97 1.42022 32 [2] TGA 8.4719 293.9 2.8989 20 [2] HPSC 6.3798 273.7 1.74615 22 [2] Hybrid 5.978 252.3 1.508 24 [2] GDI 1.0398 367.24 3.8186 20 [8] Hybrid CMOS with 4.1563 224 0.931 16 [2] TGA Hybrid CMOS with 0.3 210 0.63 10 [17] Memristor

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TABLE-VI

Results Summary of simulation of the full adders for comparison of the area in Literature

Design Area(µm2) Reference C-CMOS 127.49 [8] CPL 171.1 [8] Hybrid 106.9 [8] GDI 93.91 [8] Hybrid CMOS/Transmission 89.25 [8] gate Hybrid CMOS/Memristor 38.8 [17]

7.CONCLUSION

The discussion of the survey includes that hybrid CMOS logic style with Memristor is more advantageous by comparison of different conventional CMOS style with constraints of power, area, delay and transistor count. The future applications of Memristor are extended to neural networks and memories. The different designs implemented by the Memristor are dicussed. There is scope to work in research field of facing several challenges by Memristor in implementations of memory designs. REFERENCES:

[1] Gaurav Kumar, Kamalika Datta, “Design of Digital Functional Blocks using Hybrid Memristor Structures” Department of Computer Science & Engineering, National Institute of Technology, IEEE 2015. [2] Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, and Anup Dandapat, “Performance Analysis of a Low-Power High- Speed Hybrid 1-bit Full Adder Circuit” in IEEE Trans on VLSI systems, article has been accepted 2014 1-8. [3] Pankaj Kumar, Rajender Kumar Sharma, “Low voltage high performance hybrid full adder” in International Journal 19 (2016) 559-565 in Elsevier. [4] Phil Knag,Wei Lu and Zhengya Zhang “A Native Stochastic Computing Architecture Enabled by Memristors” in IEEE trans on nanotechnology, vol. 13, No. 2, March 2014 283-293. [5] Pilin Junsangsri and Fabrizio Lombardi, “Design of a Hybrid Memory Cell Using Memristance and Ambipolarity” in IEEE trans on nanotechnology, vol. 12, no. 1, January 2013 71-80. [6] Yuanfan Yang, Jimson Mathew, Rajat Subhra Chakraborty, Marco Ottavi Senior and Dhiraj K. Pradhan “Low Cost Memristor Associative Memory Design for Full and Partial Matching Applications” in IEEE transactions on nanotechnology, vol. 15, no. 3, may 2016 527-538. [7] Reto Zimmermann and Wolfgang Fichtner “Low-Power Logic Styles: CMOS Versus Pass- Transistor Logic” IEEE journal of solid-state circuits, vol. 32, no. 7, July 1997 1-12.

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[8] Vahid Foroutan, Mohammad RezaTaheri , KeivanNavi, Arash Azizi Mazreah “Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style” in Integration, the VLSI journal 47(2014) 48-61 Elsevier. [9] Kamela C. Rahman, Dan Hammerstrom,Yiwei Li, Hongyan Castagnaro, and Marek A. Perkowski, “Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture” in IEEE transactions on nanotechnology, vol. 15, no. 4, July 2016 675-686. [10] Georgios Papandroulidakis, Ioannis Vourkas, Angel Abusleme, ,Georgios Ch. Sirakoulis and Antonio Rubio “Crossbar-Based Memristive Logic-in-Memory Architecture” IEEE trans on nanotech, vol. 16, no. 3, May 2017 1-11 . [11] Lutz Nielen, Anne Siemon, Stefan Tappertzhofen, Rainer Waser, Stephan Menzel,and Eike Linn, “Study of Memristive Associative Capacitive Networks for CAM Applications” IEEE journal on emerging and selected topics in circuits and systems 2015 1-9. [12] Yuanfan Yang, Jimson Mathew, Salvatore Pontarelli,Marco Ottavi, and Dhiraj K. Pradhan, “Complementary Resistive Switch-Based Arithmetic Logic Implementations Using Material Implication” IEEE trans on nanotech, vol. 15, no. 1, Jan 2016 1-14. [13] Mohammed Affan Zidan, Hesham Omran, Ahmed Sultan, Hossam A. H. Fahmy, and Khaled N. Salama “Compensated Readout for High-Density MOS-Gated Memristor Crossbar Array” in IEEE trans on nanotech, vol. 14, no. 1, Jan 2015 3-6. [14] Hadi Owlia n, ParvizKeshavarzi, Abdalhossein Rezai “A novel digital logic implementation approach on nano crossbar arrays using memristor-based multiplexers” in Microelectronics Journal 45 (2014) 597-603 in Elsevier [15] Nishil Talati, Saransh Gupta, Pravin Mane, and Shahar Kvatinsky, “Logic Design Within Memristive Memories Using Memristor- Aided loGIC (MAGIC)” in IEEE transactions on nanotechnology, vol. 15, no. 4, July 2016 635-650. [16] Shahar Kvatinsky, Nimrod Wald, Guy Satat, Eby G. Friedman, Avinoam Kolodny, and Uri C. Weiser, “MRL - Memristor Ratioed Logic for Hybrid CMOS-Memristor Circuits” in IEEE transactions on nanotechnology, 2013 . [17] Kyoungrok Cho n, Sang-JinLee, Kamran E shraghian “Memristor- CMOS logic and digital computational component” in Microelectronics Journal 46 (2015) 214-220 in Elsevier. [18] M. Hassan Aslam, Umer Farooq,M. Naeem Awais, M. Khurram Bhatti,Naeem Shehzad, Arab J “Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor- Transistor Hybrid FPGA Architecture” in research article - computer engineering and computer science Sci Eng 41(2016) 3035-3049 springer. [19] Ioannis Vourkas, GeorgiosCh.Sirakoulis “Memristor-based combinational circuits: A design methodology for encoders/decoders” in Microelectronics Journal 45 (2014) 59-70 in Elsevier. [20] Ligang Gao, Fabien Alibart, and Dmitri B. Strukov “Programmable CMOS/Memristor Threshold Logic” in IEEE transactions on nanotechnology, vol. 12, no. 2, March 2013 115-119. [21] Fernando Garc´ıa-Redondo, Marisa L´opez-Vallejo, and Pablo Ituero “Building

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Memristor Applications: From Device Model to Circuit Design” IEEE transactions on nanotechnology, vol. 13, no. 6, november 2014 1154-1162. [21] Akshay Kumar Maan, Deepthi Anirudhan Jayadevi, and Alex Pappachen James “A Survey of Memristive Threshold Logic Circuits” in IEEE transactions on neural networks an learning systems ,Volume: 28, Aug. 2017 1-13. A. Talukdar , A.G.Radwan , K.N.Salama “Non linear dynamics of memristor based 3rdorder oscillatory system” in Microelectronics Journal 43 (2012) 169-175 in Elsevier. [22] Jimson Mathewb, Rajat Subhra Chakraborty, Durga Prasad Sahoo , YuanfanYang DhirajK.Pradhan “A novel memristor based physically unclonable function” in Integration,the VLSI journal 51 (2015) 37-45 in Elsevier. [23] Seyedeh-Nafiseh Mirebrahimi,Farshad Merrikh-Bayat “Programmable discrete-time type I and type II FIR filter design on the memristor crossbar structure” in Analog Integr Circ Sig Process (2014) 79 529-541 in springer

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