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Copyright by Lauren Elise Guckert 2016 Copyright by Lauren Elise Guckert 2016 The Dissertation Committee for Lauren Elise Guckert Certifies that this is the approved version of the following dissertation: MEMRISTOR-BASED ARITHMETIC UNITS Committee: Earl Swartzlander Jr., Supervisor Lizy John Jack Lee Michael Schulte Nur Touba MEMRISTOR-BASED ARITHMETIC UNITS by Lauren Elise Guckert, B.S.E.E.; M.S.E Dissertation Presented to the Faculty of the Graduate School of The University of Texas at Austin in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy The University of Texas at Austin December 2016 Dedication First, to my parents, Toni and Thomas Guckert, for their unwavering encouragement, understanding, and love throughout my life. Secondly, to my sister, who taught me to always strive for more but never forget to find a balance. To my friends and colleagues, for the laugh, memories, and reality checks. To Professor Swartzlander Jr., for his guidance, advice, and constant support throughout this whole journey. To Stafford, for getting me through the lowest lows and making a point to celebrate the highest highs. And last but not least, to my cat Winston, for always being there and never telling me I’m wrong. I wouldn’t be here without any of you. MEMRISTOR-BASED ARITHMETIC UNITS Lauren Elise Guckert, Ph.D. The University of Texas at Austin, 2016 Supervisor: Earl Swartzlander The modern computer architecture community is continually pushing the limits of performance, speed, and efficiency. Recently, the ability to satisfy this endeavor with popular CMOS technology has proved difficult, and in many settings, impossible. The community has begun to explore alternatives to standard practices, researching new components such as nanoscale structures. Additional research has applied these new components and their characteristics to rethink the architecture of the latest technology, moving away from the Von Neumann architecture. A leading technology in this effort is the memristor. Memristors are a new class of circuit elements that have the ability to change their resistance value while retaining knowledge of their current and past resistances. Their small form factor, high density, and fast switching times have sparked research in their applications in modern memory hierarchies. However, their utility in arithmetic has been minimally explored. This dissertation describes the prior work in the exploration of memristor technology, fabrication, modeling, and application, followed by the completed research performed in the design and implementation of arithmetic units using memristors. v Implementations of popular adders, multipliers, and dividers in the context of memristors are designed using four approaches: IMPLY, hybrid-CMOS, threshold gates, and MAD gates. Each of these approaches has different tradeoffs and benefits for memristor-based design. Although the first three approaches have been defined in prior work, MAD gates are a novel application for memristors proposed that offer lower power, area, and delay as compared to prior approaches. This work explores these benefits for arithmetic unit design. The details of each designs, simulation results, and analyses in terms of complexity and delay and power are presented. For arithmetic units which have been designed or presented in prior work, this research improves upon the design in each metric. Many of the designs are transformed and pipelined to leverage memristor characteristics and the various approaches rather than traditional CMOS and this is discussed in detail. Overall, the proposed designs offer significant improvements to traditional CMOS designs, motivating the effort to continue exploring memristors and their application to modern computer architecture design. vi Table of Contents List of Tables ........................................................................................................ xii List of Figures ...................................................................................................... xvi INTRODUCTION..................................................................................................1 Simulation Methodology .........................................................................................4 PRIOR WORK .......................................................................................................6 Memristor Gate Implementations ............................................................................7 IMPLY Approach ...........................................................................................7 Hybrid-CMOS Approach ..............................................................................10 Threshold Gate Approach .............................................................................13 Threshold Gates implemented with GOTO pairs ................................13 Threshold Gates implemented with CSTG gates .................................14 Alternative Approaches ................................................................................15 Ripple Carry Adders ..............................................................................................17 Prior IMPLY Ripple Carry Adders ...............................................................18 Prior Hybrid-CMOS Ripple Carry Adders ...................................................18 Prior Threshold Gate Ripple Carry Adders ..................................................19 Carry Select Adders ...............................................................................................20 Conditional Sum Adders ........................................................................................21 Carry Lookahead Adders .......................................................................................23 Memristor-Based Multipliers .................................................................................25 Shift And Add Multipliers ............................................................................25 Array Multipliers ..........................................................................................26 Dadda Multipliers .........................................................................................27 Memristor-Based Dividers .....................................................................................29 Binary Non-Restoring Dividers ....................................................................29 vii SRT Dividers ................................................................................................30 Goldschmidt Dividers ...................................................................................32 MAD GATES ........................................................................................................34 Gate Structure ........................................................................................................35 Full Adder ..............................................................................................................41 IMPROVED AND OPTIMIZED ADDER DESIGNS ......................................45 Ripple Carry Adders ..............................................................................................46 IMPLY Ripple Carry Adder .........................................................................46 Hybrid-CMOS Ripple Carry Adder ..............................................................50 Threshold Gate Ripple Carry Adder .............................................................54 MAD Gate Ripple Carry Adder ....................................................................55 Ripple Carry Adder Analysis and Comparison ............................................60 Carry Select Adders ...............................................................................................63 IMPLY Carry Select Adder ..........................................................................63 Hybrid-CMOS Carry Select Adder ...............................................................69 Threshold Gate Carry Select Adder ..............................................................72 MAD Gate Carry Select Adder .....................................................................73 Carry Select Adder Analysis and Comparison .............................................77 Conditional Sum Adders ........................................................................................81 IMPLY Conditional Sum Adder ...................................................................81 Hybrid-CMOS Conditional Sum Adder .......................................................85 Threshold Gate Conditional Sum Adder.......................................................86 MAD Gate Conditional Sum Adder .............................................................87 Conditional Sum Adder Analysis and Comparison ......................................91 Carry Lookahead Adders .......................................................................................94 IMPLY Carry Lookahead Adder ..................................................................94 Hybrid-CMOS Carry Lookahead Adder .....................................................100 Threshold Gate Carry Lookahead Adder ....................................................103 viii MAD Gate Carry Lookahead Adder ...........................................................106 Carry Lookahead Adder Analysis and Comparison ...................................113 IMPROVED AND OPTIMIZED MULTIPLIER DESIGNS .........................116 Shift And Add Multipliers ...................................................................................117
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