288 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL.37, NO. 2, APRIL 1990

A Versatile, Programmable Control and Data Acquisition System for Complex Integrated Circuits

Frederick A. Kirsten and Carl Haber Electronics Division and Physics Division Lawrence Berkeley Laboratory1 Berkeley, California, 94720

the SVX chip[2], but can be programmed for the testing of Abstract other complex ICs.

We describe a versatile, user-friendly hard- The SVX chip was developed for the readout of wadsoftware system. It has been designed for facilitating the silicon microstrip detectors. It contains 128 channels of testing, characterization and application of complex integrated analog and digital processing. This IC has gone through circuits intended for high- and low-energy physics several prototype iterations in the course of its development instrumentation. The system consists of two CAMAC and in the course of understanding its proper application in the modules and a program generation and data analysis facility acquisition of data from microstrip detectors. The hosted by a VAX computer. hardware/software system discussed in this paper was a vital tool in this learning process.

I. IhTRODUCrION Commercial instruments useful in IC testing are available, and we use some of these in part of our testing A. Motivation program. However, we found it advantageous in this case to The inexorable trend in instrumentation for develop a system that handles both digital and analog signals high-energy physics detectors is toward the use of more and that operates in an environment that is familiar to us--e.g., sophisticated data acquisition systems using more CAMAC, VAX computers, software support packages, etc. sophisticated components. Recent years have seen the The transport of this system to accelerator-based activities- introduction of complex, custom-designed integrated circuits beam tests--is thereby easier. (ICs) to accomplish the requirements of this class of insrrumentation--e.g., higher speeds of operation, reduced volume and higher levels of circuit and logical complexity. B. The Basic System The system is shown schematically in Figure 1. The Many physics laboratories are acquiring the tools basic parts are two CAMAC modules-the SRS (SVX Readout necessary to design their own ICs, which are often prototyped Sequencer module) and the SDA (SVX Data Acquisition in small quantities via foundries, such as MOSIS[l], that module)--and a programming and data analysis environment specialize in prototype work. The testing of the prototype ICs hosted by a VAX computer[3]. is a problem that automatically arises in this situation. Many CA~ACcrate ICs designed in this way have very special characteristics, A b b tailored explicitly to the application, and require special testing procedures. These procedures are often not available at the silicon foundry, and must therefore be supplied by the designer.

Our approach to this situation has been to design and implement a versatile, programmable hardware/software system for the testing, characterization and application of such complex integrated circuits. This system was initially designed to accomplish the testing of a particular IC design,

1 This work was supponed by the Director, Office of Energy Research, Fig. 1 Block diagram of the system. Office of High Energy and Nuclear Physics, Division of High Energy Physics of the US. Department of Energy under contract No. DEAC03-76SFO0098.

U.S. Government work not protected by U.S. Copyright 289

The SDA module acquires analog and digital data As shown in Figure 2, 15 of these bits--the four Command bits from the device under test and stores it in local memory. The and the 11 Data bits--are fed back to the sequencer; in SRS module contains a programmable sequencer that essence, it controls itself. Another three bits (the h4UX develops patterns of signals for controlling the device under Control bits) are used to select the external signal used for the test. Programs for the sequencer are developed in the VAX Branch Condition. In addition, a single bit is used to select and downloaded into the SRS via CAMAC. The SRS one of two 2910 cycle lengths--e.g., 100 nSec or 300 nsw. executes a downloaded program to generate sequences of digital signals that controls the device to be operated (or The important feature here is that the sequence of tested). This typically results in the generation of analog Memory Addresses also controls the pattern of vectors that are and/or digital data by the device, which is acquired by the available to exercise the device under test As shown in SDA module and stored in its local memory. The VAX then Figure 2, these vectors include 22 bits of digital signals, and analyzes the acquired data and makes the results available to an analog signal from a 12-bit DAC. the user. Additionally, five bits are used for ancillary tasks: In a simple application, the processes are one to generate a scope trigger that is synchronized with the synchronized as follows. The VAX commands the SRS to program; and four to synchronize the processes in the SDA start its program. At the appropriate spot in the program, the module. These include: trigger the ADC; store ADC data; SRS sets the SDA’s LAM. Upon seeing the LAM, the VAX store digital data from the device under test; and set SDA acquires the SDA data, and resets the LAM. The SRS senses LAM. the reset condition of the LAM, and starts another major cycle of the program. The 2910’s program--previously downloaded into the SRS memories--can be started from the front panel or by CAh4AC command. The 2910 then produces a series of 2. HARDWAREIMPLEME~TATION memory addresses; the series is governed by the instructions the 2910 is given from the instruction fields of the addressed A. The SRS Module memory locations. The bits contained in the other memory A block diagram of the SRS module is in Figure 2. fields generate a series of vectors that are output to the device The heart of the module is the 2910 Micro Sequencer[4]. The under test. 2910 has a repertoire of 16 instructions, which are exercised by the 4-bit Command field. Included are instructions such as The SRS includes a socket for a single-chip Branch on Condition, for sensing the state of external signals microprocessor, which would enable stand-alone operation of (e.g., state of the SDA’s LAM). It also accepts a 12-bit Data the module. field (only 11 are used), which contains jump addresses, or values to load into an execution (loop) counter.

6ra hSlgnals B. The SDA Module 3!ranch Condltlon A block diagram of the SDA module is in Figure 3. It contains an analog and a digital data acquisition channel; each 2910 -2 Command9 Mlcro- Address has a 2048-word memory for accumulating results. ’ Seauencer I _-I U Data- I g I1 t The ADC Span is typically adjusted so the 8-bit flash MEMORY 1 EMORY 2 MEMORYI 2915 3 ADC[5]has a span of 0 to -2.048 V (8 mV/least count). The I’ ’ Clock Gen. 16 preceding amplifier stage has an adjustable offset and I 6’ 16’ selectable gains of 1,2 4 and 8, to match the span of the ADC to the appropriate segment of the input voltage range. The digital outputs of the ADC are stored in the 8-bit Analog Data Memory. A 0-5 volt dc Calibration source and a front panel display of the ADC digital output are available for calibrating the analog channel.

Fig. 2. A block diagram of the SRS module. A 16-bit Digital Data Memory can be wired to store 16-bit digital input data, or (as in the SVX application), two The basic job of the sequencer is to generate a successive 8-bit fields per readout cycle. The stmbing of the sequence of Memory Addresses which are applied to a 48-bit, two memories, the advancement of the memory address 2096-word memory (implemented as three 16-bit memories). register (common to both analog and digital memories), and ~

290 the setting of the LAM flip-flop are all controlled by signals circuit testing process. An important task of the software generated by the program running in the SRS. These signals system is to provide a user-biendly environment for the are carried between the modules by an auxiliary cable. development of the microcode. The program of microcode is accessed by a user in an expanded format, which remains The memories, memory address register, the LAM, close to the compiled form, via a Screen editor. An example and other features are accessible via CAMAC. of such a program is in Figure 4. Lines beginning with (!) or beginning and ending with (') are comments.

The first three lines define values to be loaded into the DAC registers. The next five lines remind the programmer of the significance of the columns below. The following lines define the microcode program. This program is also shown in flow chart form in Figure 5. It starts by loading an ID number into the SVX chip (lines 0 through 5). Lines 6 through 30 contain the microcode to exercise the

CALIBRATE VOLTAGE charge integration and sample-and-hold operations performed 7%" by the SVX chip. The program loops through this exercise continually unless the branch condition specified by the field (CC = 03 on line 31) is true. If it is true, the program branches to a readout loop in which 128 values are read from the SVX chip. Fig. 3. A block diagram of the SDA module. The branch condition 03 is controlled by the state of the LAM in the SDA module. It thereby synchronizes the two C. Hardware Per3'onnance. main processes which are the microcode program operating in The hardware system has been used primarily with a the SRS, and a process operating in the host computer which 10 MHz clock frequency. It can generate patterns and acquire is acquiring data from the SDA. The broken lines are the digital and analog data at this rate. The limitations are in the synchronization points where the two processes communicate. 2910 sequencer and the 2925 "smart clock." Versions of the Other CC codes can utilize other signals as branch conditions, 2910 that work up to 30 MHz are available, but have not been including four sources whose state can be controlled via tried. CAMAC.

The last number in each line, labelled 'CLK,' sets the 3. SOETWARE cycle length for that line. A '1' chooses the longer cycle length; a '0' choose the shorter. Typically, the shorter cycle is set to be 100 ns. In this section we describe the software and programming tools which have been developed for use with the SRS and SDA module set. For our application, which is a B. Programming Environment "test bench" for silicon strip detector readout using the SVX The code used to control and program the SRS and chip, we created both compilation and code management SDA modules executes on a VAX 730 and is written in VAX- capabilities as well as a flexible data acquisition and analysis -FORTRAN . Most user input is handled with the CDF system for the data generated by the SVX chip. The basic (Collider Detector at Fermilab) standard user interface configuration of our system is a menu driven package of package, UIPACK [6]. The primitive routines include a routines spanning the basic functions of the modules (i.e., compiler for the microcode and basic CAMAC functions for download, read registers etc.) and high level, data acquisition the SRS and SDA modules. and file manipulation routines. The microcode program which is downloaded into the SRS is stored on disk as text files in the form shown in A. Microcode Figure 4. The code is accessed via routines which spawn As shown in Figure 2, the three physical memories in screen editing sessions from menu selections. Utilities exist the SRS contain 48-bit words of "microcode." The microcode for deletion, copy, rename, directory and so forth. Other has two functions: 1) to control the microsequencer itself; and menu selections provide access to the SRS and SDA functions

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...dNmW vvvz ...... 2bdZ -. -. 292 basic operations, we have developed more sophisticated, options depending upon the outcome of various tests. The menu-selectable procedures combining downloads, repetitive data from the dice are acquired by the SDA module and data acquisition cycles, data analysis, and display. An analyzed by the VAX. example is a procedure which measures charge gain and electronic noise on all channels of a system containing several SVX chips. C. Other Users A number of sets of SRS and SDA modules have An important aspect of software systems which been built and are operational. Besides four sets at LBL, there interface to complex integrated circuits through modules like are sets in use at UC Davis, Camegie Mellon University, the the SRS and SDA must be the ability to acquire, store, University of Oklahoma, Fermilab, I"-Pisa, CERN, and analyze, and display rather large quantities of data. In the case the Aerospace Corporation. of the SVX chip for example, each readout cycle generates COUNllNCROOY 128 words of address and 128 words of digitized analog data. ap Generally, the user will have some statistical procedure or some function of the acquired data which he will want to consider. The power of a system which combines a user programmable computer (the VAX in this case) interfaced to the SRS and SDA module set is the ease and flexibility with which specific analyses may be performed on the data. Typically, commercially available digital pattern generators do not offer this capability.

4. APPLICATION

In this section we describe two higher level Fig. 6 Beam test set-up. applications of the SRS and SDA system to studies made with the SVX chip. These are given as examples of the types of REFERENCES procedures which may be performed by this system. 1. MOSIS is the Metal Oxide Semiconductor Implementation System operated by the University of Southern California, A. SVX Beam Test Matina del Rey, CA 90292. A beam test of silicon strip detectors bonded to SVX chips was done at Fermilab. The configuration is shown in 2. S.A. Kleinfelder, R.P. Ely, Jr., "The SVX 128 Channel Figure 6. In this test the SRS controlled the SVX chips. The Parallel Analog Signal Acquisition Integrated Circuits," This SRS's microcode program was synchronized to a readout issue of IEEE Trans. Nucl. Sci. trigger created by the coincidence of a set of scintillation counters in the beam. Data were acquired by the SDA. read 3. The programming environment has also been installed on a out by a VAX, analyzed, and written to disk files. Macintosh computer by D.Pellet and J. Reid at the University of California at Davis and LBL.

B. SVX Production Wafer Testing 4. The 2910 Microsequencer and the 2915 Clock Controller A production run of the SVX chip has been made. It used in the SVX are manufactured by Advanced mcro consists of 40 wafers, each containing 110 individual die. A Devices, Sunnyvale, CA. Other sources are available. probe station, outfitted with a custom probe card, and controlled by the VAX via CAMAC and GPIB is used to step 5. The ADC used in the SDA is an 8-bit flash ADC, the the probe card to each die on the wafer. Each die is checked TDC1048 manufactured by TRW LSI products, Inc., La Jolla, for proper power consumption, gain, noise, data sparsification, CA. digital function, and interchip communication features. The good dice are marked so they can be identified after the wafer 6. D.A. Quarrie, UIPACK: CDF User Interface Package, is sawed. Fermilab Publication CDF-372 (1986).

In this application, the SRS executes a complex set of patterns, and passes through a number of conditional branch