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CS 152 Computer Architecture and Engineering Lecture 10 Multicycle Controller Design

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Recap CS 152 ° Partition datapath into equal size chunks to minimize Computer Architecture and Engineering cycle time Lecture 10 • ~10 levels of logic between latches Multicycle Controller Design ° Follow same 5-step method for designing “real” processor (Continued) ° Control is specified by finite state digram September 29, 1999 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/ CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.1 Lec10.2 Overview of Control Recap: Controller Design ° Control may be designed using one of several initial ° The state digrams that arise define the controller for representations. The choice of sequence control, and how logic is an instruction set processor are highly structured represented, can then be determined independently; the control can then be implemented with one of several methods using a ° Use this structure to construct a simple structured logic technique. “microsequencer” Initial Representation Finite State Diagram Microprogram ° Control reduces to programming this very simple device • microprogramming Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs sequencer datapath control control Logic Representation Logic Equations Truth Tables microinstruction (µ) micro-PC Implementation PLA ROM sequencer Technique “hardwired control” “microprogrammed control” CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.3 Lec10.4 Recap: Microprogram Control Specification The Big Picture: Where are We Now? µPC Taken Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst ° The Five Classic Components of a Computer 0000 ? inc 1 0001 0 load 0001 1 inc Processor 0010 x zero 1 1 Input BEQ 0011 x zero 1 0 Control Memory R: 0100 x inc 0 1 fun 1 0101 x zero 1 0 0 1 1 0110 x inc 0 0 or 1 ORi: Datapath Output 0111 x zero 1 0 0 1 0 1000 x inc 1 0 add 1 LW: 1001 x inc 1 0 1 ° Today’s Topics: 1010 x zero 1 0 1 1 0 • Microprogramed control SW: 1011 x inc 1 0 add 1 1100 x zero 1 0 0 1 • Administrivia • Microprogram it yourself • Exceptions CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.5 Lec10.6 How Effectively are we utilizing our hardware? “Princeton” Organization IR <- Mem[PC] A-Bus B Bus A <- R[rs]; B<– R[rt] Reg A next P IR S Mem File PC C ZX SX B W-Bus S <– A + B S <– A or ZX S <– A + SX S <– A + SX M <– Mem[S] Mem[S] <- B ° Single memory for instruction and data access • memory utilization -> 1.3/4.8 R[rd] <– S; R[rt] <– S; R[rd] <– M; PC <– PC+4; PC <– PC+4; PC <– PC+4; PC <– PC+4; PC < PC+4; PC < PC+SX; ° Sometimes, muxes replaced with tri-state buses • Difference often depends on whether buses are internal to chip ° Example: memory is used twice, at different times (muxes) or external (tri-state) • Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 ° In this case our state diagram does not change • if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 • several additional control signals ° We could reduce HW without hurting performance • must ensure each bus is only driven by one source on each cycle CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99• extra control ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.7 Lec10.8 Alternative datapath (book): Multiple Cycle Datapath Our Controller FSM Spec ° Miminizes Hardware: 1 memory, 1 adder IR <= MEM[PC] PC <= PC + 4 “instruction fetch” PCWr PCWrCond PCSrc BrWr 0000 Zero IorD MemWr IRWr RegDst RegWr ALUSelA Mux 1 Target 32 A <= R[rs] “decode” 32 B <= R[rt] PC 0 0001 Mux 0 32 Instruction Reg Rs Zero Mux 0 Ra ALU Out ALU LW BEQ 32 RAdr Rt 5 32 ALU R-type ORi SW 32 Rb busA 1 32 Ideal 5 Reg File 32 1 Mux 0 Memory Rt 4 0 S <= A fun B S <= A op ZX S <= A + SX S <= A + SX S <= A - B WrAdr 32 Rw 32 1 Execute 0100 0110 1000 1011 0010 32 Din Dout Rd busW busB 32 32 1 32 2 1 Mux 0 3 ALU Equal ~Equal << 2 Control M <= MEM[S] MEM[S] <= B 1001 PC <= PC + Memory 1100 SX || 00 0011 Imm Extend R[rd] <= S R[rt] <= S R[rt] <= M 16 32 ALUOp ExtOp MemtoReg ALUSelB 0101 0111 1010 Write-back CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.9 Lec10.10 Microprogramming (Maurice Wilkes) Sequencer-based control unit ° Control is the hard part of processor design Control Logic Multicycle ° Datapath is fairly regular and well-organized ° Memory is highly regular Datapath ° Control is irregular and global Outputs Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer Inputs Types of “branching” 1 operations • Set state to 0 Microarchitecture: • Dispatch (state 1) State Reg • Use incremented state -- Logical structure and functional capabilities of the hardware as Adder seen by the microprogrammer number Historical Note: Address Select Logic IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance Opcode CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.11 Lec10.12 “Macroinstruction” Interpretation Variations on Microprogramming User program ° “Horizontal” Microcode Main ADD plus Data – control field for each control point in the machine Memory SUB AND this can change! µseq µaddr A-mux B-mux bus enables register enables . ° “Vertical” Microcode . – compact microinstruction format for each class of DATA one of these is mapped into one microoperation of these – local decode to generate all control points execution unit branch: µseq-op µadd execute: ALU-op A,B,R CPU control AND microsequence memory: mem-op S, D memory e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Horizontal Save Answer(s) Vertical CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.13 Lec10.14 Extreme Horizontal More Vertical Format 3 1 src dst other control fields next states inputs input . N3 N2 N1 N0 select D D 1 bit for each loadable register Incr PC E E MUX enbMAR ALU control C C enbAC . Some of these may have nothing to do with registers! Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at Multiformat Microcode: the same time. 13 6 Makes sense to encode fields to save ROM space 0 cond next address Branch Jump Example: mem_to_reg and ALU_to_reg should never happen simultaneously; 13 3 3 => encode in single bit which is decoded rather than two separate bits 1 dst src alu Register Xfer Operation NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction D D E E C C CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.15 Lec10.16 Hybrid Control Vax Microinstructions VAX Microarchitecture: Not all critical control information is derived from control logic 96 bit control store, 30 fields, 4096 µinstructions for VAX ISA encodes concurrently executable "microoperations" E.g., Instruction Register (IR) contains useful control information, 95 87 84 68 65 63 11 0 such as register sources, destinations, opcodes, etc. USHF UALU USUB UJMP 001 = left 010 = A-B-1 00 = Nop enable 010 = right 100 = A+B+1 01 = CALL signals R R R Jump . 10 = RTN Address from S S D . control 1 2 Register . ALU Subroutine File 101 = left3 Control Control D D D E E E ALU Shifter C C C Control µ IR op rs1 rs2 rd Current intel architecture: 80-bit microcode, 8192 instructions to control CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.17 Lec10.18 Horizontal vs. Vertical Microprogramming Administration NOTE: previous organization is not TRUE horizontal microprogramming; ° Midterm on Wednesday (10/6) from 5:30 - 8:30 in register decoders give flavor of encoded microoperations 277 Cory Hall ° No class on next Wednesday Most microprogramming-based controllers vary between: ° Pizza and Refreshments afterwards at LaVal’s on Euclid horizontal organization (1 control bit per control point) • I’ll Buy the pizza vertical organization (fields encoded in the control memory and • LaVal’s has an interesting history must be decoded to control something) ° Review Session: • Sunday (10/3), 7:00 PM in 306 Soda Horizontal Vertical + more control over the potential + easier to program, not very parallelism of operations in the different from programming datapath a RISC machine in assembly language - uses up lots of control store - extra level of decoding may slow the machine down CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.19 Lec10.20 Designing a Microinstruction Set 1&2) Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg. is written 1) Start with list of control signals MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd 2) Group signals together that make sense (vs.
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