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Home , Datapath, Microsequencer

Recap

CS 152 ° Partition into equal size chunks to minimize Architecture and Engineering cycle time Lecture 10 • ~10 levels of logic between latches

Multicycle Controller Design ° Follow same 5-step method for designing “real” (Continued) ° Control is specified by finite state digram

September 29, 1999 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.1 Lec10.2

Overview of Control Recap: Controller Design ° Control may be designed using one of several initial ° The state digrams that arise define the controller for representations. The choice of sequence control, and how logic is an instruction set processor are highly structured represented, can then be determined independently; the control can then be implemented with one of several methods using a ° Use this structure to construct a simple structured logic technique. “” Initial Representation Finite State Diagram Microprogram ° Control reduces to programming this very simple device • microprogramming Sequencing Control Explicit Next State Microprogram Function + Dispatch ROMs sequencer datapath control control

Logic Representation Logic Equations Truth Tables microinstruction (µ)

micro-PC Implementation PLA ROM sequencer Technique “hardwired control” “microprogrammed control” CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.3 Lec10.4 Recap: Microprogram Control Specification The Big Picture: Where are We Now?

µPC Taken Next IR PC Ops Exec Mem Write-Back en sel A B Ex Sr ALU S R W M M-R Wr Dst ° The Five Classic Components of a Computer 0000 ? inc 1 0001 0 load 0001 1 inc Processor 0010 x zero 1 1 Input BEQ 0011 x zero 1 0 Control Memory R: 0100 x inc 0 1 fun 1 0101 x zero 1 0 0 1 1 0110 x inc 0 0 or 1 ORi: Datapath Output 0111 x zero 1 0 0 1 0 1000 x inc 1 0 add 1 LW: 1001 x inc 1 0 1 ° Today’s Topics: 1010 x zero 1 0 1 1 0 • Microprogramed control SW: 1011 x inc 1 0 add 1 1100 x zero 1 0 0 1 • Administrivia • Microprogram it yourself • Exceptions

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.5 Lec10.6

How Effectively are we utilizing our hardware? “Princeton” Organization

IR <- Mem[PC] A-Bus B Bus A <- R[rs]; B<– R[rt] Reg A next P IR S Mem File PC C ZX SX B W-Bus S <– A + B S <– A or ZX S <– A + SX S <– A + SX

M <– Mem[S] Mem[S] <- B ° Single memory for instruction and data access • memory utilization -> 1.3/4.8 R[rd] <– S; R[rt] <– S; R[rd] <– M; PC <– PC+4; PC <– PC+4; PC <– PC+4; PC <– PC+4; PC < PC+4; PC < PC+SX; ° Sometimes, muxes replaced with tri-state buses • Difference often depends on whether buses are internal to chip ° Example: memory is used twice, at different times (muxes) or external (tri-state) • Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 ° In this case our state diagram does not change • if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 • several additional control signals ° We could reduce HW without hurting performance • must ensure each bus is only driven by one source on each cycle CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99• extra control ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.7 Lec10.8 Alternative datapath (book): Multiple Cycle Datapath Our Controller FSM Spec

° Miminizes Hardware: 1 memory, 1 IR <= MEM[PC] PC <= PC + 4 “instruction fetch” PCWr PCWrCond PCSrc BrWr 0000 Zero

IorD MemWr IRWr RegDst RegWr ALUSelA Mux 1 Target 32 A <= R[rs] “decode” 32 B <= R[rt] PC 0 0001

Mux 0 32 Reg Instruction Rs Zero

Mux 0 Ra ALU Out LW BEQ 32 RAdr Rt 5 32 ALU R-type ORi SW 32 Rb busA 1 32 Ideal 5 Reg File 32 1 Mux 0 Memory Rt 4 0 S <= A fun B S <= A op ZX S <= A + SX S <= A + SX S <= A - B WrAdr 32 Rw 32

1 Execute 0100 0110 1000 1011 0010 32 Din Dout Rd busW busB 32 32 1 32 2 1 Mux 0 3 ALU Equal ~Equal << 2 Control M <= MEM[S] MEM[S] <= B 1001 PC <= PC + Memory 1100 SX || 00 0011 Imm Extend R[rd] <= S R[rt] <= S R[rt] <= M 16 32 ALUOp ExtOp MemtoReg ALUSelB 0101 0111 1010 Write-back CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.9 Lec10.10

Microprogramming (Maurice Wilkes) Sequencer-based

° Control is the hard part of Control Logic Multicycle ° Datapath is fairly regular and well-organized ° Memory is highly regular Datapath ° Control is irregular and global Outputs

Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer Inputs Types of “branching” 1 operations • Set state to 0 : • Dispatch (state 1) State Reg • Use incremented state -- Logical structure and functional capabilities of the hardware as Adder seen by the microprogrammer number

Historical Note: Address Select Logic IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance Opcode CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.11 Lec10.12 “Macroinstruction” Interpretation Variations on Microprogramming

User program ° “Horizontal” Main ADD plus Data – control field for each control point in the machine Memory SUB AND this can change! µseq µaddr A-mux B-mux bus enables register enables . . ° “Vertical” Microcode . – compact microinstruction format for each class of DATA one of these is mapped into one microoperation of these – local decode to generate all control points branch: µseq-op µadd execute: ALU-op A,B,R CPU control AND microsequence memory: mem-op S, D memory e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Horizontal Save Answer(s) Vertical

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.13 Lec10.14

Extreme Horizontal More Vertical Format 3 1 src dst other control fields next states inputs . . . N3 N2 input N1 N0 select D D 1 bit for each loadable register Incr PC E E MUX enbMAR ALU control C C enbAC . . . Some of these may have nothing to do with registers! Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at Multiformat Microcode: the same time. 13 6 Makes sense to encode fields to save ROM space 0 cond next address Branch Jump

Example: mem_to_reg and ALU_to_reg should never happen simultaneously; 13 3 3 => encode in single bit which is decoded rather than two separate bits 1 dst src alu Register Xfer Operation NOTE: the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction D D E E C C CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.15 Lec10.16 Hybrid Control Vax Microinstructions VAX Microarchitecture:

Not all critical control information is derived from control logic 96 bit , 30 fields, 4096 µinstructions for VAX ISA encodes concurrently executable "microoperations" E.g., (IR) contains useful control information, 95 87 84 68 65 63 11 0 such as register sources, destinations, opcodes, etc. USHF UALU USUB UJMP

001 = left 010 = A-B-1 00 = Nop enable 010 = right 100 = A+B+1 01 = CALL signals R R R Jump . 10 = RTN Address from S S D . control 1 2 Register . ALU Subroutine File 101 = left3 Control Control D D D E E E ALU Shifter C C C Control

µ IR op rs1 rs2 rd Current intel architecture: 80-bit microcode, 8192 instructions to control

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Horizontal vs. Vertical Microprogramming Administration

NOTE: previous organization is not TRUE horizontal microprogramming; ° Midterm on Wednesday (10/6) from 5:30 - 8:30 in register decoders give flavor of encoded microoperations 277 Cory Hall ° No class on next Wednesday Most microprogramming-based controllers vary between: ° Pizza and Refreshments afterwards at LaVal’s on Euclid horizontal organization (1 control bit per control point) • I’ll Buy the pizza vertical organization (fields encoded in the control memory and • LaVal’s has an interesting history must be decoded to control something) ° Review Session: • Sunday (10/3), 7:00 PM in 306 Soda Horizontal Vertical

+ more control over the potential + easier to program, not very parallelism of operations in the different from programming datapath a RISC machine in assembly language - uses up lots of control store - extra level of decoding may slow the machine down

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.19 Lec10.20 Designing a Microinstruction Set 1&2) Start with list of control signals, grouped into fields Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg. is written 1) Start with list of control signals MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd 2) Group signals together that make sense (vs. TargetWrite None Target reg. = ALU random): called “fields” MemRead None Memory at address is read MemWrite None Memory at address is written 3) Places fields in some logical order IorD Memory address = PC Memory address = ALU IRWrite None IR = Memory (e.g., ALU operation & ALU operands first and PCWrite None PC = PCSource

microinstruction sequencing last) Single Bit Control PCWriteCond None IF ALUzero then PC = PCSource 4) Create a symbolic legend for the microinstruction Signal name Value Effect format, showing name of field values and how they ALUOp 00 ALU adds set the control signals 01 ALU subtracts 10 ALU does function code • Use to design computers 11 ALU does logical OR ALUSelB 000 2nd ALU input = Reg[rt] 5) To minimize the width, encode operations that will 001 2nd ALU input = 4 never be used at the same time 010 2nd ALU input = sign extended IR[15-0] 011 2nd ALU input = sign extended, shift left 2 IR[15-0] 100 2nd ALU input = zero extended IR[15-0] PCSource 00 PC = ALU Multiple Bit Control CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 01 PC = Target ©UCB Fall 1999 Lec10.21 10 PC = PC+4[29-26] : IR[25–0] << 2 Lec10.22

Start with list of control signals, cont’d 3) Microinstruction Format: unencoded vs. encoded fields

° For next state function (next microinstruction address), Field Name Width Control Signals Set use Sequencer-based control unit from last lecture wide narrow • Called “microPC” or “µPC” vs. state register ALU Control 4 2 ALUOp Signal Value Effect Sequen 00 Next µaddress = 0 1 SRC1 2 1 ALUSelA -cing 01 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1 SRC2 5 3 ALUSelB Adder microPC ALU Destination 4 2 RegWrite, MemtoReg, RegDst, TargetWr. Mux Memory 4 3 MemRead, MemWrite, IorD 2 1 0 0 Memory Register 1 1 IRWrite µAddress ROM PCWrite Control 3 2 PCWrite, PCWriteCond, PCSource Select Logic Sequencing 3 2 AddrCtl Opcode Total width 26 16 bits

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.23 Lec10.24 4) Legend of Fields and Symbolic Names Microprogram it yourself!

Field Name Values for Field Function of Field with Specific Value ALU Add ALU adds Label ALU SRC1 SRC2 ALU Dest. Memory Mem. Reg. PC Write Sequencing Subt. ALU subtracts Fetch Add PC 4 Read PC IR ALU Seq Func code ALU does function code Or ALU does logical OR SRC1 PC 1st ALU input = PC rs 1st ALU input = Reg[rs] SRC2 4 2nd ALU input = 4 Extend 2nd ALU input = sign ext. IR[15-0] Extend0 2nd ALU input = zero ext. IR[15-0] Extshft 2nd ALU input = sign ex., sl IR[15-0] rt 2nd ALU input = Reg[rt] ALU destination Target Target = ALUout rd Reg[rd] = ALUout rt Reg[rt] = ALUout Memory Read PC Read memory using PC Read ALU Read memory using ALU output Write ALU Write memory using ALU output Memory register IR IR = Mem Write rt Reg[rt] = Mem Read rt Mem = Reg[rt] PC write ALU PC = ALU output Target-cond. IF ALU Zero then PC = Target jump addr. PC = PCSource Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99Dispatch ©UCB Dispatch Fall 1999 using ROM. 9/29/99 ©UCB Fall 1999 Lec10.25 Lec10.26

Alternative datapath (book): Multiple Cycle Datapath Microprogram it yourself!

° Miminizes Hardware: 1 memory, 1 adder Label ALU SRC1 SRC2 ALU Dest. Memory Mem. Reg. PC Write Sequencing

PCWr PCWrCond PCSrc BrWr Fetch Add PC 4 Read PC IR ALU Seq Zero Add PC Extshft Target Dispatch

IorD MemWr IRWr RegDst RegWr ALUSelA Mux 1 Target 32 32 Rtype Func rs rt Seq PC 0 rd Fetch

Mux 0 32 Reg Instruction Rs Zero

Mux 0 Ra ALU Out LW Add rs Extend Seq 32 RAdr Rt 5 32 ALU 32 Rb busA 1 Read ALU Write rt Fetch 32 Ideal 5 Reg File 32 1 Memory Rt Mux 0 4 0 WrAdr 32 Rw 32 SW Add rs Extend Seq 1 32 Din Dout Rd busW busB 32 32 Write ALU Read rt Fetch 1 32 2 1 Mux 0 3 ALU << 2 Control BEQ1 Subt. rs rt Target– cond. Fetch

JUMP1 jump address Fetch

Extend Imm 16 32 ORI Or rs Extend0 Seq ALUOp rt Fetch ExtOp MemtoReg ALUSelB CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.27 Lec10.28 Legacy Software and Microprogramming Microprogramming Pros and Cons

° IBM bet company on 360 Instruction Set Architecture (ISA): ° Ease of design single instruction set for many classes of machines ° Flexibility • (8-bit to 64-bit) • Easy to adapt to changes in organization, timing, technology ° Stewart Tucker stuck with job of what to do about software compatibility • Can make changes late in design cycle, or even in the field ° If microprogramming could easily do same instruction set on ° Can implement very powerful instruction sets many different , then why couldn’t multiple (just more control memory) microprograms do multiple instruction sets on the same microarchitecture? ° Generality ° Coined term “emulation”: instruction set interpreter in • Can implement multiple instruction sets on same machine. microcode for non-native instruction set • Can tailor instruction set to application. ° Very successful: in early years of IBM 360 it was hard to know whether old instruction set or new instruction set was more ° Compatibility frequently used • Many organizations, same instruction set ° Costly to implement ° Slow CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.29 Lec10.30

An Alternative MultiCycle DataPath What about a 2-Bus Microarchitecture (datapath)?

A-Bus

B Bus Instruction Fetch Reg A A-Bus next P inst IR S mem File B Bus PC C mem ZX SX B Reg A W-Bus next P IR S Mem File M PC C ZXSX B ° In each clock cycle, each Bus can be used to transfer from one source Decode / Operand Fetch ° µ-instruction can simply contain B-Bus and W-Dst fields

Reg A next P IR S Mem File M PC C ZXSX B

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.31 Lec10.32 Load Exceptions Execute System user program Exception Reg A Handler next P IR S Mem Exception: File M PC C ZXSX B

Mem

addr return from Reg A next P IR S Mem exception File M PC C ZXSX B normal control flow: sequential, jumps, branches, calls, returns Write-back ° Exception = unprogrammed control transfer • system takes action to handle the exception - must record the address of the offending instruction Reg A next P IR S Mem File M • returns control to user PC C ZXSX B • must save & restore user state

° What about 1 bus ? 1 adder? 1 Register port?CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99° Allows constuction of ©UCB a “Falluser 1999 virtual machine” Lec10.33 Lec10.34

What happens to Instruction with Exception? Two Types of Exceptions

° Interrupts ° MIPS architecture defines the instruction as having • caused by external events no effect if the instruction causes an exception. • asynchronous to program execution ° When get to we will see that certain • may be handled between instructions classes of exceptions must prevent the instruction • simply suspend and resume user program from changing the machine state. ° Traps ° This aspect of handling exceptions becomes complex • caused by internal events and potentially limits performance => why it is hard - exceptional conditions (overflow) - errors (parity) - faults (non-resident page) • synchronous to program execution • condition must be remedied by the handler • instruction may be retried or simulated and program continued or program may be aborted

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.35 Lec10.36 MIPS convention: Addressing the Exception Handler ° exception means any unexpected change in control flow, without distinguishing internal or external; use the term interrupt only when the event is externally caused. ° Traditional Approach: Interupt Vector • PC <- MEM[ IV_base + cause || 00] Type of event From where? MIPS terminology I/O device request External Interrupt • 370, 68000, Vax, 80x86, . . . handler Invoke OS from user program Internal Exception iv_base code Arithmetic overflow Internal Exception cause Using an undefined instruction Internal Exception ° RISC Handler Table Hardware malfunctions Either Exception or Interrupt • PC <– IT_base + cause || 0000 • saves state and jumps • Sparc, PA, M88K, . . . handler entry code ° MIPS Approach: fixed entry iv_base • PC <– EXC_addr cause • Actually very small table - RESET entry - TLB - other CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.37 Lec10.38

Saving State Additions to MIPS ISA to support Exceptions?

° EPC–a 32-bit register used to hold the address of the affected ° Push it onto the stack instruction (register 14 of 0). • Vax, 68k, 80x86 ° Cause–a register used to record the cause of the exception. In the MIPS architecture this register is 32 bits, though some bits ° Save it in special registers are currently unused. Assume that bits 5 to 2 of this register • MIPS EPC, BadVaddr, Status, Cause encodes the two possible exception sources mentioned above: undefined instruction=0 and arithmetic overflow=1 (register 13 of ° Shadow Registers coprocessor 0). • M88k ° BadVAddr - register contained memory address at which memory reference occurred (register 8 of coprocessor 0) • Save state in a shadow of the internal pipeline registers ° Status - interrupt mask and enable bits (register 12 of coprocessor 0) ° Control signals to write EPC , Cause, BadVAddr, and Status ° Be able to write exception address into PC, increase mux to add as input 01000000 00000000 00000000 01000000two (8000 0080hex) ° May have to undo PC = PC + 4, since want EPC to point to offending instruction (not its successor); PC = PC - 4

CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.39 Lec10.40 Recap: Details of Big Picture: user / system modes

15 8 5 4 3 2 1 0 ° By providing two modes of execution (user/system) Status Mask k e k e k e it is possible for the computer to manage itself • operating system is a special program that runs in the old prev current priviledged mode and has access to all of the resources of the computer ° Mask = 1 bit for each of 5 hardware and 3 software • presents “virtual resources” to each user that are more interrupt levels convenient that the physical resurces • 1 => enables interrupts - files vs. disk sectors • 0 => disables interrupts ° k = kernel/user - virtual memory vs physical memory • 0 => was in the kernel when interrupt occurred • protects each user program from others • 1 => was running user mode ° e = interrupt enable ° Exceptions allow the system to taken action in • 0 => interrupts were disabled response to events that occur while user program • 1 => interrupts were enabled is executing ° When interrupt occurs, 6 LSB shifted left 2 bits, • O/S begins at the handler setting 2 LSB to 0 • run in kernel mode with interrupts disabled

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Recap: Details of Cause register Precise Interrupts 15 10 52 ° Precise ⇒ state of the machine is preserved as if Status program executed up to the offending instruction Pending Code • All previous instructions completed ° Pending interrupt 5 hardware levels: bit set if interrupt occurs • Offending instruction and all following instructions act as if they have but not yet serviced not even started • handles cases when more than one interrupt occurs at same time, • Same system code will work on different implementations or while records interrupt requests when interrupts disabled • Position clearly established by IBM ° Exception Code encodes reasons for interrupt • Difficult in the presence of pipelining, out-ot-order execution, ... • 0 (INT) => external interrupt • MIPS takes this position • 4 (ADDRL) => address error exception (load or instr fetch) ° Imprecise ⇒ system software has to figure out what is • 5 (ADDRS) => address error exception (store) where and put it all back together • 6 (IBUS) => bus error on instruction fetch ° Performance goals often lead designers to forsake • 7 (DBUS) => bus error on data fetch precise interrupts • 8 (Syscall) => Syscall exception • system software developers, user, markets etc. usually wish they had not done this • 9 (BKPT) => Breakpoint exception • 10 (RI) => Reserved Instruction exception ° Modern techniques for out-of-order execution and • 12 (OVF) => Arithmetic overflow exception branch prediction help implement precise interrupts CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.43 Lec10.44 How Control Detects Exceptions in our FSD Modification to the Control Specification

° Undefined Instruction–detected when no next state is IR <= MEM[PC] undefined instruction defined from state 1 for the op value. PC <= PC + 4 • We handle this exception by defining the next state value for all op EPC <= PC - 4 values other than lw, sw, 0 (R-type), jmp, beq, and ori as new state 12. A <= R[rs] other PC <= exp_addr • Shown symbolically using “other” to indicate that the op field does B <= R[rt] cause <= 10 (RI) not match any of the opcodes that label arcs out of state 1. LW BEQ ° Arithmetic overflow– R-type ORi SW • Chapter 4 included logic in the ALU to detect overflow, and a signal S <= A - B ~Equal called Overflow is provided as an output from the ALU. S <= A fun B S <= A op ZX S <= A + SX S <= A + SX 0010 • This signal is used in the modified finite state machine to specify an Equal overflow additional possible next state PC <= PC + M <= MEM[S] MEM[S] <= B SX || 00 ° Note: Challenge in designing control of a real machine 0011 is to handle different interactions between instructions and other exception-causing events such that control R[rd] <= S R[rt] <= S R[rt] <= M logic remains small and fast. • Complex interactions makes the control unit the most challenging Additional condition from aspect of hardware design EPC <= PC - 4 Datapath CS152 / Kubiatowicz PC <= exp_addr CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.45 cause <= 12 (Ovf) Lec10.46

Summary Summary: Microprogramming one inspiration for RISC ° Specialize state-diagrams easily captured by microsequencer ° If simple instruction could execute at very high … • simple increment & “branch” fields ° If you could even write compilers to produce • datapath control fields microinstructions… ° Control design reduces to Microprogramming ° If most programs use simple instructions and ° Exceptions are the hard part of control addressing modes… ° If microcode is kept in RAM instead of ROM so as to ° Need to find convenient place to detect exceptions and fix bugs … to branch to state or microinstruction that saves PC and invokes the operating system ° If same memory used for control memory could be used instead as for “macroinstructions”… ° For pipelined CPUs that support page faults on memory accesses, it gets even harder: ° Then why not skip instruction interpretation by a microprogram and simply compile directly into lowest • Need precise interrupts: language of machine? The instruction cannot complete AND you must be able to restart the program at exactly the instruction with the exception CS152 / Kubiatowicz CS152 / Kubiatowicz 9/29/99 ©UCB Fall 1999 9/29/99 ©UCB Fall 1999 Lec10.47 Lec10.48