GRAPHICS ACCELERATOR
Preliminary Data Sheet
Features ■ Video interface — Shared frame buffer interface for multimedia The ARTIST Graphics 3GA graphics accelerator is a 64 bit, — Supports S3 Vision/VA full screen video with a state-of-the-art 3D graphics processor designed to accelerate shared frame buffer graphical user interfaces, 2D and 3D vector drawing, and 3D ■ Flexible local memory rendering. — 64 bit wide memory bus ■ High performance 3D graphics processor — VRAM block write support — 16 bit Z-buffer for automatic 3D hidden surface — Supports 1 to 4 megabytes VRAM display memory removal — Supports 0 to 8 megabytes of off screen DRAM for — Secondary 16 bit Z-buffer for arbitrary frontal Z Z-buffers, fonts, etc. clipping ■ Single chip accelerator — Gouraud shading for realistic 3D rendering — On-chip 32 bit VGA for fast DOS performance — Dithering for superior shading at 8 and 16 bits per — Support for Microsoft Plug & Play ISA specification pixel — Interfaces directly to VESA VL-Bus and PCI with — Texture mapping to map 2D textures onto 3D no glue logic surfaces — Interfaces to ISA bus with two 74F245 buffers — Six arithmetic raster operations (Add, Add with — 128 byte host FIFO for passing data and commands Saturation, Sub, Sub with Saturation, Min, Max) — 240 pin plastic quad flat pack ■ Powerful 2D GUI accelerator — 50 MHz clock frequency — Accelerated drawing at 8, 16, 24 and 32 bits per ■ Software drivers pixel — Microsoft Windows 3.1, Windows NT and — 256 Microsoft Windows raster operations in Windows ‘95 (when released) hardware — OS/2 2.1 and OS/2 Warp — Color expanding BitBLTs provide extremely fast text — AutoCAD — On-chip 8 x 8 color expanding pattern — Hoops — Variable sized color pattern up to 64 x 64 pixels — OpenGL — Rectangular and arbitrary region clipping — 3D APIs: Argonaut BRender, Criterion Software — Eight stencil modes RenderWare, Rendermorphic Reality Lab, Intel 3DR — Multicolored “styled” lines and polylines ■ Display controller System Overview — VRAM based display controller for maximum A graphics system designed around the 3GA graphics performance accelerator requires only VRAM, a video DAC, clock — Supports displays up to 2048 x 2048 pixels generator, and a small number of external buffers. The 3GA — Refresh rates up to 90Hz at 1600 x 1200 resolution graphics accelerator supports a 64 bit wide data path to its — VESA DPMS support for green PC applications local memory array and contains interfaces to an external clock generator, DAC, and ROM BIOS.
ARTIST Graphics PROPRIETARY DATA 1 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Performance
Estimated performance, based on 8 bits per pixel, 10 pixel lines, 50 pixel triangles, 90MHz Pentium CPU, PCI bus. ■ 2D lines...... 1,600,000 lines/second ■ 3D lines (shaded, Z-buffered)...... 280,000 lines/second ■ 2D texture mapped triangles...... 75,000 triangles/second ■ 3D texture mapped triangles (Z-buffered)...... 65,000 triangles/second ■ 3D Gouraud shaded triangles (Z-buffered)...... 110,000 triangles/second ■ Screen-to-screen BitBLTs...... 80,000,000 pixels/second ■ Memory-to-screen BitBLTs (color expanding) ...... 245,000,000 pixels/second ■ Fill rate ...... 1,100,000,000 pixels/second
2 PROPRIETARY DATA ARTIST Graphics A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Pin Information
The 3GA graphics accelerator is available in a 240-pin quad flat pack for PCI, ISA, and VESA VL-Bus configurations.
Pin Diagram — PCI Bus VCC GND LD63 LD62 LD61 LD60 LD59 LD58 LD57 LD56 LD55 LD54 LD53 LD52 LD51 LD50 GND GND LD49 LD48 LD47 LD46 LD45 LD44 LD43 LD42 LD41 LD40 LD39 VCC SYSCLK VCC LCLKOUT LD38 LD37 LD36 LD35 LD34 LD33 LD32 DEVSTRB LD31 LD30 LD29 GND GND LD28 LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 GND VCC
VCC 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 120121 VCC GND 182 119 GND TN 183 118 LD16 GND 184 117 LD15 GND 185 116 LD14 GND 186 115 LD13 GND 187 114 LD12 GND 188 113 LD11 GND 189 112 LD10 GND 190 111 LD9 GND 191 110 LD8 GND 192 109 LD7 GND 193 108 LD6 GND 194 107 LD5 GND 195 106 LD4 GND 196 105 GND GND 197 104 GND GND 198 103 LD3 GND 199 102 LD2 GND 200 101 LD1 GND 201 100 LD0 GND 202 99 CAS7 GND 203 98 CAS6 GND 204 97 CAS5 GND 205 96 CAS4 GND 206 95 VGACAS3 GND 207 94 CAS3 VCC 208 93 VGACAS2 VCC 209 92 CAS2 GND 210 91 VCC GND 211 90 GND GND 212 89 SCLK GND 213 88 VCC GND 214 87 SCLK0 GND 215 86 SCLK1 GND 216 85 VGACAS1 GND 217 84 CAS1 INTA 218 83 VGACAS0 IDSEL 219 82 CAS0 RST 220 81 RCA9 CLK 221 80 RCA8 AD31 222 TOP VIEW 79 RCA7 AD30 223 78 RCA6 GND 224 77 RCA5 GND 225 PCI Bus 76 PCLK VIO 226 75 PIXCLK AD29 227 74 GND AD28 228 73 GND AD27 229 72 RCA4 AD26 230 71 RCA3 AD25 231 70 RCA2 AD24 232 69 RCA1 C/BE3 233 68 RCA0 VIO 234 67 DWE AD23 235 66 DRAS AD22 236 65 DSF AD21 237 64 VWE AD20 238 63 DTOE AD19 239 62 GND GND 240 61 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VIO
VIO
VIO
PAR
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
AD9 AD8
AD7 AD6 AD5 AD4 AD3
AD2 AD1 AD0
GND VCC
VCC GND GND
VCC
GND
GND
IRDY
AD11
AD18 AD17 AD16
AD15 AD14
AD13 AD12
AD10
TRDY
STOP
SOE0
SOE1
C/BE2
C/BE1
C/BE0
VRAS0
VRAS1
BLANK
FRAME
VSYNC
HSYNC
VGAWE
DEVSEL
CLKSEL1 CLKSEL0
VGARAS0 VGARAS1
VGADTOE
ARTIST Graphics PROPRIETARY DATA 3 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Pin Diagram — VESA VL-Bus VCC GND LD63 LD62 LD61 LD60 LD59 LD58 LD57 LD56 LD55 LD54 LD53 LD52 LD51 LD50 GND GND LD49 LD48 LD47 LD46 LD45 LD44 LD43 LD42 LD41 LD40 LD39 VCC SYSCLK VCC LCLKOUT LD38 LD37 LD36 LD35 LD34 LD33 LD32 DEVSTRB LD31 LD30 LD29 GND GND LD28 LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 GND VCC
VCC 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 120121 VCC GND 182 119 GND TN 183 118 LD16 W/R 184 117 LD15 A2 185 116 LD14 A3 186 115 LD13 A4 187 114 LD12 A5 188 113 LD11 A6 189 112 LD10 A7 190 111 LD9 A8 191 110 LD8 A9 192 109 LD7 A10 193 108 LD6 GND 194 107 LD5 GND 195 106 LD4 A24 196 105 GND A11 197 104 GND A12 198 103 LD3 A13 199 102 LD2 A14 200 101 LD1 A15 201 100 LD0 A16 202 99 CAS7 A17 203 98 CAS6 A18 204 97 CAS5 A19 205 96 CAS4 A20 206 95 VGACAS3 A21 207 94 CAS3 VCC 208 93 VGACAS2 VCC 209 92 CAS2 GND 210 91 VCC A22 211 90 GND A23 212 89 SCLK A25 213 88 VCC A26 214 87 SCLK0 A27 215 86 SCLK1 A28 216 85 VGACAS1 A29 217 84 CAS1 A30 218 83 VGACAS0 A31 219 82 CAS0 RESET 220 81 RCA9 LCLK 221 80 RCA8 D31 222 TOP VIEW 79 RCA7 D30 223 78 RCA6 GND 224 77 RCA5 GND 225 VL-Bus 76 PCLK VCC 226 75 PIXCLK D29 227 74 GND D28 228 73 GND D27 229 72 RCA4 D26 230 71 RCA3 D25 231 70 RCA2 D24 232 69 RCA1 IRQ 233 68 RCA0 VCC 234 67 DWE D23 235 66 DRAS D22 236 65 DSF D21 237 64 VWE D20 238 63 DTOE D19 239 62 GND GND 240 61 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
D9 D8
D7 D6 D5 D4 D3
D2 D1 D0
BE3 BE2 BE1 BE0
D11
D18 D17 D16
D15 D14
D13 D12
D10
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
ADS
VCC
VCC
GND VCC
VCC
VCC GND GND
VCC
GND
GND
M/IO
LDEV
LRDY
SOE0
SOE1
VRAS0
VRAS1
BLANK
VSYNC
HSYNC
VGAWE
RDYRTN
CLKSEL1 CLKSEL0
VGARAS0 VGARAS1
VGADTOE
4 PROPRIETARY DATA ARTIST Graphics A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Pin Diagram — ISA Bus VCC GND LD63 LD62 LD61 LD60 LD59 LD58 LD57 LD56 LD55 LD54 LD53 LD52 LD51 LD50 GND GND LD49 LD48 LD47 LD46 LD45 LD44 LD43 LD42 LD41 LD40 LD39 VCC SYSCLK VCC LCLKOUT LD38 LD37 LD36 LD35 LD34 LD33 LD32 DEVSTRB LD31 LD30 LD29 GND GND LD28 LD27 LD26 LD25 LD24 LD23 LD22 LD21 LD20 LD19 LD18 LD17 GND VCC
VCC 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 120121 VCC GND 182 119 GND TN 183 118 LD16 MCS16 184 117 LD15 SA2 185 116 LD14 SA3 186 115 LD13 SA4 187 114 LD12 SA5 188 113 LD11 SA6 189 112 LD10 SA7 190 111 LD9 SA8 191 110 LD8 SA9 192 109 LD7 SA10 193 108 LD6 GND 194 107 LD5 GND 195 106 LD4 IOCHRDY 196 105 GND SA11 197 104 GND SA12 198 103 LD3 SA13 199 102 LD2 SA14 200 101 LD1 SA15 201 100 LD0 SA16 202 99 CAS7 LA17 203 98 CAS6 LA18 204 97 CAS5 LA19 205 96 CAS4 LA20 206 95 VGACAS3 LA21 207 94 CAS3 VCC 208 93 VGACAS2 VCC 209 92 CAS2 GND 210 91 VCC LA22 211 90 GND LA23 212 89 SCLK MEMW 213 88 VCC MEMR 214 87 SCLK0 BLCK 215 86 SCLK1 SBHE 216 85 VGACAS1 BALE 217 84 CAS1 NOWS 218 83 VGACAS0 IRQ12 219 82 CAS0 RESDRV 220 81 RCA9 SYSCLK 221 80 RCA8 PULLUP 222 TOP VIEW 79 RCA7 PULLUP 223 78 RCA6 GND 224 77 RCA5 GND 225 ISA Bus 76 PCLK VCC 226 75 PIXCLK PULLUP 227 74 GND PULLUP 228 73 GND PULLUP 229 72 RCA4 PULLUP 230 71 RCA3 PULLUP 231 70 RCA2 PULLUP 232 69 RCA1 IRQ10 233 68 RCA0 VCC 234 67 DWE PULLUP 235 66 DRAS PULLUP 236 65 DSF PULLUP 237 64 VWE PULLUP 238 63 DTOE PULLUP 239 62 GND GND 240 61 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
IOR
SA0
SA1
VP7 VP6 IOW VP5 VP4 VP3 VP2 VP1 AEN VP0
SD9 SD8
SD7 SD6 SD5 SD4 SD3
SD2 SD1 SD0
VCC
VCC
GND VCC
VCC
VCC GND GND
VCC
GND
GND
HDIR
SD11
SD15 SD14
SD13 SD12
SD10
SOE0
SOE1
VRAS0
VRAS1
HDEN1
BLANK
HDEN0
VSYNC
HSYNC
VGAWE
PULLUP PULLUP PULLUP
REFRESH
CLKSEL1 CLKSEL0
VGARAS0 VGARAS1
VGADTOE
ARTIST Graphics PROPRIETARY DATA 5 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
3GA Pin Descriptions
The following table gives a brief description of each of the 3GA graphic accelerator’s pins and their function for the PCI, ISA, and VESA VL-Bus interface:
I Defines an input signal O Defines an output signal I/O Defines a bi-directional signal
PCI Bus Interface
Name Type Pin Number(s) Description
AD[31-0] I/O 222, 223, 227, 228, 229, 230, PCI Multiplexed Address/Data Bus. A bus transaction 231, 232, 235, 236, 237, 238, consists of an address phase followed by one or 239, 2, 3, 4, 14, 15, 18, 19, 20, more data phases. 21, 22, 23, 26, 27, 28, 29, 30, 32, 33, 34
C / BE[3 − 0] I 233, 5, 13, 24 PCI Multiplexed Bus Commands/Byte Enables. During the address phase they define the bus command. During the data phase they are used as byte enables. When used as byte enables these signals are active low.
RST I 220 PCI System Reset. Resets PCI-specific registers, 3GA registers, and sets 3GA state machines to a known state. Active low.
CLK I 221 PCI System Clock. Provides timing for all transactions on the PCI interface. All timing is referenced to the rising edge.
IDSEL I 219 PCI Initialization Device Select. Used as a chip select during configuration read and write transactions. Active high.
FRAME I 6 PCI Cycle Frame. Indicates beginning and duration of an access. Active low.
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Preliminary Data Sheet
PCI Bus Interface (continued)
Name Type Pin Number(s) Description
IRDY I 7 PCI Initiator Ready. Indicates the initiating agent’s ability to complete the current data phase of the transaction. Active low.
INTA O 218 PCI Interrupt A. Used to request an interrupt. Active low.
TRDY O 8 PCI Target Ready. Indicates the target agent's ability to complete the current data phase of the transaction. Active low.
DEVSEL O 9 PCI Device Select. Indicates the driving device has decoded its address as the target of the current access. Active low.
STOP O 11 PCI Stop. Indicates the current target is requesting the master to stop the current transaction. Active low.
PAR O 12 PCI Parity. Parity is even across AD[31-0] and C/BE[3-0]. Active high.
Unused PCI I 184, 185, 186, 187, 188, 189, These pins are not used when the 3GA is configured 190, 191, 192, 193, 196, 197, for the PCI interface, but they must be connected to 198, 199, 200, 201, 202, 203, ground. 204, 205, 206, 207, 211, 212, 213, 214, 215, 216, 217
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Preliminary Data Sheet
VESA VL-Bus Interface
Name Type Pin Number(s) Description
A[31-2] I 219, 218, 217, 216, 215, 214, VL-Bus Address Bus. Provides memory or I/O port 213, 196, 212, 211, 207, 206, addresses to the VL-Bus target. 205, 204, 203, 202, 201, 200, 199, 198, 197, 193, 192, 191, 190, 189, 188, 187, 186, 185
D[31-0] I/O 222, 223, 227, 228, 229, 230, VL-Bus Data Bus. Provides a bi-directional data path 231, 232, 235, 236, 237, 238, between VL-Bus devices and the CPU. 239, 2, 3, 4, 14, 15, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 32, 33, 34
BE[3 − 0] I 6, 7, 8, 9 VL-Bus Byte Enables. Indicates which byte lanes of the 32-bit data bus are involved with the current VL- Bus transfer. Active low.
LCLK I 221 VL-Bus Local CPU Clock. A 1x clock that follows the same phase as a 486-type CPU. The rising edge of the clock signifies the change of CPU states.
W/R I 184 VL-Bus Write or Read Status. Indicates the type of access currently executing on the VL-Bus. Write access is indicated by a high, while a read access is indicated by a low.
M/IO I 5 VL-Bus Memory or I/O Status. Indicates the type of access currently executing on the VL-Bus. Memory access is indicated by a high, while an I/O access is indicated by a low.
ADS I 24 VL-Bus Address Data Strobe. Indicates the start of the VL-Bus cycle. Active low.
RDYRTN I 13 VL-Bus Ready Return. Establishes a handshake so the VL-Bus target knows when the cycle has ended. Active low.
8 PROPRIETARY DATA ARTIST Graphics A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
VESA VL-Bus Interface (continued)
Name Type Pin Number(s) Description
RESET I 220 VL-Bus System Reset. A master reset that is asserted after system power up and before any valid CPU cycles take place. Active low.
IRQ O 233 Interrupt Request Line. Used to request an interrupt. Compatible with the ISA interrupt request lines. Triggered on the Rising edge.
LRDY O 12 VL-Bus Local Ready. Begins the handshake that terminates the current active bus cycle when the target is not bursting. Active low.
LDEV O 11 VL-Bus Local Device. Indicates that the current address on the VL-Bus is addressing the VL-Bus target. Active low.
ISA Bus Interface
Name Type Pin Number(s) Description
SD[15-0] I/O 14, 15, 18, 19, 20, 21, 22, 23, ISA System Data Bus. Used for data transfer. 26, 27, 28, 29, 30, 32, 33, 34
SA[16-0] I 202, 201, 200, 199, 198, 197, ISA System Address Bus. They are used to address 193, 192, 191, 190, 189, 188, I/O and Memory cycles and are valid throughout the 187, 186, 185, 11, 6 bus command cycle.
LA[23-17] I 212, 211, 207, 206, 205, 204, ISA Latchable Address Bus. Used to address memory 203 cycles and are not valid throughout the bus command cycle.
MEMW I 213 ISA Memory Write. Is asserted to indicate that the addressed memory slave may latch data from the memory bus. Active low.
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Preliminary Data Sheet
ISA Bus Interface (continued)
Name Type Pin Number(s) Description
MEMR I 214 ISA Memory Read. Is asserted to indicate that the addressed memory slave should drive data onto the memory bus. Active low.
IOW I 8 ISA I/O Write. Is asserted to indicate that the addressed I/O slave may latch data from the data bus. Active low.
IOR I 7 ISA I/O Read. Is asserted to indicate that the addressed I/O slave should drive data onto the data bus. Active low.
SBHE I 216 ISA System Bus High Enable. Indicates that expansion boards that support 16-bit data transfers should drive data on the high half of the system data bus. Active low.
BALE I 217 ISA Buffered Address Latch Enable. Indicates that a valid address is present in the latchable address bus. Active High.
REFRESH I 5 ISA Refresh. Indicates a refresh cycle in progress. Active low.
AEN I 13 ISA Address Enable. Indicates that the I/O slave may respond to addresses and I/O commands on the bus. Active high.
BCLK I 215 ISA Bus Clock. Provided to synchronize events with the main system clock.
SYSCLK I 221 3GA System Clock. Used to synchronize the host interface to the local interface.
RESDRV I 220 ISA Reset Driver. When asserted causes a hardware reset of ISA expansion boards. Active low.
10 PROPRIETARY DATA ARTIST Graphics A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
ISA Bus Interface (continued)
Name Type Pin Number(s) Description
Unused ISA I 4, 3, 2, 239, 238, 237, 236, These pins are not used when the 3GA is configured 235, 232, 231, 230, 229, 228, for the ISA interface, but they must be connected to 227, 223, 222 VCC through a pull-up resistor.
IRQ10 O 233 ISA Interrupt Request Level 10. Used to interrupt the CPU to request some service. Positive edge triggered.
IRQ12 O 219 ISA Interrupt Request Level 12. Used to interrupt the CPU to request some service. Positive edge triggered.
MCS16 O 184 ISA Memory Chip Select 16. Signals the system that the ISA memory is capable of transferring 16 bits of data at once. Active low.
CHRDY O 196 ISA Channel Ready. An I/O or memory slave can negate the signal to lengthen the bus cycle from the default time. Active high.
NOWS O 218 ISA No Wait State. An ISA memory slave asserts this signal after the address and command have been decoded to indicate that the remaining clock cycles are not required. Active low.
HDIR O 9 Host Data Buffer Direction. Controls the direction of the data buffers for read and write operations. A high it indicates a write to the 3GA. A low indicates a read from the 3GA.
HDEN0 O 24 Host Data Buffer Enable 0. Enables the data buffer that is connected to the 8 low order bits of the host data bus. Active low.
HDEN1 O 12 Host Data Buffer Enable 1. Enables the data buffer that is connected to the 8 high order bits of the host data bus. Active low.
ARTIST Graphics PROPRIETARY DATA 11 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Clock Inputs
Name Type Pin Number(s) Description
PIXCLK I 75 VGA Pixel Clock. The internal VGA’s pixel clock on the 3GA. Used exclusively as the pixel clock to the internal VGA. Up to 80MHz.
SCLKIN I 89 3GA Shift Clock Input. Free Running reference clock. Not gated off with the blanking signal. Used to generate shift clock outputs to the frame buffer, load clock to the DAC, and as a reference for all video signals in non VGA modes. Up to 50MHz/
SYSCLK I 150 3GA System Clock. 50MHz clock provides timing for all local data bus transactions.
Memory Interface
Name Type Pin Number(s) Description
RCA[9-0] O 81, 80, 79, 78, 77, 72, 71, 70, Local Memory Address Bus. Specify the row and 69, 68 column address for the local memory.
LD[63-0] I/O 178, 177, 176, 175, 174, 173, Local Memory Data Bus. LD[31-0] are also used as 172, 171, 170, 169, 168, 167, system configuration strapping bits, that are sensed 166, 165, 162, 161, 160, 159, at reset. LD[63-32] are used to provide an interface 158, 157, 156, 155, 154, 153, for local devices such as a RAMDAC, and a BIOS. 152, 147, 146, 145, 144, 143, 142, 141, 139, 138, 137, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123, 118, 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 103, 102, 101, 100
SCLK[1-0] O 86, 87 Video Memory Shift Clock. SCLK[1-0] are used to shift pixel data out of the VRAM to the RAMDAC. Serial data is accessed on the rising edge of SCLK[1-0].
12 PROPRIETARY DATA ARTIST Graphics A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Memory Interface (continued)
Name Type Pin Number(s) Description
SOE[1 − 0] O 58, 56 Video Memory Serial Output Enable. Enable/disable the serial data outputs on the VRAM. Active low.
DSF O 65 Video Memory Special Function Select. Determines which of the special functions are invoked on VRAM cycles. Active high.
DTOE O 63 Video Memory Data Transfer Output Enable. Selects either DRAM or transfer operation on the VRAM. Active low.
VGADTOE O 53 Video Memory Data Transfer Output Enable for the VRAM that is used by internal VGA. Selects either DRAM or transfer operation on the VRAM. Active low.
VWE O 64 Video Memory Write enable. Enables data to be written to the VRAM. Active low.
VGAWE O 54 Video Memory Write enable for the VRAM that is used by the internal VGA. Enables data to be written to the VRAM. Active low.
DWE O 67 DRAM Write Enable. DWE- enables data to be written to the expansion DRAM. Active low.
VRAS[1− 0] O 57, 55 Video Memory Row Address Strobe. Initiates all DRAM cycles and transfer cycles on the falling edge. Active low.
VGARAS[1− 0] O 52, 51 Video Memory Row Address Strobe for the VRAM that is used by the internal VGA. All DRAM cycles and transfer cycles are initiated by the falling edge. Active low.
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Preliminary Data Sheet
Memory Interface (continued)
Name Type Pin Number(s) Description
DRAS O 66 DRAM Row Address Strobe. All DRAM cycles are initiated by the falling edge. Active low.
CAS[7 − 0] O 99, 98, 97, 96, 94, 92, 84, 82 Local Memory Column Address Strobe. Latch the states of DSF and column address. Active low.
VGACAS[3 − 0] O 95, 93, 85, 83 Video Memory Column Address Strobe for the VRAM that is used by the internal VGA. Latch the states of DSF and column address. Active low.
RAMDAC Interface
Name Type Pin Number(s) Description
VP[7-0] O 36, 37, 38, 39, 40, 41, 42, 43 VGA Pixel outputs. VGA pixel bus from the internal VGA.
PCLK O 76 VGA Pixel Clock Output. VGA pixel clock output that is synchronized to the VGA pixel outputs. VGA pixels are latched in on the rising edge. Up to 80MHz.
HSYNC O 50 Horizontal Sync Pulse. Horizontal sync output used for both internal VGA modes and 3GA modes. Polarity is programmable.
VSYNC O 49 Vertical Sync Pulse. Vertical sync output used for both internal VGA modes and 3GA modes. Polarity is programmable.
BLANK O 48 Blanking Pulse. Blanking output used for both internal VGA modes and 3GA modes. Active low.
LCLKOUT O 148 Load Clock output. LCLK is synchronized with BLANK- to load pixels into the RAMDAC. Pixels are latched on the rising edge. Up to 50MHz.
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Preliminary Data Sheet
Miscellaneous
Name Type Pin Number(s) Description
CLKSEL[1-0] O 46, 47 Clock Select Bits. Used in VGA and 3GA modes to select the appropriate pixel clock from the clocking source.
DEVSTRB O 140 Local Device Strobe. Used to decode access to devices connected to the LD[63-32] bus, such as the RAMDAC and BIOS. Active low.
TN O 183 Test Mode Input. Must be connected to VCC for all applications.
Power and Ground
Name Type Pin Number(s) Description
VIO 10, 25, 35, 226, 234 Power supply input for PCI I/O. The voltage level on these supply inputs can be either +5v or +3.3v. This is selected by a system configuration strapping bit.
In ISA and VESA VL-Bus modes these power pins are connected to the same +5v supply as the VCC pins.
VCC 31, 45, 60, 61, 88, 91, 120, Power Supply. The voltage level on these supply 121, 149, 151, 180, 181, 208, inputs must be +5v. 209
GND 1, 16, 17, 44, 59, 62, 73, 74, Ground. 90, 104, 105, 119, 122, 135, 136, 163, 164, 179, 182, 194, 195, 210, 224, 225, 240
ARTIST Graphics PROPRIETARY DATA 15 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Functional Description
The 3GA offers a 3D graphics accelerator with VGA compatibility.
3GA Chip Block Diagram
32 32 FIFO GRAPHICS AND (32x32) DISPLAY REGISTERS
DRAWING ENGINE
SETUP
PRIMITIVE ENGINE
ISA VL PCI HOST INTERFACE AND PIXEL CONFIGURATION ENGINE REGISTERS
64 64 RAS, CAS, etc.
MEMORY RCA[9:0] CONTROLLER 32
LD[63:0]
DISPLAY HSYNC CONTROLLER VSYNC BLANK
32 VGA PCLK VP[7:0]
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Preliminary Data Sheet
Functional Blocks The following functional blocks are integrated into the 3GA graphics accelerator. ■ Host Interface and Configuration Registers The host interface provides a 32-bit interface on the PCI bus and VESA VL-Bus. It also provides a 16-bit interface to the ISA bus. The ISA interface is Plug and Play compatible. ■ FIFO The FIFO is a write buffer for drawing engine commands that decouples the CPU-host interface from the 3GA drawing engine. It contains 32 longword (32 bits) entries. On the input side, the FIFO captures host writes to the drawing engine registers and allows the host to proceed immediately without waiting. In conjunction with the drawing engine, the FIFO passes the data on to the appropriate registers. The FIFO manages all pipeline issues with the drawing engine and will not overwrite a register that is in use. When using the FIFO, programmers need only to determine if their is enough free locations in the FIFO prior to writing data. ■ Graphics and Display Registers These registers control most of the 3GA Enhanced Mode operations. They consist of display control, frame buffer base addresses and pitches, coordinates, primitive and interpolation registers. ■ Drawing Engine Setup: Computes the initial decision variables and dimensions for each primitive. It runs concurrent with the primitive engine. Example: If the primitive engine is working on primitive N, setup can be calculating primitive N+1. Primitive Engine: The primitive engine tracks X, Y, Z, R, G, B values for each graphics primitive. Pixel Engine: The pixel engine services requests from the primitive engine, fetching and writing the data necessary for each set of pixels provided by the primitive engine. ■ Display Controller The display controller provides the memory requests for REFRESH, READ-TRANSFER and SPLIT-READ-TRANSFER operations in 3GA Enhanced Mode. It also generates the syncs and blanks needed by the external VIDEO RAMDAC. Note that the display controller is distinct from the VGA CRT controller. ■ Memory Controller The memory controller services requests from the display controller, host interface and pixel engine. It generates all of the VRAM/DRAM control signals as well as the local device cycles needed to access the BIOS ROM, DAC and clock generator. ■ VGA The VGA is 100% VGA compatible. It supports the following extended SuperVGA modes: 800 x 600 x 16 and 256 colors, and 1024 x 768 x 16 and 256 colors. The VGA is VESA compatible and VESA drivers are available. The PCI bus and VESA VL-Bus provide a 32 bit host interface to the VGA.
ARTIST Graphics PROPRIETARY DATA 17 A Control Systems Company GRAPHICS ACCELERATOR
Preliminary Data Sheet
Reference Design
The following reference designs are example graphics systems designed around the 3GA graphic accelerator. Three examples are given: one interfacing to the PCI bus, one to the VL-Bus, and one to the ISA bus. These designs use two megabytes of VRAM and support the following resolutions and pixel depths at high refresh:
Resolution Bits per pixel
640 x 480 8, 16, 24, or 32
800 x 600 8, 16, 24, or 32
1024 x 768 8 or 16
1152 x 870 8 or 16
1280 x 1024 8
1600 x 1200 8
The reference designs use the IBM RGB525 DAC with a 64 bit wide pixel data path. The DAC has an on-chip clock generator for the pixel clock.
Interfacing to the PCI and VL busses require no glue logic, and the 3GA connects directly to the bus. The ISA design requires two additional 74F245 data buffers to connect to the ISA bus. The display memory is 64 bits wide and is made up of four 256Kx16 VRAM’s with the SOE inputs tied to ground. Series dampening resistors are recommended on all memory control signals. The local device interface uses a 74F138 for decoding and a 74F245 for a data buffer. The local device interface is used to read and write the DAC and to read the BIOS ROM. The SYSCLK signal is provided by a 50MHz TTL oscillator. The pixel clock is generated by the DAC’s on-chip clock generator. Video timing for the VGA is provided by the SCLK output from the DAC. The 3GA outputs the VGA pixel clock on its PCLKOUT pin. For 3GA enhanced modes, the 3GA outputs the DAC load clock on its LCLKOUT pin. The rising edge of this clock latches sixty-four bits of pixel data in the DAC. The 3GA automatically generates the VRAM shift clocks, and the BLANK and SYNC signals.
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Preliminary Data Sheet
Bill of Materials
The following is a bill of materials for a reference graphics adapter using the 3GA graphic accelerator.
Item Quantity Description
1 1 3GA 3D graphics accelerator
2 1 IBM RGB525 DAC
3 4 256Kx16 70ns VRAM's
4 1 BIOS ROM—32K x 8 bits 150ns EPROM
51 174F245
6 1 74F138
7 1 50MHz TTL oscillator
8 1 four layer printed circuit board
9 32 power-up configuration resistors
10 28 series dampening resistors
11 60 decoupling capacitors
12 — miscellaneous DAC components: ferrite beads, diodes, etc.
13 1 15 pin D-Sub connector
1ISA interface requires three 74F245 buffers.
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Preliminary Data Sheet
PCI System Block Diagram
3GA IBM RGB525 50 MHz TTL SYSCLK DAC Oscillator
RS[2:0] PCI BUS 74F245 G D[7:0] AD[31:0] DIR BIOS ROM BA D[7:0]
C/BE0 A[14:0]
C/BE1 DEVSTRB G Y1 OE
C/BE2 A Y2 RD B C/BE3 C Y3 WR 74F138 SCLK1 SCLK Four 256Kx16 RST LD[63:0] D[15:0] VRAM's
CLK RCA[8:0] A[8:0] RED
DSF DSF S[15:0] PIX[63:0] GREEN
IDSEL VGARAS0 RAS BLUE
FRAME VGARAS1 CASU
IRDY VRAS1 CASL HSYNCOUT
VGACAS[3:0] WE VSYNCOUT
INTA CAS[7:4] DTOE
TRDY VGAWE
DEVICE VWE
STOP VGADTOE
PAR DTOE
CLKSEL0 FS0
CLKSEL1 FS1
PIXCLK SCLK
SCLKIN
PCLK EXTCLK
LCLKOUT LCLK
VP[7:0] VGA[7:0]
HSYNC HSYNCIN
VSYNC VSYNCIN
BLANK BLANK
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Preliminary Data Sheet
VL-Bus System Block Diagram
3GA IBM RGB525 50 MHz TTL SYSCLK DAC Oscillator
RS[2:0] VL-BUS 74F245 G D[7:0] A[31:2] DIR BIOS ROM D[31:0] BA D[7:0]
BE0 A[14:0]
BE1 DEVSTRB G Y1 OE
BE2 A Y2 RD B BE3 C Y3 WR 74F138 SCLK1 SCLK Four 256Kx16 LCLK LD[63:0] D[15:0] VRAM's
R/W RCA[8:0] A[8:0] RED
M/IO DSF DSF S[15:0] PIX[63:0] GREEN
ADS VGARAS0 RAS BLUE
RDYRTN VGARAS1 CASU
RESET VRAS1 CASL HSYNCOUT
VGACAS[3:0] WE VSYNCOUT
IRQ CAS[7:4] DTOE
LRDY VGAWE
LDEV VWE
VGADTOE
DTOE
CLKSEL0 FS0
CLKSEL1 FS1
PIXCLK SCLK
SCLKIN
PCLK EXTCLK
LCLKOUT LCLK
VP[7:0] VGA[7:0]
HSYNC HSYNCIN
VSYNC VSYNCIN
BLANK BLANK
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Preliminary Data Sheet
ISA Interface System Block Diagram
3GA IBM RGB525 SYSCLK 50 MHz TTL DAC Oscillator ISA BUS
74F245 RS[2:0] 74F245 G HDEN1 G D[7:0] DIR HDIR DIR SD[15:8] BIOS ROM BA SD[15:8] BA D[7:0]
74F245 A[14:0]
G HDEN0 DEVSTRB G Y1 OE
DIR A Y2 RD SD[7:0] B BA SD[7:0] C Y3 WR 74F138 SCLK1 SCLK Four 256Kx16 SA[16:0] LD[63:0] D[15:0] VRAM's
LA[23:17] RCA[8:0] A[8:0] RED
MEMR DSF DSF S[15:0] PIX[63:0] GREEN
MEMW VGARAS0 RAS BLUE
IOR VGARAS1 CASU
IOW VRAS1 CASL HSYNCOUT
SBHE VGACAS[3:0] WE VSYNCOUT
BALE CAS[7:4] DTOE
REFRESH VGAWE
AEN VWE
BCLK VGADTOE
RESDRV DTOE
MCS16 CLKSEL0 FS0
CHRDY CLKSEL1 FS1
NOWS PIXCLK SCLK
IRQ10 SCLKIN
IRQ12 PCLK EXTCLK
LCLKOUT LCLK
VP[7:0] VGA[7:0]
HSYNC HSYNCIN
VSYNC VSYNCIN
BLANK BLANK
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Preliminary Data Sheet
Shared Frame Buffer Block Diagram:
3GA Memory Signals +5 VDC S3
74F244 10 KOhm VISION/VA
N / C GND VRAS[1]
VRAS1 VRAS[0]
VGARAS0 WE[1]
VGARAS1 OE[1]
VWE
VGAWE
DTOE
VGADTOE
OE1 MASTER_ OE2 GND
WE[0] OE[0]
VRAS0
CAS[7:4] CAS[7:4]
VGACAS[3:0] CAS[3:0]
RCA[8:0] MA[8:0]
N / C MB[8:0]
LD[63:0] MD[63:0]
+5 VDC +5 VDC 10 KOhm 10 KOhm
DSF
CAS[3:0]
(DRAS) BREQ_ BREQ_
(DWE) BGNT_ BGNT_
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Preliminary Data Sheet
© 1994 Control Systems, Inc. All rights reserved.
Preliminary product information describes products that are in preliminary production, but for which full characterization data is not yet available. ARTIST Graphics believes the information contained in this document is accurate and reliable. However, it is marked Preliminary and is subject to change without notice. No responsibility is assumed by ARTIST Graphics, for its use, nor for infringements of patents or other rights of third parties. This document implies no license under patents or copyrights. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise, without the prior written consent of ARTIST Graphics. ARTIST and the ARTIST logo are registered trademarks and 3GA is a trademark of Control Systems, Inc. Other trademarks in this document belong to their respective companies.
Printed in the United States of America. 12/94-2. 8-9751
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