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FULLTEXT01.Pdf !" # $%$& ' (%%$&() *+***,-.$&%/ !!" #! $ % & $ $ '% %( )% * + &%( , ( !!-( . & $ /% 0 ( ( 1( ( ( 2.34 50--10"1 506( )% 7 % & $ * * % & % $ % 8/'9( )% $ /' * % & 0 $$ % ( 2 % * % $ % % & % $ % ( )% % * % $ % % * : $ % & & % * & % $ /'( 2 % ; * : % 7 *%% & % & $ * ( )% % : $ ( )% % & $ $ ( ) * % % : & & $ 0& $ % & & % % $ % ( )* % & 7 # )% <./= % & 7 *%% & % &% % & % + * % % & $ & :* % * % & %( *% & & 0% * 0 % ( >% & & * & ( 2 %$ * : % $ % $ $ % ( )% % % $ % % 7 $ 0 * *%% * : % & $ % & $ ( ! " ##$ %&$'()' * ? , !!- 2..4 "-0" 1 2.34 50--10"1 506 # ### 0" -! 8% #@@ (:(@ A B # ### 0" -!9 Till min familj List of Papers This thesis is based on the following papers, which are referred to in the text by the capital letters A through G. A. Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution Martin Karlsson and Erik Hagersten Technical Report 2005-040, Department of Information Technology, Uppsala University, Sweden, December 2005. Submitted for publication B. Timestamp-Based Selective Cache Allocation Martin Karlsson and Erik Hagersten In High Performance Memory Systems, Chapter 4, Edited by H. Hadimiouglu, D. Kaeli, J. Kuskin, A. Nanda, and J. Torrellas, pages 43-59, Springer-Verlag, 2003. ISBN 038700310X C. Skewed Caches from a Low-Power Perspective Mathias Spjuth, Martin Karlsson and Erik Hagersten In Proceedings of the ACM International Conference on Computing Frontiers, Ischia, Italy, May 2005. D. TMA: A Trap-Based Memory Architecture Håkan Zeffer, Zoran Radovic,´ Martin Karlsson and Erik Hagersten Technical Report 2005-041, Department of Information Technology, Uppsala University, Sweden, December 2005. Submitted for publication E. Memory System Behaviour of Java-Based Middleware Martin Karlsson, Kevin Moore, Erik Hagersten and David Wood In Proceeding of the Ninth International Symposium on High Performance Computer Architecture, Anaheim, California, USA, February 2003. F. Exploring Processor Design Options for Java-Based Middleware Martin Karlsson, Kevin Moore, Erik Hagersten and David Wood In Proceedings of the 34th International Conference on Parallel Processing, Oslo, Norway, June 2005. G. VASA: A Simulator Infrastructure with Adjustable Fidelity Dan Wallin, Håkan Zeffer, Martin Karlsson and Erik Hagersten In Proceedings of the International Conference on Parallel and Distributed Com- puting and Systems, Phoenix, Arizona, USA, November 2005. 5 Other Publications • Timestamp-Based Selective Cache Allocation, Martin Karlsson and Erik Hagersten, In Proceedings of the 1st Annual Workshop on Memory Performance Issues (WMPI 2001), held in conjunction with the 28th International Symposium on Computer Architecture (ISCA28), Göteborg, Sweden, May 2002. • Memory Characterization of the ECperf Benchmark, Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood, In Proceedings of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA29), Anchorage, Alaska, USA, May 2002. • Skewed Caches from a Low-Power Perspective Mathias Spjuth, Martin Karlsson and Erik Hagersten, In Proceedings of the 4th Annual Workshop on Memory Performance Issues (WMPI 2004), held in conjunction with the 31th International Symposium on Computer Architecture (ISCA31), Munich, Germany, June 2004. • Cache Memory Design Trade-offs for Current and Emerging Workloads Martin Karlsson, Licentiate Thesis 2003-009, Department of Information Technology, Uppsala Uni- versity, September 2003. 7 Comments on my Participation A. Conserving Memory Bandwidth in Chip Multiprocessors with Runahead Execution I am the principal author and have performed all the experiments in this work. B. Timestamp-Based Selective Cache Allocation I am the principal author and have performed all the experiments in this work. C. Skewed Caches from a Low-Power Perspective I am the principal author of the paper while Mathias Spjuth is the principal investigator of the project. The energy model was developed jointly, while the performance model was based on Mathias Spjuth’s Masters thesis which I advised. D. TMA: A Trap-Based Memory Architecture Håkan Zeffer is the principal investigator of the project and has performed all the experiments. I am the principal author of the article together with Håkan Zeffer and we also co-designed the trap mechanism. I have had no part in the protocol implementation, which was carried out by Håkan Zeffer and Zoran Radovic.´ E. Memory System Behaviour of Java-Based Middleware The paper was jointly written with Kevin Moore. From an experimental point of view, Kevin Moore was responsible for setting up and tuning the workload while I designed most of the experiments and provided the initial benchmark setup inside Simics. F. Exploring Processor Design Options for Java-Based Middleware The paper was written jointly with Kevin Moore. I designed and performed all the experiments in this project G. VASA: A Simulator Infrastructure with Adjustable Fidelity All authors have contributed to all aspects of this project. I am the principal author of the article together with Dan Wallin who also designed and performed all the experiments. Håkan Zeffer is the main contributor to the Vasa implementation. 9 Acknowledgments My first attempt at research during an internship at Los Alamos National Lab- oratories was not much of a success, quite the opposite. The result was that I decided that getting a PhD (in databases), which I had been contemplating, was not anything for me. I am therefore very grateful to my advisor Profes- sor Erik Hagersten who persuaded me to get a PhD and accepted me in his research group, which at that time was lacking members. I have since that day never regretted my decision and would do it all over again without hesitation. Erik’s role somewhere along the way blurred between advisor, mentor and friend. I consider myself very fortunate to have had Erik as an advisor dur- ing these years. I am especially grateful to Erik for allowing me to pursue my own ideas to a large extent. I have learned many things from him, a surprising amount in areas unrelated to computer architecture. Thank you! Apart from Erik I have been very fortunate to have had an extraordinary set of teachers and mentors during my education, many of which have indirectly been instru- mental in reaching this goal. While the list is too long to be included here my thanks goes out to all of you. The Uppsala Architecture Team (UART) members have been excellent com- panions along this long winding road. Lars Albertson, Erik Berg, Henrik Löf, Zoran Radovic,´ Dan Wallin and Håkan Zeffer. I will miss our daily interaction a great deal. The IT department has been an excellent workplace and I have enjoyed the friendly atmosphere among faculty and staff very much. I would like to thank the collection of wise men that have joined me at the grad student friday pub. Without the administrative staff, coffee breaks certainly would not have been such a pleasure. The computer administrators helped me out with numerous is- sues. I would like to thank the staff at Virtutech, particularly Andreas Moestedt, for countless hours of Simics support. Sverker Holmgren provided computa- tional resources and shipped me to Sri Lanka, installing linux boxes, in the middle of the cold dark winter. Thanks! During the course of this work I have had three very rewarding internships at Sun Microsystems. I would like to thank the people at Sun Laboratories and the Processor Performance Group for making my visits there so enjoyable, especially Paul Caprioli and Shailender Chaudhry. 11 I would also like to express my gratitude towards my fellow student co- authors and collaborators Kevin Moore, Mathias Spjuth, Håkan Zeffer, Dan Wallin and Zoran Radovic.´ I think in each project the result was far greater than the sum of our efforts. I would especially like to thank Kevin Moore for proofreading this thesis. Till slut vill jag tacka min familj, vänner och andra närstående för allt stöd och uppmuntran som jag erhållit under de här åren. För det kommer jag för alltid att vara tacksam. Jag vill rikta ett speciellt tack till Josefin som genom sin oändliga klokhet under den senare delen av denna resa hjälpt mig bibehålla perspektiv på saker och ting. Thanks! This research has been supported by a grant from the Swedish Foundation for Strategic Research (SSF) under the ARTES/PAMP program. 12 Introduction The services provided by multiprocessor servers are increasingly becoming a part of our every day lives. For example when we make an online reservation or purchase, servers running databases and web applications keep track of prod- ucts in stock or available seats, and are used to deliver the service to us. The cost and performance of these multiprocessor servers are important. Multipro- cessor servers are used in many domains. In the scientific computing arena, faster multiprocessor servers allow for more detailed and accurate modeling of for example weather and pharmaceuticals. The discrepancy between the speed of processing and the time to access memory has made memory system
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