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2-Wire Time Independent Asynchronous Communications By Pj Radcliffe B.Eng. (Melb), M.Eng. (RMIT) A dissertation submitted in fulfillment of the requirements for the degree of Doctor of Philosophy School of Electrical & Computer Engineering Science, Engineering & Technology Portfolio RMIT University Melbourne, Victoria Australia Submitted November 2006 Abstract Communications both to and between low end microprocessors represents a real cost in a number of industrial and consumer products. This thesis starts by examining the properties of protocols that help to minimize these expenses and comes to the conclusion that the derived set of properties define a new category of communications protocol : Time Independent Asynchronous ( TIA) communications. To show the utility of the TIA category we develop a novel TIA protocol that uses only 2-wires and general IO pins on each host. The protocol is analyzed using the Petri net based STG ( Signal Transition Graph) which is widely use to model asynchronous logic. It is shown that STGs do not accurately model the behavior of software driven systems and so a modified form called STG-FT ( STG For Threads) is developed to better model software systems. A simulator is created to take an STG-FT model and perform a full reachability tree analysis to prove correctness and analyze livelock and deadlock properties. The simulator can also examine the full reachability tree for every possible system state ( the cross product of all sub-system states), and analyze deadlock and livelock issues related to unexpected inputs and unusual situations. Reachability pruning algorithms are developed which decrease the search tree by a factor of approximately 250 million. The 2-wire protocol is implemented between a PC and an Atmel Tiny26 microprocessor, there is also a variant that works between microprocessors. Testing verifies the simulation results including an avoidable livelock condition with data throughput peaking at a useful 50 kilobits/second in both directions. The first practical application of 2-wire TIA is part of a novel debugger for the Atmel Tiny26 microprocessor. The approach can be extended to any microprocessor with general IO pins. TIA communications, developed in this thesis, is a serious contender whenever low end microprocessors must communicate with other processors. Consumer and industrial products may be able to achieve cost saving by using this new protocol. Copyright © Pj Radcliffe 2006 Page ii Declarations Except where due acknowledgment has been made, all work is that of the candidate alone. This thesis has not been submitted previously, in whole or in part, to qualify for any other award. The content of this thesis is the result of work which has been carried out since the official commencement date of the approved research program. Any editorial work, paid or unpaid, carried out by a third party is acknowledged. signed ( Pj Radcliffe) Acknowledgments First I must acknowledge my family for being so supportive and helping me find time to pursue this thesis. Next I would like to acknowledge the support and encouragement of the best PhD supervisor I have seen in a long time : Dr. Xinghuo Yu. Copyright © Pj Radcliffe 2006 Page iii Table of Contents 1 Introduction...............................................................................................................8 1.1 The Problem Faced...........................................................................................8 1.2 The State of the Field........................................................................................9 1.3 Motivation and Objectives...............................................................................9 1.4 Overview of Thesis Structure.........................................................................10 1.5 Contributions of This Thesis..........................................................................11 2 Literature Survey : Communications Category Identification...........................13 2.1 Communications Attributes and Categories...................................................14 2.2 Existing Time Independent Asynchronous Protocols.....................................19 2.2.1 Non-TIA Protocols..........................................................................19 2.2.2 Existing TIA Protocols.....................................................................23 2.3 Summary and Conclusions.............................................................................26 3 Literature Survey : Protocol Verification & Modeling Issues............................28 3.1 Protocol Properties to Verify..........................................................................29 3.1.1 Specification Level Verification.......................................................32 3.1.2 Implementation Level Verification...................................................33 3.2 Modelling Methods for TIA...........................................................................36 3.2.1 Finite State Machines ( FSM) & SDL..............................................36 3.2.2 Signal Transition Graphs and Problems...........................................38 3.2.3 Signal Transition Graph For Threads...............................................39 3.2.4 Reachability......................................................................................48 3.3 Summary and Conclusions.............................................................................52 4 2-Wire Time Independent Asynchronous Protocol .............................................54 4.1 Initial Design Problems..................................................................................55 4.2 Waveforms and Protocol................................................................................56 4.3 STG-FT Model...............................................................................................59 4.4 STG-FT Simulator and Results......................................................................61 4.4.1 Simulator Implementation................................................................62 4.4.2 Simulation of Normal Operation .....................................................65 4.4.3 Simulation of Any Initial State........................................................69 4.5 2-Wire TIA Implementation and Conformance Testing.................................71 4.5.1 Implementation Details.....................................................................72 4.5.2 Test Setup.........................................................................................75 4.5.3 Testing Results..................................................................................77 4.6 Summary and Conclusions.............................................................................80 5 2B-2B Variant of 2-wire Time Independent Asynchronous Protocol...............82 Copyright © Pj Radcliffe 2006 Page iv 5.1 2B-2B Waveforms..........................................................................................83 5.2 STG-FT Model & Simulation.........................................................................85 5.3 Summary and Conclusions.............................................................................86 6 Practical Use as an Embedded Debugger..............................................................88 6.1 Existing Microprocessor Debugging Tools....................................................90 6.1.1 Ad-hoc Approaches..........................................................................91 6.1.2 Monitor ROM Debuggers.................................................................92 6.1.3 In Circuit Emulators.........................................................................95 6.1.4 Boundary Scan Systems...................................................................97 6.1.5 Microprocessor Simulators...............................................................99 6.1.6 Debugger Programs........................................................................100 6.1.7 Built in Debugging.........................................................................101 6.2 Low End Microprocessor Debuggers and TIA.............................................103 6.3 TIA Based Debugger Implementation..........................................................105 6.4 Summary and Conclusions...........................................................................112 7 Discussion and Conclusions..................................................................................113 7.1 Summary of Conclusions..............................................................................113 7.2 Future Research Directions...........................................................................115 8 References..............................................................................................................117 9 Appendix A............................................................................................................124 Copyright © Pj Radcliffe 2006 Page v List of Illustrations Illustration 2.1: Concept Map of TIA Features to Applications..................................................18 Illustration 2.2: Section of I2C Waveform..................................................................................20 Illustration 2.3: SPI Timing from Freescale AN-991..................................................................20 Illustration 2.4: I2S Waveform from Philips Specification.........................................................21 Illustration 2.5:

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