ASP-DAC 2017 Advance Program 22nd Asia and South Pacific Design Automation Conference Date: January, 16-19, 2017 Place: Chiba/Tokyo, Japan Highlights Special Sessions Tutorial-2: Towards Energy-Efficient Intelligence in Power- /Area-Constrained Hardware Opening and Keynote I 1S: (Presentation + Poster Discussion) University Design Contest Monday, January 16, 2017, 9:30-11:30, 12:45-14:45 Tuesday, January 17, 2017, 11:05-13:50 Tuesday, January 17, 2017, 8:30-10:35 Organizer: 2S: (Invited Talks) Neuromorphic Computing and Low-Power Im- Jae-sun Seo (Arizona State Univ.) Keynote I: In Memory of Edward J. McCluskey: The Next age Recognition Speakers: Wave of Pioneering Innovations Tuesday, January 17, 2017, 13:50-15:30 Zhengya Zhang (U. Michigan, Ann Arbor) Organizers/Chairs: Mingoo Seok (Columbia Univ.) Subhasish Mitra (Stanford University) 3S: (Invited Talks) Let’s Secure the Physics of Cyber-Physical Sys- Jae-sun Seo (Arizona State Univ.) Deming Chen (University of Illinois at Urbana-Champaign) tems Tuesday, January 17, 2017, 15:50-17:30 Tutorial-3: Post-Silicon Validation and Emulation-Based Val- This special plenary session will celebrate Prof. McCluskey idation Using Exercisers (who passed away in 2016) through three keynote speeches by 4S: (Invited Talks) Emerging Technologies for Biomedical Appli- Monday, January 16, 2017, 9:30-11:30, 15:15-17:15 world-renowned scholars on the next wave of pioneering innova- cations: Artificial Vision Systems and Brain Machine Interface Organizers: tions, starting with a memorial speech by Prof. Jacob Abraham Wednesday, January 18, 2017, 10:15-12:20 Ronny Morad (IBM Research - Haifa) of University of Texas at Austin. 7S: (Invited Talks) When Backend Meets Frontend: Cross-Layer Vitali Sokhin (IBM Research - Haifa) Design & Optimization for System Robustness Speakers: Keynote I-1: K.-T. Tim Cheng (Hong Kong University of Science Thursday, January 19, 2017, 10:15-12:20 Ronny Morad (IBM Research - Haifa) and Technology) “Heterogeneous Integration of X-tronics: De- Vitali Sokhin (IBM Research - Haifa) sign Automation and Education” Designers’ Forum Tutorial-4: Quick Start Guide of Digital PLL for Digital De- Keynote I-2: John Rogers (Northwestern University) “Electron- signers ics for the Human Body” 5S: (Oral Session) Advanced Devices and Networks for IoT Appli- Monday, January 16, 2017, 9:30-11:30, 15:15-17:15 Keynote I-3: Hiroto Yasuura (Kyushu University) “Design of cations Organizer: Society: Beyond Digital System Design” Wednesday, January 18, 2017, 13:50-15:30 Kenichi Okada (Tokyo Institute of Technology) 6S: (Panel Discussion) What is future AI we will create? Speakers: Kenichi Okada (Tokyo Institute of Technology) – “Doraemon” or “Terminator” ? – Keynote II Salvatore Levantino (Politecnico di Milano) Wednesday, January 18, 2017, 15:50-17:30 Wednesday, January 18, 2017, 9:00-9:50 Tutorial-5: The Emergence of Hardware Oriented Security 8S: (Oral Session) Advanced Automotive Security and Trust Napoleon Torres-Martinez (CEA LETI) “Emerging Medical Thursday, January 19, 2017, 13:50-15:30 Technologies for Interfacing the Brain: From Deep Brain Monday, January 16, 2017, 12:45-14:45, 15:15-17:15 Stimulation to Brain Computer Interfaces” 9S: (Oral Session) Advanced Image Sensing and Processing Organizer: Thursday, January 19, 2017, 15:50-17:30 Chip-Hong Chang (Nanyang Technological Univ.) Speakers: Keynote III Chip-Hong Chang (Nanyang Technological Univ.) Tutorials Yier Jin (Univ. of Central Florida) Thursday, January 19, 2017, 9:00-9:50 Tutorial-1: Silicon Photonics for Computing Systems: Opportu- Tutorial-6: Cross-Layer Reliability Aware Design, Optimiza- Steve Trimberger (Xilinx Research Labs) “All-Programmable nities, Challenges, and Implementations tion and Dynamic Management FPGAs: More Powerful Devices Require More Powerful Monday, January 16, 2017, 9:30-11:30, 12:45-14:45 Monday, January 16, 2017, 12:45-14:45, 15:15-17:15 Tools” Organizers: Organizer: Jiang Xu (Hong Kong University of Science and Technology) Sheldon Tan (UC Riverside) Yuichi Nakamura (NEC) Speakers: Speakers: Sheldon Tan (UC Riverside) Jiang Xu (Hong Kong University of Science and Technology) Mehdi Tahoori (Karlsruhe Inst. Tech.) Shigeru Nakamura (NEC) Hai-Bao Chen (Shanghai Jiao Tong Univ.) Monday, January 16, 2017
ASP-DAC 2017 offers attendees a set of two-hour intense introductions to specific topics. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the six topics.
Registration (8:00 - ) Room 102 Room 103 Room 104 Room 105 9:30 Tutorial 1: Silicon Photonics for Computing Sys- Tutorial 2: Towards Energy-Efficient Intelligence Tutorial 3: Post-Silicon Validation and Tutorial 4: Quick Start Guide of Digital PLL for tems: Opportunities, Challenges, and Implemen- in Power-/Area-Constrained Hardware Emulation-Based Validation Using Exercis- Digital Designers tations ers Organizers: Organizer: Organizers: Organizer: Jiang Xu (Hong Kong University of Science and Technology) Jae-sun Seo (Arizona State Univ.) Ronny Morad (IBM Research - Haifa) Kenichi Okada (Tokyo Institute of Technology) Yuichi Nakamura (NEC) Vitali Sokhin (IBM Research - Haifa) Speakers: Speakers: Speakers: Speakers: Jiang Xu (Hong Kong University of Science and Technology) Zhengya Zhang (U. Michigan, Ann Arbor) Ronny Morad (IBM Research - Haifa) Kenichi Okada (Tokyo Institute of Technology) Shigeru Nakamura (NEC) Mingoo Seok (Columbia Univ.) Vitali Sokhin (IBM Research - Haifa) Salvatore Levantino (Politecnico di Milano) Jae-sun Seo (Arizona State Univ.) 11:30 Lunch Break (11:30 - 12:45) 12:45 Tutorial 1: Silicon Photonics for Computing Sys- Tutorial 2: Towards Energy-Efficient Intelligence Tutorial 5: The Emergence of Hardware Ori- Tutorial 6: Cross-Layer Reliability Aware De- tems: Opportunities, Challenges, and Implemen- in Power-/Area-Constrained Hardware ented Security and Trust sign, Optimization and Dynamic Management tations Organizers: Organizer: Organizer: Organizer: Jiang Xu (Hong Kong University of Science and Technology) Jae-sun Seo (Arizona State Univ.) Chip-Hong Chang (Nanyang Technological Univ.) Sheldon Tan (UC Riverside) Yuichi Nakamura (NEC) Speakers: Speakers: Speakers: Speakers: Jiang Xu (Hong Kong University of Science and Technology) Zhengya Zhang (U. Michigan, Ann Arbor) Chip-Hong Chang (Nanyang Technological Univ.) Sheldon Tan (UC Riverside) Shigeru Nakamura (NEC) Mingoo Seok (Columbia Univ.) Yier Jin (Univ. of Central Florida) Mehdi Tahoori (Karlsruhe Inst. Tech.) Jae-sun Seo (Arizona State Univ.) Hai-Bao Chen (Shanghai Jiao Tong Univ.) 14:45 Coffee Break (14:45 - 15:15) 15:15 Tutorial 3: Post-Silicon Validation and Tutorial 4: Quick Start Guide of Digital PLL for Tutorial 5: The Emergence of Hardware Ori- Tutorial 6: Cross-Layer Reliability Aware De- Emulation-Based Validation Using Exercis- Digital Designers ented Security and Trust sign, Optimization and Dynamic Management ers Organizers: Organizer: Organizer: Organizer: Ronny Morad (IBM Research - Haifa) Kenichi Okada (Tokyo Institute of Technology) Chip-Hong Chang (Nanyang Technological Univ.) Sheldon Tan (UC Riverside) Vitali Sokhin (IBM Research - Haifa) Speakers: Speakers: Speakers: Speakers: Ronny Morad (IBM Research - Haifa) Kenichi Okada (Tokyo Institute of Technology) Chip-Hong Chang (Nanyang Technological Univ.) Sheldon Tan (UC Riverside) Vitali Sokhin (IBM Research - Haifa) Salvatore Levantino (Politecnico di Milano) Yier Jin (Univ. of Central Florida) Mehdi Tahoori (Karlsruhe Inst. Tech.) Hai-Bao Chen (Shanghai Jiao Tong Univ.) 17:15 Tuesday, January 17, 2017
Registration (7:00 - ) 8:30 1K: Opening & Keynote I Chair: Naofumi Takagi (Kyoto University) Keynote I: In Memory of Edward J. McCluskey: The Next Wave of Pioneering Innovations Organizers/Chairs: Subhasish Mitra (Stanford University), Deming Chen (University of Illinois at Urbana-Champaign) Keynote I-1: K.-T. Tim Cheng (Hong Kong University of Science and Technology) “Heterogeneous Integration of X-tronics: Design Automation and Education” Keynote I-2: John Rogers (Northwestern University) “Electronics for the Human Body” Keynote I-3: Hiroto Yasuura (Kyushu University) “Design of Society: Beyond Digital System Design” 10:35 Coffee break (10:35 - 11:05) 11:05 1S: University Design Contest 1A: Design Assurance and Reliability 1B: New Frontiers of Hardware Accelerator Syn- 1C: Analysis Techniques for Reliability and Man- thesis ufacturability Chairs: Noriyuki Miura (Kobe Univ., Japan), Hiroyuki Chairs: Chih-Tsun Huang (National Tsing Hua Univ., Tai- Chairs: Seiya Shibata (NEC, Japan), Takefumi Chairs: Shao-Yun Fang (National Taiwan Univ. of Science Ito (Tokyo Inst. of Tech., Japan) wan), Franco Fummi (Univ. of Verona, Italy) Miyoshi (e-trees.Japan) and Tech., Taiwan), Song Chen (Univ. of Science and Tech. of China, China) (The titles of the presentations are listed in the next 1A-1: “AGARSoC: Automated Test and Coverage- 1B-1: “Efficient Floating Point Precision Tuning for 1C-1: “Lithography Hotspot Detection by Two- page) Model Generation for Verification of Accelerator- Approximate Computing” Nhut-Minh Ho, Elavarasi stage Cascade Classifier Using Histogram of Ori- Rich SoCs” Biruk Mammo, Doowon Lee, Harrison Manogaran, Weng-Fai Wong (National Univ. of Singapore, ented Light Propagation” Yoichi Tomioka (Univ. of Davis, Yijun Hou, Valeria Bertacco (Univ. of Michigan, Singapore), Asha Anoosheh (Univ. of California, Berkeley, Aizu, Japan), Tetsuaki Matsunawa, Chikaaki Kodama, U.S.A.) U.S.A.) Shigeki Nojima (Toshiba, Japan)
1A-2: “Feature Extraction from Design Documents 1B-2: “Area Constrained Technology Mapping 1C-2: “Reliability Analysis of Memories suffering to Enable Rule Learning for Improving Assertion for In-Memory Computing Using ReRAM De- MBUs for the Effect of Negative Bias Temperature Coverage” Kuo-Kai Hsieh, Sebastian Siatkowski, vices” Debjyoti Bhattacharjee, Arvind Easwaran, Instability” Shanshan Liu, Liyi Xiao, Xuebing Cao, Li-Chung Wang (Univ. of California, Santa Barbara, U.S.A.), Anupam Chattopadhyay (Nanyang Technological Univ., Zhigang Mao (Harbin Inst. of Tech., China) Wen Chen, Jayanta Bhadra (NXP Semiconductors, U.S.A.) Singapore)
1A-3: “Trust is good, Control is better: Hardware- 1B-3: “Tessellating Memory Space for Parallel Ac- 1C-3: “Efficient Circuit Failure Probability Calcu- based Instruction-Replacement for Reliable cess” Juan Escondido, Mingjie Lin (UCF, U.S.A.) lation along Product Lifetime Considering Device Processor-IPs” Kenneth Schmitz, Arun Chan- Aging” Hiromitsu Awano, Masayuki Hiromoto, drasekharan, Jonas Gomes Filho, Daniel Große, Takashi Sato (Kyoto Univ., Japan) Rolf Drechsler (Univ. of Bremen, Germany) 12:20 Lunch Break (12:20 - 13:50) University LSI Design Contest Poster Presentation [Food will be served] (12:20 - 13:50) 11:05 1S: University Design Contest Chairs: Noriyuki Miura (Kobe Univ., Japan), Hiroyuki Ito (Tokyo Inst. of Tech., Japan)
2S-2: “CNN-based Object Detection Solutions for 2A-2: “Efficient Mapping of CDFG onto 2B-2: “A Novel Basis for Logic Rewriting” Win- 2C-2: “Workload-aware Static Aging Monitoring Embedded Heterogeneous Multi-core SoCs” Cheng Coarse-Grained Reconfigurable Array Archi- ston Haaswijk, Mathias Soeken (EPFL, Switzerland), of Timing-critical Flip-flops” Arunkumar Vijayan, Wang, Ying Wang, Yinhe Han, Lili Song, Zhenyu tectures” Satyajit Das, Kevin Martin, Philippe Luca Amaru´ (Synopsys, U.S.A.), Pierre-Emmanuel Saman Kiamehr, Fabian Oboril (Karlsruhe Inst. of Tech., Quan, Jiajun Li, Xiaowei Li (Chinese Academy of Sci- Coussy (Univ. of South Brittany, France), Davide Rossi, Gaillardon (Univ. of Utah, U.S.A.), Giovanni De Micheli Germany), Krishnendu Chakrabarty (Duke Univ., U.S.A.), ences, China) Luca Benini (Univ. of Bologna, Italy) (EPFL, Switzerland) Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
2S-3: “Low-Power Neuromorphic Speech Recog- 2A-3: “Timing Window Wiper : A New Scheme for 2B-3: “Multi-level Logic Benchmarks: An Exact- 2C-3: “Enhancing Robustness of Sequential Cir- nition Engine with Coarse-Grain Sparsity” Shihui Reducing Refresh Power of DRAM” Ho Hyun Shin, ness Study” Luca Amaru´ (Synopsys, U.S.A.), Mathias cuits Using Application-specific Knowledge and Yin, Deepak Kadetotad (Arizona State Univ., U.S.A.), Bo- Hyeokjun Seo, Byunghoon Lee, Jeongbin Kim, Eui- Soeken, Winston Haaswijk, Eleonora Testa (EPFL, Formal Methods” Sebastian Huhn (Univ. of Bremen, nan Yan, Chang Song, Yiran Chen (Univ. of Pittsburgh, Young Chung (Yonsei Univ., Republic of Korea) Switzerland), Patrick Vuillod, Jiong Luo (Synopsys, Germany), Stefan Frehse (DFKI GmbH Bremen, Germany), U.S.A.), Chaitali Chakrabarti, Jae-sun Seo (Arizona State U.S.A.), Pierre-Emmanuel Gaillardon (Univ. of Utah, Robert Wille (Johannes Kepler Univ. Linz, Austria), Rolf Univ., U.S.A.) U.S.A.), Giovanni De Micheli (EPFL, Switzerland) Drechsler (Univ. of Bremen, Germany)
2S-4: “Towards Acceleration of Deep Convolutional 2A-4: “On Efficient Message Passing in Energy 2B-4: “Approximate Logic Synthesis for FPGA by 2C-4: “WIPE: Wearout Informed Pattern Elimi- Neural Networks Using Stochastic Computing” Ji Harvesting Based Distributed System” Ye Tian, Wire Removal and Local Function Change” Yi Wu, nation to Improve the Endurance of NVM-based Li (Univ. of Southern California, U.S.A.), Ao Ren, Zhe Li, Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Jason Chuyu Shen, Yi Jia, Weikang Qian (Shanghai Jiao Tong Caches” Sina Asadi, Amir Mahdi Hosseini Mon- Caiwen Ding (Syracuse Univ., U.S.A.), Bo Yuan (City Univ. Xue (City Univ. of Hong Kong, Hong Kong) Univ., China) azzah, Hamed Farbeh, Seyed Ghassem Miremadi of New York, U.S.A.), Qinru Qiu, Yanzhi Wang (Syracuse (Sharif Univ. of Tech., Iran) Univ., U.S.A.)
15:30 Coffee break (15:30 - 15:50) 15:50 3S: (Special Session) Let’s Secure the Physics of 3A: Novel Techniques to Improve the Simulation 3B: Formal and Informal Verification 3C: Pursuing System to Circuit Level Optimality Cyber-Physical Systems Performance in Timing and Power Integrity Organizers: Mohammad Al Faruque (Univ. of Cal- Chairs: Ing-Jer Huang (National Sun Yat-sen Univ., Tai- Chairs: Jason Verley (Sandia National Laboratory, U.S.A.), Chairs: Takashi Sato (Kyoto Univ., Japan), Sheldon Tan ifornia Irvine, U.S.A.), Anupam Chattopadhyay (Nanyang wan), Masashi Tawada (Waseda Univ., Japan) Rajit Manohar (Cornell Univ., U.S.A.) (Univ. of California, Riverside, U.S.A.) Technological Univ., Singapore), Francesco Regazzoni (ALaRI - USI, Switzerland) 3S-1: “Securing the Hardware of Cyber-Physical 3A-1: “Automated Generation of Dynamic Binary 3B-1: “Efficient Parallel Verification of Galois Field 3C-1: “Algorithm for Synthesis and Exploration of Systems” Francesco Regazzoni (ALaRI - USI, Switzer- Translators for Instruction Set Simulation” Katsumi Multipliers” Cunxi Yu, Maciej Ciesielski (Univ. of Clock Spines” Youngchan Kim, Taewhan Kim (Seoul land), Ilia Polian (Univ. of Passau, Germany) Okuda, Minoru Yoshida, Haruhiko Takeyama, Mi- Massachusetts, Amherst, U.S.A.) National Univ., Republic of Korea) noru Nakamura (Mitsubishi Electric, Japan)
3A-2: “Loop Aware IR-Level Annotation Frame- 3B-2: “Property Mining Using Dynamic Depen- 3C-2: “Yield-Driven Redundant Power Bump As- 3S-2: “Cross-Domain Security of Cyber-Physical work for Performance Estimation in Native Simula- dency Graphs” Jan Malburg (German Aerospace Cen- signment for Power Network Robustness” Yu-Min Systems” Sujit Rokka Chhetri, Jiang Wan, Moham- tion” Omayma Matoussi, Fred´ eric´ Petrot´ (Laboratoire ter, Germany), Tino Flenker (Univ. of Bremen, Germany), Lee, Chi-Han Lee, Yan-Cheng Zhu (National Chiao Tung mad Al Faruque (Univ. of California Irvine, U.S.A.) TIMA, Univ. Grenoble Alpes, France) Gorschwin¨ Fey (German Aerospace Center, Germany) Univ., Taiwan)
3A-3: “Hybrid Analysis of SystemC Models for Fast 3B-3: “CEGAR-Based EF Synthesis of Boolean 3C-3: “A Tighter Recursive Calculus to Compute and Accurate Parallel Simulation” Tim Schmidt, Functions with an Application to Circuit Rectifica- the Worst Case Traversal Time of Real-Time Traf- 3S-3: “A Systematic Security Analysis of Real-Time Guantao Liu, Rainer Domer¨ (Univ. of California, Irvine, tion” Heinz Riener (German Aerospace Center, Germany), fic over NoCs” Meng Liu, Matthias Becker, Moris Cyber-Physical Systems” Arvind Easwaran, Anu- U.S.A.) Rudiger¨ Ehlers (Univ. Bremen, Germany), Goerschwin Behnam, Thomas Nolte (Malardalen¨ Univ., Sweden) (Nanyang Techno- pam Chattopadhyay, Shivam Bhasin Fey (German Aerospace Center, Germany) logical Univ., Singapore)
3A-4: “Virtual Prototyping of Smart Systems 3B-4: “An Extensible Perceptron Framework for 3C-4: “An Efficient Homotopy-Based Poincare-´ through Automatic Abstraction and Mixed-Signal Revision RTL Debug Automation” John Adler, Lindstedt Method for the Periodic Steady-State Scheduling” Michele Lora, Enrico Fraccaroli, Ryan Berryhill, Andreas Veneris (Univ. of Toronto, Analysis of Nonlinear Autonomous Oscilla- Franco Fummi (Univ. of Verona, Italy) Canada) tors” Zhongming Chen, Kim Batselier (Univ. of Hong Kong, Hong Kong), Haotian Liu (Cadence Design Systems, U.S.A.), Ngai Wong (Univ. of Hong Kong, Hong Kong)
17:30 ACM SIGDA Student Research Forum at ASP-DAC 2017 [Food will be served] (18:00 - 20:00) (The title of the posters are listed in the next page) 18:00 ACM SIGDA Student Research Forum at ASP-DAC2017
SRF-1: “Memory Sleep-Aware Task Allocation and Scheduling Algorithm Design for Energy Efficiency” Chenchen Fu (City University of Hong Kong) SRF-2: “Linearity Enhancements of Receiver Front-end Circuits for Wireless Communication” Mohammed Abdulaziz (Lund University) SRF-3: “Exploiting Process Variation for LDPC Read Performance Improvement on Flash Memory based Storage Systems” Qiao Li (Chongqing University) SRF-4: “Cross-Layer Approach for Power Delivery and System Architecture Co-Exploration” Kassan Unda (University of Notre Dame) SRF-5: “Performance and Reliability Optimization of NoC-based MPSoCs Via Fine-grained Communication Consideration” Lei Yang (Chongqing University) SRF-6: “Real-Time Communication over Wormhole-Switched On-Chip Networks” Meng Liu (Malardalen¨ University) SRF-7: “Making Frequent Pattern Mining Durable and Scalable” Yi Lin (Chongqing University) SRF-8: “Piracy Prevention of Digital Microfluidic Biochips” Ching-Wei Hsieh (National Tsing Hua University) SRF-9: “Energy-Efficient and Secure Reconfigurable Computing Architecture” Robert Karam (University of Florida) SRF-10: “Consolidating Automotive Applications on Clustered Many-Core Platforms” Matthias Becker (Malardalen¨ University) SRF-11: “Modeling and calibration of interconnect corners” Daijoon Hyun (KAIST) SRF-12: “A Highly Parallel Query Processor on 65-nm SOTB Process For Fast Data Analytics” Xuan-Thuan Nguyen (The University of Electro-Communications) SRF-13: “Area-Efficient Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components” Junghoon Oh (Japan Advanced Institute of Science and Technology) SRF-14: “A Guided Maze-based Length Controllable Router for Signal Delay Matching” Mitsuru Matsushita (Kochi University) SRF-15: “An Arithmetic Processor Using CORDIC Algorithm” Hong-Thu Nguyen (The University of Electro-Communications) 20:00 Wednesday, January 18, 2017
Registration (7:30 - ) 9:00 2K: Keynote II Chair: Masaharu Imai (Osaka Univ., Japan) Napoleon Torres-Martinez (CEA LETI, France) “Emerging Medical Technologies for Interfacing the Brain: From Deep Brain Stimulation to Brain Computer Interfaces” 9:50 Coffee break (9:50 - 10:15) 10:15 4S: (Special Session) Emerging Technologies for 4A: Power and Thermal Management 4B: Emerging Topics in Hardware Security 4C: Manufacturability and Emerging Techniques Biomedical Applications: Artificial Vision Sys- tems and Brain Machine Interface Organizer/Chair: Masaharu Imai (Osaka Univ., Japan), Chair: Koji Inoue (Kyushu Univ., Japan) Chairs: Xiaoxiao Wang (Beihang Univ., China), Kazuo Chairs: Taewhan Kim (Seoul National Univ., Republic of Moderator: Yoshinori Takeuchi (Osaka Univ., Japan) Sakiyama (Univ. of Electrical Communications, Japan) Korea), Wenjing Rao (Univ. of Illinois, U.S.A.) 4S-1: “Smart Electrode - Toward a Retinal Stimu- 4A-1: “A Tool for Synthesizing Power-Efficient 4B-1: “Ensuring System Security through Proxim- 4C-1: “Network Flow Based Cut Redistribution lator with the Large Number of Electrodes -” Jun and Custom-Tailored Wavelength-Routed Optical ity Based Authentication” Joshua Marxen, Alex and Insertion for Advanced 1D Layout Design” Ye Ohta (NAIST, Japan) Rings” Marta Ort´ın-Obon´ (Univ. of Zaragoza, Spain), Orailoglu (Univ. of California, San Diego, U.S.A.) Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan Luca Ramini (Univ. of Ferrara, Italy),V´ıctor Vinals-˜ (Fudan Univ., China), Hai Zhou (Northwestern Univ., U.S.A.), Yufera´ (Univ. of Zaragoza, Spain), Davide Bertozzi (Univ. Dian Zhou (Univ. of Texas, Dallas, U.S.A.), Xuan Zeng (Fu- of Ferrara, Italy) dan Univ., China) 4S-2: “Strategic Circuits for Neuromodulation of 4A-2: “Islands of Heaters: A Novel Thermal Man- 4B-2: “VOLtA: Voltage Over-scaling Based 4C-2: “An Efficient Algorithm for Stencil Planning the Visual System” Gregg Jorgen Suaning (Univ. of agement Framework for Photonic NoCs” Dharanid- Lightweight Authentication for IoT Applica- and Optimization in E-Beam Lithography” Jiabei New South Wales, Australia) har Dang (Texas A&M Univ., U.S.A.), Sai Vineel Reddy tions” Md Tanvir Arafin, Mingze Gao, Gang Qu Ge, Changhao Yan (Fudan Univ., China), Hai Zhou (North- Chittamuru (Colorado State Univ., U.S.A.), Rabi N Mahap- (Univ. of Maryland, College Park, U.S.A.) western Univ., U.S.A.), Dian Zhou (Univ. of Texas, Dallas, atra (Texas A&M Univ., U.S.A.), Sudeep Pasricha (Colorado U.S.A.), Xuan Zeng (Fudan Univ., China) State Univ., U.S.A.) 4A-3: “Energy-Aware Loops Mapping on Multi- 4B-3: “Security Analysis of Anti-SAT” Muhammad 4C-3: “Flexible Interconnect in 2.5D ICs to Min- 4S-3: “Design Considerations and Clinical Ap- Vdd CGRAs without Performance Degrada- Yasin (New York Univ., U.S.A.), Bodhisatwa Mazumdar, imize the Interposer’s Metal Layers” Daniel P. plications of Closed-Loop Neural Disorder Con- tion” Jiangyuan Gu, Shouyi Yin, Leibo Liu, Ozgur Sinanoglu (New York Univ. Abu Dhabi, United Arab Seemuth, Azadeh Davoodi, Katherine Morrow (Univ. trol SoCs” Chung-Yu Wu, Cheng-Hsiang Cheng, Shaojun Wei (Tsinghua Univ., China) Emirates), Jeyavijayan Rajendran (Univ. of Texas, Dallas, of Wisconsin - Madison, U.S.A.) Yi-Huan Ou-Yang (National Chiao Tung Univ., Taiwan), U.S.A.) Chiung-Chu Chen (Chang Gung Memorial Hospital and Univ., Taiwan), Wei-Ming Chen, Ming-Dou Ker, Chen- 4A-4: “Algorithm Accelerations for Luminescent 4B-4: “Exploiting Accelerated Aging Effect for On- 4C-4: “Optimizing DSA-MP Decomposition Yi Lee (National Chiao Tung Univ., Taiwan), Sheng-Fu Solar Concentrator-Enhanced Reconfigurable On- line Configurability and Hardware Tracking” Yang and Redundant Via Insertion with Dummy Liang, Fu-Zen Shaw (National Cheng Kung Univ., Taiwan) board Photovoltaic System” Caiwen Ding (Syra- You, Jie Gu (Northwestern Univ., U.S.A.) Vias” Chung-Yao Hung, Peng-Yi Chou, Wai- cuse Univ., U.S.A.), Ji Li (Univ. of Southern California, Kei Mak (National Tsing Hua Univ., Taiwan) U.S.A.), Weiwei Zheng (Syracuse Univ., U.S.A.), Nae- hyuck Chang (Korea Advanced Institute of Science and Engi- neering (KAIST), Republic of Korea), Xue Lin (Northeastern 4S-4: “Emerging Technologies for Biomedical Ap- Univ., U.S.A.), Yanzhi Wang (Syracuse Univ., U.S.A.) plications: Artificial Vision Systems and Brain Ma- 4A-5: “Two-stage Thermal-Aware Scheduling of 4B-5: “SGXCrypter: IP Protection for Portable Ex- 4C-5: “Design of Multiple Fanout Clock Distribu- chine Interface” Jun Ohta (NAIST, Japan), Gregg Jor- Task Graphs on 3D Multi-cores Exploiting Applica- ecutables Using Intel’s SGX Technology” Dimitrios tion Network for Rapid Single Flux Quantum Tech- gen Suaning (Univ. of New South Wales, Australia), Chung- tion and Architecture Characteristics” Zuomin Zhu Tychalas (New York Univ. Abu Dhabi, United Arab Emirates), nology” Naveen Katam, Alireza Shafaei, Massoud Yu Wu (National Chiao Tung Univ., Taiwan), Napoleon (Hong Kong Univ. of Science and Tech., Hong Kong), Vivek Nektarios Georgios Tsoutsos (New York Univ. Polytechnic Pedram (Univ. of Southern California, U.S.A.) Torres-Martinez (CEA-Leti, France) Chaturvedi (Nanyang Technological Univ., Singapore), Amit School of Engineering, U.S.A.), Michail Maniatakos (New Kumar Singh (Univ. of Southampton, U.K.), Wei Zhang York Univ. Abu Dhabi, United Arab Emirates) (Hong Kong Univ. of Science and Tech., Hong Kong), Yingnan 12:20 Cui (Nanyang Technological Univ., Singapore) Lunch Break (12:20 - 13:50) Supporters’ Session [Food will be served] (12:20 - 13:50) 13:50 5S: (Designers’ Forum) Advanced Devices and 5A: Approximate Computation for Energy Effi- 5B: Advance Test and Fault Tolerant Technolo- 5C: Advanced Placement and Routing Tech- Networks for IoT Applications ciency gies niques Organizers: Koichiro Yamashita (Fujitsu Labs., Japan), Chairs: Li Shang (Univ. of Colorado, U.S.A.), Shinobu Chairs: Satoshi Ohtake (Oita Univ., Japan), Ying Wang Chairs: Seokhyeong Kang (UNIST, Republic of Korea), Tatsuo Shiozawa (Toshiba, Japan), Masaru Kokubo (Hi- Miwa (Univ. of Electro-Communications, Japan) (Chinese Academy of Sciences, China) Wai-Kei Mak (National Tsing Hua Univ., Taiwan) tachi, Japan), Chair: Koichiro Yamashita (Fujitsu Labs., Japan) Chair: Koichiro Yamashita (Fujitsu Labs., Japan) 5S-1: “Implementation of Reliable and 5A-1: “A Novel Data Format for Approximate 5B-1: “An Artificial Neural Network Approach for 5C-1: “Regularity-aware Routability-driven Place- Maintenance-Free Wireless Multihop Net- Arithmetic Computing” Mingze Gao, Qian Wang, Screening Test Escapes” Fan Lin (Univ. of California, ment Prototyping Algorithm for Hierarchical works” Ren Sakata, Suhwuk Kim, Hiroki Kudo Akshaya Sharma Kankanhalli Nagendra, Gang Qu Santa Barbara, U.S.A.), Kwang-Ting Tim Cheng (Hong Mixed-size Circuits” Jai-Ming Lin, Bo-Heng Yu, (Toshiba, Japan) (Univ. of Maryland, College Park, U.S.A.) Kong Univ. of Science and Tech., Hong Kong) Li-Yen Chang (National Cheng Kung Univ., Taiwan)
5S-2: “High-performance and Low-power Embed- 5A-2: “ApproxPIM: Exploiting Realistic 3D- 5B-2: “Processor Shield for L1 Data Cache 5C-2: “Floorplan and Placement Methodology for ded Memory for Edge Computing System” Masami stacked DRAM for Energy-Efficient Processing In- Software-Based On-line Self-testing” Ching-Wen Improved Energy Reduction in Stacked Power- Nakajima (Renesas Electronics, Japan) memory” Yibin Tang, Ying Wang, Huawei Li, Xi- Lin, Chung-Ho Chen (National Cheng Kung Univ., Taiwan) Domain Design” Kristof Blutman, Hamed Fatemi aowei Li (Chinese Academy of Sciences, China) (NXP Semiconductors, Netherlands), Andrew B. Kahng (Univ. of California, San Diego, U.S.A.), Ajay Kapoor (NXP Semiconductors, Netherlands), Jiajia Li (Univ. of California, San Diego, U.S.A.), Jose´ Pineda de Gyvez (NXP Semicon- ductors, U.S.A.) 5S-3: “Ultra-Low-Power Wireless Sensor Nodes 5A-3: “ApproxEye: Enabling Approximate Compu- 5B-3: “Predicting Vt Variation and Static IR 5C-3: “An Effective Legalization Algorithm for with Energy Harvesting, and IoT gateway Technol- tation Reuse for Microrobotic computer Vision” Xin Drop of Ring Oscillators Using Model-Fitting Tech- Mixed-Cell-Height Standard Cells” Chao-Hung ogy” Hiroki Morimura (NTT, Japan) He (Chinese Academy of Sciences/Univ. of Chinese Academy of niques” Tzu-Hsuan Huang, Wei-Tse Hung, Hao-Yu Wang, Yen-Yi Wu (National Taiwan Univ., Taiwan), Jianli Sciences, China), Guihai Yan (Chinese Academy of Sciences, Yang, Wen-Hsiang Chang (National Chiao Tung Univ., Tai- Chen (Fuzhou Univ., China), Yao-Wen Chang, Sy- China), Faqiang Sun (Chinese Academy of Sciences/Univ. of wan), Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee Yen Kuo (National Taiwan Univ., Taiwan), Wenxing Zhu, Chinese Academy of Sciences, China), Yinhe Han, Xiaowei (Realtek Semiconductor, Taiwan), Mango Chia-Tso Chao Genghua Fan (Fuzhou Univ., China) Li (Chinese Academy of Sciences, China) (National Chiao Tung Univ., Taiwan)
5S-4: “Fast Channel Switching Technique for Inter- 5A-4: “On Resilient Task Allocation and Schedul- 5B-4: “A Local Reconfiguration Based Scalable 5C-4: “Delay-driven Layer Assignment for Ad- ference Avoidance with 5 GHz Dual Channel Wire- ing with Uncertain Quality Checkers” Qian Zhang, Fault Tolerant Many-processor Array” Soumya vanced Technology Nodes” Szu-Yuan Han (National less LAN” Takashi Takeuchi (Hitachi, Japan) Ting Wang, Qiang Xu (Chinese Univ. of Hong Kong, Hong Banerjee, Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.) Tsing Hua Univ., Taiwan), Wen-Hao Liu (Cadence Design Kong) Systems, U.S.A.), Rickard Ewetz (Univ. of Central Florida, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.), Kai- Yuan Chao (Intel, U.S.A.), Ting-Chi Wang (National Tsing Hua Univ., Taiwan) 15:30 Coffee break (15:30 - 15:50) 15:50 6S: (Designers’ Forum) Panel Discussion: What 6A: Recent Advances in Circuit Simulation and 6B: Application-Aware Embedded Architecture 6C: Advances in Microfluidic Biochips is future AI we will create ? - “Doraemon” or Optimization Design “Terminator” ? - Organizers: Hiroe Iwasaki (NTT, Japan), Sunao Chairs: Markus Olbrich (Univ. of Hannover, Germany), Chairs: Chun-Yi Lee (NTHU, Taiwan), Shao-Yun Fang Chairs: Juinn-Dar Huang (National Chiao Tung Univ., Trii (ExaScaler, Japan), Akihiko Inoue (Panasonic, Japan), Ibrahim (Abe) Elfadel (Masdar Inst. of Science and Tech., (National Taiwan Univ. of Science and Tech., Taiwan) Taiwan), Weikang Qian (Shanghai Jiao Tong Univ., China) Chair: Satoshi Kurihara (Univ. of Electro-Communications, United Arab Emirates) Japan) Moderator: 6A-1: “STEAM: Spline-based Tables for Efficient 6B-1: “Throughput Optimization for Streaming 6C-1: “Piracy Prevention of Digital Microfluidic Satoshi Kurihara (Univ. Electro-Communications, Japan) and Accurate Device Modelling” Archit Gupta, Applications on CPU-FPGA Heterogeneous Sys- Biochips” Ching-Wei Hsieh (National Tsing Hua Univ., Panelists: Tianshi Wang, Ahmet Gokcen Mahmutoglu, Jaijeet tems” Xuechao Wei, Yun Liang (Peking Univ., China), Taiwan), Zipeng Li (Duke Univ., U.S.A.), Tsung-Yi Ho (Na- Hiroshi Yamakawa (dwango, Japan) Roychowdhury (UC Berkeley, U.S.A.) Tao Wang (Peking Univ./PKU-UCLA Joint Research Institute in tional Tsing Hua Univ., Taiwan) Luca Rigazio (Panasonic Silicon Valley Lab, Japan) Science and Engineering, China), Songwu Lu, Jason Cong Takeshi Yamada (NTT, Japan) (Peking Univ./UCLA/PKU-UCLA Joint Research Institute in Sci- ence and Engineering, U.S.A.) Akira Naruse (NVIDIA, Japan) Shinji Nakadai (NEC, Japan) 6A-2: “A Time Domain Behavioral Model for Os- 6B-2: “Dark Silicon-Aware Hardware-Software 6C-2: “On Reliability Hardening in Cyber-Physical cillators Considering Flicker Noise” Hui Zhang, Bo Collaborated Design for Heterogeneous Many-Core Digital-Microfluidic Biochips” Guan-Ruei Lu, Wang (Peking Univ. Shenzhen Graduate School, China) Systems” Lei Yang, Weichen Liu (Chongqing Univ., Guan-Ming Huang (National Chiao Tung Univ., Taiwan), China), Nan Guan (Hong Kong Polytechnic Univ., Hong Ansuman Banerjee, Bhargab B. Bhattacharya (Ad- Kong), Mengquan Li, Peng Chen, Edwin H. M. Sha vanced Computing & Microelectronics Unit, Indian Statistical In- (Chongqing Univ., China) stitute, India), Tsung-Yi Ho (National Tsing Hua Univ., Tai- wan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
6A-3: “Parasitic-Aware GP-based Many-objective 6B-3: “Non-Intrusive Dynamic Profiler for Multi- 6C-3: “Hamming-Distance-Based Valve-Switching Sizing Methodology for Analog and RF Integrated core Embedded Systems” Sudarshan Sargur, Roman Optimization for Control-Layer Multiplexing in Circuits” Tuotian Liao, Lihong Zhang (Memorial Univ. Lysecky (Univ. of Arizona, U.S.A.) Flow-Based Microfluidic Biochips” Qin Wang, of Newfoundland, Canada) Shiliang Zuo, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Bing Li, Ulf Schlichtmann (Tech. Univ. of Munich, Germany), Yici Cai (Tsinghua Univ., China)
6A-4: “High-Speed Stochastic Circuits Using Syn- 6B-4: “Design of A Pre-Scheduled Data Bus for Ad- 6C-4: “Close-to-Optimal Placement and Routing chronous Analog Pulses” M. Hassan Najafi, David vanced Encryption Standard Encrypted System-on- for Continuous-Flow Microfluidic Biochips” An- J. Lilja (Univ. of Minnesota, twin cities, U.S.A.) Chips (SoCs)” Xiaokun Yang (Univ. of Houston Clear dreas Grimmer (Johannes Kepler Univ., Austria), Qin Lake, U.S.A.), Wujie Wen (Florida International Univ., U.S.A.) Wang, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Robert Wille (Jo- 17:30 hannes Kepler Univ., Austria) Banquet (18:00 - 20:00) Thursday, January 19, 2017
Registration (7:30 - ) 9:00 3K: Keynote III Chair: Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) Steve Trimberger (Xilinx Research Labs, U.S.A.) “All-Programmable FPGAs: More Powerful Devices Require More Powerful Tools” 9:50 Coffee break (9:50 - 10:15) 10:15 7S: (Special Session) When Backend Meets Fron- 7A: NVM/Flash: From Advanced Storage Design 7B: Hardware Diversity and Hardware Trojan 7C: Hardware Accelerator for Emerging Appli- tend: Cross-Layer Design & Optimization for to Emerging Applications cations System Robustness Organizers: Cheng Zhuo (Zhejiang Univ.), Masanori Chairs: Sungjoo Yoo (Seoul National Univ., Republic of Chairs: Wujie Wen (Florida International Univ., U.S.A.), Chairs: Tohru Ishihara (Kyoto Univ., Japan), Yongpan Hashimoto (Osaka Univ., Japan) Korea), Ya-Shu Chen (National Taiwan Univ. of Science and Chip Hong Chang (Nanyang Technological Univ., Singapore) Liu (Tsinghua Univ., China) Tech., Taiwan) 7S-1: “Containing Guardbands” Hussam Amrouch, 7A-1: “Improving LDPC Performance Via Asym- 7B-1: “Trojan Localization Using Symbolic Alge- 7C-1: “Towards Scalable and Efficient GPU- Jorg¨ Henkel (Karlsruhe Inst. of Tech., Germany) metric Sensing Level Placement on Flash Mem- bra” Farimah Farahmandi, Yuanwen Huang, Prab- Enabled Slicing Acceleration in Continuous 3D ory” Qiao Li, Liang Shi (Chongqing Univ., China), Chun hat Mishra (Univ. of Florida, U.S.A.) Printing” Aosen Wang, Chi Zhou (State Univ. of New Jason Xue (City Univ. of Hong Kong, Hong Kong), Qingfeng York, Buffalo, U.S.A.), Zhanpeng Jin (State Univ. of New Zhuge, Edwin H.-M. Sha (Chongqing Univ., China) York, Binghamton, U.S.A.), Wenyao Xu (State Univ. of New York, Buffalo, U.S.A.) 7A-2: “A Flash Scheduling Strategy for Cur- 7B-2: “Detecting Hardware Trojans in Unspecified 7C-2: “FPGA-based Accelerator for Long Short- 7S-2: “Pattern Based Runtime Voltage Emergency rent Capping in Multi-Power-Mode SSDs” Li-Pin Functionality Through Solving Satisfiability Prob- Term Memory Recurrent Neural Networks” Yijin Prediction: An Instruction-Aware Block Sparse Chang, Chia-Hsiang Cheng, Kai-Hsiang Lin (National lems” Nicole Fern (UC Santa Barbara, U.S.A.), Ismail San Guan, Zhihang Yuan (Peking Univ., China), Guangyu Compressed Sensing Approach” Yu-Guang Chen Chiao Tung Univ., Taiwan) (Anadolu Univ., Turkey), Kwang-Ting (Tim) Cheng (Hong Sun (Peking Univ./PKU-UCLA Joint Research Institute in Sci- (National Tsing Hua Univ., Taiwan), Michihiro Shintani, Kong Univ. of Science and Tech., Hong Kong) ence and Engineering, China), Jason Cong (Peking Univ./PKU- Takashi Sato (Kyoto Univ., Japan), Yiyu Shi (Univ. of UCLA Joint Research Institute in Science and Engineering/Univ. of Notre Dame, U.S.A.), Shih-Chieh Chang (National Tsing Hua California, Los Angeles, U.S.A.) Univ., Taiwan) 7A-3: “Temperature-Aware Data Allocation Strat- 7B-3: “Routing Perturbation for Enhanced Security 7C-3: “Fine-Grained Accelerators for Sparse Ma- 7S-3: “Heterogeneous Chip Power Delivery Mod- egy for 3D Charge-Trap Flash Memory” Yi Wang, in Split Manufacturing” Yujie Wang, Pu Chen, Jiang chine Learning Workloads” Asit K Mishra, Eriko eling and Co-Synthesis for Practical 3DIC Realiza- Mingxu Zhang (Shenzhen Univ., China), Jing Yang (Harbin Hu (Texas A&M Univ., U.S.A.), Jeyavijayan Rajendran Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, tion” Wei-Hsun Liao (National Chiao Tung Univ., Tai- Inst. of Tech., China) (Univ. of Texas, Dallas, U.S.A.) Debbie Marr (Intel, U.S.A.) wan), Chang-Tzu Lin (ITRI, Taiwan), Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Ding-Ming Kwai, Yung-Fa Chou (ITRI, Taiwan) 7A-4: “Scalable Frequent-Pattern Mining on Non- 7B-4: “MUTARCH: Architectural Diversity for 7C-4: “High Throughput Hardware Architecture for volatile Memories” Yi Lin (Chongqing Univ., China), Po- FPGA Device and IP Security” Robert Karam, Accurate Semi-Global Matching” Yan Li, Chen Chun Huang (Yuan Ze Univ., Taiwan), Duo Liu, Liang Tamzidul Hoque (Univ. of Florida, U.S.A.), Sandip Ray Yang, Wei Zhong, Zhiwei Li, Song Chen (Univ. of Liang (Chongqing Univ., China) (NXP Semiconductors, U.S.A.), Mark Tehranipoor, Swarup Science and Tech. of China, China) 7S-4: “CN-SIM: A Cycle-Accurate Full System Bhunia (Univ. of Florida, U.S.A.) Power Delivery Noise Simulator” Kassan Unda 7A-5: “KVFTL: Optimization of Storage Space Uti- 7B-5: “Security Vulnerability Analysis of Design- 7C-5: “A Memristor-based Neuromorphic Engine (Univ. of Notre Dame, U.S.A.), Chung-Han Chou, Shih- lization for Key-Value-Specific Flash Storage De- for-Test Exploits for Asset Protection in SoCs” Gus- with a Current Sensing Scheme for Artificial Neural Chieh Chang (National Tsing Hua Univ., Taiwan), Cheng vices” Yen-Ting Chen (National Tsing Hua Univ., Tai- tavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Network Applications” Chenchen Liu, Qing Yang Zhuo (Zhejiang Univ., China), Yiyu Shi (Univ. of Notre Dame, wan), Ming-Chang Yang, Yuan-Hao Chang, Tseng-Yi Domenic Forte, Mark Tehranipoor (Univ. of Florida, (Univ. of Pittsburgh, U.S.A.), Chi Zhang, Hao Jiang (San U.S.A.) Chen (Academia Sinica, Taiwan), Hsin-Wen Wei (Tamkang U.S.A.) Francisco State Univ., U.S.A.), Qing Wu (Air Force Research Univ., Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Lab, U.S.A.), Hai (Helen) Li (Univ. of Pittsburgh, U.S.A.) 12:20 Taiwan) Lunch Break (12:20 - 13:50) 13:50 8S: (Designers’ Forum) Advanced Automotive 8A: Scheduling, Resource Management, and 8B: Machine Learning: Acceleration and Appli- 8C: Design Automation and Modeling for Emerg- Security Simulation for Multi-Core Systems cation ing Technologies Organizers: Shinichi Shibahara (Renesas System Design, Chairs: Yuko Hara-Azumi (Tokyo Inst. of Tech., Japan), Chairs: Weichen Liu (Chongqing Univ., China), Nan Chair: Yiran Chen (Univ. of Pittsburgh, U.S.A.) Japan), Akihiko Inoue (Panasonic, Japan), Chair: Shinichi Yi Wang (Shenzhen Univ., China) Guan (Hong Kong Polytechnic Univ., Hong Kong) Shibahara (Renesas System Design, Japan) Chair: Shinichi Shibahara (Renesas System Design, Japan) 8S-1: “Using Security Applications for Automotive 8A-1: “An Adaptive On-line CPU-GPU Governor 8B-1: “Spendthrift: Machine Learning Based Re- 8C-1: “Reservoir and Mixer Constrained Schedul- Hardware Security Modules” Dennis Kengo Oka for Games on Mobile Devices” Po-Kai Chuang, Ya- source and Frequency Scaling for Ambient Energy ing for Sample Preparation on Digital Microfluidic (ETAS, Japan) Shu Chen, Po-Hao Huang (National Taiwan Univ. of Sci- Harvesting Nonvolatile Processors” Kaisheng Ma, Biochips” Varsha Agarwal, Ananya Singla (Indian ence and Tech., Taiwan) Xueqing Li, Srivatsa Rangachar Srinivasa (Pennsylva- Inst. of Tech. Roorkee, India), Mahammad Samiuddin nia State Univ., U.S.A.), Yongpan Liu (Tsinghua Univ., China), (Indian Inst. of Tech. Kharagpur, India), Sudip Roy (Indian John (Jack) Sampson (Pennsylvania State Univ., U.S.A.), Inst. of Tech. Roorkee, India), Tsung-Yi Ho (National Tsing Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Vi- Hua Univ., Taiwan), Indranil Sengupta (Indian Inst. of Tech. jaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.) Kharagpur, India), Bhargab B. Bhattacharya (Indian Statis- tical Institute Kolkata, India) 8S-2: “An Embedded Hardware Security Module 8A-2: “A Static Scheduling Approach to Enable 8B-2: “Modular Reinforcement Learning for Self- 8C-2: “Exact Routing for Micro-Electrode-Dot- for Automotive ECUs” Yasuhisa Shimazaki (Renesas Safety-Critical OpenMP Applications” Alessandra Adaptive Energy Efficiency Optimization in Multi- Array Digital Microfluidic Biochips” Oliver Electronics, Japan) Melani (Scuola Superiore Sant’Anna, Italy), Maria A. Ser- core System” Zhe Wang, Zhongyuan Tian, Jiang Keszocze (Univ. of Bremen, Germany), Zipeng Li (Duke rano (Barcelona Supercomputing Center and Technical Univ. of Xu, Rafael Kioji Vivas Maeda, Haoran Li, Peng Univ., U.S.A.), Andreas Grimmer, Robert Wille (Jo- Catalonia, Spain), Marko Bertogna (Univ. di Modena e Reggio Yang, Zhehui Wang, Luan H. K. Duong, Zhifei hannes Kepler Univ., Austria), Krishnendu Chakrabarty Emilia, Italy), Isabella Cerutti (Scuola Superiore Sant’Anna, Wang, Xuanqi Chen (Hong Kong Univ. of Science and Tech., (Duke Univ., U.S.A.), Rolf Drechsler (Univ. of Bremen and Italy), Eduardo Quinones˜ (Barcelona Supercomputing Cen- Hong Kong) DFKI GmbH, Germany) ter, Spain), Giorgio Buttazzo (Scuola Superiore Sant’Anna, Italy) 8S-3: “Security Hardware for Automotive Applica- 8A-3: “Communication Driven Remapping of Pro- 8B-3: “BHNN: a Memory-Efficient Accelerator for 8C-3: “Majority Logic Circuits Optimisation by tions” Takeshi Fujino (Ritsumeikan Univ., Japan) cessing Element (PE) in Fault-tolerant NoC-based Compressing Deep Neural Networks with Blocked Node Merging” Chun-Che Chung (National Tsing Hua MPSoCs” Chia-Ling Chen, Yen-Hao Chen, TingT- Hashing Techniques” Jingyang Zhu (Hong Kong Univ. Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), ing Hwang (National Tsing Hua Univ., Taiwan) of Science and Tech., Hong Kong), Zhiliang Qian (Shanghai Chun-Yao Wang, Chia-Cheng Wu (National Tsing Hua Jiao Tong Univ., China), Chi-Ying Tsui (Hong Kong Univ. of Univ., Taiwan) Science and Tech., Hong Kong)
8S-4: “Physical and Logical Attacks against LSI 8A-4: “Detailed and Highly Parallelizable 8B-4: “Scalable Stochastic-Computing Accelerator 8C-4: “A Statistical STT-RAM Retention Model for Chips and Their Countermeasures” Shinichi Kawa- Cycle-Accurate Network-on-Chip Simulation for Convolutional Neural Networks” Hyeonuk Sim, Fast Memory Subsystem Designs” Zihao Liu, Wujie mura (Toshiba, Japan) on GPGPU” Amir Charif, Alexandre Coelho, Dong Nguyen, Jongeun Lee (UNIST, Republic of Korea), Wen (Florida International Univ., U.S.A.), Lei Jiang (Indiana Nacer-Eddine Zergainoh, Michael Nicolaidis (TIMA Kiyoung Choi (Seoul National Univ., Republic of Korea) Univ. Bloomington, U.S.A.), Yier Jin (Univ. of Central Florida, Lab., France) U.S.A.), Gang Quan (Florida International Univ., U.S.A.)
15:30 Coffee break (15:30 - 15:50) 15:50 9S: (Designers’ Forum) Advanced Image Sensing 9A: New Directions in Networks on Chip 9B: Memory Architecture: Now and Future 9C: Intelligent Computing with Memristor Tech- and Processing nologies Organizers: Yusuke Oike (Sony Semiconductor Solutions, Chair: Kun-Chih Chen (National Sun Yat-Sen Univ., Tai- Chairs: Hyung Gyu Lee (Daegu Univ., Republic of Korea), Chair: Yuan-Hao Chang (Academia Sinica, Taiwan) Japan), Masaitsu Nakajima (Socionext, Japan), Yusuke wan) Shimpei Sato (Tokyo Inst. of Tech., Japan) Oike (Sony Semiconductor Solutions, Japan) Chair: Yusuke Oike (Sony Semiconductor Solutions, Japan) 9S-1: “An APS-H-Size 250Mpixel CMOS Im- 9A-1: “DLPS: Dynamic Laser Power Scaling for 9B-1: “Building Energy-Efficient Multi-Level Cell 9C-1: “Classification Accuracy Improvement for age Sensor Using Column Single-Slope ADCs with Optical Network-on-Chip” Fan Lan (Zhejiang Univ., STT-RAM Caches with Data Compression” Liu Neuromorphic Computing Systems with One-level Dual-Gain Amplifiers” Hirofumi Totsuka (Canon, China), Rui Wu, Chong Zhang (Univ. of Californis, Santa Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, Precision Synapses” Yandan Wang, Wei Wen, Ling- Japan) Barbara, U.S.A.), Yun Pan (Zhejiang Univ., China), Kwang- Yuan Xie (Univ. of California, Santa Barbara, U.S.A.) hao Song, Hai Li (Univ. of Pittsburgh, U.S.A.) ting Cheng (Univ. of Californis, Santa Barbara, U.S.A.)
9S-2: “A 1/1.7-inch 20Mpixel Back-Illuminated 9A-2: “Adaptive Load Distribution in Mixed- 9B-2: “MPIM: Multi-Purpose In-Memory Process- 9C-2: “Binary Convolutional Neural Network on Stacked CMOS Image Sensor” Chihiro Okada (Sony Critical Networks-On-Chip” Adam Kostrzewa, Se- ing Using Configurable Resistive Memory” Mohsen RRAM” Tianqi Tang, Lixue Xia, Boxun Li, Yu Semiconductor Solutions, Japan) bastian Tobuschat, Leonardo Ecco, Rolf Ernst (TU Imani, Yeseong Kim, Tajana Rosing (Univ. of California Wang, Huazhong Yang (Tsinghua Univ., China) Braunschweig, Germany) San Diego, U.S.A.)
9S-3: “Emerging Applications Based on High-speed 9A-3: “BoDNoC: Providing Bandwidth-on- 9B-3: “Extending the Lifetime of Object-based 9C-3: “Algorithm-Hardware Co-Optimization of Computational Vision” Yoshihiro Watanabe (Univ. of Demand Interconnection for Multi-Granularity NAND Flash Device with STT-RAM/DRAM Hy- the Memristor-Based Framework for Solving SOCP Tokyo, Japan) Memory Systems” Shiqi Lian, Ying Wang, Yinhe brid Buffer” Chuhan Min, Jie Guo, Hai Li, Yiran and Homogeneous QCQP Problems” Ao Ren (Syra- Han, Xiaowei Li (Chinese Academy of Sciences, China) Chen (Univ. of Pittsburgh, U.S.A.) cuse Univ., U.S.A.), Sijia Liu (Univ. of Michigan, U.S.A.), Ruizhe Cai (Syracuse Univ., U.S.A.), Wujie Wen (Florida International Univ., U.S.A.), Pramod K. Varshney, Yanzhi Wang (Syracuse Univ., U.S.A.)
9S-4: “Acceleration of Partial Image Matching on 9A-4: “Using Segmentation to Improve Schedu- 9B-4: “Locality-Aware Bank Partitioning for Shared 9C-4: “Computation-Oriented Fault-Tolerance FPGA Platforms Using OpenCL” Noboru Yoneoka lability of RRA-based NoCs with Mixed Traf- DRAM MPSoCs” Yangguo Liu, Junlin Lu, Dong Schemes for RRAM Computing Systems” Wenqin (Fujitsu Labs., Japan) fic” Meng Liu, Matthias Becker, Moris Behnam, Tong, Xu Cheng (Peking Univ., China) Huangfu, Lixue Xia, Ming Cheng, Xiling Yin, Thomas Nolte (Malardalen¨ Univ., Sweden) Tianqi Tang, Boxun Li (Tsinghua Univ., China), Krish- nendu Chakrabarty (Duke Univ., U.S.A.), Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Yu Wang, Huazhong 17:30 Yang (Tsinghua Univ., China) Registration The conference fee includes: • Admission to all sessions including keynote speeches and Designers’ Forum except tutorials Conference pre-registration through Web is available. Please visit the Online Registration page: • A conference kit (a final program and an authority to access the download site for the confer- ence proceedings) The download site will be open on Jan. 16, 2017. Please note that neither CD-ROM nor USB http://www.aspdac.com/ memory are provided. • One refreshment per break The Designers’ Forum fee includes: FEES • Admission to Designers’ Forum sessions and keynote speeches Category By Dec.2, 2016 From Dec.3, 2016 On site • A conference kit (a final program and an authority to access the download site for the confer- to Jan.12, 2017 ence proceedings) [Conference] The download site will be open on Jan. 16, 2017. Please note that neither CD-ROM nor USB ∗Member 57,000 yen 62,000 yen 64,000 yen memory are provided. ∗∗Speaker 57,000 yen — — • One refreshment per break Non-member 67,000 yen 72,000 yen 74,000 yen Full-time Student 35,000 yen 40,000 yen 42,000 yen The tutorial fee includes: [Keynotes + Designers’ Forum] • Admission to tutorials 25,000 yen 30,000 yen 32,000 yen • ∗ Access to electronic files of tutorial presentations Member of IEEE, ACM SIGDA, IEICE, IPSJ • One lunch coupon ∗∗Please note that each paper shall be accompanied by at least one different con- • One refreshment per break ference registration at the speaker’s registration rate (e.g., two speaker regis- trations are needed for presenting two accepted papers). But any registered Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for co-author can present the work at the conference. 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Speakers are not allowed to cancel [Tutorial] registrations. ∗Member 22,000 yen 26,000 yen 26,000 yen Non-member 26,000 yen 30,000 yen 30,000 yen ON-SITE REGISTRATION HOURS Full-time Student 14,000 yen 16,000 yen 16,000 yen ∗∗∗Student Group 10,000 yen 12,000 yen N/A Monday, January 16: 8:00 – 18:00 ∗ Member of IEEE, ACM SIGDA, IEICE, IPSJ Tuesday, January 17: 7:00 – 17:00 ∗∗∗“Student Group” discount is applied to a group of four or more students from Wednesday, January 18: 7:30 – 17:00 the same affiliation (faculty or graduate school). A list of the group members Thursday, January 19: 7:30 – 17:00 must be submitted. Please check the details in the web registration page. Advance Registration Deadline: Dec. 2nd, 2016 Information Currency Exchange: Only Japanese yen (JPY, Y) is acceptable at regular stores and restaurants. Certain foreign Proceedings: currencies may be accepted at a limited number of hotels, restaurants and souvenir shops. You can ASP-DAC 2017 will be producing an authority to access the download site for the conference buy yen at foreign exchange banks and other authorized money exchangers on presentation of your proceedings. The site will be open on Jan. 16, 2017. Please note that neither CD-ROM nor USB passport. memory are provided. Travelers checks and credit cards: Banquet: Travelers checks are accepted only by leading banks and major hotels in principal cities, and Conference registrants are invited to attend a banquet to be held on January 18, 2017. The ban- the use of travelers checks in Japan is not as popular as in some other countries. VISA, Master- quet will be held from 18:00 to 20:00 at the Convention Hall A. Regular Member and Non-member Card, Diners Club, and American Express are widely accepted at hotels, department stores, shops, Conference registrants receive a ticket to the banquet when they register at the conference. Full- restaurants and nightclubs. time students, Designers’ Forum-only registrants, and Tutorial-only registrants wishing to attend the banquet will be required to pay 5,000 yen for a ticket when they register on site. Tipping: In Japan, tips are not necessary anywhere, even at hotels and restaurants. Visa Application: Without a legal visa, foreign participants may be denied entry into Japan. Please contact your Electricity: nearest Japanese embassy in order to ensure entry. Presenters may contact Electric voltage is uniformly 100 volts, AC, throughout Japan, but with two different cycles: 50 [email protected] in Eastern Japan*, and 60 in Western Japan**. Leading hotels in major cities have two outlets of for an invitation letter. Notice that the ASP-DAC 2017 Organizing Committee issues the invitation 100 and 220 volts but their sockets usually accept a two-leg plug only. letters and supports the VISA applications only for presenters of the conference papers. All the *Eastern Japan :Tokyo, Chiba, Yokohama, Tohoku, Hokkaido other attendees have to apply for VISA through their travel agents or by yourself. In some cases it **Western Japan :Nagoya, Osaka, Kyoto, Hiroshima, Shikoku, Kyushu may take two months to obtain a legal visa. The following Web page of Japanese embassy may be helpful. Shopping: Shops and other sales outlets in Japan are generally open on Saturdays, Sundays and national http://www.mofa.go.jp/j info/visit/visa/ holidays as well as weekdays from 10:00 to 20:00. Department stores, however, are closed on one Duty free import: weekday, differing by store, and certain specialty shops may not open on Sundays and national Personal effects and professional equipment can be brought into Japan duty free as long as their holidays. contents and quantities are deemed reasonable by the customs officer. You can also bring in 400 cigarettes, 500 grams of tobacco or 100 cigars; 3 bottles of alcoholic beverages; 2 ounces of per- Other Information: fume; and gifts and souvenirs whose total market price is less than 200,000 yen or its equivalent. Participants can get sightseeing information at the JTB Travel desk in the Conference site during There is no allowance for tobacco or alcoholic beverages for persons aged 19 years or younger. the Conference period. Firearms and other types of weapons, and narcotics are strictly prohibited. Insurance: Welcome to Chiba Official Tourism Website http://www.chiba-tour.jp/html/sight tokatsu en.html/ The organizer cannot accept responsibility for accidents that might occur. Delegates are encour- aged to purchase travel insurance before leaving their home country. Insurance plans typically JAPAN NATIONAL TOURISM ORGANIZATION cover accidental loss of belongings, medical costs in case of injury or illness, and other possible http://www.jnto.go.jp/ risks of international travel. NARITA AIRPORT http://www.narita-airport.jp/en/ Climate: HANEDA AIRPORT Average temperature in winter (Jan.): http://www.haneda-airport.jp/en/ GO TOKYO http://www.gotokyo.org/en/ T(F) T(C) Sapporo 26.4 -4.1 Sendai 34.7 1.5 Tokyo, Chiba 42.4 5.8 Nagoya 39.7 4.3 Kyoto 38.3 3.5 Osaka 42.4 5.8 Fukuoka 43.5 6.4 Naha 61.9 16.6 Access to Makuhari Messe
• ASP-DAC 2017 Conference will take place at “International Conference Hall.” It is located in Makuhari Messe International Convention Complex.
Makuhari Messe is a 10-minute walk from Kaihin Makuhari Station. From Kaihin Makuhari Sta- tion, turn left after going out the the ticket wicket, pass through the Station square Traffic Terminal, turn right at the T-junction in front of Hotel New Otani, and then cross an passover. Makuhari Messe is found on the left side. Makuhari Messe can be also reached by bus from Makuhari Hongo Station. Take a Keisei bus and get off at Makuhari Messe Chuo Bus stop. In Makuhari Messe, ASP-DAC registration is on the 1st floor of International Conference Hall.
• From Narita Airport (New Tokyo International Airport) Narita Airport handles most international flights for Chiba/Tokyo area. Narita Airport has two train stations “Narita Airport” for terminal 1 and “Airport Terminal 2” for terminal 2.
– by Train Take a Keisei Line Limited Express at Terminal 2. Transfer to Keisei Chiba Line at Keisei Tsudanuma Station. Get off at Keisei Makuhari Station and walk to Makuhari Messe. (fare 740 Yen, approx. 55 minutes) – by Train + Bus Take a Keisei Line Limited Express at Terminal 2. Transfer to Keisei Chiba Line at Keisei Tsudanuma Station. Get off at Keisei Makuhari Hongo Station. Take a Keisei bus to Makuhari Messe Chuo Bus stop. (fare 990 Yen, approx. 65 minutes) – by Bus Take a Keisei Highway bus to Makuhari Messe Chuo Bus stop. (fare 900 Yen, approx. 40-45 minutes)
• From Haneda Airport (Tokyo International Airport)
– by Train Tokyo monorail + Rinkai Line + JR Take a Tokyo monorail at Terminal 1. Transfer to Rinkai Line at Tennozu Isle Station. Transfer to JR Keiyo Line (Rapid) at Shinkiba Station. Get off at JR Kaihin Makuhari Station. (fare 1,140 Yen, approx. 70 minutes) Visit our web site – by Bus http://www.aspdac.com/ Take a Keisei Highway bus to Makuhari Messe Chuo. (fare 1,370 Yen, approx. 55 minutes)
• From Tokyo Station ASP-DAC 2017 SECRETARIAT Japan Electronics Show Association 5F Ote Center Bldg., – by Train 1-1-3 Otemachi, Chiyoda-ku, Tokyo 100-0004 Japan Take a JR Keiyo Line (Rapid) to Kaihin Makuhari Station. (fare 550 Yen, approx. 35 Phone: +81-3-6212-5231 Fax: +81-3-6212-5225 minutes) E-mail: [email protected]